Semiconductor devices and their fabrication methods

Abstract

This invention provides a semiconductor device and a method for fabricating the same, comprising: providing a substrate, forming a source structure on the substrate; forming a plurality of material pillars, the plurality of material pillars being at least partially located on the source structure; sequentially forming a channel layer and a gate dielectric layer to cover the material pillars; forming a sacrificial layer to fill between each pair of adjacent material pillars; etching away a portion of the sacrificial layer between two or more adjacent material pillars to form a plurality of first openings; forming a first isolation material layer to fill the first openings; etching away the remaining sacrificial layer to form a plurality of second openings; forming a gate structure to fill the second openings, wherein a portion of the gate structure located in a first direction between two adjacent material pillars serves as a gate substructure; and forming a drain structure located above the gate structure, and the drain structure being in contact with the channel layer. This invention can improve the reliability of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method. Background Technology

[0002] Semiconductor transistors (such as metal-oxide-semiconductor transistors (MOS transistors)) have been used in various applications, such as power supplies, power converters, and switches. Traditional MOS transistors employ a planar structure. However, with the continuous development of semiconductor integrated circuit technology, MOS transistors have adopted a stacked structure to achieve transistor miniaturization. In the design of a stacked structure, etching the gate structure to form the gate dielectric layer results in etching effects on the gate structure. This etching damages the interface between the gate structure and the gate dielectric layer, affecting the quality of the gate structure and the integrity of the interface between the gate structure and the gate dielectric layer, thereby reducing device reliability. Summary of the Invention

[0003] The purpose of this invention is to provide a semiconductor device and a method for fabricating the same, thereby improving the reliability of the device.

[0004] To achieve the above objectives, the present invention provides a method for fabricating a semiconductor device, comprising:

[0005] A substrate is provided on which a source structure is formed, the source structure extending along a first direction;

[0006] Multiple material pillars are formed, and at least part of the multiple material pillars are located on the source structure;

[0007] A channel layer and a gate dielectric layer are sequentially formed to cover the material pillars;

[0008] A sacrificial layer is formed between each two adjacent material columns;

[0009] Etching removes a portion of the sacrificial layer between two or more adjacent material pillars to form a plurality of first openings, the bottom of the first openings exposing the source structure, and the sidewalls of the first openings having retained sacrificial layers.

[0010] A first insulating material layer is formed to fill the first opening;

[0011] Etching removes the remaining sacrificial layer to form a plurality of second openings, the second openings exposing the gate dielectric layer;

[0012] A gate structure is formed to fill the second opening, wherein the gate structure and the source structure have the channel layer and the gate dielectric layer between them, and the portion of the gate structure located between two adjacent material pillars along the first direction serves as a gate substructure; and...

[0013] A drain structure is formed above the gate structure, and the drain structure is in contact with the channel layer.

[0014] Optionally, the material column comprises a first material layer, a second material layer, and a third material layer stacked sequentially from bottom to top, and the step of forming the material column includes:

[0015] The first material layer, the second material layer, and the third material layer are sequentially formed, with at least one layer located on the source structure.

[0016] The first material layer, the second material layer, and the third material layer are etched to form a plurality of material pillars.

[0017] Optionally, the first material layer, the second material layer, and the third material layer respectively include a semiconductor material, a dielectric material, and a semiconductor material; or, the first material layer, the second material layer, and the third material layer respectively include a barrier material, a semiconductor material, and a semiconductor material, and the doping concentration of the semiconductor material in the second material layer is greater than the doping concentration of the semiconductor material in the third material layer.

[0018] Optionally, each of the drain structures covers one of the material pillars or two adjacent material pillars.

[0019] Optionally, each of the drain structures covers two adjacent gate substructures or three adjacent gate substructures.

[0020] Optionally, when the channel layer and the gate dielectric layer are formed to cover the material pillars, the channel layer and the gate dielectric layer also cover the source structure; when etching to form the first opening, a portion of the channel layer and a portion of the gate dielectric layer on the source structure between two or more adjacent material pillars are also etched away to expose the source structure.

[0021] Optionally, when forming the first isolation material layer to fill the first opening, the first isolation material layer also covers the material pillar and the retained sacrificial layer; after forming the first isolation material layer to fill the first opening, the first isolation material layer with a portion of its thickness is removed by a grinding process, as well as the channel layer and the gate dielectric layer at the top of the material pillar.

[0022] Optionally, when forming the first opening, at least one of the first openings has a material column as a dummy structure.

[0023] Optionally, the material pillar is also located in a region outside the source structure, and the material pillar located in the region outside the source structure is a dummy structure.

[0024] The present invention also provides a semiconductor device, comprising:

[0025] A substrate on which an active electrode structure is formed, the active electrode structure extending along a first direction;

[0026] Multiple material pillars, at least partially located on the source structure, are arranged along the first direction;

[0027] The channel layer is located on the sidewall of the material pillar and on part of the source structure;

[0028] A gate dielectric layer is located on the channel layer and surrounds the material pillar;

[0029] A gate structure is located on the gate dielectric layer, the gate structure comprising a plurality of gate substructures located between two adjacent material pillars along the first direction;

[0030] Multiple drain structures are located above the gate structure and at least a portion of the material pillars.

[0031] Optionally, the material pillar comprises a first material layer, a second material layer, and a third material layer stacked sequentially from bottom to top, wherein the first material layer, the second material layer, and the third material layer respectively comprise a semiconductor material, a dielectric material, and a semiconductor material; or, the first material layer, the second material layer, and the third material layer respectively comprise a barrier material, a semiconductor material, and a semiconductor material, and the doping concentration of the semiconductor material in the second material layer is greater than the doping concentration of the semiconductor material in the third material layer.

[0032] Optionally, each of the drain structures covers two adjacent material pillars.

[0033] Optionally, each of the drain structures covers the three adjacent gate substructures.

[0034] Optionally, it also includes a first isolation material layer, which is disposed in the opening between the gate structures respectively covered by the two adjacent drain structures, and the first isolation material layer also has material pillars as dummy structures.

[0035] Optionally, the gate dielectric layer includes a U-shaped structure and an L-shaped structure, wherein the gate dielectric layer of the U-shaped structure is disposed between two adjacent material pillars covered by each of the drain structures.

[0036] Optionally, the gate substructure is also located on the gate dielectric layer of the U-shaped structure.

[0037] Optionally, at least a portion of the gate dielectric layer covers the two sidewalls and the bottom surface of one of the gate substructures.

[0038] Optionally, the three adjacent gate substructures covered by each of the drain structures along the first direction may have at least two different thicknesses.

[0039] In the semiconductor device and its fabrication method provided by this invention, a complete material pillar is first formed, then a channel layer and a gate dielectric layer are formed to cover the material pillar. After a series of fabrications to form a second opening, a gate structure is formed to fill the second opening. This avoids etching effects on the gate structure, thereby ensuring the quality of the gate structure and the interface integrity between the gate structure and the gate dielectric layer, thus improving the reliability of the device. Furthermore, the presence of a channel layer and a gate dielectric layer between the gate structure and the source structure enables the formation of a high resistance between the gate structure and the source structure, maintaining good isolation. Moreover, forming a complete material pillar first avoids the formation of void defects in the material pillar when forming the material pillar using a filling method, thus improving the reliability of the device. Attached Figure Description

[0040] Figure 1 A flowchart of a method for fabricating a semiconductor device provided by the present invention.

[0041] Figures 2 to 16 This is a schematic diagram of the corresponding steps in the method for fabricating a semiconductor device provided in Embodiment 1 of the present invention.

[0042] Figure 17 This is a cross-sectional schematic diagram of the semiconductor device provided in Embodiment 2 of the present invention.

[0043] Figure 18 This is a top view of the semiconductor device provided in Embodiment 2 of the present invention.

[0044] Figures 19-29 This is a schematic diagram of the corresponding steps in the method for fabricating a semiconductor device provided in Embodiment 3 of the present invention.

[0045] Figure 30 This is a top view of the semiconductor device provided in Embodiment 4 of the present invention.

[0046] The attached figures are labeled as follows:

[0047] 10-Substrate; 20-Dielectric layer; 22-Electrical connector; 30-Source structure; 31-First source barrier layer; 32-Source metal layer; 33-Second source barrier layer; 34-Source semiconductor layer; 41-First material layer; 42-Second material layer; 43-Third material layer; 40a-Material pillar; 50-Channel layer; 60-Gate dielectric layer; 70-Sacrificial layer; 71-First opening; 72-Second opening; 73-Third opening; 81-First isolation material layer; 82-Second isolation material layer; 90-Gate structure; 100-Drain structure; 101-Drain barrier layer; 102-Drain metal layer. Detailed Implementation

[0048] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.

[0049] Figure 1 A flowchart illustrating the method for fabricating the semiconductor device provided by this invention. Please refer to... Figure 1 This invention provides a method for fabricating a semiconductor device, comprising:

[0050] Step S1: Provide a substrate, and form a source structure on the substrate, the source structure extending along a first direction;

[0051] Step S2: Form multiple material pillars, with at least a portion of the material pillars located on the source structure;

[0052] Step S3: Sequentially form channel layer and gate dielectric layer covering material pillars;

[0053] Step S4: Form a sacrificial layer to fill between every two adjacent material columns;

[0054] Step S5: Etch away part of the sacrificial layer between two or more adjacent material pillars to form several first openings. The bottom of the first opening exposes the source structure, and the sidewalls of the first opening have the sacrificial layer retained.

[0055] Step S6: Form a first insulating material layer to fill the first opening;

[0056] Step S7: Etch away the remaining sacrificial layer to form several second openings, which expose the gate dielectric layer;

[0057] Step S8: Form a gate structure to fill the second opening. There is a channel layer and a gate dielectric layer between the gate structure and the source structure. The part of the gate structure located between two adjacent material pillars along the first direction serves as the gate substructure.

[0058] Step S9: Form a drain structure above the gate structure, and the drain structure is in contact with the channel layer.

[0059] In the semiconductor device and its fabrication method provided by this invention, a complete material pillar is first formed, then a channel layer and a gate dielectric layer are formed to cover the material pillar. After a series of fabrications to form a second opening, a gate structure is formed to fill the second opening. This avoids etching effects on the gate structure, thereby ensuring the quality of the gate structure and the interface integrity between the gate structure and the gate dielectric layer, thus improving the reliability of the device. Furthermore, the presence of a channel layer and a gate dielectric layer between the gate structure and the source structure enables the formation of a high resistance between the gate structure and the source structure, maintaining good isolation. Moreover, forming a complete material pillar first avoids the formation of void defects in the material pillar when forming the material pillar using a filling method, thus improving the reliability of the device.

[0060] Example 1

[0061] Figures 2 to 16 This is a schematic diagram of the corresponding steps in the semiconductor device fabrication method provided in this embodiment. The following is in conjunction with... Figures 2 to 16 The method for fabricating the semiconductor device provided in this embodiment will be described in detail.

[0062] Execution step S1: Please refer to Figure 2 A substrate 10 is provided, which can be a silicon substrate, a gallium arsenide substrate, a germanium substrate, a germanium-silicon substrate, or a fully depleted silicon-on-insulator substrate, and is not limited thereto. A source structure 30 is formed on the substrate 10, and the source structure 30 extends along a first direction D1. In this embodiment, the source structure 30 includes a first source barrier layer 31, a source metal layer 32, a second source barrier layer 33, and a source semiconductor layer 34 stacked sequentially from bottom to top. The materials of the first source barrier layer 31 and the second source barrier layer 33 may include TiN, the material of the source metal layer 32 may include W, and the material of the source semiconductor layer 34 may include polysilicon, and is not limited to the above materials.

[0063] In this embodiment, a dielectric layer 20 is also formed on the substrate 10, located between the substrate 10 and the source structure 30. The dielectric layer 20 can be a stacked structure composed of different material layers, such as a stacked structure composed of an oxide layer and a nitride layer, or it can be a single material layer, such as an oxide layer or a nitride layer, and is not limited thereto. An electrical connector 22 is formed in the dielectric layer 20, and the electrical connector 22 penetrates the dielectric layer 20 and is electrically connected to the substrate 10 and the source structure 30.

[0064] Step S2: The steps for forming multiple material columns include: Please refer to... Figure 2 The first material layer 41, the second material layer 42, and the third material layer 43 are sequentially formed on at least the source structure 30; please refer to Figure 3The first material layer 41, the second material layer 42, and the third material layer 43 are etched to form a plurality of material pillars 40a, such that each material pillar 40a includes the first material layer 41, the second material layer 42, and the third material layer 43 stacked sequentially from bottom to top, and the surface of the source structure 30 is exposed between adjacent material pillars 40a; please refer to Figure 4 , Figure 4 for Figure 3 Top view, Figure 3 for Figure 4 The cross-sectional view along the A1A2 section line shows that multiple material pillars 40a are located on the source structure (specifically on the source semiconductor layer 34), and the multiple material pillars 40a are arranged along the first direction D1.

[0065] In this embodiment, the first material layer 41, the second material layer 42, and the third material layer 43 respectively include a semiconductor material, a dielectric material, and a semiconductor material; or, the first material layer 41, the second material layer 42, and the third material layer 43 respectively include a barrier material, a semiconductor material, and a semiconductor material, and the doping concentration of the semiconductor material in the second material layer 42 is greater than the doping concentration of the semiconductor material in the third material layer 43; wherein the semiconductor material may include amorphous silicon, the dielectric material may include silicon oxide, and the barrier material may include titanium nitride, and is not limited to the above materials.

[0066] Execution step S3: Please refer to Figure 5 A channel layer 50 and a gate dielectric layer 60 are sequentially formed to conformally cover the material pillars 40a (covering the sidewalls and top of the material pillars 40a) and the surface of the source structure 30 between adjacent isolation pillars 40a. In this embodiment, the material of the channel layer 50 may include polysilicon (with doped ions), and may also include one or more combinations of metal silicides, ferroelectric materials, high-k dielectric materials, and IGZO; the material of the gate dielectric layer 60 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride, and is not limited to the above materials.

[0067] Execution step S4: Please refer to Figure 5 A sacrificial layer 70 is formed to fill the space between each two adjacent material pillars 40a and to cover the gate dielectric layer 60 on top of the material pillars 40a (the sacrificial layer 70 also covers the area outside the source structure 30, i.e., the sacrificial layer 70 covers the entire surface of the device); the material of the sacrificial layer 70 may include silicon nitride, but is not limited to this material.

[0068] Execution step S5: Please refer to Figure 6The etching process removes a portion of the sacrificial layer 70 between two adjacent material pillars 40a to form several first openings 71. Since the channel layer 50 and gate dielectric layer 60 also cover the source structure 30 when forming the first openings 71, a portion of the channel layer 50 and a portion of the gate dielectric layer 60 on the source structure 30 between two adjacent material pillars 40a are also etched away to expose the source structure 30. This results in the bottom of the first opening 71 extending to the surface of the source structure 30, meaning the bottom of the first opening 71 exposes the source structure 30, and the sidewalls of the first opening 71 retain the sacrificial layer 70. Please refer to [reference needed]. Figure 7 , Figure 7 for Figure 6 This is a top view. Figure 6 for Figure 7 A cross-sectional view along section line A1A2 is shown. To clearly illustrate the sacrificial layer 70 covering the material column 40a, in... Figure 7 The channel layer and gate dielectric layer are not fully shown in the figure, and the transparency of the sacrificial layer 70 is set. After etching part of the sacrificial layer 70, part of the channel layer and part of the gate dielectric layer to expose the source structure (source semiconductor layer 34), a number of first openings 71 are formed. The first openings 71 are strip-shaped and extend along the second direction D2 and are arranged along the first direction D1. The first openings 71 span multiple drain structures and the area outside the drain structures (the area outside the drain structures can be an isolation material layer).

[0069] Further, please refer to Figure 8 The sacrificial layer 70 on the gate dielectric layer 60 at the top of the material pillar 40a is etched away, so that the top of the sacrificial layer 70 is flush (approximately flush) with the surface of the gate dielectric layer 60 at the top of the material pillar 40a.

[0070] Execution step S6: Please refer to Figure 9 A first isolation material layer 81 is formed to fill the first opening 71, and the first isolation material layer 81 covers the material pillar 40a and the retained sacrificial layer 70 (not shown in the figure); a polishing process is performed to polish away part of the first isolation material layer 81, part of the sacrificial layer 70, and the gate dielectric layer 60 and channel layer 50 at the top of the material pillar 40a, exposing the top of the material pillar 40a after polishing, and the top of the first isolation material layer 81 is flush with the top of the material pillar 40a; the material of the first isolation material layer 81 may include one of low-k dielectric materials, oxides, nitrides, oxynitrides and silicon oxynitride, and is not limited to the above materials.

[0071] Execution step S7: Please refer to Figure 9 and Figure 10The remaining sacrificial layer 70 is etched away to form several second openings 72 (the area where the sacrificial layer 70 is located becomes the second opening 72), and the second openings 72 expose the gate dielectric layer 60.

[0072] Execution step S8: Please refer to Figure 11 A gate structure 90 is formed to fill the second opening. A channel layer 50 and a gate dielectric layer 60 are located between the gate structure 90 and the source structure 30. The portion of the gate structure 90 located between two adjacent material pillars 40a along the first direction D1 serves as a gate substructure. Please refer to... Figure 12 , Figure 12 for Figure 11 Top view, Figure 11 for Figure 12 A cross-sectional view along section line A1A2. Figure 12 Transparency is set for the gate structure 90 and the first isolation material layer 81. Figure 12 The dashed box in the diagram selectively illustrates a portion of the gate structure 90 located between two adjacent material pillars 40a along the first direction D1 as a gate substructure. The gate structure 90 extends along the second direction D2 and is arranged along the first direction D1. The material of the gate structure 90 may include TiN or W, but is not limited to these materials; and the gate structure 90 may be a metal stack.

[0073] Further, please refer to Figure 13 The gate structure 90, with a portion of its thickness removed by etching, is such that the top of the gate structure 90 after etching is lower than the top of the material pillar 40a (the top of the gate structure 90 after etching may be higher than the top of the second material layer 42), and a third opening 73 is formed at the top of the gate structure 90. Please refer to [reference needed]. Figure 14 The second insulating material layer 82 is formed to fill the third opening, and the top of the second insulating material layer 82 is flush with the top of the material pillar 40a. The material of the second insulating material layer 82 may include one of the following: low-k dielectric material, oxide, nitride, oxynitride and silicon oxynitride, and is not limited to the above materials.

[0074] Execution step S9: Please refer to Figure 15A drain structure 100 is formed above the gate structure 90 and contacts the channel layer 50. Each drain structure 100 covers a material pillar 40a and covers two adjacent gate substructures. The drain structure 100 includes a drain barrier layer 101 and a drain metal layer 102 stacked sequentially from bottom to top. The material of the drain barrier layer 101 may include TiN, and the material of the drain metal layer 102 may include W, but is not limited to these materials. Furthermore, a third isolation material layer 83 is formed between adjacent drain structures 100. The material of the third isolation material layer 83 may include one of low-k dielectric materials, oxides, nitrides, oxynitrides, and silicon oxynitride, but is not limited to these materials. Please refer to [reference needed]. Figure 16 , Figure 16 for Figure 15 Top view, Figure 15 for Figure 16 A cross-sectional view along section line A1A2. Figure 16 For the purpose of illustrating the gate structure 90, the second isolation material layer on the gate structure 90 is not shown. Figure 16 The gate structure 90, drain structure 100, and third isolation material layer 83 are given transparency to illustrate the obscured material pillars 40a. Each drain structure 100 covers one material pillar 40a, and each drain structure 100 covers two adjacent gate substructures. Figure 16 As shown in the dashed box, the drain structure 100 covers the gate substructure on both sides of the material pillar 40a along the first direction D1.

[0075] In this embodiment, a complete material pillar 40a is first formed, comprising a first material layer 41, a second material layer 42, and a third material layer 43 stacked sequentially from bottom to top. Then, a channel layer 50 and a gate dielectric layer 60 are formed to cover the material pillar 40a. A sacrificial layer 70 is then used to form a first opening 71 and a second opening 72. A first isolation material layer 81 is formed to fill the first opening 71, and a gate structure 90 is formed to fill the second opening 72. At this point, the gate structure 90 is in direct contact with the gate dielectric layer 60, which avoids etching at the interface between the gate structure 90 and the gate dielectric layer 60, thereby ensuring the quality of the gate structure 90 and the integrity of the interface between the gate structure 90 and the gate dielectric layer 60. The device exhibits high reliability. Furthermore, the presence of a channel layer 50 and a gate dielectric layer 60 between the gate structure 90 and the source structure 30 allows for the formation of high resistance and maintains good isolation between them. In typical fabrication processes, the gate structure is formed first, followed by the formation of vias within the gate structure and subsequent filling to form material pillars. Alternatively, partial material pillars are formed first, followed by filling to form complete material pillars. The filling method can easily lead to void defects in the material pillars, affecting device reliability. In this embodiment, three material layers are formed first, followed by etching to form a complete material pillar 40a. Therefore, void defects in the material pillar 40a are avoided when using the filling method, thus improving device reliability.

[0076] This embodiment also provides a semiconductor device, which is fabricated using the semiconductor device fabrication method described above. Please refer to... Figure 15 and Figure 16 The semiconductor device provided in this embodiment includes: a substrate 10, a plurality of material pillars 40a, a channel layer 50, a gate dielectric layer 60, a gate structure 90, and a drain structure 100. A source structure 30 is formed on the substrate 10, extending along a first direction D1. In this embodiment, the source structure 30 includes a first source barrier layer 31, a source metal layer 32, a second source barrier layer 33, and a source semiconductor layer 34 stacked sequentially from bottom to top. In this embodiment, a dielectric layer 20 is also formed on the substrate 10, located between the substrate 10 and the source structure 30. An electrical connector 22 is formed in the dielectric layer 20, penetrating the dielectric layer 20 and electrically connected to the substrate 10 and the source structure 30.

[0077] Multiple material pillars 40a are located on the source structure 30 (specifically on the source semiconductor layer 34), and the multiple material pillars 40a are arranged along the first direction D1. The material pillars 40a include a first material layer 41, a second material layer 42, and a third material layer 43 stacked sequentially from bottom to top, with the surface of the source structure 30 exposed between adjacent material pillars 40a. In this embodiment, the first material layer 41, the second material layer 42, and the third material layer 43 respectively include a semiconductor material, a dielectric material, and a semiconductor material; or, the first material layer 41, the second material layer 42, and the third material layer 43 respectively include a barrier material, a semiconductor material, and a semiconductor material, and the doping concentration of the semiconductor material in the second material layer 42 is greater than the doping concentration of the semiconductor material in the third material layer 43; wherein the semiconductor material may include amorphous silicon, the dielectric material may include silicon oxide, and the barrier material may include titanium nitride, and is not limited to the above materials.

[0078] The channel layer 50 is located on the sidewall of the material pillar 40a and part of the source structure 30. Figure 16 The channel layer is not fully shown in the top view. The gate dielectric layer 60 is located on the channel layer 50 and surrounds the material pillar 40a. The tops of the gate dielectric layer 60 and the channel layer 50 are flush with the top of the material pillar 40a. Figure 15 As shown in the cross-sectional schematic, the channel layer 50 and the gate dielectric layer 60 include an L-shaped structure. The gate structure 90 is located on the gate dielectric layer 60 (on the L-shaped structure). The gate structure 90 and the drain structure 30 are separated by the gate dielectric layer 60 and the channel layer 50, enabling the formation of a high resistance between the gate structure 90 and the source structure 30, maintaining good isolation. The gate structure 90 extends along the second direction D2, and includes multiple gate substructures located along the first direction D1 between two adjacent material pillars 40a. In this embodiment, the gate structure 90 includes two gate substructures located along the first direction D1 between two adjacent material pillars 40a (e.g., ...). Figure 15 (as shown in the dashed box in the figure). Furthermore, the top of the gate structure 90 is lower than the top of the material pillar 40a (the top of the gate structure 90 may be higher than the top of the second material layer 42), the second isolation material layer 82 is located above the gate structure 90, and the top of the second isolation material layer 82 is flush with the top of the material pillar 40a.

[0079] Multiple drain structures 100 are located above the gate structure 90 and the material pillar 40a, and the drain structures 100 are in contact with the channel layer 50. Each drain structure 100 covers one material pillar 40a and covers two adjacent gate substructures. Each drain structure 100 includes a drain barrier layer 101 and a drain metal layer 102 stacked from bottom to top. Furthermore, it also includes a first isolation material layer 81 and a third isolation material layer 83. The first isolation material layer 81 is disposed within the opening between the gate structures 90 covered by two adjacent drain structures 100; the third isolation material layer 83 is located between adjacent drain structures 100. For the materials of the above process layers, please refer to the description in the semiconductor device fabrication method.

[0080] Example 2

[0081] Figure 17 This is a cross-sectional schematic diagram of the semiconductor device provided in this embodiment; Figure 18 This is a top view of the semiconductor device provided in this embodiment. Figure 18 for Figure 17 Top view, Figure 17 for Figure 18 A cross-sectional view along section line A1A2. To clearly illustrate the material pillar 40a, the drain structure 100 has been made transparent. The steps of the semiconductor device fabrication method are not shown in Example 2. Please refer to... Figure 17 and Figure 18 The semiconductor device fabrication method provided in this embodiment differs from the semiconductor device fabrication method provided in Embodiment 1 in that: etching removes a portion of the sacrificial layer between two adjacent material pillars 40a to form several first openings; each drain structure 100 covers two adjacent material pillars 40a; and each drain structure 40a covers three adjacent gate substructures. Figure 18 The dashed box in the middle shows three adjacent gate substructures along the first direction D1. During fabrication, etching removes part of the sacrificial layer between two adjacent material pillars 40a to form several first openings. Specifically, each pair of material pillars 40a is treated as a group, and etching removes part of the sacrificial layer between each group of material pillars to form several first openings. The subsequently formed drain structures 100 cover the two material pillars 40a.

[0082] Please refer to Figure 17 and Figure 18The difference between the semiconductor device provided in this embodiment and the semiconductor device provided in Embodiment 1 is that: each drain structure 100 covers two adjacent material pillars 40a, and each drain structure 100 covers three adjacent gate substructures. Along the first direction D1, the three adjacent gate substructures covered by each drain structure 100 include at least two different thicknesses (thickness refers to the dimension of the gate substructure along the first direction D1; for example, the thickness of the gate substructure in the middle below the drain structure 100 can be greater than the thickness of the gate substructures at the two edges below the drain structure 100). Figure 17 From the cross-sectional schematic diagram, the gate dielectric layer 60 includes a U-shaped structure and an L-shaped structure. The U-shaped gate dielectric layer 60 is disposed between two adjacent material pillars 40a covered by each drain structure 100, and the L-shaped gate dielectric layer 60 is disposed on one side of the two adjacent material pillars 40a covered by each drain structure 100. A gate substructure is also located on the U-shaped gate dielectric layer 60 (e.g., Figure 17 (As shown in the dashed box in the middle), at least a portion of the gate dielectric layer 60 covers the two sidewalls and the bottom surface of a gate substructure.

[0083] Example 3

[0084] Figures 19-29 This is a schematic diagram of the corresponding steps in the semiconductor device fabrication method provided in this embodiment. The semiconductor device fabrication method provided in this embodiment differs from the semiconductor device fabrication method provided in Embodiment 2 in that: when forming the first opening, at least one first opening has a material pillar as a dummy structure.

[0085] The following is combined Figures 19-29 The method for fabricating the semiconductor device provided in this embodiment will be described in detail.

[0086] Execution step S1: Please refer to Figure 19 A substrate 10 is provided, on which a source structure 30 is formed, extending along a first direction D1. The source structure 30 includes a first source barrier layer 31, a source metal layer 32, a second source barrier layer 33, and a source semiconductor layer 34 stacked sequentially from bottom to top. In this embodiment, a dielectric layer 20 is also formed on the substrate 10, located between the substrate 10 and the source structure 30. An electrical connector 22 is formed in the dielectric layer 20, penetrating the dielectric layer 20 and electrically connected to the substrate 10 and the source structure 30.

[0087] Execution step S2: Please refer to Figure 19 A first material layer 41, a second material layer 42, and a third material layer 43 are sequentially formed, at least on the source structure 30; the first material layer 41, the second material layer 42, and the third material layer 43 are etched to form a plurality of material pillars 40a, exposing the surface of the source structure 30 between adjacent material pillars 40a; please refer to Figure 20 , Figure 20 for Figure 19 Top view, Figure 19 for Figure 20 The cross-sectional view along the A1A2 section line shows that multiple material pillars 40a are located on the source structure (specifically on the source semiconductor layer 34), and the multiple material pillars 40a are arranged along the first direction D1.

[0088] Execution step S3: Please refer to Figure 21 The channel layer 50 and the gate dielectric layer 60 are sequentially formed to conformally cover the material pillar 40a (covering the sidewalls and top of the material pillar 40a) and the surface of the source structure 30 between adjacent isolation pillars 40a.

[0089] Execution step S4: Please refer to Figure 21 A sacrificial layer 70 is formed to fill the space between each two adjacent material pillars 40a and to cover the gate dielectric layer 60 on top of the material pillars 40a (the sacrificial layer 70 also covers the area outside the source structure 30, i.e., the sacrificial layer 70 covers the entire surface of the device).

[0090] Execution step S5: Please refer to Figure 22 The etching process removes a portion of the sacrificial layer 70 between two adjacent material pillars 40a to form several first openings 71. Further, when forming the first openings 71, at least one first opening 71 contains a material pillar 40a as a dummy structure. Since the channel layer 50 and gate dielectric layer 60 also cover the source structure 30 when forming the channel layer 50 and gate dielectric layer 60 covering the material pillars 40a, when etching to form the first openings 71, a portion of the channel layer 50 and a portion of the gate dielectric layer 60 on the source structure 30 between two adjacent material pillars 40a are also etched away to expose the source structure 30. This causes the bottom of the first opening 71 to extend to the surface of the source structure 30, i.e., the bottom of the first opening 71 exposes the source structure 30, and the sidewalls of the first opening 71 have retained sacrificial layer 70. Please refer to [reference needed]. Figure 23 , Figure 23 for Figure 22 This is a top view. Figure 22 for Figure 23 A cross-sectional view along section line A1A2 is shown. To clearly illustrate the sacrificial layer 70 covering the material column 40a, in... Figure 7 The channel layer and gate dielectric layer are not fully shown in the figure, and the transparency of the sacrificial layer 70 is set. After etching part of the sacrificial layer 70, part of the channel layer and part of the gate dielectric layer to expose the source structure (source semiconductor layer 34), a number of first openings 71 are formed. The first openings 71 are strip-shaped and extend along the second direction D2 and are arranged along the first direction D1. The first openings 71 span multiple drain structures and the area outside the drain structures (the area outside the drain structures can be an isolation material layer).

[0091] Furthermore, the sacrificial layer 70 on the gate dielectric layer 60 at the top of the material pillar 40a is etched away, so that the top of the sacrificial layer 70 after etching is flush (approximately flush) with the surface of the gate dielectric layer 60 at the top of the material pillar 40a.

[0092] Execution step S6: Please refer to Figure 24 A first isolation material layer 81 is formed to fill the first opening 71, and the first isolation material layer 81 covers the material pillar 40a and the retained sacrificial layer 70 (not shown in the figure); a polishing process is performed to polish away part of the first isolation material layer 81, part of the sacrificial layer 70, and the gate dielectric layer 60 and channel layer 50 at the top of the material pillar 40a, exposing the top of the material pillar 40a after polishing, and the top of the first isolation material layer 81 is flush with the top of the material pillar 40a.

[0093] Execution step S7: Please refer to Figure 25 The remaining sacrificial layer 70 is etched away to form several second openings 72 (the area where the sacrificial layer 70 is located becomes the second opening 72), and the second openings 72 expose the gate dielectric layer 60.

[0094] Execution step S8: Please refer to Figure 26 A gate structure 90 is formed to fill the second opening. A channel layer 50 and a gate dielectric layer 60 are provided between the gate structure 90 and the source structure 30. The portion of the gate structure 90 located between two adjacent material pillars 40a along the first direction D1 serves as a gate substructure.

[0095] Further, please refer to Figure 27 The gate structure 90 with a portion of its thickness is etched away. After etching, the top of the gate structure 90 is lower than the top of the material pillar 40a (the top of the gate structure 90 after etching may be higher than the top of the second material layer 42), and a third opening is formed on the top of the gate structure 90. A second isolation material layer 82 is formed to fill the third opening, and the top of the second isolation material layer 82 is flush with the top of the material pillar 40a.

[0096] Execution step S9: Please refer to Figure 28 A drain structure 100 is formed above the gate structure 90, and the drain structure 100 is in contact with the channel layer 50. Each drain structure 100 covers two material pillars 40a, and each drain structure 100 covers three adjacent gate substructures. The drain structure 100 includes a drain barrier layer 101 and a drain metal layer 102 stacked sequentially from bottom to top; furthermore, a third isolation material layer 83 is formed between adjacent drain structures 100. Please refer to... Figure 29 , Figure 29 for Figure 28 Top view, Figure 28 for Figure 29 A cross-sectional view along section line A1A2. Figure 29 For the purpose of illustrating the gate structure 90, the second isolation material layer on the gate structure 90 is not shown. Figure 29 The gate structure 90, drain structure 100, and third isolation material layer 83 are given transparency to facilitate the illustration of the shielded material pillars 40a. Each drain structure 100 covers two material pillars 40a, and each drain structure 100 covers three adjacent gate substructures. Figure 29 As shown in the dashed box, the drain structure 100 covers the gate substructures on both sides of the material pillar 40a along the first direction D1. For the material of the above-mentioned process layer, please refer to the description in the semiconductor device fabrication method of Example 1.

[0097] Please refer to Figure 28 and Figure 29 The difference between the semiconductor device provided in this embodiment and the semiconductor device provided in Embodiment 2 is that the first isolation material layer 81 also has material pillars 40a as a dummy structure. The dummy structure can uniformly distribute the pattern density, making the semiconductor device easier to fabricate.

[0098] Example 4

[0099] Figure 30 This is a top view of the semiconductor device provided in this embodiment. To clearly illustrate the material pillar 40a, the drain structure 100 has been made transparent. The step-by-step diagrams of the semiconductor device fabrication method are not shown in Embodiment 4. Please refer to... Figure 30 The semiconductor device fabrication method provided in this embodiment differs from the semiconductor device fabrication method provided in Embodiment 3 in that: multiple material pillars 40a are formed, and the multiple material pillars 40a are also located in the region outside the source structure 30. The material pillars 40a located in the region outside the source structure 30 serve as dummy structures. Increasing the dummy structures can further uniformly distribute the pattern density, making the semiconductor device easier to fabricate.

[0100] Please refer to Figure 30 The difference between the semiconductor device provided in this embodiment and the semiconductor device provided in Embodiment 3 is that: multiple material pillars 40a are also located in the region outside the source structure 30, and the material pillars 40a located in the region outside the source structure 30 are used as dummy structures.

[0101] In summary, in the semiconductor device and its fabrication method provided by this invention, a complete material pillar is first formed, then a channel layer and a gate dielectric layer are formed to cover the material pillar. After a series of fabrications to form a second opening, a gate structure is formed to fill the second opening. This avoids etching effects on the gate structure, thereby ensuring the quality of the gate structure and the interface integrity between the gate structure and the gate dielectric layer, thus improving the reliability of the device. Furthermore, the presence of a channel layer and a gate dielectric layer between the gate structure and the source structure enables the formation of a high resistance between the gate structure and the source structure, maintaining good isolation. Moreover, forming a complete material pillar first avoids the formation of void defects in the material pillar when using a filling method to form the material pillar, thus improving the reliability of the device.

[0102] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided on which a source structure is formed, the source structure extending along a first direction; Multiple material pillars are formed, and at least part of the multiple material pillars are located on the source structure; A channel layer and a gate dielectric layer are sequentially formed to cover the material pillar, and the gate dielectric layer is disposed around the material pillar; A sacrificial layer is formed between each two adjacent material columns; Etching removes a portion of the sacrificial layer between two or more adjacent material pillars to form a plurality of first openings, the bottom of the first openings exposing the source structure, and the sidewalls of the first openings having retained sacrificial layers. A first insulating material layer is formed to fill the first opening; Etching removes the remaining sacrificial layer to form a plurality of second openings, the second openings exposing the gate dielectric layer; A gate structure is formed to fill the second opening, wherein the gate structure and the source structure have the channel layer and the gate dielectric layer between them, and the portion of the gate structure located between two adjacent material pillars along the first direction serves as a gate substructure; and... A drain structure is formed above the gate structure, and the drain structure is in contact with the channel layer.

2. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The material column comprises a first material layer, a second material layer, and a third material layer stacked sequentially from bottom to top, and the steps for forming the material column include: The first material layer, the second material layer, and the third material layer are sequentially formed, with at least one layer located on the source structure. The first material layer, the second material layer, and the third material layer are etched to form a plurality of material pillars.

3. The method for fabricating a semiconductor device as described in claim 2, characterized in that, The first material layer, the second material layer, and the third material layer respectively comprise a semiconductor material, a dielectric material, and a semiconductor material; or, the first material layer, the second material layer, and the third material layer respectively comprise a barrier material, a semiconductor material, and a semiconductor material, and the doping concentration of the semiconductor material in the second material layer is greater than the doping concentration of the semiconductor material in the third material layer.

4. The method for fabricating a semiconductor device as described in claim 1, characterized in that, Each of the drain structures covers one of the material pillars or two adjacent material pillars.

5. The method for fabricating a semiconductor device as described in claim 4, characterized in that, Each of the drain structures covers two adjacent gate substructures or three adjacent gate substructures.

6. The method for fabricating a semiconductor device as described in claim 1, characterized in that, When the channel layer and the gate dielectric layer are formed to cover the material pillars, the channel layer and the gate dielectric layer also cover the source structure; when etching to form the first opening, a portion of the channel layer and a portion of the gate dielectric layer on the source structure between two or more adjacent material pillars are also etched away to expose the source structure.

7. The method for fabricating a semiconductor device as described in claim 1, characterized in that, When the first isolation material layer is formed to fill the first opening, the first isolation material layer also covers the material pillar and the retained sacrificial layer; after the first isolation material layer is formed to fill the first opening, the first isolation material layer with a portion of its thickness is removed by a grinding process, as well as the channel layer and the gate dielectric layer at the top of the material pillar.

8. The method for fabricating a semiconductor device as described in claim 1, characterized in that, When the first opening is formed, at least one of the first openings has a material column as a dummy structure.

9. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The material pillar is also located in a region outside the source structure, and the material pillar located in the region outside the source structure is a dummy structure.

10. A semiconductor device, characterized in that, include: A substrate on which an active electrode structure is formed, the active electrode structure extending along a first direction; Multiple material pillars, at least partially located on the source structure, are arranged along the first direction; The channel layer is located on the sidewall of the material pillar and on part of the source structure; A gate dielectric layer is located on the channel layer and surrounds the material pillar; A gate structure is located on the gate dielectric layer, the gate structure comprising a plurality of gate substructures located between two adjacent material pillars along the first direction; Multiple drain structures are located above the gate structure and at least a portion of the material pillars; The process involves first forming the material pillar, then forming the channel layer and the gate dielectric layer to cover the material pillar, and finally forming the gate structure in contact with the gate dielectric layer.

11. The semiconductor device as claimed in claim 10, characterized in that, The material pillar comprises a first material layer, a second material layer, and a third material layer stacked sequentially from bottom to top, wherein the first material layer, the second material layer, and the third material layer respectively comprise a semiconductor material, a dielectric material, and a semiconductor material; Alternatively, the first material layer, the second material layer, and the third material layer may each comprise a barrier material, a semiconductor material, and a semiconductor material, respectively, and the doping concentration of the semiconductor material in the second material layer may be greater than the doping concentration of the semiconductor material in the third material layer.

12. The semiconductor device as claimed in claim 10, characterized in that, Each of the drain structures covers two adjacent material pillars.

13. The semiconductor device as claimed in claim 12, characterized in that, Each of the drain structures covers the three adjacent gate substructures.

14. The semiconductor device as claimed in claim 10, characterized in that, It also includes a first isolation material layer, which is disposed in the opening between the gate structures respectively covered by the two adjacent drain structures, and the first isolation material layer also has material pillars as dummy structures.

15. The semiconductor device as claimed in claim 12, characterized in that, The gate dielectric layer includes a U-shaped structure and an L-shaped structure, wherein the gate dielectric layer of the U-shaped structure is disposed between two adjacent material pillars covered by each of the drain structures.

16. The semiconductor device as claimed in claim 15, characterized in that, The gate substructure is also located on the gate dielectric layer of the U-shaped structure.

17. The semiconductor device as claimed in claim 10, characterized in that, At least a portion of the gate dielectric layer covers the two sidewalls and the bottom surface of the gate substructure.

18. The semiconductor device as claimed in claim 13, characterized in that, The three adjacent gate substructures covered by each of the drain structures along the first direction include at least two different thicknesses.

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