A circular Schottky barrier thin film transistor and a method for manufacturing the same

Abstract

The present application provides a circular Schottky barrier thin film transistor and a preparation method thereof, relating to the field of semiconductor technology. The present application sequentially prepares a circular gate layer, a gate dielectric layer, a circular semiconductor layer, a circular barrier control layer, a source layer with a circular boundary contour, a passivation layer, a drain wiring layer, and a source wiring layer electrically connected to the source layer on a substrate, wherein the gate layer, the semiconductor layer, the barrier control layer, and the source layer coincide with the center of the circle, the conductive film layer portion of the semiconductor layer not covered by the source layer and the barrier control layer will be electrically connected to the drain wiring layer as a drain region, the source layer is in direct contact with a portion of the semiconductor film layer portion of the semiconductor layer to form an ohmic (quasi-ohmic) contact, and the barrier control layer is separated from another portion of the semiconductor film layer portion to form a Schottky barrier.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a circular Schottky barrier thin film transistor and a method for preparing the same. Background Art

[0002] With the continuous development of technology, Schottky barrier metal oxide thin film transistors (SBMO-TFTs) have gradually attracted more attention due to their excellent intrinsic electrical properties. Compared with ordinary metal oxide thin film transistors, SBMO-TFTs generally have the advantages of high intrinsic gain, low power consumption, significantly reduced short channel effect, better device stability, and stable current output characteristics after saturation. Therefore, SBMO-TFTs are suitable for application in high-pixel density AMLCDs (active matrix liquid crystal displays), AMOLEDs (active matrix organic light-emitting diode displays), Mini-LED (mini light-emitting diode) display devices, Micro-LED (micro light-emitting diode) display devices and other current-driven display devices or low-power integrated circuits. They are also suitable for use in the construction of dynamic random access memory (DRAM).

[0003] In the actual application process of SBMO-TFT, SBMO-TFT is often required to have a higher saturation output current. The SBMO-TFT architecture currently adopted by the industry is a rectangular TFT architecture (that is, the source electrode and drain electrode of the corresponding SBMO-TFT are both rectangular and parallel to each other in a top-down perspective, and the rectangular semiconductor layer between the source electrode and the drain electrode is the device channel). It is usually necessary to introduce a barrier control layer between the source electrode and the semiconductor layer along the vertical direction of the architecture, so that a part of the source electrode is directly in contact with the semiconductor layer to form an ohmic contact or a quasi-ohmic contact, and the other part of the source electrode is separated by the barrier control layer to form a Schottky contact with the semiconductor layer, so as to ensure that the SBMO-TFT can have a higher saturation output current by simultaneously realizing ohmic contact and Schottky barrier contact at the source electrode, wherein the length of the semiconductor layer within the coverage of the barrier control layer determines the size of the saturation output current of the corresponding SBMO-TFT.

[0004] However, it is worth noting that this SBMO-TFT preparation scheme often causes inter-layer alignment deviation problems because the barrier control layer and the source layer belong to different film layers. As a result, the length of the semiconductor layer covered by the barrier control layer varies between different finished products of the same SBMO-TFT prepared on a large scale, resulting in obvious differences in device electrical characteristics between different finished products of the same SBMO-TFT. Summary of the Invention

[0005] In view of this, the purpose of the present application is to provide a circular Schottky barrier thin film transistor and a preparation method thereof, which can utilize the circular TFT architecture to ensure that the prepared Schottky barrier thin film transistor maintains the device electrical characteristics of a high saturation output current while adaptively compensating the output current for the inter-layer alignment deviation through the prepared circular ring-shaped depletion region, so that the total channel length difference between different finished products of the corresponding Schottky barrier thin film transistor is greatly reduced, so as to minimize the uniformity interference caused by the inter-layer alignment deviation on the device electrical characteristics, improve the uniformity of the device electrical characteristics of the corresponding Schottky barrier thin film transistor during large-scale preparation, and facilitate further expansion of the application field of the corresponding Schottky barrier thin film transistor.

[0006] In order to achieve the above objectives, the technical solutions adopted in the embodiments of the present application are as follows:

[0007] In a first aspect, the present application provides a method for preparing a circular Schottky barrier thin film transistor, the method comprising:

[0008] providing a substrate;

[0009] A gate layer, a gate dielectric layer, and a semiconductor layer are sequentially stacked on one side of the substrate to obtain a first-stage device, wherein the gate dielectric layer covers the gate layer, the projection area of ​​the semiconductor layer on the substrate is within the projection area of ​​the gate layer on the substrate, and the projection areas corresponding to the semiconductor layer and the gate layer are both circular and have the same center;

[0010] A barrier control layer and a source layer are stacked on the semiconductor layer included in the first-stage device to obtain a second-stage device, wherein the projection area of ​​the barrier control layer on the substrate is annular and is located within the projection area corresponding to the semiconductor layer; the source layer covers the first outer surface or the second outer surface of the semiconductor layer not covered by the barrier control layer, and at least partially covers the barrier control layer, wherein the projection area of ​​the first outer surface on the substrate is located inside the projection area of ​​the second outer surface on the substrate, the boundary outline of the projection area of ​​the source layer on the substrate is circular, and the centers of the projection areas corresponding to the semiconductor layer, the barrier control layer and the source layer coincide with each other;

[0011] Conducting a portion of the semiconductor layer included in the second-stage device that is not covered by the source layer and the barrier control layer to divide the semiconductor layer into a conductive film layer portion and a semiconductor film layer portion, and depositing a passivation layer on the outer surface of the second-stage device away from the substrate, wherein the conductive film layer portion is used as the drain region of the circular Schottky barrier thin-film transistor, the source layer is in direct contact with the semiconductor film layer portion to form an ohmic contact or a quasi-ohmic contact, the source layer is separated from the barrier control layer and the semiconductor film layer portion to form a Schottky barrier, and a portion of the semiconductor film layer portion adjacent to the barrier control layer forms a circular depletion region;

[0012] A source wiring layer electrically connected to the source layer and a drain wiring layer electrically connected to the conductive film layer are formed on the outer surface of the passivation layer away from the substrate.

[0013] In an optional embodiment, the step of sequentially stacking a gate layer, a gate dielectric layer, and a semiconductor layer on one side of the substrate to obtain a first-stage device includes:

[0014] forming a gate layer by sputtering deposition on one side surface of the substrate, and performing photolithographic patterning on the deposited gate layer so that the projected area of ​​the gate layer on the substrate is smaller than the side area of ​​the substrate used for forming the gate layer, and the projected area of ​​the gate layer on the substrate is circular;

[0015] On the side of the substrate where the gate layer is formed, growing the gate dielectric layer based on plasma enhanced chemical vapor deposition or atomic layer deposition, so that the gate dielectric layer covers the outer surface of the gate layer away from the substrate and the side area of ​​the substrate not blocked by the gate layer;

[0016] On the outer surface of the gate dielectric layer away from the substrate, the semiconductor layer is deposited based on the magnetron sputtering method or the atomic layer deposition method, and the deposited semiconductor layer is photolithographically patterned so that the projection area of ​​the semiconductor layer on the substrate is circular and coincides with the center of the projection area corresponding to the gate layer, and the diameter of the projection area of ​​the semiconductor layer is smaller than the diameter of the projection area of ​​the gate layer, thereby obtaining the first stage device.

[0017] In an optional embodiment, if the source layer covers the first outer surface and at least partially covers the barrier control layer, the step of stacking the barrier control layer and the source layer on the semiconductor layer included in the first-stage device to obtain the second-stage device includes:

[0018] Depositing the barrier control layer on the outer surface of the first-stage device away from the substrate based on magnetron sputtering, plasma-enhanced chemical vapor deposition, or atomic layer deposition, and performing a hole-opening process on the deposited barrier control layer to form a source circular hole on the barrier control layer that partially exposes the semiconductor layer, wherein the projection outline of the source circular hole on the substrate coincides with the center of the projection area corresponding to the semiconductor layer;

[0019] sputtering and depositing the source layer on the outer surface of the barrier control layer away from the first-stage device, and performing photolithographic patterning on the deposited source layer so that the projection area of ​​the source layer on the substrate is circular and coincides with the center of the projection area corresponding to the semiconductor layer, and the diameter of the projection area of ​​the source layer is smaller than the diameter of the projection area of ​​the semiconductor layer;

[0020] Under the shielding effect of the source layer, the barrier control layer is photolithographically patterned so that the projection area of ​​the barrier control layer on the substrate is a circular ring and coincides with the center of the projection area corresponding to the semiconductor layer, and the outer diameter of the projection area of ​​the barrier control layer is greater than or equal to the diameter of the projection area of ​​the source layer, thereby obtaining a second-stage device, wherein the outer diameter of the projection area of ​​the barrier control layer is smaller than the diameter of the projection area of ​​the semiconductor layer.

[0021] In an optional embodiment, if the source layer covers the second outer surface and at least partially covers the barrier control layer, the step of stacking the barrier control layer and the source layer on the semiconductor layer included in the first-stage device to obtain the second-stage device includes:

[0022] Depositing the barrier control layer on the outer surface of the first-stage device away from the substrate based on magnetron sputtering, plasma-enhanced chemical vapor deposition, or atomic layer deposition, and photolithographically patterning the deposited barrier control layer so that the projection area of ​​the barrier control layer on the substrate is circular and coincides with the center of the projection area corresponding to the semiconductor layer, and the diameter of the projection area of ​​the barrier control layer is smaller than the diameter of the projection area of ​​the semiconductor layer;

[0023] The source layer is formed by sputtering and depositing on the outer surface of the barrier control layer prepared in the first stage of the device, and the deposited source layer is patterned by photolithography, so that the projection area of ​​the source layer on the substrate is annular and coincides with the center of the projection area corresponding to the semiconductor layer, and the outer diameter of the projection area of ​​the source layer is larger than the diameter of the projection area of ​​the semiconductor layer but smaller than the diameter of the projection area of ​​the gate layer;

[0024] Under the shielding effect of the source layer, the barrier control layer is photolithographically patterned again, so that the projection area of ​​the barrier control layer on the substrate becomes a circular ring and coincides with the center of the projection area corresponding to the semiconductor layer, and the inner diameter of the projection area of ​​the barrier control layer is smaller than or equal to the inner diameter of the projection area of ​​the source layer, thereby obtaining the second-stage device.

[0025] In an optional embodiment, the step of conducting the film portion of the semiconductor layer included in the second-stage device that is not covered by the source layer and the barrier control layer includes:

[0026] Using argon plasma to bombard the film portion of the semiconductor layer that is not covered by the source layer and the barrier control layer, so as to convert the bombarded film portion with semiconductor characteristics into the conductive film portion, wherein the material of the passivation layer includes at least silicon nitride material and silicon dioxide material;

[0027] Alternatively, the step of conducting the film portion of the semiconductor layer included in the second-stage device that is not covered by the source layer and the barrier control layer includes:

[0028] A passivation layer is deposited directly on the outer surface of the second-stage device away from the substrate using at least silicon nitride material and silicon dioxide material, and the passivation layer is annealed so that the film layer portion of the semiconductor layer that is in direct contact with the passivation layer is conductive under the action of hydrogen diffusion doping of the passivation layer, thereby converting the film layer portion of the semiconductor layer that is in direct contact with the passivation layer and has semiconductor properties into the conductive film layer portion.

[0029] In an optional embodiment, the gate layer, the source wiring layer, and the drain wiring layer are each made of any one of Al, Cu, Mo, Ti, and ITO;

[0030] The material of the semiconductor layer is any one of InGaZnO, InZnO, InZnSnO, Ln-IZO, InGaO, ZnO, Ga2O3 and SnO2, and the material of the source layer is any one of Cu, Mo, Au, Ni, W, Cr, Pt, Au, Pd and ITO, wherein the work function of the source layer is greater than the work function of the semiconductor layer;

[0031] The gate dielectric layer is made of a stack of one or more materials selected from SiO2 and silicon nitride;

[0032] The material of the barrier control layer is any one of SiO2, Al2O3, HfO2, and ZrO2.

[0033] In an optional embodiment, the gate layer has a thickness ranging from 10 to 1000 nm;

[0034] The thickness of the gate dielectric layer is in the range of 5-500 nm;

[0035] The thickness of the semiconductor layer is in the range of 5-100 nm;

[0036] The actual thickness of the barrier control layer is less than or equal to 10 nm;

[0037] The thickness of the passivation layer is in the range of 10-1000 nm.

[0038] In a second aspect, the present application provides a circular Schottky barrier thin film transistor, comprising:

[0039] substrate;

[0040] A gate layer, a gate dielectric layer, and a semiconductor layer are sequentially stacked on one side of the substrate, wherein the gate dielectric layer covers the gate layer, a projection area of ​​the semiconductor layer on the substrate is within a projection area of ​​the gate layer on the substrate, and the projection areas corresponding to the semiconductor layer and the gate layer are both circular and have the same center;

[0041] a barrier control layer and a source layer sequentially stacked on the semiconductor layer, wherein the projection area of ​​the barrier control layer on the substrate is annular and is located within the projection area corresponding to the semiconductor layer; the source layer covers the first outer surface or the second outer surface of the semiconductor layer not covered by the barrier control layer and at least partially covers the barrier control layer; wherein the projection area of ​​the first outer surface on the substrate is located inside the projection area of ​​the second outer surface on the substrate; the boundary outline of the projection area of ​​the source layer on the substrate is circular; and the centers of the projection areas corresponding to the semiconductor layer, the barrier control layer, and the source layer coincide with each other;

[0042] a passivation layer covering and encapsulating the gate dielectric layer, the semiconductor layer, the source layer, and the barrier control layer, wherein the semiconductor layer includes a conductive film layer portion and a semiconductor film layer portion, the conductive film layer portion being the film layer portion of the semiconductor layer not covered by the source layer and the barrier control layer, the conductive film layer portion being used as the drain region of the circular Schottky barrier thin-film transistor, the source layer being in direct contact with the semiconductor film layer portion to form an ohmic contact or a quasi-ohmic contact, the source layer being separated from the barrier control layer and the semiconductor film layer portion to form a Schottky barrier, and a portion of the semiconductor film layer portion adjacent to the barrier control layer forming a circular depletion region;

[0043] A source wiring layer and a drain wiring layer are formed on the outer surface of the passivation layer away from the substrate, wherein the source wiring layer is electrically connected to the source layer through a hole, and the drain wiring layer is electrically connected to the conductive film layer through a hole.

[0044] In an optional embodiment, when the source layer covers the first outer surface and at least partially covers the barrier control layer, the projection area of ​​the source layer on the substrate is circular, the projection area diameter of the source layer is smaller than the projection area diameter of the semiconductor layer, the projection area outer diameter of the barrier control layer is greater than or equal to the projection area diameter of the source layer, and the projection area outer diameter of the barrier control layer is smaller than the projection area diameter of the semiconductor layer.

[0045] In an optional embodiment, when the source layer covers the second outer surface and at least partially covers the barrier control layer, the outer diameter of the projected area of ​​the barrier control layer is smaller than the diameter of the projected area of ​​the semiconductor layer, the projected area of ​​the source layer on the substrate is annular, the outer diameter of the projected area of ​​the source layer is larger than the diameter of the projected area of ​​the semiconductor layer, the outer diameter of the projected area of ​​the source layer is smaller than the diameter of the projected area of ​​the gate layer, and the inner diameter of the projected area of ​​the barrier control layer is smaller than or equal to the inner diameter of the projected area of ​​the source layer.

[0046] In this case, the beneficial effects of the embodiments of the present application may include the following:

[0047] The present application sequentially prepares a circular gate layer, a gate dielectric layer, a circular semiconductor layer, a circular barrier control layer, a source layer with a circular boundary contour, a passivation layer, a drain wiring layer and a source wiring layer electrically connected to the source layer on a substrate, so that the projection area of ​​the semiconductor layer on the substrate is within the projection area of ​​the gate layer on the substrate, and the gate layer, the semiconductor layer, the barrier control layer and the center of the source layer coincide with each other. At this time, the conductive film layer portion of the semiconductor layer not covered by the source layer and the barrier control layer can be used as a drain region and electrically connected to the drain wiring layer, and the source layer can directly contact part of the semiconductor film layer portion of the semiconductor layer to form an ohmic contact or a quasi-ohmic contact. At the same time, the source layer will also separate the barrier control layer and part of the semiconductor film layer portion to form a Schottky barrier, so that part of the semiconductor film layer portion adjacent to the barrier control layer can form a circular depletion region, so that in the corresponding Schottky During the large-scale preparation of base barrier thin-film transistors, the prepared annular depletion region is used to adaptively compensate for the output current for the inter-layer alignment deviation (that is, the channel length on one side of the annular depletion region in the radial direction becomes longer (shorter), so that the current at the channel on this side decreases (increases), while the channel length on the other side of the annular depletion region in the radial direction becomes shorter (longer), so that the current at the channel on this side increases (decreases), thereby reducing the difference in saturated output current between different Schottky barrier thin-film transistor products), so that the total channel length difference between different finished products of the corresponding Schottky barrier thin-film transistors is greatly reduced, thereby minimizing the uniformity interference of the device electrical characteristics caused by the inter-layer alignment deviation, improving the uniformity of the device electrical characteristics of the corresponding Schottky barrier thin-film transistor during large-scale preparation, and facilitating further expansion of the application field of the corresponding Schottky barrier thin-film transistor.

[0048] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0050] Figure 1 This is a schematic diagram of the composition of a circular Schottky barrier thin film transistor provided in an embodiment of the present application;

[0051] Figure 2 for Figure 1 A bird's-eye view of the stacking diagram of the gate layer, semiconductor layer, source layer, source wiring layer, and drain wiring layer;

[0052] Figure 3 The second schematic diagram of the composition of the circular Schottky barrier thin film transistor provided in an embodiment of the present application;

[0053] Figure 4 for Figure 3 A bird's-eye view of the stacking diagram of the gate layer, semiconductor layer, source layer, source wiring layer, and drain wiring layer;

[0054] Figure 5 A schematic flow chart of a method for preparing a Schottky barrier thin film transistor according to an embodiment of the present application;

[0055] Figure 6 for Figure 5 A schematic flow chart of the sub-steps included in step S220;

[0056] Figure 7 A schematic diagram of the fabrication of a first-stage device according to an embodiment of the present application;

[0057] Figure 8 for Figure 5 One of the flowcharts of the sub-steps included in step S230;

[0058] Figure 9 This is one of the schematic diagrams for manufacturing the second-stage device provided in the embodiment of the present application;

[0059] Figure 10 for Figure 5 2 is a flow chart of the sub-steps included in step S230;

[0060] Figure 11 This is the second schematic diagram of the fabrication of the second-stage device provided in the embodiment of the present application.

[0061] Icon: 10-circular Schottky barrier thin film transistor; 11-substrate; 12-gate layer; 13-gate dielectric layer; 14-semiconductor layer; 15-barrier control layer; 16-source layer; 141-conductive film layer portion; 142-semiconductor film layer portion; 17-passivation layer; 18-source wiring layer; 19-drain wiring layer; 143-depletion region. DETAILED DESCRIPTION

[0062] To make the objectives, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Generally, the components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations.

[0063] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for protection, but merely represents selected embodiments of the present application. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments in the present application without creative work are within the scope of protection of the present application.

[0064] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not require further definition or explanation in subsequent drawings.

[0065] In the description of this application, it should be understood that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, or are the orientation or position relationship in which the product of the application is usually placed when in use, or are the orientation or position relationship commonly understood by those skilled in the art. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0066] It should also be noted that, in the description of this application, unless otherwise expressly specified or limited, the terms "disposed," "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0067] In addition, in the description of the present application, it is also understood that relational terms such as the terms "first" and "second" are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also include elements inherent to such process, method, article or equipment. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or equipment comprising the elements. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

[0068] The following describes some embodiments of the present application in detail with reference to the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments may be combined with each other.

[0069] Please refer to Figure 1 , Figure 1 This is one of the schematic diagrams of the composition of the circular Schottky barrier thin film transistor 10 provided in the embodiment of the present application. In the embodiment of the present application, the circular Schottky barrier thin film transistor 10 can use the TFT circular architecture to form an ohmic (quasi-ohmic) contact and a Schottky contact at the source to ensure that the corresponding Schottky barrier thin film transistor can maintain the device electrical characteristics of a high saturation output current. At the same time, the circular TFT architecture is used to construct a circular depletion region, so that during the large-scale production of transistors, the circular depletion region can be used to adaptively compensate for the output current of the inter-layer alignment deviation that occurs, so that the total channel length difference between different Schottky barrier thin film transistor products is greatly reduced, thereby improving the uniformity interference caused by the inter-layer alignment deviation on the device electrical characteristics, improving the uniformity of the device electrical characteristics of the corresponding Schottky barrier thin film transistor during large-scale production, and facilitating the further expansion of the application field of the corresponding Schottky barrier thin film transistor. Among them, the total channel length of a single Schottky barrier thin film transistor product is the sum of the channel lengths on both sides of the circular depletion region of the corresponding Schottky barrier thin film transistor product in the radial direction.

[0070] In an embodiment of the present application, the circular Schottky barrier thin film transistor 10 may include a substrate 11, a gate layer 12, a gate dielectric layer 13 and a semiconductor layer 14, a barrier control layer 15, a source layer 16, a passivation layer 17, a source wiring layer 18 and a drain wiring layer 19.

[0071] In this embodiment, the gate layer 12, the gate dielectric layer 13, and the semiconductor layer 14 are sequentially stacked on one side of the substrate 11. The gate dielectric layer 13 covers the outer surface of the gate layer 12 away from the substrate 11, and the side area of ​​the substrate 11 on which the gate layer 12 is prepared that is not blocked by the gate layer 12; the projected area of ​​the gate layer 12 on the substrate 11 is smaller than the side area of ​​the substrate 11 on which the gate layer 12 is prepared, and the projected area of ​​the gate layer 12 on the substrate 11 is circular (refer to Figure 2 Schematic diagram of the gate layer 12 in a bird's-eye view); the projection area of ​​the semiconductor layer 14 on the substrate 11 is circular, and the centers of the projection areas of the semiconductor layer 14 and the gate layer 12 coincide with each other, and the diameter of the projection area of ​​the semiconductor layer 14 is smaller than the diameter of the projection area of ​​the gate layer 12, so that the projection area of ​​the semiconductor layer 14 on the substrate 11 is within the projection area of ​​the gate layer 12 on the substrate 11.

[0072] In this embodiment, the barrier control layer 15 and the source layer 16 are sequentially stacked on the outer surface of the semiconductor layer 14 away from the substrate 11. The projection area of ​​the barrier control layer 15 on the substrate 11 is annular, and the centers of the projection areas of the semiconductor layer 14 and the barrier control layer 15 coincide with each other, and the outer diameter of the projection area of ​​the barrier control layer 15 is smaller than the diameter of the projection area of ​​the semiconductor layer 14, so that the projection area corresponding to the barrier control layer 15 is within the projection area corresponding to the semiconductor layer 14; the source layer 16 covers the first outer surface of the semiconductor layer 14 that is not covered by the barrier control layer 15, and at least partially covers the barrier control layer 15, wherein the first outer surface is the surface area where the center of the side surface of the semiconductor layer 14 is located and not covered by the barrier control layer 15. At this time, the projection area of ​​the source layer 16 on the substrate 11 is circular (refer to Figure 2 ), the boundary contour of the projection area of ​​the source layer 16 on the substrate 11 is circular and the number of corresponding boundary contours is only one, the center of the projection area corresponding to the source layer 16 and the semiconductor layer 14 coincides, and the diameter of the projection area of ​​the source layer 16 is smaller than the diameter of the projection area of ​​the semiconductor layer 14.

[0073] In this embodiment, the semiconductor layer 14 may include a conductive film layer portion 141 and a semiconductor film layer portion 142. The conductive film layer portion 141 is a conductive film layer portion of the semiconductor layer 14, and the semiconductor film layer portion 142 is a film layer portion of the semiconductor layer 14 having semiconductor properties. The conductive film layer portion 141 is a film layer portion of the semiconductor layer 14 that is not covered by the source layer 16 and the barrier control layer 15. Figure 1 The projection area of ​​the conductive film layer portion 141 on the substrate 11 is the projection area of ​​the second outer surface of the semiconductor layer 14 on the substrate 11. The projection areas of the conductive film layer portion 141 and the barrier control layer 15 coincide with each other. The projection area corresponding to the conductive film layer portion 141 is annular (refer to Figure 2 Schematic diagram of the conductive film layer portion 141 in a bird's-eye view), the conductive film layer portion 141 can serve as the drain region of the circular Schottky barrier thin film transistor 10, wherein the second outer surface is all outer surfaces of the semiconductor layer 14 other than the first outer surface that are not covered by the barrier control layer 15, and the projection area of ​​the first outer surface on the substrate 11 is located inside the projection area of ​​the second outer surface on the substrate 11; Figure 1The projection area of ​​the semiconductor film layer portion 142 on the substrate 11 is circular, and a portion of the source layer 16 is in direct contact with a portion of the semiconductor film layer portion 142 to form an ohmic contact or a quasi-ohmic contact. At the same time, another portion of the source layer 16 is separated from the barrier control layer 15 and forms a Schottky barrier (i.e., Schottky contact) with the remaining area of ​​the semiconductor film layer portion 142. At this time, the barrier height of the Schottky barrier can be regulated by the barrier control layer 15 so that the corresponding adjusted barrier height is greater than or equal to 0.4 eV. At the same time, a portion of the semiconductor film layer portion 142 adjacent to the barrier control layer 15 will form a circular depletion region 143, wherein Figure 1 When the circular Schottky barrier thin film transistor 10 shown in FIG. 1 is operating in a saturated state, the annular depletion region 143 extends from the side where the source layer 16 realizes ohmic (quasi-ohmic) contact to the side where the drain region is located, and reaches the interface between the semiconductor layer 14 and the gate dielectric layer 13 on the drain region side (refer to FIG. Figure 1 The expansion distribution of the depletion region 143 in the annular depletion region 143 is calculated to achieve a pinch-off effect of the channel. At this time, the total channel length of the annular depletion region 143 is the sum of the left channel length d1 and the right channel length d2 of the annular depletion region 143 in the radial direction, so that the output current is adaptively compensated for the inter-layer alignment deviation that occurs during the large-scale preparation of transistors through the annular depletion region 143 (that is, the left channel length of the annular depletion region 143 in the radial direction becomes longer (shorter), and the right channel length of the annular depletion region 143 in the radial direction becomes shorter (longer), thereby reducing the difference in saturated output current between different Schottky barrier thin film transistor products, thereby greatly reducing the difference in the total channel length between different Schottky barrier thin film transistor products, thereby improving the uniformity interference of the inter-layer alignment deviation on the device electrical characteristics, and improving the uniformity of the device electrical characteristics of the corresponding Schottky barrier thin film transistor during large-scale preparation.

[0074] In this embodiment, the passivation layer 17 is used to cover and encapsulate the gate dielectric layer 13, the semiconductor layer 14, the source layer 16 and the barrier control layer 15. A first via and a second via are provided on the passivation layer 17. The first via partially exposes the source layer 16, and the second via partially exposes the conductive film layer portion 141. The source wiring layer 18 is electrically connected to the source layer 16 via the first via, and the drain wiring layer 19 is electrically connected to the conductive film layer portion 141 via the second via. In one implementation of this embodiment, the projection areas of the source wiring layer 18 and the drain wiring layer 19 on the substrate 11 are both rectangular (refer to Figure 2 Schematic diagram of the source wiring layer 18 and the drain wiring layer 19 in FIG. 1 from a bird's-eye view).

[0075] Therefore, the present application can use the TFT circular structure to form an ohmic (quasi-ohmic) contact and a Schottky contact at the source to ensure that the corresponding Schottky barrier thin-film transistor can maintain the device electrical characteristics of a high saturation output current. At the same time, the TFT circular structure is used to construct a circular depletion region, so that during the large-scale preparation of transistors, the output current is adaptively compensated for the inter-layer alignment deviation that occurs through the circular depletion region, so that the total channel length difference between different Schottky barrier thin-film transistor products is greatly reduced, thereby improving the uniformity interference caused by the inter-layer alignment deviation on the device electrical characteristics, and improving the uniformity of the device electrical characteristics of the corresponding Schottky barrier thin-film transistor during large-scale preparation, so as to further expand the application field of the corresponding Schottky barrier thin-film transistor.

[0076] In the embodiment of the present application, the work function of the source layer 16 is greater than the work function of the semiconductor layer 14 so that a Schottky barrier between the source layer 16 adjacent to the barrier control layer 15 and the semiconductor layer 14 can be normally generated.

[0077] In the embodiment of the present application, the gate layer 12, the source wiring layer 18, and the drain wiring layer 19 are generally made of the same material, and the thickness of the gate layer 12 is in the range of 10-1000 nm. In one implementation of the present embodiment, the material of each of the gate layer 12, the source wiring layer 18, and the drain wiring layer 19 is any one of Al, Cu, Mo, Ti, and ITO.

[0078] In an embodiment of the present application, the material of the semiconductor layer 14 is any one of InGaZnO, InZnO, InZnSnO, Ln-IZO, InGaO, ZnO, Ga2O3 and SnO2, and the thickness range of the semiconductor layer 14 is 5-100nm; the material of the source layer 16 is any one of Cu, Mo, Au, Ni, W, Cr, Pt, Au, Pd, and ITO.

[0079] In the embodiment of the present application, the substrate 11 can be a rigid substrate such as glass or silicon, or a flexible polymer substrate such as polyimide or polyethylene naphthalate. It is understood that the actual type of the substrate 11 includes but is not limited to the aforementioned examples, and any material that can serve as a substrate for a metal oxide thin film transistor device falls within the scope of protection of the present application.

[0080] In the embodiment of the present application, the material of the gate dielectric layer 13 is a stack of any one or more materials selected from SiO 2 and silicon nitride, and the thickness of the gate dielectric layer 13 is in the range of 5-500 nm.

[0081] In the embodiment of the present application, the material of the barrier control layer 15 is any one of SiO 2 , Al 2 O 3 , HfO 2 , and ZrO 2 , and the actual thickness of the barrier control layer 15 is less than or equal to 10 nm.

[0082] In the embodiment of the present application, the material of the passivation layer 17 includes at least one of a silicon nitride material and a silicon dioxide material, and the thickness of the passivation layer 17 ranges from 10 nm to 1000 nm. Specifically, when the passivation layer 17 is formed using silicon nitride and silicon dioxide materials, the passivation layer 17 can be formed by stacking an oxide layer formed using silicon dioxide and a silicon nitride layer formed using silicon nitride, wherein the silicon nitride layer is disposed on a side of the oxide layer away from the semiconductor layer 14.

[0083] Alternatively, see Figure 3 , Figure 3 This is the second schematic diagram of the composition of the circular Schottky barrier thin film transistor 10 provided in the embodiment of the present application. Figure 1 Compared with the circular Schottky barrier thin film transistor 10 shown, Figure 3 The circular Schottky barrier thin film transistor 10 shown is relatively Figure 1 The main difference between the circular Schottky barrier thin film transistor 10 shown is that the source layer 16 covers the second outer surface of the semiconductor layer 14 that is not covered by the barrier control layer 15, and the source layer 16 at least partially covers the barrier control layer 15, and the projection area of ​​the conductive film layer part 141 on the substrate 11 is the projection area of ​​the first outer surface of the semiconductor layer 14 on the substrate 11.

[0084] Specifically, in the embodiments of the present application, Figure 3 The projection area of ​​the source layer 16 on the substrate 11 in the circular Schottky barrier thin film transistor 10 shown is annular (refer to Figure 4 The outer diameter of the projected area of ​​the source layer 16 is larger than the diameter of the projected area of ​​the semiconductor layer 14, the outer diameter of the projected area of ​​the source layer 16 is smaller than the diameter of the projected area of ​​the gate layer 12, the inner diameter of the projected area of ​​the barrier control layer 15 is smaller than or equal to the inner diameter of the projected area of ​​the source layer 16, wherein the boundary contour of the projected area of ​​the source layer 16 on the substrate 11 is circular and the number of corresponding boundary contours is two.

[0085] In the embodiments of this application, Figure 3 The conductive film portion 141 and the barrier control layer 15 have their respective projection area centers coincident, and the projection area corresponding to the conductive film portion 141 is circular (refer to Figure 4Schematic diagram of the conductive film layer portion 141 in a bird's-eye view), the conductive film layer portion 141 can serve as the drain region of the circular Schottky barrier thin film transistor 10; Figure 3 The projection area of ​​the semiconductor film layer part 142 on the substrate 11 is a circular ring, and a part of the source layer 16 is in direct contact with a part of the semiconductor film layer part 142 to form an ohmic contact or a quasi-ohmic contact. At the same time, another part of the source layer 16 is separated from the barrier control layer 15 and the remaining area of ​​the semiconductor film layer part 142 to form a Schottky barrier (i.e., Schottky contact). At this time, the barrier height of the Schottky barrier can be controlled by the barrier control layer 15, so that the corresponding adjusted barrier height is greater than or equal to 0.4 eV. At the same time, the part of the semiconductor film layer part 142 adjacent to the barrier control layer 15 will form a circular ring-shaped depletion region 143.

[0086] in, Figure 3 When the circular Schottky barrier thin film transistor 10 shown in FIG. 1 is operating in a saturated state, the annular depletion region 143 extends from the side where the source layer 16 realizes ohmic (quasi-ohmic) contact to the side where the drain region is located, and reaches the interface between the semiconductor layer 14 and the gate dielectric layer 13 on the drain region side (refer to FIG. Figure 3 The expansion distribution of the depletion region 143 in the annular depletion region 143 is calculated to achieve a pinch-off effect of the channel. At this time, the total channel length of the annular depletion region 143 is the sum of the left channel length d1 and the right channel length d2 of the annular depletion region 143 in the radial direction, so that the output current is adaptively compensated for the inter-layer alignment deviation that occurs during the large-scale preparation of transistors through the annular depletion region 143 (that is, the left channel length of the annular depletion region 143 in the radial direction becomes longer (shorter), and the right channel length of the annular depletion region 143 in the radial direction becomes shorter (longer), thereby reducing the difference in saturated output current between different Schottky barrier thin film transistor products, thereby greatly reducing the difference in the total channel length between different Schottky barrier thin film transistor products, thereby improving the uniformity interference of the inter-layer alignment deviation on the device electrical characteristics, and improving the uniformity of the device electrical characteristics of the corresponding Schottky barrier thin film transistor during large-scale preparation.

[0087] In this application, to ensure Figure 1 or Figure 3 The circular Schottky barrier thin film transistor 10 shown can be prepared and formed quickly and orderly to improve the uniformity interference caused by inter-layer alignment deviation on the electrical characteristics of the device with high saturation output current, improve the uniformity of the device electrical characteristics during large-scale preparation of transistors, and facilitate further expansion of the application field of the corresponding Schottky barrier thin film transistor. The embodiment of the present application achieves the above-mentioned function by providing a preparation method of a circular Schottky barrier thin film transistor.

[0088] Please refer to Figure 5 , Figure 5 FIG2 is a flow chart of a method for preparing a Schottky barrier thin film transistor according to an embodiment of the present application. In the embodiment of the present application, the preparation method may include steps S210 to S250.

[0089] Step S210: providing a substrate.

[0090] In step S220 , a gate layer, a gate dielectric layer, and a semiconductor layer are sequentially stacked on one side of the substrate to obtain a first-stage device.

[0091] In this embodiment, the gate dielectric layer 13 in the first-stage device covers the gate layer 12, and the projection area of ​​the semiconductor layer 14 in the first-stage device on the substrate 11 is within the projection area of ​​the gate layer 12 on the substrate 11. The projection areas corresponding to the semiconductor layer 14 and the gate layer 12 are both circular and their centers coincide.

[0092] Optionally, please refer to Figure 6 and Figure 7 ,in Figure 6 yes Figure 5 Schematic diagram of the flow of sub-steps included in step S220, Figure 7 Schematic diagram of the fabrication of a first-stage device according to an embodiment of the present application. In the embodiment of the present application, step S220 may include sub-steps S221 to S223 to prepare a first-stage device in which both the gate layer 12 and the semiconductor layer 14 are rounded.

[0093] In sub-step S221, a gate layer is formed by sputtering deposition on one side surface of the substrate, and the deposited gate layer is photolithographically patterned so that the projected area of ​​the gate layer on the substrate is smaller than the side area of ​​the substrate used to prepare the gate layer, and the projected area of ​​the gate layer on the substrate is circular.

[0094] in, Figure 7 (a) is a schematic diagram of a device in which a circular gate layer 12 is prepared on one surface of the substrate 11 .

[0095] In sub-step S222, a gate dielectric layer is grown on the side of the substrate on which the gate layer is prepared based on plasma enhanced chemical vapor deposition or atomic layer deposition, so that the gate dielectric layer covers the outer surface of the gate layer away from the substrate and the side area of ​​the substrate not blocked by the gate layer.

[0096] in, Figure 7 (b) is a schematic diagram of a device in which the gate dielectric layer 13 is grown on the side of the substrate 11 on which the gate layer 12 is formed.

[0097] In sub-step S223, a semiconductor layer is deposited on the outer surface of the gate dielectric layer away from the substrate based on a magnetron sputtering method or an atomic layer deposition method, and the deposited semiconductor layer is photolithographically patterned so that the projection area of ​​the semiconductor layer on the substrate is circular and coincides with the center of the projection area corresponding to the gate layer, and the diameter of the projection area of ​​the semiconductor layer is smaller than the diameter of the projection area of ​​the gate layer, thereby obtaining a first-stage device.

[0098] in, Figure 7 (c) is a schematic diagram of a device in which a circular semiconductor layer 14 is prepared on the outer surface of the gate dielectric layer 13 away from the substrate 11. Figure 7 The device structure shown in (c) is the first-stage device.

[0099] Therefore, the present application can prepare a first-stage device in which both the gate layer 12 and the semiconductor layer 14 are rounded by executing the above sub-steps S221 to S223.

[0100] In step S230 , a barrier control layer and a source layer are stacked on the semiconductor layer included in the first-stage device to obtain a second-stage device.

[0101] In this embodiment, the projection area of ​​the barrier control layer 15 in the second-stage device on the substrate 11 is annular and is within the projection area corresponding to the semiconductor layer 14. The source layer 16 in the second-stage device covers the first outer surface or the second outer surface of the semiconductor layer 14 that is not covered by the barrier control layer 15, and at least partially covers the barrier control layer 15. The boundary outline of the projection area of ​​the source layer 16 on the substrate 11 is circular, and the centers of the projection areas corresponding to the semiconductor layer 14, the barrier control layer 15 and the source layer 16 coincide with each other.

[0102] Optionally, please refer to Figure 8 and Figure 9 ,in Figure 8 yes Figure 5 One of the flowcharts of the sub-steps included in step S230, Figure 9 This is one of the schematic diagrams for fabricating a second-stage device provided in an embodiment of the present application. In this embodiment of the present application, when the source layer 16 is required to cover the first outer surface and at least partially cover the barrier control layer 15, step S230 may include sub-steps S231 to S233 to prepare a second-stage device in which the first outer surface is covered by the source layer 16.

[0103] In sub-step S231, a barrier control layer is deposited on the outer surface of the device away from the substrate in the first stage based on magnetron sputtering, plasma enhanced chemical vapor deposition or atomic layer deposition, and the deposited barrier control layer is subjected to a hole-opening process to form a source circular hole that partially exposes the semiconductor layer on the barrier control layer, wherein the projection outline of the source circular hole on the substrate coincides with the center of the projection area corresponding to the semiconductor layer.

[0104] in, Figure 9 (a) is a schematic diagram of a device in which a barrier control layer 15 having a source circular hole in the form of a complete film layer is prepared on the first-stage device.

[0105] In sub-step S232, a source layer is formed by sputtering deposition on the outer surface of the barrier control layer away from the first-stage device, and the deposited source layer is photolithographically patterned so that the projection area of ​​the source layer on the substrate is circular and coincides with the center of the projection area corresponding to the semiconductor layer, and the projection area diameter of the source layer is smaller than the projection area diameter of the semiconductor layer.

[0106] in, Figure 9 (b) is a schematic diagram of a device in which a circular source layer 16 is prepared on the outer surface of the barrier control layer 15 away from the first-stage device. In one implementation of this embodiment, a photoresist layer can be spin-coated on the outer surface of the newly deposited source layer 16 away from the barrier control layer 15, and the photoresist layer can be patterned so that the projection area of ​​the patterned photoresist layer on the substrate 11 is circular and coincides with the center of the projection area corresponding to the semiconductor layer 14, and the projection area diameter of the patterned photoresist layer is ensured to be smaller than the projection area diameter of the semiconductor layer 14. Then, under the shielding effect of the patterned photoresist layer, the local area of ​​the source layer 16 not covered by the photoresist layer is etched to ensure that the projection area of ​​the source layer 16 finally etched on the substrate 11 is circular and coincides with the center of the projection area corresponding to the semiconductor layer 14, and the projection area diameter of the source layer 16 is smaller than the projection area diameter of the semiconductor layer 14.

[0107] In sub-step S233, under the shielding effect of the source layer 16, the barrier control layer is photolithographically patterned so that the projection area of ​​the barrier control layer on the substrate is a circular ring and coincides with the center of the projection area corresponding to the semiconductor layer, and the outer diameter of the projection area of ​​the barrier control layer is greater than or equal to the diameter of the projection area of ​​the source layer, thereby obtaining a second-stage device, wherein the outer diameter of the projection area of ​​the barrier control layer is smaller than the diameter of the projection area of ​​the semiconductor layer.

[0108] in, Figure 9(c) is a schematic diagram of a device in which the barrier control layer 15 is circularized under the shielding effect of the source layer 16 or the patterned photoresist layer on the source layer 16. Figure 9 The device structure shown in (c) is a second-stage device corresponding to the first outer surface being covered by the source layer 16. In one implementation of this embodiment, under the shielding effect of the source layer 16 or the patterned photoresist layer on the source layer 16, dry etching can be used to remove all local areas of the barrier control layer 15 not covered by the photoresist layer or the source layer 16 to complete the circularization effect of the barrier control layer 15. Then, acetone can be used to remove the patterned photoresist layer to obtain the second semiconductor device.

[0109] Therefore, the present application can prepare a second-stage device whose corresponding first outer surface is covered by the source layer 16 by executing the above sub-steps S231 to S233.

[0110] Optionally, please refer to Figure 10 and Figure 11 ,in Figure 10 yes Figure 5 The second flowchart of the sub-steps included in step S230 is as follows: Figure 11 This is the second schematic diagram of the second-stage device fabrication provided in an embodiment of the present application. In this embodiment of the present application, when the source layer 16 is required to cover the second outer surface and at least partially cover the barrier control layer 15, step S230 may include sub-steps S235 to S237 to fabricate a second-stage device in which the second outer surface is covered by the source layer 16.

[0111] In sub-step S235, a barrier control layer is deposited on the outer surface of the first-stage device away from the substrate based on a magnetron sputtering method, a plasma-enhanced chemical vapor deposition method or an atomic layer deposition method, and the deposited barrier control layer is photolithographically patterned so that the projection area of ​​the barrier control layer on the substrate is circular and coincides with the center of the projection area corresponding to the semiconductor layer, and the diameter of the projection area of ​​the barrier control layer is smaller than the diameter of the projection area of ​​the semiconductor layer.

[0112] in, Figure 11 (a) is a schematic diagram of a device in which a circular barrier control layer 15 is prepared on the first-stage device.

[0113] In sub-step S236, a source layer is formed by sputtering deposition on the outer surface of the barrier control layer prepared in the first stage of the device, and the deposited source layer is photolithographically patterned so that the projection area of ​​the source layer on the substrate is a circular ring and coincides with the center of the projection area corresponding to the semiconductor layer, and the outer diameter of the projection area of ​​the source layer is larger than the diameter of the projection area of ​​the semiconductor layer but smaller than the diameter of the projection area of ​​the gate layer.

[0114] in, Figure 11 (b) is a schematic diagram of a device in which a circular source layer 16 is prepared on the outer surface of the barrier control layer 15 away from the first-stage device. In one implementation of this embodiment, a photoresist layer can be spin-coated on the outer surface of the newly deposited source layer 16 away from the barrier control layer 15, and the photoresist layer can be patterned so that the projection area of ​​the patterned photoresist layer on the substrate 11 is circular and coincides with the center of the projection area corresponding to the semiconductor layer 14, and ensures that the projection area of ​​the patterned photoresist layer is larger than the projection area diameter of the semiconductor layer 14 but smaller than the projection area diameter of the gate layer 12. Then, under the shielding effect of the patterned photoresist layer, the local area of ​​the source layer 16 not covered by the photoresist layer is etched to ensure that the projection area of ​​the source layer 16 finally etched on the substrate 11 is circular and coincides with the center of the projection area corresponding to the semiconductor layer 14, and at the same time, the outer diameter of the projection area of ​​the source layer 16 is larger than the projection area diameter of the semiconductor layer 14 but smaller than the projection area diameter of the gate layer 12.

[0115] In sub-step S237, under the shielding effect of the source layer, the barrier control layer is again photolithographically patterned so that the projection area of ​​the barrier control layer on the substrate becomes a circular ring and coincides with the center of the projection area corresponding to the semiconductor layer, and the inner diameter of the projection area of ​​the barrier control layer is smaller than or equal to the inner diameter of the projection area of ​​the source layer, thereby obtaining a second-stage device.

[0116] in, Figure 11 (c) is a schematic diagram of a device in which the barrier control layer 15 is circularized under the shielding effect of the source layer 16 or the patterned photoresist layer on the source layer 16. Figure 11 The device structure shown in (c) is a second-stage device corresponding to the second outer surface covered by the source layer 16. In one implementation of this embodiment, under the shielding effect of the source layer 16 or the patterned photoresist layer on the source layer 16, dry etching can be used to remove all local areas of the barrier control layer 15 not covered by the photoresist layer or the source layer 16 to complete the circularization effect of the barrier control layer 15. Then, acetone can be used to remove the patterned photoresist layer to obtain the second semiconductor device.

[0117] Therefore, the present application can prepare a second-stage device whose corresponding second outer surface is covered by the source layer 16 by executing the above sub-steps S231 to S233.

[0118] In step S240, the film layer portion of the semiconductor layer included in the second-stage device that is not covered by the source layer and the barrier control layer is conductively processed to divide the semiconductor layer into a conductive film layer portion and a semiconductor film layer portion, and a passivation layer is deposited on the outer surface of the second-stage device away from the substrate.

[0119] In this embodiment, the conductive film layer portion 141 is used as the drain region of the circular Schottky barrier thin film transistor 10, the source layer 16 is in direct contact with the semiconductor film layer portion 142 to form an ohmic contact or a quasi-ohmic contact, the source layer 16 separates the barrier control layer 15 and the semiconductor film layer portion 142 to form a Schottky barrier, and the partial area of ​​the semiconductor film layer portion 142 adjacent to the barrier control layer 15 forms a circular depletion region 143.

[0120] In one implementation of this embodiment, the step of “conducting the film portion of the semiconductor layer 14 included in the second-stage device that is not covered by the source layer 16 and the barrier control layer 15 ” in step S240 may include:

[0121] Argon plasma is used to bombard the film portion of the semiconductor layer 14 that is not covered by the source layer 16 and the barrier control layer 15 , so as to convert the bombarded film portion with semiconductor characteristics into the conductive film portion 141 .

[0122] On this basis, the material used for the corresponding passivation layer 17 includes at least silicon nitride material and silicon dioxide material. When the corresponding passivation layer 17 is formed by using silicon nitride material and silicon dioxide material, the passivation layer 17 can be formed by stacking an oxide layer formed by using silicon dioxide material and a silicon nitride layer formed by using silicon nitride material, wherein the silicon nitride layer is arranged on the side of the oxide layer away from the semiconductor layer 14.

[0123] In another implementation of this embodiment, the step of “conducting the film portion of the semiconductor layer 14 included in the second-stage device that is not covered by the source layer 16 and the barrier control layer 15 ” in step S240 may include:

[0124] A passivation layer 17 is deposited directly on the outer surface of the second-stage device away from the substrate 11 using at least silicon nitride material and silicon dioxide material, and the passivation layer 17 is annealed so that the film layer portion of the semiconductor layer 14 that is in direct contact with the passivation layer 17 is conductive under the action of hydrogen diffusion doping of the passivation layer 17, thereby converting the film layer portion of the semiconductor layer 14 that is in direct contact with the passivation layer 17 and has semiconductor properties into the conductive film layer portion 141.

[0125] Among them, the portion of the film layer that is in direct contact with the passivation layer 17 is the portion of the film layer that is not covered by the source layer 16 and the barrier control layer 15; when the corresponding passivation layer 17 is prepared by using silicon nitride material and silicon dioxide material, the passivation layer 17 can be formed by stacking an oxide layer formed by using silicon dioxide material and a silicon nitride layer formed by using silicon nitride material, wherein the silicon nitride layer is arranged on the side of the oxide layer away from the semiconductor layer 14.

[0126] In step S250 , a source wiring layer electrically connected to the source layer and a drain wiring layer electrically connected to the conductive film layer are formed on the outer surface of the passivation layer away from the substrate.

[0127] In this embodiment, the passivation layer 17 can be subjected to a hole-forming process to form a first via hole for partially exposing the source layer 16 and a second via hole for partially exposing the conductive film layer portion 141 on the passivation layer 17. Then, an electrode film layer is sputter-deposited on the side of the passivation layer 17 away from the substrate 11 with the hole formed therein using the same or different material as the gate layer 12. The electrode film layer is then wet-etched to form a source wiring layer 18 and a drain wiring layer 19 that are not connected to each other, so that the source wiring layer 18 can be directly electrically connected to the source layer 16 through the first via hole, and the drain wiring layer 19 can be directly electrically connected to the conductive film layer portion 141 serving as the drain region through the second via hole.

[0128] Therefore, this application can ensure that the above steps S210 to S250 are executed. Figure 1 or Figure 3 The circular Schottky barrier thin film transistor 10 shown can be prepared and formed quickly and orderly to improve the uniformity interference caused by inter-layer alignment deviation on the electrical characteristics of the device with high saturation output current, improve the uniformity of the device electrical characteristics during large-scale preparation of transistors, and facilitate further expansion of the application field of the corresponding Schottky barrier thin film transistor.

[0129] The above are merely various embodiments of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A method for preparing a circular Schottky barrier thin film transistor, characterized in that: The preparation method comprises: providing a substrate; A gate layer, a gate dielectric layer, and a semiconductor layer are sequentially stacked on one side of the substrate to obtain a first-stage device, wherein the gate dielectric layer covers the gate layer, the projection area of ​​the semiconductor layer on the substrate is within the projection area of ​​the gate layer on the substrate, and the projection areas corresponding to the semiconductor layer and the gate layer are both circular and have the same center; A barrier control layer and a source layer are stacked on the semiconductor layer included in the first-stage device to obtain a second-stage device, wherein the projection area of ​​the barrier control layer on the substrate is annular and is located within the projection area corresponding to the semiconductor layer; the source layer covers the first outer surface or the second outer surface of the semiconductor layer not covered by the barrier control layer, and at least partially covers the barrier control layer, wherein the projection area of ​​the first outer surface on the substrate is located inside the projection area of ​​the second outer surface on the substrate, the boundary outline of the projection area of ​​the source layer on the substrate is circular, and the centers of the projection areas corresponding to the semiconductor layer, the barrier control layer and the source layer coincide with each other; Conducting a portion of the semiconductor layer included in the second-stage device that is not covered by the source layer and the barrier control layer to divide the semiconductor layer into a conductive film layer portion and a semiconductor film layer portion, and depositing a passivation layer on the outer surface of the second-stage device away from the substrate, wherein the conductive film layer portion is used as the drain region of the circular Schottky barrier thin-film transistor, the source layer is in direct contact with the semiconductor film layer portion to form an ohmic contact or a quasi-ohmic contact, the source layer is separated from the barrier control layer and the semiconductor film layer portion to form a Schottky barrier, and a portion of the semiconductor film layer portion adjacent to the barrier control layer forms a circular depletion region; A source wiring layer electrically connected to the source layer and a drain wiring layer electrically connected to the conductive film layer are formed on the outer surface of the passivation layer away from the substrate.

2. The preparation method according to claim 1, characterized in that The step of sequentially stacking a gate layer, a gate dielectric layer, and a semiconductor layer on one side of the substrate to obtain a first-stage device comprises: forming a gate layer by sputtering deposition on one side surface of the substrate, and performing photolithographic patterning on the deposited gate layer so that the projected area of ​​the gate layer on the substrate is smaller than the side area of ​​the substrate used for forming the gate layer, and the projected area of ​​the gate layer on the substrate is circular; On the side of the substrate where the gate layer is formed, growing the gate dielectric layer based on plasma enhanced chemical vapor deposition or atomic layer deposition, so that the gate dielectric layer covers the outer surface of the gate layer away from the substrate and the side area of ​​the substrate not blocked by the gate layer; On the outer surface of the gate dielectric layer away from the substrate, the semiconductor layer is deposited based on the magnetron sputtering method or the atomic layer deposition method, and the deposited semiconductor layer is photolithographically patterned so that the projection area of ​​the semiconductor layer on the substrate is circular and coincides with the center of the projection area corresponding to the gate layer, and the diameter of the projection area of ​​the semiconductor layer is smaller than the diameter of the projection area of ​​the gate layer, thereby obtaining the first stage device.

3. The preparation method according to claim 1, characterized in that If the source layer covers the first outer surface and at least partially covers the barrier control layer, the step of stacking the barrier control layer and the source layer on the semiconductor layer included in the first-stage device to obtain the second-stage device includes: Depositing the barrier control layer on the outer surface of the first-stage device away from the substrate based on magnetron sputtering, plasma-enhanced chemical vapor deposition, or atomic layer deposition, and performing a hole-opening process on the deposited barrier control layer to form a source circular hole on the barrier control layer that partially exposes the semiconductor layer, wherein the projection outline of the source circular hole on the substrate coincides with the center of the projection area corresponding to the semiconductor layer; sputtering and depositing the source layer on the outer surface of the barrier control layer away from the first-stage device, and performing photolithographic patterning on the deposited source layer so that the projection area of ​​the source layer on the substrate is circular and coincides with the center of the projection area corresponding to the semiconductor layer, and the diameter of the projection area of ​​the source layer is smaller than the diameter of the projection area of ​​the semiconductor layer; Under the shielding effect of the source layer, the barrier control layer is photolithographically patterned so that the projection area of ​​the barrier control layer on the substrate is a circular ring and coincides with the center of the projection area corresponding to the semiconductor layer, and the outer diameter of the projection area of ​​the barrier control layer is greater than or equal to the diameter of the projection area of ​​the source layer, thereby obtaining a second-stage device, wherein the outer diameter of the projection area of ​​the barrier control layer is smaller than the diameter of the projection area of ​​the semiconductor layer.

4. The preparation method according to claim 1, characterized in that If the source layer covers the second outer surface and at least partially covers the barrier control layer, the step of stacking the barrier control layer and the source layer on the semiconductor layer included in the first-stage device to obtain the second-stage device includes: Depositing the barrier control layer on the outer surface of the first-stage device away from the substrate based on magnetron sputtering, plasma-enhanced chemical vapor deposition, or atomic layer deposition, and photolithographically patterning the deposited barrier control layer so that the projection area of ​​the barrier control layer on the substrate is circular and coincides with the center of the projection area corresponding to the semiconductor layer, and the diameter of the projection area of ​​the barrier control layer is smaller than the diameter of the projection area of ​​the semiconductor layer; The source layer is formed by sputtering and depositing on the outer surface of the barrier control layer prepared in the first stage of the device, and the deposited source layer is patterned by photolithography, so that the projection area of ​​the source layer on the substrate is annular and coincides with the center of the projection area corresponding to the semiconductor layer, and the outer diameter of the projection area of ​​the source layer is larger than the diameter of the projection area of ​​the semiconductor layer but smaller than the diameter of the projection area of ​​the gate layer; Under the shielding effect of the source layer, the barrier control layer is photolithographically patterned again, so that the projection area of ​​the barrier control layer on the substrate becomes a circular ring and coincides with the center of the projection area corresponding to the semiconductor layer, and the inner diameter of the projection area of ​​the barrier control layer is smaller than or equal to the inner diameter of the projection area of ​​the source layer, thereby obtaining the second-stage device.

5. The preparation method according to claim 1, characterized in that The step of conducting the film portion of the semiconductor layer included in the second-stage device that is not covered by the source layer and the barrier control layer comprises: Using argon plasma to bombard the film portion of the semiconductor layer that is not covered by the source layer and the barrier control layer, so as to convert the bombarded film portion with semiconductor characteristics into the conductive film portion, wherein the material of the passivation layer includes at least silicon nitride material and silicon dioxide material; Alternatively, the step of conducting the film portion of the semiconductor layer included in the second-stage device that is not covered by the source layer and the barrier control layer includes: A passivation layer is deposited directly on the outer surface of the second-stage device away from the substrate using at least silicon nitride material and silicon dioxide material, and the passivation layer is annealed so that the film layer portion of the semiconductor layer that is in direct contact with the passivation layer is conductive under the action of hydrogen diffusion doping of the passivation layer, thereby converting the film layer portion of the semiconductor layer that is in direct contact with the passivation layer and has semiconductor properties into the conductive film layer portion.

6. The preparation method according to any one of claims 1 to 5, characterized in that The gate layer, the source wiring layer, and the drain wiring layer are each made of any one of Al, Cu, Mo, Ti, and ITO; The material of the semiconductor layer is any one of InGaZnO, InZnO, InZnSnO, Ln-IZO, InGaO, ZnO, Ga2O3 and SnO2, and the material of the source layer is any one of Cu, Mo, Au, Ni, W, Cr, Pt, Au, Pd and ITO, wherein the work function of the source layer is greater than the work function of the semiconductor layer; The gate dielectric layer is made of a stack of one or more materials selected from SiO2 and silicon nitride; The material of the barrier control layer is any one of SiO2, Al2O3, HfO2, and ZrO2.

7. The preparation method according to any one of claims 1 to 5, characterized in that The thickness of the gate layer is in the range of 10-1000 nm; The thickness of the gate dielectric layer is in the range of 5-500 nm; The thickness of the semiconductor layer is in the range of 5-100 nm; The actual thickness of the barrier control layer is less than or equal to 10 nm; The thickness of the passivation layer is in the range of 10-1000 nm.

8. A circular Schottky barrier thin film transistor, characterized in that: The thin film transistor includes: substrate; A gate layer, a gate dielectric layer, and a semiconductor layer are sequentially stacked on one side of the substrate, wherein the gate dielectric layer covers the gate layer, a projection area of ​​the semiconductor layer on the substrate is within a projection area of ​​the gate layer on the substrate, and the projection areas corresponding to the semiconductor layer and the gate layer are both circular and have the same center; a barrier control layer and a source layer sequentially stacked on the semiconductor layer, wherein the projection area of ​​the barrier control layer on the substrate is annular and is located within the projection area corresponding to the semiconductor layer; the source layer covers the first outer surface or the second outer surface of the semiconductor layer not covered by the barrier control layer and at least partially covers the barrier control layer; wherein the projection area of ​​the first outer surface on the substrate is located inside the projection area of ​​the second outer surface on the substrate; the boundary outline of the projection area of ​​the source layer on the substrate is circular; and the centers of the projection areas corresponding to the semiconductor layer, the barrier control layer, and the source layer coincide with each other; a passivation layer covering and encapsulating the gate dielectric layer, the semiconductor layer, the source layer, and the barrier control layer, wherein the semiconductor layer includes a conductive film layer portion and a semiconductor film layer portion, the conductive film layer portion being the film layer portion of the semiconductor layer not covered by the source layer and the barrier control layer, the conductive film layer portion being used as the drain region of the circular Schottky barrier thin-film transistor, the source layer being in direct contact with the semiconductor film layer portion to form an ohmic contact or a quasi-ohmic contact, the source layer being separated from the barrier control layer and the semiconductor film layer portion to form a Schottky barrier, and a portion of the semiconductor film layer portion adjacent to the barrier control layer forming a circular depletion region; A source wiring layer and a drain wiring layer are formed on the outer surface of the passivation layer away from the substrate, wherein the source wiring layer is electrically connected to the source layer through a hole, and the drain wiring layer is electrically connected to the conductive film layer through a hole.

9. The thin film transistor according to claim 8, wherein: When the source layer covers the first outer surface and at least partially covers the barrier control layer, the projection area of ​​the source layer on the substrate is circular, the projection area diameter of the source layer is smaller than the projection area diameter of the semiconductor layer, the projection area outer diameter of the barrier control layer is greater than or equal to the projection area diameter of the source layer, and the projection area outer diameter of the barrier control layer is smaller than the projection area diameter of the semiconductor layer.

10. The thin film transistor according to claim 8, wherein: When the source layer covers the second outer surface and at least partially covers the barrier control layer, the outer diameter of the projection area of ​​the barrier control layer is smaller than the diameter of the projection area of ​​the semiconductor layer, the projection area of ​​the source layer on the substrate is annular, the outer diameter of the projection area of ​​the source layer is larger than the diameter of the projection area of ​​the semiconductor layer, the outer diameter of the projection area of ​​the source layer is smaller than the diameter of the projection area of ​​the gate layer, and the inner diameter of the projection area of ​​the barrier control layer is smaller than or equal to the inner diameter of the projection area of ​​the source layer.

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