An orthogonal all-pass filter with integrated load impedance matching and chip circuit

Abstract

The present invention proposes an orthogonal all-pass filter and chip circuit with integrated load impedance matching, wherein the orthogonal all-pass filter includes a differential orthogonal network structure; the orthogonal all-pass filter is provided with a positive input port Vin+, a negative input port Vin‑, positive output ports VI+, VQ+ and negative output ports VI‑, VQ‑ of an orthogonal differential signal; a fifth inductor L5 is added between the inductor L3 and the positive output port VI+; a sixth inductor L6 is added between the capacitor C3 and the negative output port VQ‑; a seventh inductor L7 is added between the capacitor C4 and the positive output port VQ+; and an eighth inductor L8 is added between the inductor L4 and the negative output port VI‑. The present invention offsets the capacitive impedance of the load end by connecting inductors in series at the four output ends, thereby achieving a pure resistance impedance matching effect.

Description

Technical Field

[0001] The invention relates to an orthogonal all-pass filter, belongs to the field of radio frequency integrated circuits, and specifically relates to an orthogonal all-pass filter with integrated load impedance matching and a chip circuit. Background Art

[0002] Radio frequency integrated circuits are the core of modern information technology and play a vital role in my country's national defense and civil construction. In recent years, with the rapid development of technologies such as the Internet of Things, big data and artificial intelligence, wireless communication technology, phased array millimeter wave technology, and radio frequency transceiver technology are undergoing a new round of technological changes. Phase shifters, as key modules, are also constantly developing in depth. Phase shifters are a control element that controls the phase change of signals. They are key modules that affect the performance of phased arrays and are an important part of phased array systems. Among them, broadband phase shifters play an even more important role in phased array radars, millimeter wave communication systems, and other aspects. Among them, the Cartesian vector synthesis active phase shifter solution is the most widely used phase shifting solution, with the advantages of large bandwidth, high phase resolution and high voltage gain. It obtains a phase response with relative accuracy by modulating orthogonal signals with varying amplitudes. For the Cartesian vector synthesis phase shifter, the four groups of orthogonal signals generated by the orthogonal all-pass filter determine its shifting accuracy. The principle is to divide the input signal into two pairs of mutually orthogonal differential signals, and change the phase of the synthetic vector by controlling the two pairs of orthogonal differential signals. Then, the phase and amplitude of the two signals are optimized and adjusted according to the shifting angle required by the phase shifter, and then the signals are synthesized to obtain the required phase output signal. The orthogonal all-pass filter plays an important role in the phased array phase shifter and directly affects the phase shifting accuracy, so it is very important to design an orthogonal all-pass filter with high-precision phase error and amplitude.

[0003] The traditional orthogonal all-pass filter has a simple structure and can achieve a wider bandwidth and better gain, but it has high requirements for the load. The traditional orthogonal all-pass filter is an asymmetric structure, and the I path and Q path are not symmetrical. For the millimeter wave frequency band, because the frequency band is higher, the requirements for the load are more sensitive; therefore, when the load impedance has an imaginary impedance, that is, a capacitive impedance, the performance of the circuit is extremely easily affected, and the phase error and amplitude error of the output signal will fluctuate greatly. Summary of the invention

[0004] Aiming at the problem that traditional orthogonal all-pass filters are sensitive to loads, the present invention proposes an orthogonal all-pass filter and a chip circuit with integrated load impedance matching to solve the shortcomings of traditional orthogonal all-pass filters in terms of load issues. The capacitive impedance of the load end is offset by connecting inductors in series at the four output ends, thereby achieving a pure resistive impedance matching effect.

[0005] The present invention adopts the following technical solutions:

[0006] In a first aspect, the present invention provides an orthogonal all-pass filter with integrated load impedance matching, comprising a differential orthogonal network structure;

[0007] The orthogonal all-pass filter is provided with a positive input port Vin+, a negative input port Vin-, a first positive output port VI+, a second positive output port VQ+, a first negative output port VI-, and a second negative output port VQ- of an orthogonal differential signal;

[0008] The differential orthogonal network structure includes a first inductor L1, a second inductor L2, a third inductor L3, a fourth inductor L4, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a first resistor R1 and a second resistor R2;

[0009] The positive input port Vin+ and the negative input port Vin- are used to be connected to the two ends of the differential input signal respectively.

[0010] The positive input port Vin+ is connected to one end of the first inductor L1 and the first capacitor C1 respectively, the other end of the first capacitor C1 is connected to the first resistor R1 and the third inductor L3 respectively, and the other end of the third inductor L3 is connected to the first positive output port VI+;

[0011] The other end of the first resistor R1 is connected to the third capacitor C3, and the other end of the third capacitor C3 is connected to the second negative output port VQ-;

[0012] The negative input port Vin- is connected to the second inductor L2 and one end of the second capacitor C2 respectively, the other end of the second capacitor C2 is connected to the second resistor R2 and the fourth inductor L4 respectively, and the other end of the fourth inductor L4 is connected to the first negative output port VI-;

[0013] The other end of the second resistor R2 is connected to the fourth capacitor C4, and the other end of the fourth capacitor C4 is connected to the second positive output port VQ+;

[0014] A fifth inductor L5 is added between the inductor L3 and the first positive output port VI+;

[0015] A sixth inductor L6 is added between the capacitor C3 and the second negative output port VQ-;

[0016] A seventh inductor L7 is added between the capacitor C4 and the second positive output port VQ+;

[0017] An eighth inductor L8 is added between the inductor L4 and the first negative output port VI-.

[0018] The effect achieved by the above setting is: by introducing four inductors L5, L6, L7 and L8, the capacitive impedance of the load end is offset by connecting the inductors in series at the four output ends, and the imaginary part of the inductor and the imaginary part of the capacitive load end are completely offset. After the capacitance and inductance are offset, only the real part of the load is left, thereby achieving the effect of a pure resistive load and obtaining ideal signal amplitude and phase results, that is, by increasing impedance matching to eliminate the imaginary part of the capacitive load impedance, the transmission of orthogonal differential signals with high-precision amplitude and phase is achieved.

[0019] Furthermore, the inductance values ​​of the fifth inductor L5 , the sixth inductor L6 , the seventh inductor L7 and the eighth inductor L8 are equal.

[0020] Further, the inductance values ​​L of the fifth inductor L5, the sixth inductor L6, the seventh inductor L7 and the eighth inductor L8 are calculated by the following formula:

[0021]

[0022] Wherein, w is the angular frequency of the orthogonal all-pass filter, C is the capacitance value equivalent to the capacitive load of the orthogonal all-pass filter, and L is the inductance value.

[0023] Furthermore, the inductance values ​​of the first inductor L1 and the second inductor L2 are the same;

[0024] The inductance values ​​of the third inductor L3 and the fourth inductor L4 are the same;

[0025] The first capacitor C1 and the second capacitor C2 have the same capacitance value;

[0026] The capacitance values ​​of the third capacitor C3 and the fourth capacitor C4 are the same;

[0027] The first resistor R1 and the second resistor R2 have the same resistance value, and R1=R2= ; L1 is the inductance value of the first inductor L1, and C1 is the capacitance value of the first capacitor.

[0028] Furthermore, the first resistor R1 and the second resistor R2 are both metal film resistors.

[0029] The first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 are all interdigital capacitors.

[0030] The first inductor L1 , the second inductor L2 , the third inductor L3 , the fourth inductor L4 , the fifth inductor L5 , the sixth inductor L6 , the seventh inductor L7 and the eighth inductor L8 are all square inductors.

[0031] Further, a ninth inductor L9 is used to replace the third inductor L3 and the fifth inductor L5; one end of the ninth inductor L9 is connected to the first capacitor C1, and the other end is connected to the first positive output port VI+;

[0032] The tenth inductor L10 is used to replace the fourth inductor L4 and the eighth inductor L8; one end of the tenth inductor L10 is connected to the second capacitor C2, and the other end is connected to the second positive output port VQ+.

[0033] The effect of the above settings is: when designing the layout, inductors L3 and L5 are combined into L9, and inductors L4 and L8 are combined into L10, so as to reduce the number of inductors, reduce the self-resonant frequency and mutual inductance coupling interference of the inductors, and improve the reliability of the circuit.

[0034] Furthermore, the inductance values ​​of the ninth inductor L9 and the tenth inductor L10 are equal.

[0035] Further, the inductance value of the ninth inductor L9 is equal to the sum of the inductance values ​​of the third inductor L3 and the fifth inductor L5;

[0036] The inductance of the tenth inductor L10 is equal to the sum of the inductances of the third inductor L3 and the fifth inductor L5.

[0037] In a second aspect, the present invention provides a chip circuit, comprising an orthogonal all-pass filter with integrated load impedance matching as described in the first aspect.

[0038] Compared with the prior art, the advantages and beneficial effects of the present invention are:

[0039] 1. The traditional orthogonal all-pass filter is an asymmetric structure, and the I path and the Q path are not symmetrical, so when the load impedance has an imaginary impedance, the performance of the circuit is extremely easily affected, and the phase and amplitude will fluctuate greatly. The present invention introduces four inductors, L5, L6, L7 and L8, and connects the inductors in series at the four output ends to offset the capacitive impedance of the load end, and the imaginary part of the inductor and the imaginary part of the capacitive load end are completely offset. After the capacitance and inductance are offset, only the real part of the load remains, thereby achieving the effect of pure resistance impedance matching, thereby achieving the effect of pure resistance load, and obtaining the ideal signal amplitude and phase results, that is, by increasing impedance matching to eliminate the imaginary part of the capacitive load impedance, the transmission of orthogonal differential signals with high-precision amplitude and phase is achieved;

[0040] 2. The present invention meets the requirements of high precision and good flatness of the phase and amplitude of the orthogonal differential signal under the same capacitive load condition;

[0041] 3. When designing the layout of the chip circuit of the present invention, L5 and L6 are merged into L9, and L7 and L8 are merged into L10 for better layout; while improving the performance index, the miniaturized design of the chip is realized to better meet the current market demand.

[0042] 4. The present invention eliminates capacitive impedance, reduces the sensitivity of the orthogonal all-pass filter to the load, and further expands the bandwidth. In practical applications, under the same capacitive load, it can ensure high precision and good stability of the phase and amplitude of the orthogonal differential signal, the IQ signal amplitude error is guaranteed to be ±2dB, and the in-band phase fluctuation does not exceed ±0.5°.

[0043] 5. The present invention can ensure high precision of the phase and amplitude of the output orthogonal differential signal under any capacitive load, and ensure good stability within the working frequency band while ensuring good phase error and amplitude error. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 It is the circuit schematic diagram of the traditional orthogonal all-pass filter;

[0045] Figure 2 This is a structural principle diagram of an orthogonal all-pass filter with integrated load impedance matching proposed by the present invention;

[0046] Figure 3 It is a principle diagram of an orthogonal all-pass filter with a capacitive load in a specific example of an orthogonal all-pass filter with integrated load impedance matching proposed by the present invention;

[0047] Figure 4 The Smith chart matching is a specific example of the orthogonal all-pass filter with integrated load impedance matching proposed by the present invention.

[0048] Figure 5 This is a graph showing the phase variation with frequency of the four output signals of a traditional orthogonal all-pass filter under the same capacitive load.

[0049] Figure 6 This is a graph showing how the amplitude of the four output signals of a traditional orthogonal all-pass filter changes with frequency under the same capacitive load.

[0050] Figure 7 This is a circuit layout of a specific example of an orthogonal all-pass filter with integrated load impedance matching proposed by the present invention.

[0051] Figure 8 for Figure 7 The phase of the four output signals changes with frequency under the circuit layout.

[0052] Fig. 9 for Figure 7The amplitude of the four output signals varies with frequency under the circuit layout.

[0053] Fig.10 The circuit schematic diagram of the orthogonal all-pass filter that combines L3 and L5, L4 and L8.

[0054] In the figure: L1, the first inductor; L2, the second inductor; L3, the third inductor; L4, the fourth inductor; L5, the fifth inductor; L6, the sixth inductor; L7, the seventh inductor; L8, the eighth inductor; L9, the ninth inductor; L10, the tenth inductor; C1, the first capacitor; C2, the second capacitor; C3, the third capacitor; C4, the fourth capacitor; Vin+, the positive input port; Vin-, the negative input port; VI+, the first positive output port; VI-, the first negative output port; VQ+, the second positive output port; VQ-, the second negative output port. DETAILED DESCRIPTION

[0055] The present invention will be described clearly, completely and intuitively below in conjunction with the accompanying drawings in specific examples of the present invention.

[0056] refer to Figure 1 , the circuit structure of the traditional orthogonal all-pass filter is as follows Figure 1 As shown, the circuit structure is composed of a first inductor L1, a second inductor L2, a third inductor L3, a fourth inductor L4, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a first resistor R1 and a second resistor R2; the positive input port Vin+ and the negative input port Vin- are respectively connected to the two ends of the differential input signal, the positive input port Vin+ is connected to the first inductor L1 and one end of the first capacitor C1, the other end of the first capacitor C1 is connected to the first resistor R1 and the third inductor L3, and the third inductor L3 and the branch where it is located are used as the first of the orthogonal differential output signals. Positive output port VI+; the other end of the first resistor R1 is connected to the third capacitor C3, and the branch where the third capacitor C3 is located serves as the second negative output port VQ- of the orthogonal differential output signal; the negative input port Vin- is connected to the second inductor L2 and one end of the second capacitor C2, the other end of the second capacitor C2 is connected to the second resistor R2 and the fourth inductor L4, and the branch where the fourth inductor L4 is located serves as the first negative output port VI- of the orthogonal differential output signal; the other end of the second resistor R2 is connected to the fourth capacitor C4, and the branch where the fourth capacitor C4 is located serves as the second positive output port VQ+ of the orthogonal differential output signal.

[0057] In terms of specific parameters, the first inductor L1=the second inductor L2, the third inductor L3=the fourth inductor L4, the first capacitor C1=the second capacitor C2, the third capacitor C3=the fourth capacitor C4, the first resistor R1=the second resistor R2= .

[0058] After the differential signal enters the orthogonal all-pass filter, it is divided into two pairs of mutually orthogonal differential signals. The amplitude and phase of the orthogonal differential signal determine the shifting accuracy of the Cartesian phase shifter.

[0059] The two ends of the differential input signal are respectively connected to the positive input port Vin+ and the negative input terminal Vin- of the orthogonal all-pass filter, the positive input port Vin+ is connected to the first inductor L1 and the first capacitor C1, the other end of the first capacitor C1 is connected to the first resistor R1 and the third inductor L3, and the branch where the third inductor L3 is located serves as the first positive output port VI+ of the orthogonal differential output signal; the other end of the first resistor R1 is connected to the third capacitor C3, and the branch where the third capacitor C3 is located serves as the positive The second negative output port VQ- of the orthogonal differential output signal; the negative input port Vin- is connected to one end of the second inductor L2 and the second capacitor C2, the other end of the second capacitor C2 is connected to the second resistor R2 and the fourth inductor L4, and the branch where the fourth inductor L4 is located serves as the first negative output port VI- of the orthogonal differential output signal; the other end of the second resistor R2 is connected to the fourth capacitor C4, and the branch where the fourth capacitor C4 is located serves as the second positive output port VQ+ of the orthogonal differential output signal.

[0060] Embodiment 1:

[0061] like Figure 2 As shown, based on the prior art of the traditional orthogonal all-pass filter, this embodiment adds four inductors, namely the fifth inductor L5, the sixth inductor L6, the seventh inductor L7 and the eighth inductor L8 (the sizes of the four inductors are adjusted according to different capacitive loads), the fifth inductor L5=the sixth inductor L6=the seventh inductor L7=the eighth inductor L8; the fifth inductor L5 is added between the third inductor L3 and the first positive output port VI+ of the orthogonal differential output signal; the sixth inductor L6 is added between the third capacitor C3 and the second negative output port VQ- of the orthogonal differential output signal; the seventh inductor L7 is added between the fourth capacitor C4 and the second positive output port VQ+ of the orthogonal differential output signal; and the eighth inductor L8 is added between the fourth inductor L4 and the first negative output port VI- of the orthogonal differential output signal.

[0062] The inductance values ​​of the fourth inductor, namely, the fifth inductor L5 , the sixth inductor L6 , the seventh inductor L7 , and the eighth inductor L8 are equal: the fifth inductor L5 = the sixth inductor L6 = the seventh inductor L7 = the eighth inductor L8 .

[0063] The specific inductance value is calculated according to the following method:

[0064] The load impedance values ​​of the four output ports are equal and capacitive. The load impedance can be written as

[0065] ,

[0066] After adding four inductors, the output impedance is ,

[0067] When satisfied When the capacitive load of the load impedance is offset, a load value of pure resistive impedance can be achieved.

[0068] Among them, w is the angular frequency of the orthogonal all-pass filter, the capacitor C is the capacitance value equivalent to the capacitive load of the orthogonal all-pass filter, and the inductor L is the inductance value.

[0069] The first resistor R1 and the second resistor R2 are metal film resistors, the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 are all interdigital capacitors, and the first inductor L1, the second inductor L2, the third inductor L3, the fourth inductor L4, the fifth inductor L5, the sixth inductor L6, the seventh inductor L7, and the eighth inductor L8 are square inductors.

[0070] Metal film resistors have high precision, good stability, and little change with temperature fluctuations.

[0071] Finger capacitors are specifically used for the design of small capacitors, and have higher accuracy when designing capacitors with smaller capacitance values.

[0072] Square inductors allow for better layout and are conducive to chip miniaturization design.

[0073] The present invention also provides a layout for reducing the layout area of ​​the orthogonal all-pass filter, thereby realizing the miniaturized design of the chip.

[0074] like Fig.10 As shown, the third inductor L3 and the fifth inductor L5 are combined into the ninth inductor L9, and the fourth inductor L4 and the eighth inductor L8 are combined into the first and tenth inductors L10 during the layout design, so as to reduce the number of inductors, reduce the self-resonant frequency and mutual inductance coupling interference of the inductors, and improve the reliability of the circuit. The inductance value of the ninth inductor L9 = the first and tenth inductors L10.

[0075] For specific inductance values, the ninth inductor L9 = the third inductor L3 + the fifth inductor L5 , and the first to tenth inductors L10 = the fourth inductor L4 + the eighth inductor L8 .

[0076] refer to Figure 1 , VQ+ exhibits high-pass characteristics from the perspective of Vin+, and exhibits low-pass characteristics from the perspective of Vin-. The linear combination of these characteristics constitutes the transfer function of the traditional orthogonal all-pass filter. The specific function formula is as follows:

[0077]

[0078] Where s is the complex frequency. s=jw, w is the angular frequency.

[0079] Since parasitic load capacitance will still introduce IQ errors in the differential orthogonal all-pass filter, and in the actual application of phased arrays, the orthogonal all-pass filter is usually followed by a phase shifter, the input impedance of the phase shifter will have a large negative imaginary part; and because the I and Q paths are asymmetrical, the capacitive load will greatly affect the performance of the circuit.

[0080] The present invention connects inductors in series at four output ports, which is achieved by additionally compensating the capacitive load impedance, and does not change the zero point distribution of the transfer function of the traditional orthogonal all-pass filter. It is ensured that the orthogonal all-pass filter with integrated load impedance matching proposed by the present invention does not change the output characteristics of the orthogonal all-pass of the traditional structure.

[0081] refer to Figure 4 , take the capacitive load impedance as 50-j*58 ohms (the four inductors can be adjusted according to the actual load impedance). According to the impedance matching theory, connecting an inductor in series can offset the imaginary part of the load impedance, thereby achieving a matching effect, which is intuitively reflected in the Smith circle diagram, such as Figure 4 shown.

[0082] refer to Figure 5 and Figure 8 , take the capacitive load impedance as 50-j*58 ohms (the four inductors can be adjusted according to the actual load impedance). Figure 5 The phase simulation result diagram of the output signal of the four output ports of the traditional orthogonal all-pass filter under the same capacitive load is shown in Figure 2. Figure 8 The phase simulation result diagram of the output signals of the four output ports of the orthogonal all-pass filter with integrated load impedance matching proposed by the present invention under the same capacitive load, phase refers to the phase, and the closer the difference between the four phase curves of phase1, phase2, phase3, and phase4 is to 90°, the smaller the phase error is; Figure 5 and Figure 8It can be seen that the orthogonal all-pass filter with integrated load impedance matching proposed in the present invention outputs an orthogonal differential signal with a smaller phase error, each curve is close to a 90° phase, and is very stable in the 15 GHz-25 GHz frequency band.

[0083] refer to Figure 6 and Fig. 9 , Figure 6 The figure below shows the result of the amplitude of the output signal of the four output ports of the traditional orthogonal all-pass filter changing with the frequency under the same capacitive load. Fig. 9 This is a graph showing the amplitude of the output signals of the four output ports of the orthogonal all-pass filter with integrated load impedance matching under the same capacitive load as a function of frequency. S21, S31, S41, and S51 refer to the amplitudes of the four output signals. The closer the values ​​of the four curves are, the smaller the amplitude error is. Figure 6 and Fig. 9 It can be seen that the amplitude error of the orthogonal differential signal output by the orthogonal all-pass filter with integrated load impedance matching proposed in the present invention is very small (the curves are basically overlapped in pairs), and the error of the amplitude of the four output signals can still be maintained within ±2dB despite the capacitive load.

[0084] In summary, combined Figure 8 and Fig. 9 The amplitude error of the orthogonal differential signal output by the structure proposed in the present invention is guaranteed to be within ±2dB, and the phase fluctuation within the band does not exceed ±0.5°. High precision of phase and amplitude is maintained in a wide frequency band, and the influence of capacitive load on the performance of the orthogonal all-pass filter is basically eliminated.

[0085] Figure 5 , 6 The middle horizontal axis represents the operating frequency;

[0086] Figure 6 The middle vertical axis is the S parameter (scattering parameter), and the four lines refer to the voltage gain, which is used to describe the output amplitude of the orthogonal signal. The closer the four signals (four lines) fit, the better.

[0087] Figure 5 The vertical coordinate phase refers to the phase, which is required to differ by 90° in sequence. The closer to 90° the better, and the phase cannot fluctuate too much with the frequency.

[0088] Figure 8-9 The middle horizontal axis represents the operating frequency;

[0089] Fig. 9 The middle vertical axis is the S parameter (scattering parameter), and the four lines refer to the voltage gain, which is used to describe the output amplitude of the orthogonal signal. The closer the four signals (four lines) fit, the better.

[0090] Figure 8The vertical coordinate phase refers to the phase, which is required to differ by 90° in sequence. The closer to 90° the better, and the phase cannot fluctuate too much with the frequency.

[0091] refer to Figure 7 The third inductor L3 and the third-fifth inductor L5 are merged into the ninth inductor L9, the third-fourth inductor L4 and the third-eighth inductor L8 are merged into the ninth inductor L9. The merged inductor also uses a square inductor to reduce the chip area. In the specific example where the capacitive load impedance is 50-j*58 ohms, the area of ​​this chip layout is 365mm*370mm.

[0092] The layout size is very small. Nowadays, chips are all pursuing miniaturization. The size of 365mm*370mm shows that this structure can be applied to chip miniaturization design.

[0093] Obviously, the described embodiments have actual capacitive load values, but the viewpoint of the present invention is that no matter what kind of capacitive load, the imaginary part of the capacitive load can be offset by adjusting the inductance value, thereby achieving a pure resistance matching effect; the embodiments are only a part of the present invention, and are only for better illustrating the viewpoint of the present invention.

[0094] Embodiment 2:

[0095] This embodiment provides a chip circuit, including the orthogonal all-pass filter with integrated load impedance matching as described in the first embodiment.

[0096] refer to Figure 7 The third inductor L3 and the third-fifth inductor L5 are merged into the ninth inductor L9, the third-fourth inductor L4 and the third-eighth inductor L8 are merged into the ninth inductor L9. The merged inductor also uses a square inductor to reduce the chip area. In the specific example where the capacitive load impedance is 50-j*58 ohms, the area of ​​this chip layout is 365mm*370mm.

[0097] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features, and in the description of the present invention, "plurality" means two or more, unless otherwise clearly and specifically defined.

[0098] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0099] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0100] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0101] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations on the present invention. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present invention without departing from the principles and purpose of the present invention.

Claims

1. An orthogonal all-pass filter with integrated load impedance matching, characterized in that: Including differential orthogonal network structure; The orthogonal all-pass filter is provided with a positive input port, a negative input port, a first positive output port, a second positive output port, a first negative output port, and a second negative output port of an orthogonal differential signal; The differential orthogonal network structure includes a first inductor, a second inductor, a third inductor, a fourth inductor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first resistor and a second resistor; The positive input port and the negative input port are used to be connected to the two ends of the differential input signal respectively. The positive input port is connected to one end of the first inductor and the first capacitor respectively, the other end of the first capacitor is connected to the first resistor and the third inductor respectively, and the other end of the third inductor is connected to the first positive output port; The other end of the first resistor is connected to the third capacitor, and the other end of the third capacitor is connected to the second negative output port; The negative input port is connected to the second inductor and one end of the second capacitor respectively, the other end of the second capacitor is connected to the second resistor and the fourth inductor respectively, and the other end of the fourth inductor is connected to the first negative output port; The other end of the second resistor is connected to a fourth capacitor, and the other end of the fourth capacitor is connected to the second positive output port; A fifth inductor is added between the third inductor and the first positive output port; A sixth inductor is added between the third capacitor and the second negative output port; A seventh inductor is added between the fourth capacitor and the second positive output port; An eighth inductor is added between the fourth inductor and the first negative output port; The inductance values ​​of the fifth inductor, the sixth inductor, the seventh inductor and the eighth inductor are equal; The inductance values ​​L of the fifth inductor, the sixth inductor, the seventh inductor and the eighth inductor satisfy the following formula: ； Wherein, w is the angular frequency of the orthogonal all-pass filter, C is the capacitance value equivalent to the capacitive load of the orthogonal all-pass filter, and L is the inductance value; The inductance values ​​of the first inductor and the second inductor are the same; The inductance values ​​of the third inductor and the fourth inductor are the same; The capacitance values ​​of the first capacitor and the second capacitor are the same; The capacitance values ​​of the third capacitor and the fourth capacitor are the same; The resistance values ​​R1 and R2 of the first resistor and the second resistor are the same, and R1=R2= ; L1 is the inductance value of the first inductor, and C1 is the capacitance value of the first capacitor.

2. The orthogonal all-pass filter with integrated load impedance matching according to claim 1, characterized in that: The first resistor and the second resistor are both metal film resistors. The first capacitor, the second capacitor, the third capacitor and the fourth capacitor are all interdigital capacitors. The first inductor, the second inductor, the third inductor, the fourth inductor, the fifth inductor, the sixth inductor, the seventh inductor and the eighth inductor are all square inductors.

3. The orthogonal all-pass filter with integrated load impedance matching according to claim 1, characterized in that: A ninth inductor is used to replace the third inductor and the fifth inductor; one end of the ninth inductor is connected to the first capacitor, and the other end of the ninth inductor is connected to the first positive output port; A tenth inductor is used to replace the fourth inductor and the eighth inductor; one end of the tenth inductor is connected to the second capacitor, and the other end of the tenth inductor is connected to the second positive output port.

4. The orthogonal all-pass filter with integrated load impedance matching according to claim 3, characterized in that: The inductance values ​​of the ninth inductor and the tenth inductor are equal.

5. The orthogonal all-pass filter with integrated load impedance matching according to claim 4, characterized in that: The inductance value of the ninth inductor is equal to the sum of the inductance values ​​of the third inductor and the fifth inductor; The inductance value of the tenth inductor is equal to the sum of the inductance values ​​of the third inductor and the fifth inductor.

6. A chip circuit, comprising the integrated load impedance matched orthogonal all-pass filter according to any one of claims 1 to 5.

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