Ring oscillators, phase-locked loops, circuit board assemblies and electronic devices
By designing multiple bias circuits in the ring oscillator to generate different bias currents, the stability of the ring oscillator frequency and the adjustment gain are separated, and the problem of difficult balance between frequency stability and adjustment gain in the prior art is solved.
Patent Information
- Application Number
- CN202411227632.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-03
- Publication Date
- 2025-03-14
- Estimated Expiration
- 2044-09-03
AI Technical Summary
It is difficult to balance the frequency stability and the adjustment gain, and the separation between the frequency stability and the adjustment gain is difficult to achieve.
A ring oscillator is designed, including a first bias circuit, a second bias circuit and a third bias circuit, through which different bias currents are generated, and the oscillation circuit generates an oscillation signal according to these currents, thereby separating the gain and frequency.
The stability of the ring oscillator frequency and the existence of large adjustment gain are achieved, solving the balance problem between frequency stability and adjustment gain.
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Figure CN118740146B_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present application relate to the field of circuit technology, and in particular to a ring oscillator, a phase-locked loop, a circuit board assembly, and an electronic device. Background Art
[0002] At present, due to the simple structure and small area of the ring oscillator (RO), it is usually used in the phase-locked loop (PLL) when the communication system has low requirements for phase noise. Controlling the current of the ring oscillator is one of the basic methods to adjust the oscillator frequency. In the related technology, the ring oscillator is used to receive the current transmitted by the filter. The magnitude of the current determines the frequency of the ring oscillator, and the magnitude of the current change with the voltage determines the adjustment gain of the ring oscillator.
[0003] However, in the related art, if the frequency of the ring oscillator is required to be stable, the current input to the oscillator needs to change less, which will result in a smaller adjustment gain of the oscillator; if the adjustment gain of the ring oscillator is required to be larger, the current input to the oscillator needs to change more, which will result in an unstable oscillator frequency; making it impossible to achieve a balance between the stability of the ring oscillator frequency and the adjustment gain. Summary of the invention
[0004] The purpose of the embodiments of the present application is to provide a ring oscillator, a phase-locked loop, a circuit board assembly and an electronic device, so that the frequency of the ring oscillator is separated from the adjustment gain, and the stability of the ring oscillator frequency and a larger adjustment gain can be achieved simultaneously.
[0005] To solve the above technical problems, an embodiment of the present application provides a ring oscillator, comprising: a first bias circuit, a second bias circuit, a third bias circuit, and an oscillation circuit; the input end of the first bias circuit serves as the input end of the ring oscillator, and the output end of the first bias circuit is connected to the output end of the second bias circuit; the input end of the oscillation circuit is connected to any node between the output end of the first bias circuit and the output end of the second bias circuit; the input end of the oscillation circuit is also connected to the output end of the third bias circuit; the first bias circuit is used to generate a first bias current, the second bias circuit is used to generate a second bias current, and the third bias circuit is used to generate a third bias current; the oscillation circuit is used to generate an oscillation signal according to the first bias current, the second bias current, and the third bias current.
[0006] An embodiment of the present application also provides a phase-locked loop, comprising: a phase detector, a low-pass filter, a feedback loop, and the above-mentioned ring oscillator; the output end of the phase detector is connected to the input end of the low-pass filter; the output end of the low-pass filter is connected to the input end of the ring oscillator; the output end of the ring oscillator is connected to the input end of the phase detector through the feedback loop.
[0007] An embodiment of the present application further provides a circuit board assembly, comprising: the above-mentioned ring oscillator or phase-locked loop.
[0008] An embodiment of the present application further provides an electronic device, comprising: the above-mentioned circuit board assembly.
[0009] In some embodiments, the first bias circuit includes multiple first switch branches; each of the first switch branches includes a first PMOS tube and a first NMOS tube, the source of each of the first PMOS tubes is commonly used as the output end of the first bias circuit, the drain of the first PMOS tube is connected to the drain of the first NMOS tube, and the source of the first NMOS tube is grounded; the gate of each of the first PMOS tubes is used to receive a first bias signal; the gate of each of the first NMOS tubes is commonly used as the input end of the first bias circuit, for receiving a first bias voltage; the first bias circuit is used to generate the first bias current according to the first bias signal and the first bias voltage.
[0010] In some embodiments, the second bias circuit includes multiple second switch branches; each of the second switch branches includes a second PMOS tube and a second NMOS tube, the source of each of the second NMOS tubes is commonly used as the output end of the second bias circuit, the drain of the second PMOS tube is connected to the drain of the second NMOS tube, and the source of the second PMOS tube is connected to the power supply; the gate of each of the second NMOS tubes is used to receive a second bias signal; the gate of each of the second PMOS tubes is commonly used as the input end of the second bias circuit, for receiving a second bias voltage; the second bias circuit is used to generate the second bias current according to the second bias signal and the second bias voltage.
[0011] In some embodiments, the third bias circuit includes multiple third switch branches; each of the third switch branches includes a third PMOS tube and a third NMOS tube, the source of each of the third PMOS tubes is commonly used as the output end of the third bias circuit, the drain of the third PMOS tube is connected to the drain of the third NMOS tube, and the source of the third NMOS tube is grounded; the gate of each of the third PMOS tubes is used to receive a third bias signal; the gate of each of the third NMOS tubes is commonly used as the input end of the third bias circuit, for receiving a third bias voltage; the third bias circuit is used to generate the third bias current according to the third bias signal and the third bias voltage.
[0012] In some embodiments, the third bias circuit includes multiple fourth switch branches; each of the fourth switch branches includes a fourth PMOS tube and a fourth NMOS tube, the source of each of the fourth NMOS tubes is commonly used as the output end of the third bias circuit, the drain of the fourth PMOS tube is connected to the drain of the fourth NMOS tube, and the source of the fourth PMOS tube is connected to the power supply; the gate of each of the fourth NMOS tubes is used to receive a third bias signal; the gate of each of the fourth PMOS tubes is commonly used as the input end of the third bias circuit, for receiving a third bias voltage; the third bias circuit is used to generate the third bias current according to the third bias signal and the third bias voltage.
[0013] In some embodiments, the ring oscillator further includes a first filter; the first filter is connected to an input terminal of the second bias circuit.
[0014] In some embodiments, the ring oscillator further includes a second filter; the second filter is connected to an input terminal of the third bias circuit.
[0015] The embodiments of the present disclosure have at least the following advantages:
[0016] The input end of the first bias circuit is used as the input end of the ring oscillator. The magnitude of the first bias current generated by the first bias circuit is determined according to the voltage input to the input end of the ring oscillator. The change of the first bias current can determine the adjustment gain of the ring oscillator. Secondly, the second bias current generated by the second bias circuit can offset the first bias current generated by the first bias circuit, so that the current input to the oscillation circuit is mainly determined by the third bias current generated by the third bias circuit, that is, the third bias current determines the frequency of the ring oscillator. In other words, the adjustment gain of the ring oscillator of this embodiment is determined by the first bias current, and the frequency of the ring oscillator is determined by the third bias current, so that the frequency of the ring oscillator is separated from the adjustment gain, and the stability of the frequency of the ring oscillator and a larger adjustment gain can be achieved at the same time. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.
[0018] Figure 1 is a schematic diagram of a circuit structure of a ring oscillator according to an embodiment of the present application;
[0019] Figure 2 is a circuit structure diagram of a first bias circuit according to an embodiment of the present application;
[0020] Figure 3 is a circuit structure diagram of a second bias circuit according to an embodiment of the present application;
[0021] Figure 4 is a circuit structure diagram of a third bias circuit according to an embodiment of the present application;
[0022] Figure 5 is another circuit structure schematic diagram of a third bias circuit according to an embodiment of the present application;
[0023] Figure 6 is a schematic diagram of a circuit structure of a ring oscillator according to an embodiment of the present application;
[0024] Figure 7 4 is a schematic diagram of a circuit structure of a ring oscillator according to an embodiment of the present application. DETAILED DESCRIPTION
[0025] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in detail below in conjunction with the accompanying drawings. However, it will be appreciated by those skilled in the art that in the present application, many technical details are proposed in order to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical scheme claimed in the present application can also be implemented. The division of the following embodiments is for the convenience of description, and the specific implementation of the present application should not be construed as any limitation, and the various embodiments can be combined and referenced with each other under the premise of no contradiction.
[0026] An embodiment of the present application relates to a ring oscillator, and a specific circuit structure diagram is shown in FIG. Figure 1 As shown, the ring oscillator includes: a first bias circuit 101 , a second bias circuit 102 , a third bias circuit 103 , and an oscillation circuit 104 .
[0027] Specifically, the input end of the first bias circuit 101 serves as the input end of the ring oscillator, and the output end of the first bias circuit 101 is connected to the output end of the second bias circuit 102; the input end of the oscillation circuit 104 is connected to any node between the output end of the first bias circuit 101 and the output end of the second bias circuit 102; the input end of the oscillation circuit 104 is also connected to the output end of the third bias circuit 103; the first bias circuit 101 is used to generate a first bias current I1, the second bias circuit 102 is used to generate a second bias current I2, and the third bias circuit 103 is used to generate a third bias current I3; the oscillation circuit 104 is used to generate an oscillation signal according to the first bias current I1, the second bias current I2, and the third bias current I3.
[0028] Specifically, the output end of the first bias circuit 101 of the ring oscillator of this embodiment is connected to the output end of the second bias circuit 102. When the input end of the oscillation circuit 104 is connected to any node between the output end of the first bias circuit 101 and the output end of the second bias circuit 102, the current input to the oscillation circuit 104 is the difference Itune between the first bias current I1 and the second bias current I2. The input end of the oscillation circuit 104 is also connected to the output end of the third bias circuit 103, so that the current input to the oscillation circuit also includes the third bias circuit I3. Therefore, the total current I actually input to the oscillation circuit 总 =I3+Itune.
[0029] It is worth mentioning that the second bias current I2 generated by the second bias circuit 102 is set according to the size of the first bias current I1, so that the difference between the first bias current I1 and the second bias current I2 is small, and the difference Itune between the first bias current I1 and the second bias current I2 can be ignored compared with the third bias current I3 generated by the third bias circuit 103, so that the total current I input to the oscillation circuit 104 is 总 It is mainly determined by the third bias current I3 generated by the third bias circuit 103 , that is, the third bias current I3 determines the frequency of the ring oscillator.
[0030] In this embodiment, the input end of the first bias circuit 101 is used as the input end of the ring oscillator. The magnitude of the first bias current I1 generated by the first bias circuit 101 is determined according to the voltage input to the input end of the ring oscillator. The change of the first bias current I1 can determine the adjustment gain of the ring oscillator. Secondly, the second bias current I2 generated by the second bias circuit 102 can offset the first bias current I1 generated by the first bias circuit 101, so that the current input to the oscillation circuit 104 is mainly determined by the third bias current I3 generated by the third bias circuit 103, that is, the third bias current I3 determines the frequency of the ring oscillator. In other words, the adjustment gain of the ring oscillator in this embodiment is determined by the first bias current I1, and the frequency of the ring oscillator is determined by the third bias current I3, so that the frequency of the ring oscillator is separated from the adjustment gain, and the stability of the frequency of the ring oscillator and a larger adjustment gain can be achieved at the same time.
[0031] In one embodiment, the first bias circuit 101 includes a plurality of first switch branches. Figure 2 FIG. 1 is a schematic diagram of the circuit structure of the first bias circuit 101 of the present embodiment. The first bias circuit 101 of the present embodiment includes a plurality of first switch branches, each of which includes a first PMOS transistor Q P1 , the first NMOS tube Q N1 , each first PMOS tube Q P1 The source S of the first PMOS transistor Q P1 The drain D is connected to the first NMOS tube Q N1 The drain D of the first NMOS tube Q N1 The source S is grounded.
[0032] Specifically, each first PMOS tube Q P1 The gate G is used to receive the first bias signal switch1; each first NMOS tube Q N1 The gate G of the switch 1 and the gate G of the switch 1 are used together as the input terminal of the first bias circuit 101 for receiving the first bias voltage V1; the first bias circuit 101 is used for generating a first bias current I1 according to the first bias signal switch1 and the first bias voltage V1.
[0033] Specifically, in this embodiment, the first PMOS transistor Q of each first switch branch P1 The gate G receives the first bias signal switch1, and the first NMOS transistor Q of each first switch branch is N1 The gate G of the first bias circuit 101 is used as the input terminal of the first bias circuit 101 to receive the first bias voltage V1. The first bias signal switch1 includes a control signal for each first PMOS tube Q P1The information of on or off is provided, and each first bias signal switch1 can be different; in this embodiment, the number of the first switch branches that are turned on can be selected according to the required size of the first bias current I1, that is, the first switch branch that needs to be turned on is turned on by the corresponding first bias signal switch1, and the turned-on first switch branch provides a bias current of corresponding size through the first bias voltage V1, and multiple first switch branches jointly output the first bias current I1, so that the size of the first bias current I1 can be controlled according to actual needs. That is, the first PMOS tube Q of the first switch branch in this embodiment is P1 Used as a switch, the first NMOS tube Q N1 It is used as an NMOS current source. It should be noted that, when the first bias voltage V1 remains unchanged, the more the number of first switch branches that are turned on is, the larger the first bias current I1 is, and the fewer the number of first switch branches that are turned on is, the smaller the first bias current I1 is.
[0034] In one embodiment, the second bias circuit 102 includes a plurality of second switch branches, such as Figure 3 FIG. 1 is a schematic diagram of the circuit structure of the second bias circuit 102 of the present embodiment. The second bias circuit 102 of the present embodiment includes a plurality of second switch branches; each second switch branch includes a second PMOS transistor Q P2 , the second NMOS tube Q N2 , each second NMOS tube Q N2 The source S of the second bias circuit 102 is used as the output terminal B of the second PMOS tube Q P2 The drain D is connected to the second NMOS tube Q N2 The drain D of the first PMOS tube Q P2 The source S is connected to the power supply VDD.
[0035] Specifically, each second NMOS tube Q N2 The gate G is used to receive the second bias signal switch2; each second PMOS tube Q P2 The gate G of the switch 2 is used together as the input terminal of the second bias circuit 102 for receiving the second bias voltage V2; the second bias circuit 102 is used to generate a second bias current I2 according to the second bias signal switch2 and the second bias voltage V2.
[0036] Specifically, in this embodiment, the second NMOS transistor Q of each second switch branch N2 The gate G receives the second bias signal switch2, and the second PMOS transistor Q of each second switch branch is P2 The gate G of the second bias circuit 102 is used as the input terminal of the second bias circuit 102 to receive the second bias voltage V2. The second bias signal switch2 includes a control signal for each second NMOS tube QN2 The information of turning on or off, each second bias signal switch2 can be different; in this embodiment, the number of the second switch branches that are turned on can be selected according to the required size of the second bias current I2, that is, the second switch branch that needs to be turned on is turned on by the corresponding second bias signal switch2, and the turned-on second switch branch provides a bias current of corresponding size through the second bias voltage V2, and multiple second switch branches jointly output the second bias current I2, so that the size of the second bias current I2 can be controlled according to actual needs. That is, the second PMOS tube Q of the second switch branch in this embodiment is P1 Used as a PMOS current source, the second NMOS tube Q N2 It is used as a switch. It should be noted that, when the second bias voltage V2 remains unchanged, the more the number of the second switch branches that are turned on is, the larger the second bias current I2 is, and the fewer the number of the second switch branches that are turned on is, the smaller the second bias current I2 is.
[0037] It is worth mentioning that the circuit structures of the first bias circuit 101 and the second bias circuit 102 in the above embodiment can be interchanged, that is, the first bias circuit 101 is connected to the first NMOS transistor Q of each first switch branch. N1 The gate G receives the first bias signal switch1, and the first PMOS transistor Q of each first switch branch is P1 The gates G of the first bias circuit 101 are used as the input terminal of the first bias circuit 101 to receive the first bias voltage V1; the second bias circuit 102 receives the first bias voltage V1 through the second PMOS transistor Q of each second switch branch. P2 The gate G receives the second bias signal switch2, and the second NMOS transistor Q of each second switch branch is N2 The gates G of the transistors 102 serve together as an input terminal of the second bias circuit 102 to receive the second bias voltage V2.
[0038] In one embodiment, the third bias circuit 103 includes a plurality of third switch branches; Figure 4 FIG. 1 is a schematic diagram of the circuit structure of the third bias circuit 103 of the present embodiment. The third bias circuit 103 of the present embodiment includes a plurality of third switch branches; each third switch branch includes a third PMOS transistor Q P3 、The third NMOS tube Q N3 , each third PMOS tube Q P3 The source S of the third PMOS tube Q P3 The drain D is connected to the third NMOS tube Q N3 The drain D of the third NMOS tube Q N3 The source S is grounded.
[0039] Specifically, each third PMOS tube Q P3 The gate G is used to receive the third bias signal switch3; each third NMOS tube Q N3 The gate G of the switch 102 is used together as the input terminal of the third bias circuit 103 for receiving the third bias voltage V3; the third bias circuit 103 is used to generate a third bias current I3 according to the third bias signal switch3 and the third bias voltage V3.
[0040] Specifically, in this embodiment, the third PMOS transistor Q of each third switch branch is P3 The gate G receives the third bias signal switch3, and the third NMOS transistor Q of each third switch branch is N3 The gate G of the third bias circuit 103 is used as the input terminal to receive the third bias voltage V3. The third bias signal switch3 includes a control signal for each PMOS tube Q P3 The information of turning on or off, each third bias signal switch3 can be different; in this embodiment, the number of the third switch branches to be turned on can be selected according to the required size of the third bias current I3, that is, the third switch branches to be turned on are turned on by the corresponding third bias signal switch3, and the turned-on third switch branches provide a bias current of corresponding size through the third bias voltage V3, and multiple third switch branches jointly output the third bias current I3, so that the size of the third bias current I3 can be controlled according to actual needs. That is, the third PMOS tube Q of the third switch branch in this embodiment is P3 Used as a switch, the third NMOS tube Q N3 It is used as an NMOS current source. It should be noted that, when the third bias voltage V3 remains unchanged, the more the third switch branches are turned on, the larger the third bias current I3 is, and the fewer the third switch branches are turned on, the smaller the third bias current I3 is.
[0041] like Figure 5 FIG. 1 is another schematic diagram of the circuit structure of the third bias circuit of the present embodiment. The third bias circuit 103 of the present embodiment includes a plurality of fourth switch branches; each fourth switch branch includes a fourth PMOS transistor Q P4 , the fourth NMOS tube Q N4 , each fourth NMOS tube Q N4 The source S of the third bias circuit 103 is used as the output terminal C of the fourth PMOS tube Q P4 The drain D is connected to the fourth NMOS tube Q N4 The drain D of the fourth PMOS tube Q P4 The source S is connected to the power supply VDD.
[0042] Specifically, each fourth NMOS tube QN4 The gate G is used to receive the third bias signal switch3; each fourth PMOS tube Q P4 The gate G of the switch 102 is used together as the input terminal of the third bias circuit 103 for receiving the third bias voltage V3; the third bias circuit 103 is used to generate a third bias current I3 according to the third bias signal switch3 and the third bias voltage V3.
[0043] Specifically, in this embodiment, the fourth NMOS transistor Q of each fourth switch branch is N4 The gate G receives the third bias signal switch3, and the fourth PMOS transistor Q of each fourth switch branch is P4 The gate G of the third bias circuit 103 is used as the input terminal to receive the third bias voltage V3. The third bias signal switch3 includes a control signal for controlling each third NMOS tube Q N3 The information of the on or off signal, each third bias signal switch3 may be different; in this embodiment, the number of the fourth switch branches to be turned on may be selected according to the required size of the third bias current I3, that is, the fourth switch branches to be turned on may be turned on by the corresponding third bias signal switch3, and the turned-on fourth switch branches may provide a bias current of a corresponding size through the third bias voltage V3, and a plurality of fourth switch branches may jointly output the third bias current I3, so that the size of the third bias current I3 may be controlled according to actual needs. That is, the third PMOS tube Q of the first switch branch in this embodiment may be P3 Used as a PMOS current source, the third NMOS tube Q N3 It should be noted that, when the third bias voltage V3 remains unchanged, the more the third switch branches are turned on, the greater the third bias current I3 is, and the fewer the third switch branches are turned on, the smaller the third bias current I3 is.
[0044] In one embodiment, the ring oscillator further comprises a first filter; the first filter is connected to the input end of the second bias circuit. Figure 6 , which is a schematic diagram of the structure of the ring oscillator of this embodiment, the first filter 105 of this embodiment is connected to the input end of the second bias circuit 102 .
[0045] The second bias circuit 102 of this embodiment receives the second bias voltage V2 through the first filter 105, thereby filtering the second bias voltage V2 and eliminating noise in the second bias voltage V2.
[0046] Specifically, the second PMOS transistor Q of the second bias circuit 102 P2When the gate G of the second bias circuit 102 is used as the input terminal of the second bias circuit 102 to receive the second bias voltage V2, the first filter 105 is connected to the second PMOS transistor Q of each second switch branch. P2 The gate G of the second NMOS transistor Q in the second bias circuit 102 N2 When the gate G of the second bias circuit 102 is used as the input terminal of the second bias circuit 102 to receive the second bias voltage V2, the first filter 105 is connected to the second NMOS transistor Q of each second switch branch. N2 The gate G.
[0047] In one embodiment, the ring oscillator further includes a second filter; the second filter is connected to the input end of the third bias circuit. Figure 7 , which is a schematic diagram of the structure of the ring oscillator of this embodiment, the second filter 106 of this embodiment is connected to the input end of the third bias circuit 103.
[0048] The third bias circuit 103 of this embodiment receives the third bias voltage V3 through the second filter 106, thereby filtering the third bias voltage V3 and eliminating noise in the third bias voltage V3.
[0049] Specifically, the third bias circuit 103 passes through the third NMOS transistor Q N3 When the gate G receives the third bias voltage V3, the second filter 106 is connected to the NMOS transistor Q of each third switch branch. N3 The gate G of the third bias circuit is connected to the fourth PMOS tube Q P4 When the gate G receives the third bias voltage V3, the second filter 106 is connected to the fourth PMOS transistor Q of each fourth switch branch. P4 The gate G.
[0050] It is worth mentioning that when the ring oscillator of this embodiment is connected to a phase-locked loop, the input end of the first bias circuit 101 is connected to the low-pass filter in the phase-locked loop as the input end of the ring oscillator, and the first bias voltage V1 input to the first bias circuit 101 is filtered by the low-pass filter. Therefore, there is no need to set a filter at the input end of the first bias circuit 101.
[0051] In this embodiment, the filtering parameters of the first bias voltage input to the first bias circuit are controlled by a phase-locked loop, and the filtering parameters of the second bias voltage and the third bias voltage input to the second bias circuit and the third bias circuit can be set according to the current source noise optimization requirements, so that the noise optimization of the ring oscillator and the dynamic response optimization of the phase-locked loop are independent.
[0052] On the other hand, an embodiment of the present application further provides a phase-locked loop, including: a phase detector, a low-pass filter, a feedback loop, and the ring oscillator in the above embodiment.
[0053] Specifically, the output end of the phase detector is connected to the input end of the low-pass filter; the output end of the low-pass filter is connected to the input end of the ring oscillator; and the output end of the ring oscillator is connected to the input end of the phase detector through a feedback loop.
[0054] On the other hand, an embodiment of the present application further provides a circuit board assembly, including: a ring oscillator or a phase-locked loop as in any of the above embodiments.
[0055] It is not difficult to find that this embodiment is a circuit board assembly embodiment corresponding to the circuit embodiment, and this embodiment can be implemented in conjunction with the circuit embodiment. The relevant technical details mentioned in the circuit embodiment are still valid in this embodiment, and in order to reduce repetition, they are not repeated here. Accordingly, the relevant technical details mentioned in this embodiment can also be applied in the circuit embodiment.
[0056] In addition, in order to highlight the innovative part of the present application, the present embodiment does not introduce units that are not closely related to solving the technical problems proposed by the present application, but this does not mean that there are no other units in the present embodiment.
[0057] Another aspect of the present application embodiment further provides an electronic device, including: a circuit board assembly as described in the above embodiment.
[0058] The division of various components above is only for clear description. When implemented, they can be combined into one component or some components can be split and decomposed into multiple components. As long as they include the same logical relationship, they are all within the protection scope of the present invention.
[0059] Those skilled in the art will appreciate that the above embodiments are specific embodiments for implementing the present application, and in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present application.
Claims
1. A ring oscillator, characterized in that: include: A first bias circuit, a second bias circuit, a third bias circuit, and an oscillation circuit; The input end of the first bias circuit serves as the input end of the ring oscillator, and the output end of the first bias circuit is connected to the output end of the second bias circuit; The input end of the oscillation circuit is connected to any node between the output end of the first bias circuit and the output end of the second bias circuit; The input end of the oscillation circuit is also connected to the output end of the third bias circuit; The first bias circuit is used to generate a first bias current, the second bias circuit is used to generate a second bias current, and the third bias circuit is used to generate a third bias current; The second bias current is used to offset the first bias current; The oscillation circuit is used to generate an oscillation signal according to the first bias current, the second bias current, and the third bias current.
2. The ring oscillator according to claim 1, characterized in that The first bias circuit includes a plurality of first switch branches; each of the first switch branches includes a first PMOS tube and a first NMOS tube, the source of each of the first PMOS tubes is commonly used as the output end of the first bias circuit, the drain of the first PMOS tube is connected to the drain of the first NMOS tube, and the source of the first NMOS tube is grounded; The gate of each of the first PMOS tubes is used to receive a first bias signal; The gate of each of the first NMOS transistors is commonly used as an input terminal of the first bias circuit, for receiving a first bias voltage; The first bias circuit is used to generate the first bias current according to the first bias signal and the first bias voltage.
3. The ring oscillator according to claim 2, characterized in that: The second bias circuit includes a plurality of second switch branches; each of the second switch branches includes a second PMOS tube and a second NMOS tube, the source of each second NMOS tube serves as the output end of the second bias circuit, the drain of the second PMOS tube is connected to the drain of the second NMOS tube, and the source of the second PMOS tube is connected to a power supply; The gate of each second NMOS tube is used to receive a second bias signal; the gate of each second PMOS tube serves as an input terminal of the second bias circuit, and is used to receive a second bias voltage; The second bias circuit is used to generate the second bias current according to the second bias signal and the second bias voltage.
4. The ring oscillator according to any one of claims 1 to 3, characterized in that: The third bias circuit includes a plurality of third switch branches; each of the third switch branches includes a third PMOS tube and a third NMOS tube, the source of each of the third PMOS tubes is commonly used as the output end of the third bias circuit, the drain of the third PMOS tube is connected to the drain of the third NMOS tube, and the source of the third NMOS tube is grounded; The gate of each of the third PMOS tubes is used to receive a third bias signal; the gate of each of the third NMOS tubes serves together as an input end of the third bias circuit, and is used to receive a third bias voltage; the third bias circuit is used to generate the third bias current according to the third bias signal and the third bias voltage.
5. The ring oscillator according to any one of claims 1 to 3, characterized in that: The third bias circuit includes a plurality of fourth switch branches; each of the fourth switch branches includes a fourth PMOS tube and a fourth NMOS tube, the source of each of the fourth NMOS tubes serves as the output end of the third bias circuit, the drain of the fourth PMOS tube is connected to the drain of the fourth NMOS tube, and the source of the fourth PMOS tube is connected to a power supply; The gate of each of the fourth NMOS tubes is used to receive a third bias signal; the gate of each of the fourth PMOS tubes serves together as an input end of the third bias circuit, and is used to receive a third bias voltage; the third bias circuit is used to generate the third bias current according to the third bias signal and the third bias voltage.
6. The ring oscillator according to claim 1, characterized in that: The ring oscillator further includes a first filter; the first filter is connected to an input end of the second bias circuit.
7. The ring oscillator according to claim 1, characterized in that: The ring oscillator further includes a second filter; the second filter is connected to an input end of the third bias circuit.
8. A phase-locked loop, characterized in that: include: A phase detector, a low-pass filter, a feedback loop, and a ring oscillator as claimed in any one of claims 1 to 7; The output end of the phase detector is connected to the input end of the low-pass filter; the output end of the low-pass filter is connected to the input end of the ring oscillator; the output end of the ring oscillator is connected to the input end of the phase detector through the feedback loop.
9. A circuit board assembly, characterized in that: It comprises the ring oscillator according to any one of claims 1 to 7, or the phase-locked loop according to claim 8.
10. An electronic device, characterized in that: include: The circuit board assembly of claim 9.