Split Jitter Scheme in Successive Approximation Analog-to-Digital Converters

Abstract

This disclosure relates to a split jitter scheme in a successive approximation analog-to-digital converter (ADC). A system includes a jitter generator module comprising means for generating the most significant bit (MSB) of a first random value. The jitter generator module further includes means for generating the least significant bit (LSB) of a second random value. The system further includes a first digital-to-analog converter (DAC) that receives the sum of the first random value and the second random value and generates a jitter signal based on the sum of the first random value and the second random value. The system also includes an analog-to-digital converter (ADC) that receives the jitter signal and the sum of a sampled input signal and generates a first digitized signal. The system includes a subtraction module that subtracts the sum of the first random value and the second random value from the first digitized signal to generate a digitized output signal.

Description

TECHNICAL FIELD

[0001] This description relates generally to analog-to-digital converters, and in particular to using dithering in analog-to-digital converters. BACKGROUND

[0002] For example, high performance and high resolution analog-to-digital converters (ADCs) can be needed to capture radio frequency (RF) signals and convert the RF signals to digital signals. Successive approximation analog-to-digital converters (SAR ADCs) utilizing complementary metal-oxide-semiconductor (CMOS) technology have low power and compact area, and provide support for low power and high performance 5G wireless base stations using multiple SAR ADCs, sampling frequencies in the tens of gigahertz (GHz). SUMMARY

[0003] In one aspect, the disclosure is directed to a system comprising: a dither generator module comprising: a most significant bit (MSB) dither generator device configured to generate a first random value; a least significant bit (LSB) dither generator device configured to generate a second random value; and a first digital-to-analog converter (DAC) configured to receive the first random value and the second random value and generate a dither sum signal based on a sum of the first random value and the second random value; and an ADC configured to receive a sum of the dither sum signal and a sampled input signal and generate a first digitized signal.

[0004] In another aspect, the disclosure is directed to a system comprising: a first DAC having a bit range; an ADC; a dither generator module comprising: a MSB dither generator device configured to generate a first integer random value having a magnitude comprising non-zero bits limited to a first number of bits in a MSB segment, the MSB segment comprising a first portion of an upper half of the bit range; and a LSB dither generator device configured to generate a second integer random value having a magnitude comprising non-zero bits limited to a second number of bits in a LSB segment, the LSB segment comprising a second portion of a lower half of the bit range, wherein: the first DAC is configured to receive the first integer random value and the second integer random value and generate a dither signal based on a sum of the first integer random value and the second integer random value; and the ADC is configured to receive a sum of the dither signal and a sampled input signal and generate a first digitized signal; and a subtraction module configured to subtract the sum of the first integer random value and the second integer random value from the first digitized signal to generate a digitized output signal.

[0005] In another aspect, this disclosure relates to a system comprising: a DAC having a bit range; an ADC; and an MSB jitter generator device configured to generate a first integer random value, wherein the magnitude of the first integer random value has non-zero bits in an MSB segment limited to the bit range, wherein: the DAC is configured to receive the first integer random value and generate a jitter signal based on the first integer random value; and the ADC is configured to receive the jitter signal and the sum of a sampled input signal and generate a first digitized signal. Attached Figure Description

[0006] Specific features of this technology are set forth in the appended claims. However, for illustrative purposes, several aspects of this technology are depicted in the following figures.

[0007] Figure 1A and 1B Illustrated explanation of various aspects of the ADC system based on this technology.

[0008] Figure 1C The diagram illustrates the bit range of an ADC system based on various aspects of this technology.

[0009] Figure 2A and 2B A diagram illustrating the relationship between the input signal range and the output signal range, and demonstrating the jitter effects of various aspects of this technology.

[0010] Figure 3A , 3B 3C and 3D diagrams illustrate multiple charts of the spectrum of digital signals based on various aspects of this technology.

[0011] Figure 4A , 4B The 4C and 4D diagrams illustrate multiple charts representing the spectrum of digital signals according to various aspects of this technology. Detailed Implementation

[0012] The detailed description below is intended to illustrate various configurations of the present technology and is not intended to represent only the configurations in which the present technology can be practiced. The accompanying drawings are incorporated herein and form part of the detailed description, which contains specific details for providing a thorough understanding of the present technology. However, the present technology is not limited to the specific details set forth herein and can be practiced without one or more of said specific details. In some instances, structures and components are shown in block diagram form to avoid obscuring the concept of the present technology.

[0013] In this document, when an element is referred to as “connected” or “coupled” to another element, it will be understood that the element may be directly connected to the other element, or have additional intervening elements or components, and additional intervening processes between the illustrated components / processes. Furthermore, the embodiments described herein may include additional intervening elements and additional intervening processes between the illustrated components / processes / etc. In contrast, when an element is referred to as “directly connected” or “directly coupled” to another element, it should be understood that there are no intervening elements in the “direct” connection between the elements. However, the presence of a direct connection does not preclude the presence of other connections in which intervening elements may be present.

[0014] For narrowband data communication systems (e.g., wireless systems), high-performance and high-resolution ADCs are required to capture radio frequency (RF) signals and convert them into digital signals. With the advancement of CMOS technology, SAR ADCs are used due to low power consumption and minimal area requirements for substrates (e.g., circuit boards, integrated circuits, or other support materials on which or within which semiconductor devices are fabricated or attached). Time-staggered SAR ADCs can be implemented to achieve very high sampling frequencies, such as tens of GHz. RF direct sampling receivers provide low-power and high-performance wireless base stations.

[0015] Mismatches between SAR ADCs result in harmonic spurious signals throughout the time-interleaved ADC output spectrum. SAR ADCs may contain digital-to-analog converters (DACs). Although DACs can be calibrated, residual DAC calibration errors may prevent them from meeting the required spurious-free dynamic range (SFDR) specifications. Added jitter can be applied to the SAR ADC to smooth nonlinear errors, thereby reducing ADC harmonic spurious signals. One technique for applying the jitter described herein uses a split jitter method, in which two different modules generate two distinct jitter signals (e.g., a first jitter signal and a second jitter signal) to be added to the input signal. The first jitter signal has a lower random value, e.g., a positive or negative integer value with a smaller magnitude compared to the value of the second jitter signal. The second jitter signal has a higher random value, e.g., a positive or negative integer value with a larger magnitude compared to the value of the first jitter signal. In some embodiments, both the first and second jitter signals are added to the input signal of the SAR ADC. In some embodiments, only one of the first or second jitter signals is applied to the input signal before the DAC. In some embodiments, when the magnitude of the first jitter signal is presented in binary form, the first jitter signal has a lower random value that has non-zero bits in the least significant bit (LSB) segment and no non-zero bits in the most significant bit (MSB) segment. In some embodiments, as described below, when the magnitude of the second jitter signal is presented in binary form, the second jitter signal has a higher random value that has non-zero bits in the MSB segment and no non-zero bits in the LSB segment. In some embodiments, the magnitude of the number is the absolute value of the number.

[0016] In some embodiments, the SAR jitter range is determined based on the sensitive input signal range and the DAC mid-bit mismatch characteristics. Since the jitter signal is added to the analog domain, the maximum jitter range reduces the usable input signal range. The required minimum jitter step size for the first jitter signal is determined by the DAC low-bit mismatch characteristics. Using a single jitter signal to cover the required jitter range and provide the minimum jitter step size may suffer from unnecessarily reduced input signal dynamic range and may require additional jitter power. Therefore, the technique of using two jitter signals (e.g., two independent signals) (one jitter signal with a larger value and the other with a smaller value) prevents unnecessarily reduced input signal dynamic range and eliminates the need for additional jitter power. This technique can be implemented in systems (e.g., wireless base stations with 5G New Radio (NR) protocols as a non-limiting example) to improve SFDR due to SAR nonlinearity errors. In some embodiments, the component, circuitry, device, or module that converts a digital signal to an analog signal is a DAC. In some embodiments, the component, circuitry, device, or module that converts an analog signal to a digital signal is an ADC.

[0017] Figure 1A and 1B Illustrated ADC systems 100 and 170 according to various aspects of this technology. Figure 1AThe ADC system 100 includes a jitter generator module 185, which includes an MSB jitter generator device 104 and an LSB jitter generator device 106, both of which are coupled and controlled by a controller 102 using command signals 114 and 112, respectively. In some embodiments, the command signals include one or more instructions for instructing a receiver of the command signals to perform one or more tasks. The LSB jitter generator device 106 generates random values ​​107, such as random values ​​having a value occupying only LSB bits. In some embodiments, the LSB jitter generator device 106 generates random values ​​-14, -10, -6, -2, +2, +6, +10, +14, such as integer random values, such as random values ​​of integers having a value occupying only the first 4 bits (e.g., the four least significant bits from zero to three). Furthermore, the random values ​​generated by the LSB jitter generator device 106 contain only the non-zero bits of the four least significant bits. MSB jitter generator device 104 generates random values ​​105, such as random values ​​having a magnitude greater than the number of LSB bits. In some embodiments, MSB jitter generator device 104 generates random values ​​-56, -40, -24, -8, +8, +24, +40, +56, such as integer random values ​​having a magnitude of non-zero bits occupying only after the first three least significant bits (e.g., after the second bit). In some embodiments, bits greater than the LSB segment are portions of the MSB segment. In some embodiments, each of LSB jitter generator device 106 or MSB jitter generator device 104 includes a processor (not shown), and a random generator application running on the processor generates random values. In some embodiments, the random values ​​are not deterministic. In some embodiments, each of LSB jitter generator device 106 or MSB jitter generator device 104 includes circuitry that determines the random values ​​based on a physical random signal (e.g., based on current generated by thermal noise from the resistors of a circuit). In some embodiments, a single circuit is used to generate random values ​​for both the LSB jitter generator device 106 and the MSB jitter generator device 104.

[0018] In some embodiments, the MSB jitter generator device 104 generates a jitter value that has non-zero bits only in bits 3 through 5 and zero values ​​in bits 0 through 2 (e.g., non-zero bits are limited to bits 3 through 5). Therefore, the MSB segment is bits 3 through 5, and the LSB segment is bits 0 through 3, so the MSB segment overlaps the LSB segment by one bit, namely the 3rd bit. Therefore, the non-zero bits of the magnitude of the integer value generated by the MSB jitter generator device 104 are limited to the MSB segment. Furthermore, the non-zero bits of the integer value generated by the LSB jitter generator device 106 are limited to the LSB segment. In some embodiments, the MSB jitter generator device 104 generates a random value between -60 and +60, but does not generate any random value with non-zero values ​​in bits 0 and 1. In some embodiments, the LSB jitter generator device 106 generates a random value between -7 and +7, and generates a random value with a non-zero magnitude in bits 0 through 2. Therefore, the MSB segment consists of bits 2 to 5, and the LSB segment consists of bits 0 to 2. Thus, the MSB segment overlaps the LSB segment by one bit, namely the second bit. In some embodiments, the MSB jitter generator device 104 generates jitter values ​​that have non-zero bits only in the MSB segment, and the LSB jitter generator device 106 generates jitter values ​​that have non-zero bits only in the LSB segment. In some embodiments, the MSB segment has a first digit between 3 and 8, and the LSB segment has a second digit between 2 and 6. In some embodiments, the first digit comprises the upper half of the bit range of the ADC system 100 or ADC system 170, and the second digit comprises the lower half of the bit range. In some embodiments, if the bit range has 2k bits, then the lower half of the bit range is bits 0 to k-1, and the upper half of the bit range is bits k to 2k-1, and each bit in either the lower or upper half is zero or one. In some embodiments, each lower half bit has a lower position value compared to the position value of each upper half bit.

[0019] In some embodiments, the bit range is 12 bits, for example, bits 0 to 11. In some embodiments, the MSB segment is the upper half of the bit range of the ADC system 100, for example, the upper 6 bits, bits 6 to 11. In some embodiments, the LSB segment is the lower half of the bit range of the ADC system 100, for example, the lower 6 bits, bits 0 to 5. In some embodiments, the LSB segment is bits 0 to 3, and the MSB segment is bits 4 to 11. In some embodiments, the MSB segment contains only four bits of the upper half of the bit range, and the LSB segment contains only three bits of the lower half of the bit range. In some embodiments, the bit range has 24 bits or 48 bits, and the MSB segment contains the upper half of the bit range.

[0020] In some embodiments, controller 102 controls (e.g., specifies) the number of most significant bits, the number of least significant bits, and whether the most significant bits and least significant bits overlap or not (e.g., overlap is empty). Therefore, controller 102 can use command signals 114 and 112 to modify the jitter value of LSB jitter generator device 106 and the jitter value of MSB jitter generator device 104. The jitter value can be positive or negative. However, when MSB segments overlap with LSB segments, the jitter value is appropriate for either the MSB segment or the LSB segment, or both. ADC system 100 also includes switches 108 and 118 (shown as S2 and S1) controlled by controller 102, such that controller 102 can open or close the switches independently of each other. As shown, random value 107 reaches adder module 110 (e.g., algebraic sum module) via switch 108. Furthermore, random value 105 reaches adder module 110 via switch 118, and adder module 110 generates jitter sum value 128. Moreover, since random values ​​105 and 107 are digital signals, jitter sum value 128 is a digital jitter signal. In some embodiments, the MSB segment is the upper half or upper 7 / 12 of the bit range, and the LSB segment is the lower half of the bit range. In some embodiments, the MSB segment and LSB segment do not correspond to the exact upper and lower halves of the bit range, but the MSB segment covers a higher bit range compared to the LSB segment.

[0021] In some embodiments, controller 102 commands both switches 108 and 118 to close, and therefore, the sum of the signals equals the sum of random values ​​105 and 107. In some embodiments, controller 102 commands switch 108 to close and commands switch 118 to open, and therefore, the jitter sum 128 equals the random value 107. In some embodiments, controller 102 commands switch 118 to close via command signal 122 and commands switch 108 to open via command signal 116, and therefore, the jitter sum 128 equals the random value 105.

[0022] As described above, random values ​​105 and 107 are random numbers, such as random digital signals. Therefore, the jitter sum value 128 is also a random number, such as a random digital signal. The jitter sum value 128 is sent to a digital-to-analog converter (DAC) 140 to produce an output as a jitter sum signal 132, such as an analog signal representing the jitter sum value 128. The DAC 140 also receives a reference voltage 115 and generates the jitter sum signal 132, such as a jitter signal, based on the reference voltage 115. The ADC system 100 further includes a sample-and-hold (S / H) module 142 that receives an input signal 125, samples it, and then holds the input signal 125, generating a sampled input signal 123, such as a sample of the input signal 125. As shown, the adder module 120 receives the jitter sum signal 132 and the sampled input signal 123 (e.g., a sampled voltage). At the output of adder module 120, a sum of the sampled input signal 123 and the jitter signal 132 is generated, i.e., the sampled input plus the jitter signal 133 (e.g., the modified input signal). In some embodiments, the sampled input plus the jitter signal 133 is digitized by ADC system 100. In some embodiments, the bit range of ADC system 100 is the same as the bit range (e.g., the number of input bits) of DAC 140.

[0023] In some embodiments, the sampled input signal 123 is a sequence of rectangular pulses, each having a fixed duration T and a height (which is a sampled value of the input signal 125). In some embodiments, the jitter sum 128 is a sequence of random numbers, such as random values ​​that vary over time. Furthermore, in some embodiments, the jitter sum signal 132 is a sequence of rectangular pulses such that the height of the pulses is a random value of the jitter sum 128, and each pulse lasts for a duration T, where T is the sampling period of the sample and hold (S / H) module 142. Therefore, in some embodiments, the jitter sum signal 132 is a set of additional pulses, each having a duration T, and the height of these pulses is a random value. The jitter sum signal 132 is added to the sampled input signal 123 to produce an input plus jitter signal 133. Thus, for each duration T, a random value is generated, and rectangular pulses having a duration T and the generated random value as their height are added to the pulses of the sampled input signal 123. Therefore, for each duration T, a jitter sum 128 is generated, and the jitter sum 128 is added to the height of the pulse of the sampled input signal 123 to generate an input plus jitter signal 133.

[0024] like Figure 1AAs shown, the input, plus a jitter signal 133, is sent to the ADC module 160 to convert it into a digital output. As illustrated, the ADC module 160 generates a first digitized signal 146, which is a digital representation of the input plus the jitter signal 133 sent to a subtraction module 130 (e.g., an algebraic sum module). The subtraction module receives two values ​​and determines the difference between the two values, or receives two signals and determines another signal as the difference between the two signals. In some embodiments, the subtraction module 130 subtracts the jitter sum value 128 from the first digitized signal 146 to produce an output signal 152 (e.g., a digitized output signal), which is a digital representation of the input signal 125 of the ADC system 100. Therefore, subtracting the jitter sum value 128 originally added to the input signal 125 from the first digitized signal 146 (e.g., a signal value) produces the output signal 152 (e.g., an output value) as a digitized form of the input signal. In some embodiments, adding the jitter sum signal 132 helps reduce non-random distortion (e.g., nonlinearity) of the ADC.

[0025] Figure 1B ADC system 170 and Figure 1A The ADC system 170 is identical to the ADC system 100, except that it includes a spectrum detector 165 connected to the output signal 152. Additionally, Figure 1BThe components of an ADC module 160, including a comparator module 135, are shown. In some embodiments, as shown, the comparator module 135 has a non-inverting node 127 and an inverting node 121. At the output of the comparator module 135, a comparison signal 138 is the result of subtracting a first signal coupled to the inverting node 121 from a second signal coupled to the non-inverting node 127. An input plus jitter signal 133 is sent to the non-inverting node 127 of the comparator module 135. The comparator module 135 also receives an initial estimate (e.g., an initial approximation) of the input plus jitter signal 133 as a signal 148 through the inverting node 121. In some embodiments, the comparator module 135 determines a difference signal, which is the signal coupled to the non-inverting node 127 minus the signal coupled to the inverting node 121. The comparator module 135 compares the two input signals (e.g., signal 148 and the input plus jitter signal 133) and generates the comparison signal 138. In some embodiments, comparison signal 138 is the difference between the input plus jitter signal 133 and signal 148. When comparison signal 138 is positive, it indicates that the input plus jitter signal 133 is greater than signal 148 (e.g., estimated), and when comparison signal 138 is negative, it indicates that the input plus jitter signal 133 is less than the initial estimate. When comparison signal 138 is within a predefined (e.g., predetermined) range, signal 148 (e.g., the estimated signal) is acceptable, and the iterative method of digitizing the sample of the input plus jitter signal 133 is complete and can be terminated, and the next sample can be obtained, a jitter value added, and then digitized. However, when comparison signal 138 is not within the predefined range, the estimated signal is unacceptable, and the iterative method of digitizing the sample of the input plus jitter signal 133 is not complete. Therefore, the next estimate of the first digitized signal continues to be generated until the comparison signal is within the predefined range.

[0026] In some embodiments, the input plus jitter signal 133 is digitized by the ADC module 160, and a first digitized signal 146 is generated using an iterative method. In some embodiments, the sampling frequency is five to ten times slower than the clock signal 136 (Clk) coupled to the digitization device 155. In some embodiments, the digitization device 155 may be any hardware, software, or a combination of both for performing successive approximations to generate the digitized signal. Thus, during each sampling cycle, the sampled input plus jitter signal 133 is converted into a digital value, and an iteration for successive approximation is performed during the sampling cycle. The digital value of the sampled input plus jitter signal 133 can be determined before the end of the sampling cycle, and then the next input plus jitter signal 133 is sampled, and then the digital value is determined.

[0027] As shown, a comparison signal 138 is sent to a digitization device 155. The digitization device 155 also receives a clock signal 136 (Clk). Based on the comparison signal 138, the digitization device 155 can determine that successive approximation has been completed. By determining that successive approximation has been completed, the existing approximation (e.g., the current estimate) is maintained and sent as a first digitized signal 146 to the subtraction module 130. However, if the comparison signal 138 indicates that successive approximation has not been completed, based on the clock signal 136, the digitization device 155 enters a next state and generates a next approximation (e.g., the next estimate) in the next iteration (e.g., the next cycle of clock signal 136), and sends the next approximation to the DAC 150 via signal 143. The DAC 150 converts the approximation into an analog signal (e.g., signal 148) as the next estimate. As indicated above, iteration continues until the comparison signal 138 indicates that the iteration of successive approximation has been completed.

[0028] like Figure 1B As shown, as the input signal 125 is continuously sampled and digitized, the output signal 152 is sent to the spectrum detector 165 to generate the spectrum of the output signal 152. In some embodiments, DAC 140 is included in DAC 150. In some embodiments, the jitter sum 128 and signal 143 are time-multiplexed, and the result of the multiplexing is fed as input to DAC 150. The output of DAC 150 is fed into a time multiplexer to generate signal 148 and jitter sum signal 132.

[0029] Figure 1C Illustrated diagram of an ADC system (e.g., Figure 1A and 1B The bit range 180 is shown for ADC systems 100 and 170 respectively. Bit range 180 is from zero to n bits. Figure 1B The bit range of the ADC module 160 shown in the figure. In some embodiments, the bit range 180 has 12 bits, 16 bits, 24 bits or 32 bits, and therefore n is 11, 15, 23 or 31. Figure 1C LSB segment 182 and MSB segment 184 are shown. In some embodiments, LSB segment 182 and MSB segment 184 cover the entire bit range 180. In some embodiments, LSB segment 182 and MSB segment 184 overlap in segment 186. In some embodiments, LSB segment 182 and MSB segment 184 do not cover the entire bit range 180. In some embodiments, LSB segment 182 has 2 to 6 bits. In some embodiments, MSB segment 184 has 3 to 6 bits.

[0030] Figure 2A and 2BA diagram illustrating the relationship between the input signal range and the output signal range, and demonstrating the jitter effects of various aspects of this technology. Figure 2A and 2B Graphs 208 and 218 are shown respectively regarding the relationship between output range 202 and input range 204. Graphs 208 and 218 show the signal (e.g., voltage) after passing through the SAR ADC and the signal before applying the SAR ADC. Figure 2A Interruption 205 is shown in display area 206. Additionally... Figure 2A Demonstrates segmentation via MSB (e.g., Figure 1B Jitter is applied to the MSB segment 184 shown in the figure, which improves the interrupt in region 206 into line 210. Figure 2B Displays periodically repeating interruptions 205 in multiple regions 216. Figure 2B It also demonstrates how jitter can be applied in LSB segments (e.g., LSB segment 182) to improve interruptions in several regions 216 into lines 220.

[0031] Figure 3A , 3B 3C and 3D diagrams illustrate multiple charts of the spectrum of digital signals based on various aspects of this technology. Figure 3A , 3B The 3C and 3D diagrams illustrate the relationship between the magnitude of the spectrum at coordinate 302 and the frequency of the spectrum at 304. In some embodiments, the SAR ADC digitizes a noisy signal. The signal has a single frequency of 1.8 GHz, and the digitization results using different dithering schemes are shown in graphs 300, 320, 340, and 350. In each of these graphs, the single frequency of 1.8 GHz is displayed via input frequency component 306. Graphs 300, 320, 340, and 350 also show the white noise level 308. Figure 3A No jitter is used. Figure 3B In this configuration, only 3-bit MSB jitter with values ​​of -56, -40, -24, -8, +8, +24, +40, and +56 is used. As described, input frequency component 306 is the original input, and all other frequency components (e.g., additional frequency component 305) are caused by distortion. Furthermore, in Figure 3C No jitter is used. Figure 3D In this method, only 3-bit LSB jitter with values ​​of -14, -10, -6, -2, +2, +6, +10, and +14 is used. As shown, both individual MSB jitter and individual LSB jitter help clean up the digitized signal; however, in both cases, only one of the extra frequency components 305 caused by distortion remains, and less than five percent of the energy of the extra frequency component 305 remains.

[0032] Figure 4A ,4B The 4C and 4D diagrams illustrate multiple charts representing the spectrum of digital signals according to various aspects of this technology. Figure 4A , 4B Figures 4C and 4D illustrate the relationship between the magnitude of the spectrum at coordinate 302 and the frequency of the spectrum at 304. In some embodiments, the SAR ADC digitizes a noisy signal. The signal has a single frequency of 2 GHz, and figures 400, 425, 450, and 475 show the digitization results using different dithering schemes. In each of these figures, the single frequency of 2 GHz is displayed via input frequency component 306. Figures 400, 425, 450, and 475 also show the white noise level 308. Figure 4A No jitter is used. Figure 4B In this configuration, only MSB jitter is implemented. As described, input frequency component 306 is the original input, and all additional frequency components 305 are caused by distortion. Figure 4B As shown, more than half of the remaining 305 frequency components are due to distortion. Figure 4C In this case, only LSB jitter is implemented. Although compared with Figure 4B compared to, Figure 4C The number of additional frequency components 305 is slightly less, but still about half of the additional frequency components 305 remain. Figure 4D In this process, both MSB jitter and LSB jitter are implemented. As shown, when both MSB jitter and LSB jitter are used, almost all of the extra frequency components 305 are removed. Therefore, by implementing the combination of MSB jitter and LSB jitter, less than 10% of the number of extra frequency components 305 and less than 5% of the energy of the extra frequency components 305 remain.

[0033] In some embodiments, such as Figure 3A and 4A As shown, in addition to the input frequency component 306, the spectrum of the output signal 152 also includes an additional frequency component 305. In some embodiments, and returning to... Figure 1B Based on the fact that the ratio of the energy of the additional frequency component 305 to the energy of the input frequency component 306 is greater than a predetermined value (e.g., greater than 5%), the spectrum detector 165 sends a command signal 111 to the controller 102 to change the number of bits in the LSB segment 182 and / or the number of bits in the MSB segment 184 to change the jitter and signal 132 to reduce the energy of the additional frequency component 305. In some embodiments, the spectrum detector 165 determines the magnitude and energy of the spectrum of the output signal 152, which are the magnitude of the spectrum of the output signal 152 as a function of frequency and the spectral energy as a function of said frequency.

[0034] In some embodiments, the ADC system 170 (e.g., the system) is calibrated by applying an input signal 125 having an input frequency in, for example, a frequency range between 1.0 GHz and 2.0 GHz. The spectrum of the output signal 152 is determined by a spectrum detector 165. The ratio of the energy of the additional frequency component 305 to the energy of the input frequency component 306 is determined. If the ratio is not lower than a limit, the spectrum detector 165 sends a command signal 111 to the controller 102 to change the number of bits in the LSB segment 182 and / or the number of bits in the MSB segment 184. The spectrum detector 165 then re-determines the ratio of the energy of the additional frequency component 305 to the energy of the input frequency component 306. This step is repeated iteratively until the number of bits in the LSB segment 182 and MSB segment 184 that produces a ratio below a limit (e.g., less than 5%) is determined. In some embodiments, the iterative method is repeated until the number of bits in the LSB segment 182 and MSB segment 184 that minimizes the ratio of the energy of the additional frequency component 305 to the energy of the input frequency component 306 is determined. In some embodiments, an iterative method is performed for multiple frequencies (e.g., multiple frequencies within a frequency range), and the optimal number of bits for LSB segment 182 and MSB segment 184 is determined for the frequency range.

[0035] The technique discussed above provides a method for applying one or more jitter signals to the input signal of a SAR ADC before digitizing the input signal (e.g., quantizing and converting the quantized value into a digital form). By applying one or more jitter signals, this technique reduces nonlinear effects, harmonic spurious signals, and distortion of the SAR ADC. Furthermore, this technique reduces mismatch between SAR ADCs that occurs when using multiple SAR ADCs.

[0036] According to an aspect of the present technology, a system includes a jitter generator module, the jitter generator module including most significant bit (MSB) jitter generator means for generating a first random value and least significant bit (LSB) jitter generator means for generating a second random value. The system includes a first digital-to-analog converter (DAC) that receives the first random value and the second random value and generates a jitter sum signal based on the sum of the first random value and the second random value. The system further includes an analog-to-digital converter (ADC) that receives the jitter sum signal and the sum of a sampled input signal and generates a first digitized signal.

[0037] In one aspect of this technology, the system further includes a subtraction module for subtracting the sum of the first random value and the second random value from the first digitized signal to generate a digitized output signal. In another aspect of this technology, the first random value is an integer having a first value including non-zero bits in an MSB segment limited to the bit range of the first DAC, and the second random value is an integer having a second value including non-zero bits in an LSB segment limited to the bit range of the first DAC. In another aspect of this technology, the MSB jitter generator device generates an integer random value having non-zero bits in the MSB segment, and the LSB jitter generator device generates an integer random value having non-zero bits in the LSB segment. The MSB segment includes at least the upper half of the bit range, the LSB segment includes at least the lower half of the bit range, and the MSB segment overlaps the LSB segment by at least one bit. In another aspect of this technology, the sum of the jitter signal and the sampled input signal is a modified sampled input signal. The ADC includes a comparator module that receives an initial estimate of the first digitized signal and the modified sampled input signal, compares the initial estimate of the first digitized signal with the modified sampled input signal, and provides a comparison signal. In some embodiments, a non-zero bit is a bit with a non-zero value, for example, a bit value of one. The ADC also includes a digitizing device coupled to the comparator module, receiving the comparison signal and a clock signal, and based on the comparison signal, the digitizing device performs the following operations: in response to the comparison signal being within range, maintaining the current estimate of the first digitized signal and providing the current estimate of the first digitized signal at a first output of the digitizing device; or in response to the comparison signal not being within range, generating a next estimate of the first digitized signal at the next cycle of the clock signal and providing the next estimate of the first digitized signal at a second output of the digitizing device. The ADC also includes a second DAC coupled to the digitizing device, receiving the next estimate of the first digitized signal from the second output of the digitizing device and providing the next estimate of the first digitized signal to the comparator module. The generation of the next estimate of the first digitized signal continues until the comparison signal is within the range and the second DAC includes the first DAC. In one aspect of this technology, the system further includes a sample-and-hold (S / H) module that receives an input signal, samples the input signal, and provides the sampled input signal. The system also includes an adder module coupled to the S / H module and coupled to the first DAC.The adder module receives the sampled input signal and the jitter sum signal and provides the sum of the jitter sum signal and the sampled input signal.

[0038] According to an aspect of the present technology, a system includes: a digital-to-analog converter (DAC) having a bit range; an analog-to-digital converter (ADC); and a jitter generator module including a most significant bit (MSB) jitter generator device and a least significant bit (LSB) jitter generator device, the MSB jitter generator device generating a first integer random value having a value including a non-zero bit limited to a first bit segment in the MSB segment, the MSB segment including a first portion of the upper half of the bit range; the LSB jitter generator device generating a second integer random value having a value including a non-zero bit limited to a second bit segment in the LSB segment, the LSB segment including a second portion of the lower half of the bit range. The DAC receives the first integer random value and the second integer random value and generates a jitter signal based on the sum of the first integer random value and the second integer random value. The ADC receives the jitter signal and the sum of a sampled input signal and generates a first digitized signal. The system further includes a subtraction module, which is used to subtract the sum of the first integer random value and the second integer random value from the first digitized signal to generate a digitized output signal.

[0039] In one aspect of this technology, the jitter generator module further includes an adder module coupled to the MSB jitter generator device and the LSB jitter generator device, receiving a first integer random value and a second integer random value, generating a third integer random value equal to the sum of the first integer random value and the second integer random value, and providing the third integer random value to the DAC. The jitter generator module further includes: a first switch coupled between the MSB jitter generator device and the adder module; a second switch coupled between the LSB jitter generator device and the adder module; and a controller coupled to the first switch and the second switch. The controller independently opens and closes the first switch and the second switch, such that the third integer random value: when both the first switch and the second switch are closed, is equal to the sum of the first integer random value and the second integer random value; when the first switch is closed and the second switch is open, is equal to the first integer random value; or when the first switch is open and the second switch is closed, is equal to the second integer random value. In one aspect of this technology, the sum of the jitter signal and the sampled input signal is a modified input signal. The ADC includes a comparator module for receiving an initial estimate of the first digitized signal and the modified sampled input signal, comparing the initial estimate of the first digitized signal with the modified sampled input signal, and providing a comparison signal. The ADC also includes a digitizing device that receives the comparison signal and a clock signal. Based on the comparison signal, the digitizing device maintains a current estimate of the first digitized signal and provides the current estimate of the first digitized signal, or generates a next estimate of the first digitized signal at the next cycle of the clock signal and provides the next estimate of the first digitized signal. The ADC further includes a second DAC coupled to the digitizing device to receive the next estimate of the first digitized signal from the digitizing device and provide an analog form of the next estimate of the first digitized signal to the comparator module for further estimation. In one aspect of this technology, the system further includes a sample-and-hold (S / H) module for receiving an input signal, sampling and holding a sample of the input signal, and providing the sample of the input signal. In another aspect of this technology, the comparator module receives the modified sampled input signal via a non-inverting node of the comparator module. In yet another aspect of this technology, the bit range is 12 or 24, the MSB segment comprises the upper 7 / 12 of the bit range, and the LSB segment comprises the lower half of the bit range.In one aspect of this technology, the first digit is 4 and the second digit is 4, and the first digit and the second digit do not overlap. In another aspect of this technology, the bit range has 16 bits, 24 bits, or 32 bits, the MSB segment includes the upper half of the bit range, and the LSB segment includes the lower half of the bit range.

[0040] According to an aspect of the present technology, a system includes: a digital-to-analog converter (DAC) having a bit range; an analog-to-digital converter (ADC); and a most significant bit (MSB) jitter generator means for generating a first integer random value having a magnitude including a segment of non-zero bits limited to the bit range of MSB. The DAC receives the first integer random value and generates a jitter signal based on the first integer random value. The ADC receives the jitter signal and the sum of a sampled input signal and generates a first digitized signal.

[0041] In one aspect of this technology, the system further includes a subtraction module that subtracts the first integer random value from the first digitized signal to generate a digitized output signal. In another aspect of this technology, the system further includes a spectrum detector coupled to the digitized output signal to generate a spectrum of the digitized output signal. In another aspect of this technology, the system further includes a least significant bit (LSB) jitter generator for generating a second integer random value. The magnitude of the second integer random value has non-zero bits in LSB segments limited to the bit range. The DAC generates a jitter signal based on the sum of the first integer random value and the second integer random value. In another aspect of this technology, the system further includes a subtraction module that subtracts the sum of the first integer random value and the second integer random value from the first digitized signal to generate a digitized output signal. In another aspect of this technology, the system further includes a subtraction module and an adder module coupled to the MSB jitter generator and the LSB jitter generator. The output of the adder module is provided to the DAC to generate the jitter signal. The system further includes: a first switch coupled between the MSB jitter generator device and the adder module; and a second switch coupled between the LSB jitter generator device and the adder module. The system includes a controller coupled to the first and second switches to independently open and close the first and second switches, such that the output of the adder module is equal to the sum of a first random integer value and a second random integer value when both the first and second switches are closed; equal to the first random integer value when the first switch is closed and the second switch is open; or equal to the second random integer value when the first switch is open and the second switch is closed. The subtraction module subtracts the output of the adder module from the first digitized signal to generate a digitized output signal.

[0042] Those skilled in the art will understand that the various illustrative blocks, modules, elements, components, memory systems, and algorithms described herein can be implemented as electronic hardware, computer software, or a combination of both. To illustrate this interchangeability between hardware and software, various illustrative blocks, modules, elements, components, memory systems, and algorithms have generally been described above in terms of their functionality. Whether this functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art can implement the described functionality in varying ways for each specific application. Various components and blocks can be arranged in different ways (e.g., in different orders or divided in different ways) without departing from the scope of this art.

[0043] It should be understood that the specific order or hierarchy of blocks in the disclosed process is a diagrammatic illustration of the exemplary method. Based on design preferences, it will be understood that the specific order or hierarchy of blocks in the process may be rearranged, or that all illustrated blocks should be executed. Any of the blocks may be executed simultaneously. In one or more embodiments, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system components in the embodiments described above should not be construed as requiring such separation in all embodiments, and it should be understood that the described program components and system can generally be integrated together in a single hardware or software product or packaged into multiple hardware or software products.

[0044] As used in this specification and any claims of this application, the terms "base station," "receiver," "computer," "server," "processor," "memory," "module," "controller," "adder," "subtractor," "converter," "generator," and "comparator" all refer to electronic devices or other technical devices. These terms exclude persons or groups of people. For the purposes of this specification, the term "display" means displaying on an electronic device.

[0045] As used herein, the phrase “at least one of” preceding a series of items (using the terms “and” or “or” to separate any of the items) modifies the list as a whole, not each member of the list (i.e., each item). The phrase “at least one of” does not require selection of at least one of each of the listed items; rather, the phrase allows for the meaning of at least one of any of the items and / or at least one of any combination of the items and / or at least one of each of the items. By way of example, the phrases “at least one of A, B, and C” and “at least one of A, B, or C” each refer to: only A, only B, or only C; any combination of A, B, and C; and / or at least one of each of A, B, and C.

[0046] The predicates “configured to,” “operable to,” and “programmed to” do not imply any particular tangible or intangible modification of an object, but are intended to be used interchangeably. In one or more embodiments, a processor configured to monitor and control operations or components may also mean a processor programmed to monitor and control said operations or an operable processor to monitor and control said operations. Similarly, a processor configured to execute code may be constructed as a processor programmed to execute code or operable processor to execute code.

[0047] Phrases such as "on one hand," "the said aspect," "on the other hand," "some aspects," "one or more aspects," "an implementation," "the said implementation," "another implementation," "some implementations," "one or more implementations," "an embodiment," "the said embodiment," "another embodiment," "some embodiments," "one or more embodiments," "a configuration," "the said configuration," "another configuration," "some configurations," "one or more configurations," "the present technology," "the disclosure," and other variations thereof are used for convenience and do not imply that the disclosure associated with this phrase is necessary to the present technology or that the disclosure applies to all configurations of the present technology. The disclosure associated with this phrase may apply to all configurations or one or more configurations. The disclosure associated with this phrase may provide one or more instances. For example, phrases such as "on one hand" or "some aspects" may refer to one or more aspects and vice versa, and this similarly applies to other foregoing phrases.

[0048] The term “exemplary” is used herein to mean “serving as an example, illustration, or diagram.” Embodiments described herein as “exemplary” or “examples” are not necessarily to be construed as preferred or advantageous over other embodiments. Furthermore, with regard to the use of the terms “comprising,” “having,” etc., in the description or claims, this term is intended to be inclusive in a manner similar to the meaning of the term “comprising” as interpreted when “comprising” is used as a transitional word in a claim.

[0049] All structural and functional equivalents of the various aspects described throughout this disclosure that are known or subsequently known to those skilled in the art are expressly incorporated herein by reference and are intended to be covered by the claims. Furthermore, nothing disclosed herein is intended to be public, whether or not such disclosure is expressly stated in the claims. No claim element shall be construed in accordance with 35 U.S.SC §112(f) unless the element is expressly stated using the phrase “component for…” or, in the case of a memory system claim, the element is stated using the phrase “step for…”.

[0050] The preceding description is provided to enable those skilled in the art to practice the various aspects described herein. Those skilled in the art will readily understand the various modifications to these aspects, and the general principles defined herein can be applied to other aspects. Therefore, the claims are not intended to limit them to the aspects presented herein, but should be given the full scope consistent with the language of the claims, wherein a reference to an element in the singular is not intended to mean "one and only one" (unless specifically stated so), but rather "one or more". Unless specifically stated otherwise, the term "some" means one or more. Male pronouns (e.g., his) include female and gender-neutral pronouns (e.g., her and its), and vice versa. Titles and subtitles, if present, are for convenience only and do not limit this disclosure.

Claims

1. A system comprising: A jitter generator module, comprising: A most significant bit (MSB) jitter generator device configured to generate a first random value; A least significant bit (LSB) jitter generator device configured to generate a second random value; and A first digital-to-analog converter (DAC) configured to receive the first random value and the second random value and generate jitter and a signal based on the sum of the first random value and the second random value; and An analog-to-digital converter (ADC) is configured to receive the jitter and sum of the signal and the sampled input signal and generate a first digitized signal.

2. The system according to claim 1, further comprising: A subtraction module is configured to subtract the sum of the first random value and the second random value from the first digitized signal to generate a digitized output signal.

3. The system of claim 1, wherein the first random value is an integer having a first magnitude including a non-zero bit of an MSB segment limited to the bit range of the first DAC, and wherein the second random value is an integer having a second magnitude including a non-zero bit of an LSB segment limited to the bit range of the first digital-to-analog converter DAC.

4. The system of claim 3, wherein the MSB jitter generator device is configured to generate an integer random value having non-zero bits in the MSB segment, and the LSB jitter generator device is configured to generate an integer random value having non-zero bits in the LSB segment, wherein the MSB segment includes at least the upper half of the bit range, and the LSB segment includes at least the lower half of the bit range, and wherein the MSB segment overlaps the LSB segment by at least one bit.

5. The system of claim 1, wherein the sum of the jitter signal and the sampled input signal is a modified sampled input signal, and wherein the ADC comprises: A comparator module configured to receive an initial estimate of the first digitized signal and the modified sampled input signal, compare the initial estimate of the first digitized signal with the modified sampled input signal, and provide a comparison signal; A digitizing device coupled to the comparator module and configured to receive the comparison signal and a clock signal, wherein, based on the comparison signal, the digitizing device is configured to: In response to the comparison signal being within range, the current estimate of the first digitized signal is maintained and the current estimate of the first digitized signal is provided at the first output of the digitization device, or In response to the comparison signal being outside the range, a next estimate of the first digitized signal is generated in the next cycle of the clock signal, and the next estimate of the first digitized signal is provided at the second output of the digitization device; and A second DAC, coupled to the digitization device and configured to receive the next estimate of the first digitized signal from the second output of the digitization device and provide the next estimate of the first digitized signal to the comparator module, wherein the generation of the next estimate of the first digitized signal continues until the comparison signal is within the range, and wherein the second DAC includes the first digital-to-analog converter DAC.

6. The system according to claim 1, further comprising: A sample and hold (S / H) module configured to receive an input signal, sample the input signal, and provide the sampled input signal; and An adder module coupled to the S / H module and coupled to the first digital-to-analog converter (DAC), wherein the adder module is configured to receive the sampled input signal and the jitter sum signal and provide the sum of the jitter sum signal and the sampled input signal.

7. A system comprising: The first digital-to-analog converter (DAC) has a bit range; Analog-to-digital converter (ADC); A jitter generator module, comprising: A most significant bit (MSB) jitter generator device configured to generate a first integer random value having a magnitude including a non-zero bit limited to a first bit segment in an MSB segment, the MSB segment including a first portion of the upper half of the bit range; and A least significant bit (LSB) jitter generator device configured to generate a second integer random value having a magnitude including a non-zero bit limited to a second bit segment in an LSB segment, the LSB segment comprising a second portion of the lower half of the bit range, wherein: The first digital-to-analog converter (DAC) is configured to receive the first integer random value and the second integer random value and generate a jitter signal based on the sum of the first integer random value and the second integer random value; and The ADC is configured to receive the sum of the jitter signal and the sampled input signal and generate a first digitized signal; and A subtraction module is configured to subtract the sum of the first integer random value and the second integer random value from the first digitized signal to generate a digitized output signal.

8. The system of claim 7, wherein the jitter generator module further comprises: An adder module coupled to the MSB jitter generator device and the LSB jitter generator device and configured to receive the first integer random value and the second integer random value, generate a third integer random value equal to the sum of the first integer random value and the second integer random value, and provide the third integer random value to the first digital-to-analog converter (DAC). A first switch is coupled between the MSB jitter generator device and the adder module; A second switch is coupled between the LSB jitter generator device and the adder module; and A controller coupled to a first switch and a second switch, wherein the controller is configured to independently open and close the first switch and the second switch, such that the third integer random value is: When both the first and second switches are closed, the result is equal to the sum of the first and second integer random values. When the first switch is closed and the second switch is open, it equals the first integer random value. or When the first switch is open and the second switch is closed, it equals the second integer random value.

9. The system of claim 7, wherein the sum of the jitter signal and the sampled input signal is a modified sampled input signal, and wherein the ADC comprises: A comparator module configured to receive an initial estimate of the first digitized signal and a modified sampled input signal, compare the initial estimate of the first digitized signal with the modified sampled input signal, and provide a comparison signal; A digitizing device configured to receive the comparison signal and the clock signal, wherein, based on the comparison signal, the digitizing device is configured to: Maintain the current estimate of the first digitized signal and provide the current estimate of the first digitized signal, or At the next cycle of the clock signal, a next estimate of the first digitized signal is generated, and the next estimate of the first digitized signal is provided; and A second DAC is coupled to the digitizing device and configured to receive the next estimate of the first digitized signal from the digitizing device and provide the analog form of the next estimate of the first digitized signal to the comparator module for the next estimate.

10. The system of claim 9, further comprising: A sampling and holding (S / H) module configured to receive an input signal, sample and hold a sample of the input signal, and provide the sample of the input signal.

11. The system of claim 10, wherein the comparator module is configured to receive the modified sampled input signal via a non-inverting node of the comparator module.

12. The system of claim 7, wherein the bit range is 12 or 24, the MSB segment comprises the upper 7 / 12 of the bit range, and the LSB segment comprises the lower half of the bit range.

13. The system of claim 7, wherein the first digit is 4 and the second digit is 4, and wherein the first digit and the second digit do not overlap.

14. The system of claim 7, wherein the bit range has 16 bits, 24 bits, or 32 bits, the MSB segment includes the upper half of the bit range, and the LSB segment includes the lower half of the bit range.

15. A system comprising: A digital-to-analog converter (DAC) with a bit range; Analog-to-digital converter (ADC); A most significant bit (MSB) jitter generator device configured to generate a first integer random value, wherein the magnitude of the first integer random value has non-zero bits in an MSB segment limited to the bit range, wherein: The DAC is configured to receive the first integer random value and generate a jitter signal based on the first integer random value; and The ADC is configured to receive the sum of the jitter signal and the sampled input signal and generate a first digitized signal.

16. The system of claim 15, further comprising: A subtraction module configured to subtract the first integer random value from the first digitized signal to generate a digitized output signal.

17. The system of claim 16, further comprising: A spectrum detector coupled to the digitized output signal and configured to generate the spectrum of the digitized output signal.

18. The system of claim 15, further comprising: A least significant bit (LSB) jitter generator device configured to generate a second integer random value, wherein the magnitude of the second integer random value has non-zero bits in LSB segments limited to the bit range; and The DAC is configured to generate a jitter signal based on the sum of the first integer random value and the second integer random value.

19. The system of claim 18, further comprising: A subtraction module is configured to subtract the sum of the first integer random value and the second integer random value from the first digitized signal to generate a digitized output signal.

20. The system of claim 18, further comprising: Subtraction module; An adder module coupled to the MSB jitter generator device and the LSB jitter generator device, wherein the output of the adder module is provided to the DAC to generate the jitter signal; A first switch is coupled between the MSB jitter generator device and the adder module; A second switch is coupled between the LSB jitter generator device and the adder module; and A controller coupled to a first switch and a second switch, wherein the controller is configured to independently open and close the first switch and the second switch, such that the output of the adder module is: When both the first and second switches are closed, the result is equal to the sum of the first and second integer random values. When the first switch is closed and the second switch is open, it equals the first integer random value, or When the first switch is open and the second switch is closed, the value is equal to the second integer random value; and The subtraction module is configured to subtract the output of the adder module from the first digitized signal to produce a digitized output signal.

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