PAM4 signal modulation method, system, device, storage medium and program product

Abstract

The embodiments of the present application provide a modulation method, system, device, storage medium and program product of a PAM4 signal, which relate to the field of signal modulation circuit design, wherein the modulation method of the PAM4 signal includes: obtaining an input initial signal; performing serial-to-parallel conversion processing on the initial signal to obtain a synchronized first synchronization signal and a second synchronization signal; performing a first orthogonal demodulation processing on the first synchronization signal to obtain a first orthogonal signal corresponding to the first synchronization signal, and performing a second orthogonal demodulation processing on the second synchronization signal to obtain a second orthogonal signal corresponding to the second synchronization signal; based on the first orthogonal signal and the second orthogonal signal, determining a reference signal corresponding to the initial signal; periodically sampling the reference signal to obtain a PAM4 signal corresponding to the initial signal; adopting the above scheme solves the problem of low modulation accuracy of the PAM4 signal in the related art.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of signal modulation circuit design, and specifically, to a modulation method, system, device, storage medium, and program product for a PAM4 signal. Background Art

[0002] With the development of data centers, high-speed optical communications, and telecommunications data networks, high-speed serial data rates using NRZ (Non-Return to Zero) encoding have been continuously upgraded from the traditional 10Gbps per channel to 32Gbps per channel. Due to the explosive growth of data throughput, higher single-channel data communication rates are required. However, the channel loss and reflection introduction costs of 56G / 112G signals are too high, and the tolerance for channel crosstalk is greatly reduced. It is difficult for current NRZ technology to break through the single-channel 56G transmission rate. Therefore, the industry introduced PAM4 (4 Pulse Amplitude Modulation) technology to solve the problem. Therefore, with the support of the PAM4 encoding mode, the rate of each channel can directly support 56Gbps to 112Gbps. Then, the PAM4 signal modulation circuit has become a potential technical focus.

[0003] In the related art, the linear PAM4 modulation circuit based on linear coding is realized by multiplying and adding two NRZ signals, which requires the addition of two amplitudes with different multiples of ×1 and ×2, and finally outputs a PAM4 signal. Figure 3 As shown, the linear PAM4 modulation circuit outputs V out Can be regarded as the upper branch NRZ signal V in1 and the lower branch signal V in2 Addition via a multiplier-adder. Figure 4 The figure shows the level correspondence in linear coding, where the linear coding PAM4 signal "11" is used as an example to illustrate, which means that the upper branch NRZ signal is "1" and the lower branch NRZ signal is "1". Figure 1 As shown, the level of the upper branch NRZ signal is multiplied by 2, and the level of the lower branch NRZ signal is multiplied by 1, that is, 1x2+1=3, which determines that the PAM4 level corresponding to the linear coding PAM4 signal "11" is "3".

[0004] However, in the upper branch signal / lower branch signal, the previous signal may have a tail that affects the next signal, resulting in strong interference between adjacent signals, which in turn leads to a technical problem of low modulation accuracy of the PAM4 signal. Summary of the invention

[0005] The embodiments of the present application provide a PAM4 signal modulation method, system, device, storage medium, and program product to at least solve the technical problem of low modulation accuracy of PAM4 signals in the related art.

[0006] According to one embodiment of the present application, a modulation method for a PAM4 signal is provided, including: obtaining an input initial signal; performing serial-to-parallel conversion processing on the initial signal to obtain a synchronized first synchronization signal and a second synchronization signal; performing a first orthogonal demodulation processing on the first synchronization signal to obtain a first orthogonal signal corresponding to the first synchronization signal, and performing a second orthogonal demodulation processing on the second synchronization signal to obtain a second orthogonal signal corresponding to the second synchronization signal; determining a reference signal corresponding to the initial signal based on the first orthogonal signal and the second orthogonal signal; and periodically sampling the reference signal to obtain a PAM4 signal corresponding to the initial signal.

[0007] As an optional scheme, the serial-to-parallel conversion processing of the initial signal to obtain a synchronized first synchronization signal and a second synchronization signal includes: tapping the initial signal to obtain a first tapped signal and a second tapped signal, wherein the first tapped signal and the second tapped signal are alternately arranged in the initial signal; and waveform shaping processing is performed on the first tapped signal and the second tapped signal to obtain the first synchronization signal and the second synchronization signal.

[0008] As an optional scheme, the waveform shaping processing is performed on the first tap signal and the second tap signal to obtain the first synchronization signal and the second synchronization signal, including: data sampling of the first tap signal and the second tap signal, and signal alignment of the sampled first tap signal and the sampled second tap signal to obtain the aligned first synchronization signal and the second synchronization signal, wherein the signal alignment is used to align the clock periods of the sampled first tap signal and the sampled second tap signal.

[0009] As an optional scheme, performing a first orthogonal demodulation processing on the first synchronization signal to obtain a first orthogonal signal corresponding to the first synchronization signal includes: acquiring a cosine signal generated by a phase-locked loop; and using the cosine signal to perform an orthogonal demodulation processing on the first synchronization signal to obtain the first orthogonal signal.

[0010] As an optional scheme, the first orthogonal demodulation processing is performed on the second synchronization signal to obtain a second orthogonal signal corresponding to the second synchronization signal, including: performing phase shift processing on the cosine signal to obtain a sinusoidal signal generated by the phase-locked loop; and using the sinusoidal signal to perform orthogonal demodulation processing on the second synchronization signal to obtain the second orthogonal signal.

[0011] As an optional solution, determining the reference signal corresponding to the initial signal based on the first orthogonal signal and the second orthogonal signal includes: multiplying the first orthogonal signal and the second orthogonal signal to obtain the reference signal.

[0012] As an optional scheme, the periodic sampling of the reference signal to obtain the PAM4 signal corresponding to the initial signal includes: dividing the reference signal into 12 equal parts according to the period, wherein the first time interval of the divided reference signal is 1 / 12 of the second time interval of the reference signal; using the output pulse signal to sample the divided reference signal to obtain a candidate signal, wherein the pulse signal is output according to the first time interval; and performing amplitude sampling on the candidate signal to obtain the PAM4 signal.

[0013] As an optional solution, the using the output pulse signal to sample the divided reference signal to obtain the candidate signal includes: multiplying the pulse signal and the divided reference signal to obtain the candidate signal.

[0014] As an optional solution, the use of the output pulse signal to sample the divided reference signal to obtain the candidate signal includes: using the pulse signal and a switch gate to control the conduction of the divided reference signal to obtain the candidate signal.

[0015] As an optional scheme, the amplitude sampling of the candidate signal to obtain the PAM4 signal includes: sampling the center position of the candidate signal to obtain multiple level values; maintaining the multiple level values ​​for a preset time interval to obtain the PAM4 signal, wherein the preset time interval is the time interval of the pulse signal.

[0016] As an optional scheme, the frequency of the initial signal is f, the pulse width of the initial signal is 1 / 2f, the bit rate of the initial signal is 2f, the first time interval is 1 / 24f, the pulse width of the PAM4 signal is 1 / 12f, and the bit rate of the PAM4 signal is 24f.

[0017] According to another embodiment of the present application, a modulation system for a PAM4 signal is provided, characterized in that it includes a serial-to-parallel conversion circuit, a phase-locked loop module, a first multiplication module, a second multiplication module, a third multiplication module, a sampling gate circuit, an interval single pulse circuit, and a sampling and holding circuit, wherein the serial-to-parallel conversion circuit is used to tap the input initial signal and output two synchronous signals, wherein the two synchronous signals include a first synchronization signal and a second synchronization signal; the first multiplication module is connected to the serial-to-parallel conversion circuit and the phase-locked loop module, and is used to multiply the first synchronization signal output by the serial-to-parallel conversion circuit and the cosine signal output by the phase-locked loop module to obtain a first orthogonal signal; the second multiplication module is connected to the serial-to-parallel conversion circuit and the phase-locked loop module , used to multiply the second synchronization signal output by the serial-to-parallel conversion circuit and the sinusoidal signal output by the phase-locked loop module to obtain a second orthogonal signal; the third multiplication module is connected to the first multiplication module and the second multiplication module, used to multiply the first orthogonal signal and the second orthogonal signal to obtain a reference signal; the sampling gate circuit is connected to the third multiplication module, used to divide the reference signal into periods; the interval single pulse circuit is connected to the sampling gate circuit, used to input a pulse signal to the sampling gate circuit, and the pulse signal is used to sample the divided reference signal to obtain a candidate signal; the sample and hold circuit is connected to the sampling gate circuit, used to perform amplitude sampling on the candidate signal to obtain the PAM4 signal.

[0018] As an optional scheme, the modulation system of the PAM4 signal also includes a phase shift module, which is connected to the phase-locked loop module and the second multiplication module. The phase shift module is used to shift the cosine signal of the phase-locked loop module to obtain the sine signal, and input the sine signal into the second multiplication module.

[0019] As an optional solution, the serial-to-parallel conversion module includes a tapping circuit, and the tapping circuit is used to tap the initial signal in an alternate manner to obtain a first tapped signal and a second tapped signal.

[0020] As an optional solution, the serial-to-parallel conversion module further includes a sampling and shaping circuit, and the sampling and shaping circuit is used to perform signal alignment on the first tapped signal and the second tapped signal to obtain the aligned first synchronization signal and the second synchronization signal.

[0021] As an optional solution, the clock frequencies of the tapping circuit, the sampling and shaping circuit and the phase-locked loop are all f, and the clock frequencies of the sampling gate circuit, the interval single pulse circuit and the sampling and holding circuit are all 12f.

[0022] According to another embodiment of the present application, a modulation device for a PAM4 signal is provided, including: an acquisition unit, configured to acquire an input initial signal; a conversion unit, configured to perform serial-to-parallel conversion processing on the initial signal to obtain a synchronized first synchronization signal and a second synchronization signal; a demodulation unit, configured to perform a first orthogonal demodulation processing on the first synchronization signal to obtain a first orthogonal signal corresponding to the first synchronization signal, and to perform a second orthogonal demodulation processing on the second synchronization signal to obtain a second orthogonal signal corresponding to the second synchronization signal; a determination unit, configured to determine a reference signal corresponding to the initial signal based on the first orthogonal signal and the second orthogonal signal; and a sampling unit, configured to perform periodic sampling on the reference signal to obtain a PAM4 signal corresponding to the initial signal.

[0023] According to another embodiment of the present application, a computer-readable storage medium is provided, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when run.

[0024] According to another embodiment of the present application, an electronic device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0025] According to another embodiment of the present application, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the steps of the method described in each embodiment of the present application are implemented.

[0026] Through the embodiment provided by the present application, the input initial signal is first divided into a first synchronization signal and a second synchronization signal through serial-to-parallel conversion processing, and then the first synchronization signal is subjected to a first orthogonal demodulation processing and the second synchronization signal is subjected to a second orthogonal demodulation processing respectively to obtain a first orthogonal signal and a second orthogonal signal, and the reference signal corresponding to the initial signal is determined based on the first orthogonal signal and the second orthogonal signal, and the PAM4 signal corresponding to the initial signal is obtained after periodic sampling of the reference signal. Through the above-mentioned serial-to-parallel conversion processing and orthogonal demodulation processing, the original adjacent signals in the input initial signal are branched into two different parallel signals, avoiding the problem of strong interference between adjacent signals in the subsequent signal processing process, thereby achieving the technical effect of improving the modulation accuracy of the PAM4 signal and solving the technical problem of low modulation accuracy of the PAM4 signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a hardware structure block diagram of a modulation method of a PAM4 signal according to an embodiment of the present application;

[0028] Figure 2 is a flow chart of a modulation method of a PAM4 signal according to the present application;

[0029] Figure 3 is a schematic diagram of a modulation method of a PAM4 signal according to the present application;

[0030] Figure 4 is a schematic diagram of a modulation method of a PAM4 signal according to the present application;

[0031] Figure 5 is a schematic diagram of a modulation method of a PAM4 signal according to the present application;

[0032] Figure 6 is a schematic diagram of a modulation method of a PAM4 signal according to the present application;

[0033] Figure 7 is a schematic diagram of a modulation method of a PAM4 signal according to the present application;

[0034] Figure 8 is a schematic diagram of a modulation method of a PAM4 signal according to the present application;

[0035] Fig. 9 is a schematic diagram of a modulation method of a PAM4 signal according to the present application;

[0036] Fig.10 is a schematic diagram of a modulation method of a PAM4 signal according to the present application;

[0037] Fig.11 is a schematic diagram of a modulation method of a PAM4 signal according to the present application;

[0038] Fig.12 It is a structural block diagram of a modulation device for a PAM4 signal according to an embodiment of the present application. DETAILED DESCRIPTION

[0039] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0040] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0041] The method embodiments provided in the embodiments of the present application can be executed in a computer terminal or a similar computing device. Taking running on a computer terminal as an example, Figure 1 1 is a hardware structure block diagram of a computer terminal of a PAM4 signal modulation method according to an embodiment of the present application. Figure 1 As shown, the computer terminal may include one or more ( Figure 1 Only one is shown in the figure) a processor 102 (the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, wherein the above-mentioned computer terminal may also include a transmission device 106 and an input and output device 108 for communication functions. It can be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the above-mentioned computer terminal. Figure 1 More or fewer components as shown, or with Figure 1 Different configurations are shown.

[0042] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the method for determining the mapping relationship in the embodiment of the present application. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, to implement the above method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories may be connected to the computer terminal via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0043] The transmission device 106 is used to receive or send data via a network. The specific example of the above network may include a wireless network provided by a communication provider of a computer terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0044] As an optional solution, the modulation method of the PAM4 signal includes the following specific steps:

[0045] Step S202, obtaining an input initial signal;

[0046] Step S204, performing serial-to-parallel conversion on the initial signal to obtain a synchronized first synchronization signal and a second synchronization signal;

[0047] Step S206, performing a first orthogonal demodulation process on the first synchronization signal to obtain a first orthogonal signal corresponding to the first synchronization signal, and performing a second orthogonal demodulation process on the second synchronization signal to obtain a second orthogonal signal corresponding to the second synchronization signal;

[0048] Step S208, determining a reference signal corresponding to the initial signal based on the first orthogonal signal and the second orthogonal signal;

[0049] Step S210: periodically sample the reference signal to obtain a PAM4 signal corresponding to the initial signal.

[0050] Optionally, in this embodiment, the serial-to-parallel conversion process can be implemented based on, but not limited to, a serial-to-parallel conversion circuit, and is used to tap the input initial signal to obtain a synchronized first synchronization signal and a second synchronization signal, wherein, in the tapping process, the input initial signal can be firstly divided into two parallel signals based on a tapping circuit included in the serial-to-parallel conversion circuit, but not limited to, due to the alternating distribution of the tapping circuit, one of the two parallel signals will lag behind the other signal by one clock cycle. Furthermore, in order to ensure the synchronous processing of the two parallel signals, the two parallel signals can also be subjected to data sampling and waveform shaping processing based on, but not limited to, a sampling and shaping circuit included in the serial-to-parallel conversion circuit to obtain synchronous signals, i.e., the synchronized first synchronization signal and the second synchronization signal.

[0051] To further illustrate, assuming that the input initial signal is "123456", the first synchronization signal obtained after serial-to-parallel conversion is "135" and the second synchronization signal is "246". It can be understood that the signal content corresponding to the first synchronization signal and the signal content corresponding to the second synchronization signal are staggered in the signal content corresponding to the initial signal.

[0052] Optionally, in this embodiment, the orthogonal demodulation process may be, but is not limited to, used to indicate that an original synchronization signal is processed based on a signal provided by a phase-locked loop to obtain an orthogonal signal corresponding to the original synchronization signal.

[0053] It should be noted that the first orthogonal demodulation processing can be, but is not limited to, used to indicate the use of a cosine signal generated by a phase-locked loop to perform orthogonal demodulation processing on the first synchronization signal to obtain a first orthogonal signal corresponding to the first synchronization signal; the first orthogonal demodulation processing can be, but is not limited to, used to indicate the use of a sine signal generated by a phase-locked loop to perform orthogonal demodulation processing on the second synchronization signal to obtain a second orthogonal signal corresponding to the second synchronization signal.

[0054] Optionally, in this embodiment, based on the first orthogonal signal and the second orthogonal signal, a reference signal corresponding to the initial signal is determined, which may include but is not limited to multiplying the first orthogonal signal and the second orthogonal signal to obtain a reference signal to eliminate the influence of the orthogonal phase.

[0055] For further explanation, assuming that the first synchronization signal is V m1 , the first synchronization signal V m1 The corresponding first orthogonal signal is cos(ω c t), the second synchronization signal is V m2 , the first synchronization signal V m2 The corresponding second orthogonal signal is sin(ω c t), where ω c is the frequency of the phase-locked loop output. Then the reference signal Vm can be expressed as Vm=±1 / 2sin(2ω c t) = ±cos(ω c t) sin(ω c t).

[0056] It should be noted that before the first orthogonal signal and the second orthogonal signal are multiplied, the first orthogonal signal and the second orthogonal signal can also be subjected to amplitude processing through, but not limited to, a synchronization signal. The frequency of the synchronization signal and the first orthogonal signal and the second orthogonal signal are the same, and the amplitude of the processed first orthogonal signal and the second orthogonal signal is ±1.

[0057] Optionally, in this embodiment, the reference signal is periodically sampled to obtain a PAM4 signal corresponding to the initial signal, which may include but is not limited to: first dividing the reference signal into several equal parts according to the period, and then using the output pulse signal to sample the divided reference signal to obtain a candidate signal, sampling the candidate signal at the center position to obtain multiple level values; and maintaining the multiple level values ​​for a preset time to obtain a PAM4 signal.

[0058] It can be understood that the above sampling of the candidate signal at the center position to obtain multiple level values ​​can balance the DC component of the level; the multiple level values ​​are maintained for a preset time to obtain a PAM4 signal, and a PAM4 signal with a corresponding pulse width can be obtained; and in this process, the signal rate of the obtained PAM4 will be several times the signal rate of the input initial signal, which greatly improves the signal rate.

[0059] Through the embodiment provided by the present application, the input initial signal is first divided into a first synchronization signal and a second synchronization signal through serial-to-parallel conversion processing, and then the first synchronization signal is subjected to a first orthogonal demodulation processing and the second synchronization signal is subjected to a second orthogonal demodulation processing respectively to obtain a first orthogonal signal and a second orthogonal signal, and the reference signal corresponding to the initial signal is determined based on the first orthogonal signal and the second orthogonal signal, and the PAM4 signal corresponding to the initial signal is obtained after periodic sampling of the reference signal. Through the above-mentioned serial-to-parallel conversion processing and orthogonal demodulation processing, the original adjacent signals in the input initial signal are branched into two different parallel signals, avoiding the problem of strong interference between adjacent signals in the subsequent signal processing process, thereby achieving the technical effect of improving the modulation accuracy of the PAM4 signal.

[0060] As an optional solution, performing serial-to-parallel conversion on the initial signal to obtain a synchronized first synchronization signal and a second synchronization signal includes:

[0061] Performing tapping processing on the initial signal to obtain a first tapped signal and a second tapped signal, wherein the first tapped signal and the second tapped signal are alternately arranged in the initial signal;

[0062] The first tapped signal and the second tapped signal are subjected to waveform shaping processing to obtain the first synchronization signal and the second synchronization signal.

[0063] Optionally, in this embodiment, the serial-to-parallel conversion processing may be, but is not limited to, implemented based on a serial-to-parallel conversion circuit, and the serial-to-parallel conversion circuit may be, but is not limited to, including a tapping circuit and a sampling shaping circuit, wherein the tapping circuit may be, but is not limited to, a 1:2 tapping circuit.

[0064] Optionally, in this embodiment, the input initial signal is divided into two parallel signals based on the tapping circuit. Due to the alternating distribution of the tapping circuit, one of the two parallel signals lags behind the other by one clock cycle. In order to ensure the synchronous processing of the two parallel signals, the two parallel signals are subjected to data sampling and waveform shaping processing based on the sampling and shaping circuit to obtain synchronous signals, i.e., the first synchronous signal and the second synchronous signal.

[0065] To further illustrate, assuming that the input initial signal is "123456", the first tapped signal obtained after tapping is "135" and the second tapped signal is "246". It can be understood that the first tapped signal and the second tapped signal are arranged alternately in the initial signal, that is, the signal content corresponding to the first tapped signal and the signal content corresponding to the second tapped signal are arranged alternately in the signal content corresponding to the initial signal.

[0066] Through the embodiments provided in the present application, the initial signal is tapped to obtain a first tapped signal and a second tapped signal, so that the originally adjacent signals in the input initial signal are tapped into two different parallel signals, thereby achieving the technical effect of eliminating or weakening strong interference between adjacent signals in the subsequent signal processing process; and, the first tapped signal and the second tapped signal are subjected to waveform shaping processing, thereby achieving the purpose of ensuring signal synchronization.

[0067] As an optional solution, the performing waveform shaping processing on the first tap signal and the second tap signal to obtain the first synchronization signal and the second synchronization signal includes:

[0068] Data sampling is performed on the first tap signal and the second tap signal, and signal alignment is performed on the sampled first tap signal and the sampled second tap signal to obtain the aligned first synchronization signal and the second synchronization signal, wherein the signal alignment is used to align the clock periods of the sampled first tap signal and the sampled second tap signal.

[0069] Optionally, in this embodiment, due to the alternating distribution of the tapping circuit, one of the two parallel signals lags behind the other signal by one clock cycle.

[0070] Optionally, in this embodiment, the signal alignment is performed on the sampled first tap signal and the sampled second tap signal, which may be but is not limited to indicating adjusting the tap signal that lags by one clock cycle to align it with the tap signal that is not lagged.

[0071] To further illustrate, Figure 5As shown, the initial signal 502 includes signal contents "a0, a1, a2, a3, a4, a5", and the first tapped signal 504 and the second tapped signal 506 are obtained after the tapping process, wherein the first tapped signal 504 is a tapped signal that lags behind by one clock cycle. The first tapped signal 504 is further adjusted to be aligned with the second tapped signal 506, to obtain the aligned first tapped signal 508 and the aligned second tapped signal 510, i.e., the first synchronization signal and the second synchronization signal.

[0072] Through the embodiments provided in the present application, the purpose of clock alignment of the first tap signal and the second tap signal is achieved through sampling and shaping processing, thereby ensuring the accuracy of subsequent signal processing based on the aligned first synchronization signal and the second synchronization signal, thereby improving the technical effect of the modulation accuracy of the PAM4 signal.

[0073] As an optional solution, performing a first orthogonal demodulation process on the first synchronization signal to obtain a first orthogonal signal corresponding to the first synchronization signal includes:

[0074] Get the cosine signal generated by the phase-locked loop;

[0075] The first synchronization signal is orthogonally demodulated using the cosine signal to obtain the first orthogonal signal.

[0076] Optionally, in this embodiment, a phase-locked loop (PLL for short) is an electronic circuit used for synchronizing phases.

[0077] Optionally, in this embodiment, the cosine signal generated by the phase-locked loop is used to perform orthogonal demodulation processing on the first synchronization signal, and a first orthogonal signal corresponding to the first synchronization signal is outputted.

[0078] Through the embodiments provided in the present application, the first synchronization signal is orthogonally demodulated by the cosine signal generated by the phase-locked loop to obtain a first orthogonal signal, and then a reference signal is determined based on the first orthogonal signal to serve as a signal source for periodic sampling during PAM4 signal modulation, thereby improving the accuracy of PAM4 signal modulation.

[0079] As an optional solution, performing a first orthogonal demodulation process on the second synchronization signal to obtain a second orthogonal signal corresponding to the second synchronization signal includes:

[0080] Performing phase shift processing on the cosine signal to obtain a sine signal generated by the phase-locked loop;

[0081] The second synchronization signal is orthogonally demodulated using the sinusoidal signal to obtain the second orthogonal signal.

[0082] Optionally, in this embodiment, it is possible but not limited to first acquiring a cosine signal generated by a phase-locked loop, and then using a phase shift module to perform phase shift processing on the cosine signal to obtain a sine signal generated by the phase-locked loop, wherein the phase shift processing is used to indicate a phase information shifted by -π / 2.

[0083] Optionally, in this embodiment, a sinusoidal signal generated by a phase-locked loop is used to perform orthogonal demodulation processing on the second synchronization signal, and a second orthogonal signal corresponding to the second synchronization signal is outputted.

[0084] Through the embodiments provided in the present application, a sine signal is obtained by phase shifting the cosine signal generated by a phase-locked loop, and the second synchronization signal is orthogonally demodulated using the sine signal to obtain a second orthogonal signal. Then, a reference signal is determined based on the second orthogonal signal to serve as a signal source for periodic sampling in the PAM4 signal modulation process, thereby improving the accuracy of PAM4 signal modulation.

[0085] As an optional solution, determining the reference signal corresponding to the initial signal based on the first orthogonal signal and the second orthogonal signal includes:

[0086] The first orthogonal signal and the second orthogonal signal are multiplied to obtain the reference signal.

[0087] Optionally, in this embodiment, based on the first orthogonal signal and the second orthogonal signal, a reference signal corresponding to the initial signal is determined, which may include but is not limited to multiplying the first orthogonal signal and the second orthogonal signal to obtain a reference signal to eliminate the influence of the orthogonal phase.

[0088] For further explanation, assuming that the first synchronization signal is V m1 , the first synchronization signal V m1 The corresponding first orthogonal signal is cos(ω c t), the second synchronization signal is V m2 , the first synchronization signal V m2 The corresponding second orthogonal signal is sin(ω c t), where ωc is the frequency of the phase-locked loop output. Then the reference signal Vm can be expressed as Vm=±1 / 2sin(2ω c t) = ±cos(ω c t)· sin(ω c t).

[0089] It should be noted that before the first orthogonal signal and the second orthogonal signal are multiplied, the first orthogonal signal and the second orthogonal signal can also be subjected to amplitude processing through, but not limited to, a synchronization signal. The frequency of the synchronization signal and the first orthogonal signal and the second orthogonal signal are the same, and the amplitude of the processed first orthogonal signal and the second orthogonal signal is ±1.

[0090] Through the embodiments provided in the present application, a reference signal is obtained by multiplying the first orthogonal signal and the second orthogonal signal to serve as a signal source for periodic sampling during PAM4 signal modulation, thereby improving the accuracy of PAM4 signal modulation.

[0091] As an optional solution, periodically sampling the reference signal to obtain a PAM4 signal corresponding to the initial signal includes:

[0092] Divide the reference signal into 12 equal parts according to the period, wherein the first time interval of the divided reference signal is 1 / 12 of the second time interval of the reference signal;

[0093] Using the output pulse signal, sampling the divided reference signal to obtain a candidate signal, wherein the pulse signal is output according to the first time interval;

[0094] Perform amplitude sampling on the candidate signal to obtain the PAM4 signal.

[0095] Optionally, in this embodiment, the reference signal may be divided into 12 equal parts according to a period using, but not limited to, a sampling gate circuit, wherein a first time interval of the divided reference signal is 1 / 12 of a second time interval of the reference signal.

[0096] It can be understood that if the frequency of the input initial signal is f, for the reference signal, its second time interval is 1 / 2f, and the first time interval of the divided reference signal is 1 / 24f.

[0097] Optionally, in this embodiment, the pulse signal can be but is not limited to a signal output by an interval single pulse circuit, which is used to input into a sampling gate circuit to sample the divided reference signal to obtain a candidate signal, wherein the pulse signal is output according to a first time interval.

[0098] It should be noted that the amplitude of the candidate signal is sampled to obtain a PAM4 signal.

[0099] It should also be noted that for the initial signal with a frequency of f, the pulse width is 1 / 2f, and the bit rate is 2f. Compared with the input signal, the pulse width of the PAM4 signal output by this embodiment is 1 / 12f, and the bit rate is 12 times the input signal rate, that is, 24f.

[0100] Through the embodiments provided in the present application, by dividing the reference signal and using a pulse signal for sampling and amplitude sampling, the signal rate of the obtained PAM4 signal is greatly improved, thereby achieving the technical effect of improving the modulation efficiency of the PAM4 signal.

[0101] As an optional solution, the using the output pulse signal to sample the divided reference signal to obtain the candidate signal includes:

[0102] The pulse signal and the divided reference signal are multiplied to obtain the candidate signal.

[0103] Optionally, in this embodiment, before the pulse signal and the divided reference signal are multiplied, it is ensured that the pulse signal is time-aligned with the divided reference signal.

[0104] Optionally, in this embodiment, when the pulse signal and the divided reference signal are multiplied, point-by-point multiplication can be performed but is not limited to it, that is, the values ​​of the pulse signal and the divided reference signal at the same time point are multiplied to obtain the value of the candidate signal at the corresponding time point.

[0105] According to the embodiment provided in the present application, a pulse signal and a divided reference signal are multiplied to achieve fast sampling of the signal.

[0106] As an optional solution, the using the output pulse signal to sample the divided reference signal to obtain the candidate signal includes:

[0107] The pulse signal and the switch gate are used to control the conduction of the divided reference signal to obtain the candidate signal.

[0108] Optionally, in this embodiment, the reference signal can be divided first but not limited to obtain multiple sub-signals, and then the conduction of the multiple sub-signals can be controlled by using the pulse signal and the state of the switch gate, wherein when the switch gate is open, the conduction of the sub-signal is allowed, and when the switch gate is closed, the conduction of the sub-signal is prohibited.

[0109] Optionally, in this embodiment, the turned-on sub-signals are accumulated to obtain a candidate signal.

[0110] Through the embodiments provided in the present application, pulse signals and switch gates are used to effectively control the conduction of the divided reference signals to obtain candidate signals, thereby achieving efficient and accurate sampling of the signals.

[0111] As an optional solution, the amplitude sampling of the candidate signal to obtain the PAM4 signal includes:

[0112] Sampling the candidate signal at a center position to obtain multiple level values;

[0113] The multiple level values ​​are maintained for a preset time interval to obtain the PAM4 signal, wherein the preset time interval is a time interval of the pulse signal.

[0114] Optionally, in this embodiment, the candidate signal may be amplitude sampled using a sample-and-hold circuit but is not limited thereto, wherein the sampling point of the sample-and-hold circuit is placed at the center of the candidate signal level to balance the DC component of the level and obtain multiple level values.

[0115] Optionally, in this embodiment, each level value among the multiple level values ​​is maintained for a preset time interval, that is, the interval level values ​​of the preset time interval are equally extended, that is, the level values ​​corresponding to the non-jumping time points within the preset time interval are all maintained level values.

[0116] Through the embodiments provided in the present application, the purpose of balancing the DC level can be achieved through amplitude sampling, and the sampled level value is maintained to determine the PAM4 signal of the corresponding pulse width and bit rate.

[0117] As an optional scheme, the frequency of the initial signal is f, the pulse width of the initial signal is 1 / 2f, the bit rate of the initial signal is 2f, the first time interval is 1 / 24f, the pulse width of the PAM4 signal is 1 / 12f, and the bit rate of the PAM4 signal is 24f.

[0118] Through the embodiments provided in the present application, the signal rate of the obtained PAM4 signal is greatly improved, thereby achieving the technical effect of improving the modulation efficiency of the PAM4 signal.

[0119] As an optional solution, the present application also provides a PAM4 signal modulation system, including a serial-to-parallel conversion circuit, a phase-locked loop module, a first multiplication module, a second multiplication module, a third multiplication module, a sampling gate circuit, an interval single pulse circuit, and a sample-and-hold circuit.

[0120] The serial-to-parallel conversion circuit is used to tap the input initial signal and output two synchronous signals, wherein the two synchronous signals include a first synchronous signal and a second synchronous signal.

[0121] The first multiplication module is connected to the serial-to-parallel conversion circuit and the phase-locked loop module, and is used to multiply the first synchronization signal output by the serial-to-parallel conversion circuit and the cosine signal output by the phase-locked loop module to obtain a first orthogonal signal.

[0122] The second multiplication module is connected to the serial-to-parallel conversion circuit and the phase-locked loop module, and is used to multiply the second synchronization signal output by the serial-to-parallel conversion circuit and the sinusoidal signal output by the phase-locked loop module to obtain a second orthogonal signal.

[0123] The third multiplication module is connected to the first multiplication module and the second multiplication module, and is used to perform multiplication processing on the first orthogonal signal and the second orthogonal signal to obtain a reference signal.

[0124] The sampling gate circuit is connected to the third multiplication module and is used to divide the reference signal into periods.

[0125] The interval single pulse circuit is connected to the sampling gate circuit and is used to input a pulse signal to the sampling gate circuit. The pulse signal is used to sample the divided reference signal to obtain a candidate signal.

[0126] The sample-and-hold circuit is connected to the sampling gate circuit and is used to perform amplitude sampling on the candidate signal to obtain the PAM4 signal.

[0127] To further illustrate, Figure 6 : is a logic block diagram of the modulation system of the above-mentioned PAM4 signal, wherein after the system is powered on, the signal generator ( Figure 6 (not shown) generates an input signal V with a frequency of f in (Random signal generated by pseudo-random sequence). Input signal V in First, enter the orthogonal circuit, where the orthogonal circuit is composed of a serial-to-parallel conversion circuit, a phase-locked loop module, a phase shift module, a first multiplication module, a second multiplication module and a third multiplication module. The serial-to-parallel conversion circuit can include but is not limited to a 1:2 tapping circuit and a sampling shaping circuit, and the phase shift module can also be integrated in the phase-locked loop module but is not limited to it. This embodiment does not limit this.

[0128] The phase-locked loop module provides a sine signal and a cosine signal, wherein the cosine signal is directly generated by the phase-locked loop module, and the sine signal is generated by shifting the phase of the cosine signal by -π / 2 through the phase shift module.

[0129] The input signal passes through the 1:2 tapping circuit in the serial-to-parallel conversion circuit (such as Figure 7 1:2 DeMUX) into two parallel signals, such as Figure 7 The V m1 and V m2 Due to the alternating distribution of the 1:2 tapping circuit, the signal V m2 Compared to the signal V m1 In order to ensure the synchronous processing of the two signals, the sampling and shaping circuit again processes the signal V m1 and Vm2 Perform data sampling and waveform shaping processing (i.e. Figure 7 The sampling shaping shown in the figure) obtains the synchronization signal V m11 and V m21 , its timing process is as follows Figure 5 As shown, no further description is given here.

[0130] It should be noted that before the first synchronization signal output by the serial-to-parallel conversion circuit and the cosine signal output by the phase-locked loop module are multiplied, a synchronization signal with a secondary value of ±1 (frequency and signal V m11 and V m21 The amplitude is adjusted by using the same

[0131] Further, in the first multiplication module, the cosine signal cos(ω c t) and signal V m11 Multiply, and use the sine signal sin(ω c t) and signal V m21 The multiplication result of the first multiplication module and the multiplication result of the second multiplication module are multiplied in the third multiplication module to obtain a signal V m , signal V m The waveform diagram is as follows Figure 8 As shown, where ω c is the phase-locked loop clock frequency.

[0132] Get signal V m After that, the next step is to sample it. First, the sampling gate circuit converts the signal V m The period is divided into 12 equal parts, that is, the time interval of each part is (1 / 2f) / 12.

[0133] The interval single pulse circuit outputs a pulse signal V according to the time interval p . Pulse signal V p The waveform diagram is as follows Fig. 9 As shown. Using the pulse signal V p For signal V m Sampling can be performed, but is not limited to, directly multiplying to obtain the output signal V s , but not limited to, can also be combined with the switch gate to use the signal V p Control signal V m The output signal V s , signal V s The waveform diagram is as follows Fig.10 shown.

[0134] Furthermore, the signal Vs is sampled and held using a sample-and-hold circuit. During this process, the sampling point is placed at the exact center of the signal level to balance the DC component of the level. The sampled level value is held for a time interval equal to the pulse signal. In this way, a PAM4 signal with a pulse width of (1 / 2f) / 6 and a bit rate of 12×2f can be obtained. The waveform diagram of the PAM4 signal is shown in the figure below. Fig.11 shown.

[0135] It should be noted that the pulse width of the input signal Vin is 1 / 2f, so the bit rate is 2f. Compared with the input signal Vin, the output PAM4 signal rate is 12 times the input signal rate. Under the traditional modulation method, the PAM4 signal rate is twice the input signal rate. This method greatly improves the signal rate.

[0136] It should also be noted that, considering that the frequency of the synchronization signal and the frequency of the orthogonal signal are the same, that is, the clock frequency of the 1:2 tapping circuit and the sampling shaping circuit in the serial-to-parallel conversion circuit and the clock frequency of the phase-locked loop are all f. For simple single pulse circuits, sampling gate circuits, and sample-and-hold circuits, the clock frequency is 12f. Compared with traditional modulation methods, in order to achieve a PAM4 signal with a bit rate of 12×2f, the clock frequency of the entire circuit needs to be 12f. Therefore, in comparison, this method only requires the local circuit clock frequency to be set to 12f, and there is no need to set the clock frequency of 12f for all circuits, which reduces the difficulty of designing the clock circuit (the clock circuit design difficulty of a clock frequency of 12f is higher).

[0137] It should be noted that the modulation system of the PAM4 signal includes an orthogonal circuit, an interval pulse sampling circuit and a sampling and holding circuit. The orthogonal circuit is used to weaken the interference between adjacent signals in the transmitted signal, and mainly includes a serial-to-parallel conversion circuit, an orthogonal signal circuit and a multiplication circuit. The serial-to-parallel conversion circuit is used to generate two signals from one signal, including a 1:2 tapping circuit and a sampling and shaping circuit. The orthogonal signal circuit is generated by a phase-locked loop module. For example, the phase-locked loop outputs a cosine function signal and outputs a sin function signal through a -π / 2 phase shift circuit. The interval pulse sampling circuit includes a sampling gate circuit and an interval single pulse circuit. The interval single pulse circuit transmits a single pulse signal once in 1 / 12 of the signal cycle, and is used for the sampling gate circuit to sample the input signal. After the sampling gate samples the input signal, the sampling and holding circuit samples and shapes the generated signal to obtain four different level signals, namely the PAM4 signal.

[0138] It can be understood that, through the modulation system of the above-mentioned PAM4 signal, the serial-to-parallel conversion processing is first performed through the serial-to-parallel conversion circuit to divide the input initial signal into a synchronous first synchronization signal and a second synchronization signal, and then the first synchronization signal is orthogonally demodulated through the first multiplication module and the phase-locked loop module, and the second synchronization signal is orthogonally demodulated through the second multiplication module and the phase-locked loop module to obtain the first orthogonal signal and the second orthogonal signal, and the reference signal corresponding to the initial signal is determined based on the first orthogonal signal and the second orthogonal signal through the third multiplication module, and the reference signal is periodically sampled through the sampling gate circuit, the interval single pulse circuit and the sampling and holding circuit to obtain the PAM4 signal corresponding to the initial signal. Through the above-mentioned serial-to-parallel conversion processing and orthogonal demodulation processing, the original adjacent signals in the input initial signal are branched into two different parallel signals, avoiding the strong interference problem between adjacent signals in the subsequent signal processing process, thereby achieving the technical effect of improving the modulation accuracy of the PAM4 signal.

[0139] Through the embodiments provided in this application, a high-speed PAM4 signal modulation circuit is designed using orthogonal functions, interval pulse sampling and sample-and-hold technology. The orthogonal function changes the linear relationship between adjacent signals from existing to non-existent, eliminating the interference problem to improve the performance of the subsequent equalization circuit. Interval pulse sampling not only improves the transmission rate by using equally spaced pulses, but also realizes four different level signals and reduces the design difficulty of the clock circuit in combination with the sample-and-hold circuit, thereby broadening the application scenarios of the PAM4 signal transmission interface link, and is suitable for interconnection scenarios such as C2C (Chip-to-Chip, chip to chip), C2M (Chip-to-Module, chip to module).

[0140] As an optional scheme, the modulation system of the PAM4 signal also includes a phase shift module, which is connected to the phase-locked loop module and the second multiplication module. The phase shift module is used to shift the cosine signal of the phase-locked loop module to obtain the sine signal, and input the sine signal into the second multiplication module.

[0141] Optionally, in this embodiment, the phase shift module may be, but is not limited to, used to shift the phase of the cosine signal in the phase-locked loop module by -π / 2 to obtain the sine signal.

[0142] As an optional solution, the serial-to-parallel conversion module includes a tapping circuit, and the tapping circuit is used to tap the initial signal in an alternating manner to obtain a first tapped signal and a second tapped signal.

[0143] It can be understood that, in the tapping process, the input initial signal can be divided into two parallel signals based on, but not limited to, the tapping circuit included in the serial-to-parallel conversion circuit.

[0144] To further illustrate, assuming that the input initial signal is "123456", the first decomposed signal obtained after the serial-to-parallel conversion is "135", and the second decomposed signal is "246". It can be understood that the signal content corresponding to the first decomposed signal and the signal content corresponding to the second decomposed signal are interlaced in the signal content corresponding to the initial signal.

[0145] Through the embodiments provided in the present application, the initial signal is tapped to obtain a first tapped signal and a second tapped signal, so that the originally adjacent signals in the input initial signal are tapped into two different parallel signals, thereby achieving the technical effect of eliminating or weakening strong interference between adjacent signals in subsequent signal processing.

[0146] As an optional solution, the serial-to-parallel conversion module further includes a sampling and shaping circuit, and the sampling and shaping circuit is used to perform signal alignment on the first tapped signal and the second tapped signal to obtain the aligned first synchronization signal and the second synchronization signal.

[0147] Optionally, in this embodiment, due to the alternating distribution of the tapping circuit, one of the two parallel signals lags behind the other signal by one clock cycle.

[0148] Optionally, in this embodiment, the signal alignment is performed on the sampled first tap signal and the sampled second tap signal, which may be but is not limited to indicating adjusting the tap signal that lags by one clock cycle to align it with the tap signal that is not lagged.

[0149] To further illustrate, Figure 5 As shown, the initial signal 502 includes signal contents "a0, a1, a2, a3, a4, a5", and the first tapped signal 504 and the second tapped signal 506 are obtained after the tapping process, wherein the first tapped signal 504 is a tapped signal that lags behind by one clock cycle. The first tapped signal 504 is further adjusted to be aligned with the second tapped signal 506, to obtain the aligned first tapped signal 508 and the aligned second tapped signal 510, i.e., the first synchronization signal and the second synchronization signal.

[0150] Through the embodiments provided in the present application, the purpose of clock alignment of the first tap signal and the second tap signal is achieved through sampling and shaping processing, thereby ensuring the accuracy of subsequent signal processing based on the aligned first synchronization signal and the second synchronization signal, thereby improving the technical effect of the modulation accuracy of the PAM4 signal.

[0151] As an optional solution, the clock frequencies of the tapping circuit, the sampling and shaping circuit and the phase-locked loop are all f, and the clock frequencies of the sampling gate circuit, the interval single pulse circuit and the sampling and holding circuit are all 12f.

[0152] Optionally, in this embodiment, considering that the frequency of the synchronization signal and the frequency of the orthogonal signal are the same, that is, the clock frequency of the 1:2 tapping circuit and the sampling shaping circuit in the serial-to-parallel conversion circuit and the clock frequency of the phase-locked loop are both f.

[0153] Optionally, in this embodiment, the clock frequencies of the interval single pulse circuit, the sampling gate circuit and the sample-and-hold circuit are all 12f.

[0154] It should be noted that, compared with the traditional modulation method, in order to achieve a PAM4 signal with a bit rate of 12×2f, the clock frequency of the entire circuit needs to be 12f. Therefore, in comparison, this method only requires the local circuit clock frequency to be set to 12f, and does not require the entire circuit to be set to a 12f clock frequency, which reduces the difficulty of clock circuit design (the clock circuit design difficulty of a 12f clock frequency is higher).

[0155] Through the embodiments provided in the present application, the method only needs to set the clock frequency of the local circuit to 12f, and there is no need to set the clock frequency of all circuits to 12f, which reduces the design difficulty of the clock circuit (the design difficulty of the clock circuit with a clock frequency of 12f is higher).

[0156] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0157] In this embodiment, a modulation device for a PAM4 signal is also provided, which is used to implement the above embodiments and preferred implementations, and the descriptions that have been made will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware for a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0158] Fig.12is a structural block diagram of a modulation device for a PAM4 signal according to an embodiment of the present application, such as Fig.12 As shown, the device comprises:

[0159] An acquisition unit 1202 is used to acquire an input initial signal;

[0160] A conversion unit 1204 is used to perform serial-to-parallel conversion on the initial signal to obtain a synchronized first synchronization signal and a second synchronization signal;

[0161] The demodulation unit 1206 is configured to perform a first orthogonal demodulation process on the first synchronization signal to obtain a first orthogonal signal corresponding to the first synchronization signal, and perform a second orthogonal demodulation process on the second synchronization signal to obtain a second orthogonal signal corresponding to the second synchronization signal;

[0162] A determining unit 1208, configured to determine a reference signal corresponding to the initial signal based on the first orthogonal signal and the second orthogonal signal;

[0163] The sampling unit 1210 is used to periodically sample the reference signal to obtain a PAM4 signal corresponding to the initial signal.

[0164] Optionally, in this embodiment, the serial-to-parallel conversion process can be implemented based on, but not limited to, a serial-to-parallel conversion circuit, and is used to tap the input initial signal to obtain a synchronized first synchronization signal and a second synchronization signal, wherein, in the tapping process, the input initial signal can be firstly divided into two parallel signals based on a tapping circuit included in the serial-to-parallel conversion circuit, but not limited to, due to the alternating distribution of the tapping circuit, one of the two parallel signals will lag behind the other signal by one clock cycle. Furthermore, in order to ensure the synchronous processing of the two parallel signals, the two parallel signals can also be subjected to data sampling and waveform shaping processing based on, but not limited to, a sampling and shaping circuit included in the serial-to-parallel conversion circuit to obtain synchronous signals, i.e., the synchronized first synchronization signal and the second synchronization signal.

[0165] To further illustrate, assuming that the input initial signal is "123456", the first synchronization signal obtained after serial-to-parallel conversion is "135" and the second synchronization signal is "246". It can be understood that the signal content corresponding to the first synchronization signal and the signal content corresponding to the second synchronization signal are staggered in the signal content corresponding to the initial signal.

[0166] Optionally, in this embodiment, the orthogonal demodulation process may be, but is not limited to, used to indicate that an original synchronization signal is processed based on a signal provided by a phase-locked loop to obtain an orthogonal signal corresponding to the original synchronization signal.

[0167] It should be noted that the first orthogonal demodulation processing can be, but is not limited to, used to indicate the use of a cosine signal generated by a phase-locked loop to perform orthogonal demodulation processing on the first synchronization signal to obtain a first orthogonal signal corresponding to the first synchronization signal; the first orthogonal demodulation processing can be, but is not limited to, used to indicate the use of a sine signal generated by a phase-locked loop to perform orthogonal demodulation processing on the second synchronization signal to obtain a second orthogonal signal corresponding to the second synchronization signal.

[0168] Optionally, in this embodiment, based on the first orthogonal signal and the second orthogonal signal, a reference signal corresponding to the initial signal is determined, which may include but is not limited to multiplying the first orthogonal signal and the second orthogonal signal to obtain a reference signal to eliminate the influence of the orthogonal phase.

[0169] For further explanation, assuming that the first synchronization signal is V m1 , the first synchronization signal V m1 The corresponding first orthogonal signal is cos(ω c t), the second synchronization signal is V m2 , the first synchronization signal V m2 The corresponding second orthogonal signal is sin(ω c t), where ω c is the frequency of the phase-locked loop output. Then the reference signal Vm can be expressed as Vm=±1 / 2·sin(2ωct)= ±cos(ω c t)· sin(ω c t).

[0170] It should be noted that before the first orthogonal signal and the second orthogonal signal are multiplied, the first orthogonal signal and the second orthogonal signal can also be subjected to amplitude processing through, but not limited to, a synchronization signal. The frequency of the synchronization signal and the first orthogonal signal and the second orthogonal signal are the same, and the amplitude of the processed first orthogonal signal and the second orthogonal signal is ±1.

[0171] Optionally, in this embodiment, the reference signal is periodically sampled to obtain a PAM4 signal corresponding to the initial signal, which may include but is not limited to: first dividing the reference signal into several equal parts according to the period, and then using the output pulse signal to sample the divided reference signal to obtain a candidate signal, sampling the candidate signal at the center position to obtain multiple level values; and maintaining the multiple level values ​​for a preset time to obtain a PAM4 signal.

[0172] It can be understood that the above sampling of the candidate signal at the center position to obtain multiple level values ​​can balance the DC component of the level; the multiple level values ​​are maintained for a preset time to obtain a PAM4 signal, and a PAM4 signal with a corresponding pulse width can be obtained; and in this process, the signal rate of the obtained PAM4 will be several times the signal rate of the input initial signal, which greatly improves the signal rate.

[0173] Through the present application, an input initial signal is first divided into a synchronized first synchronization signal and a second synchronization signal through serial-to-parallel conversion processing, and then the first synchronization signal is subjected to a first orthogonal demodulation processing and the second synchronization signal is subjected to a second orthogonal demodulation processing to obtain a first orthogonal signal and a second orthogonal signal, and a reference signal corresponding to the initial signal is determined based on the first orthogonal signal and the second orthogonal signal, and a PAM4 signal corresponding to the initial signal is obtained through periodic sampling of the reference signal. Through the above-mentioned serial-to-parallel conversion processing and orthogonal demodulation processing, the original adjacent signals in the input initial signal are branched into two different parallel signals, avoiding the strong interference problem between adjacent signals in the subsequent signal processing process, thereby achieving the technical effect of improving the modulation accuracy of the PAM4 signal, and solving the problem that the embodiment provided by the present application first divides the input initial signal into a synchronized first synchronization signal and a second synchronization signal through serial-to-parallel conversion processing, and then performs a first orthogonal demodulation processing on the first synchronization signal and a second orthogonal demodulation processing on the second synchronization signal, respectively, to obtain a first orthogonal signal and a second orthogonal signal, and determines the reference signal corresponding to the initial signal based on the first orthogonal signal and the second orthogonal signal, and obtains the PAM4 signal corresponding to the initial signal through periodic sampling of the reference signal. Through the above-mentioned serial-to-parallel conversion processing and orthogonal demodulation processing, the original adjacent signals in the input initial signal are branched into two different parallel signals, avoiding the strong interference problem between adjacent signals in the subsequent signal processing process, thereby achieving the technical problem of improving the low modulation accuracy of the PAM4 signal.

[0174] As an optional solution, the conversion unit 1204 includes:

[0175] A tapping module, configured to perform tapping processing on the initial signal to obtain a first tapped signal and a second tapped signal, wherein the first tapped signal and the second tapped signal are alternately arranged in the initial signal;

[0176] A shaping module is used to perform waveform shaping processing on the first tapped signal and the second tapped signal to obtain the first synchronization signal and the second synchronization signal.

[0177] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0178] As an optional solution, the shaping module includes:

[0179] An alignment submodule is used to perform data sampling on the first tap signal and the second tap signal, and to perform signal alignment on the sampled first tap signal and the sampled second tap signal to obtain the aligned first synchronization signal and the second synchronization signal, wherein the signal alignment is used to align the clock periods of the sampled first tap signal and the sampled second tap signal.

[0180] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0181] As an optional solution, the demodulation unit 1206 includes:

[0182] An acquisition module, used for acquiring a cosine signal generated by a phase-locked loop;

[0183] The first demodulation module is used to perform orthogonal demodulation processing on the first synchronization signal using the cosine signal to obtain the first orthogonal signal.

[0184] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0185] As an optional solution, the demodulation unit 1206 includes:

[0186] A phase shift module, used for performing phase shift processing on the cosine signal to obtain a sinusoidal signal generated by the phase-locked loop;

[0187] The second demodulation module is used to perform orthogonal demodulation processing on the second synchronization signal using the sinusoidal signal to obtain the second orthogonal signal.

[0188] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0189] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0190] As an optional solution, the determining unit 1208 includes:

[0191] A multiplication module is used to multiply the first orthogonal signal and the second orthogonal signal to obtain the reference signal.

[0192] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0193] As an optional solution, the sampling unit 1210 includes:

[0194] A division module, used for dividing the reference signal into 12 equal parts according to a period, wherein a first time interval of the divided reference signal is 1 / 12 of a second time interval of the reference signal;

[0195] A first sampling module, configured to use the output pulse signal to sample the divided reference signal to obtain a candidate signal, wherein the pulse signal is output according to the first time interval;

[0196] The second sampling module is used to perform amplitude sampling on the candidate signal to obtain the PAM4 signal.

[0197] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0198] As an optional solution, the first sampling module includes:

[0199] The pulse signal and the divided reference signal are multiplied to obtain the candidate signal.

[0200] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0201] As an optional solution, the first sampling module includes:

[0202] The pulse signal and the switch gate are used to control the conduction of the divided reference signal to obtain the candidate signal.

[0203] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0204] As an optional solution, the second sampling module includes:

[0205] A sampling submodule, used for sampling the candidate signal at a center position to obtain multiple level values;

[0206] The holding submodule is used to hold the multiple level values ​​for a preset time interval to obtain the PAM4 signal, wherein the preset time interval is a time interval of the pulse signal.

[0207] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0208] As an optional scheme, the frequency of the initial signal is f, the pulse width of the initial signal is 1 / 2f, the bit rate of the initial signal is 2f, the first time interval is 1 / 24f, the pulse width of the PAM4 signal is 1 / 12f, and the bit rate of the PAM4 signal is 24f.

[0209] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0210] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0211] It should be noted that the above modules can be implemented by software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.

[0212] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0213] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0214] An embodiment of the present application further provides an electronic device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0215] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0216] An embodiment of the present application further provides a computer program product, comprising a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program product, and when the computer program is executed by a processor, the steps of the method described in each embodiment of the present application are implemented.

[0217] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0218] Obviously, those skilled in the art should understand that the above modules or steps of the present application can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order from that herein, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0219] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A modulation method for a PAM4 signal, characterized in that: include: Get the initial input signal; Performing serial-to-parallel conversion on the initial signal to obtain a synchronized first synchronization signal and a second synchronization signal; The first synchronization signal is subjected to a first orthogonal demodulation process to obtain a first orthogonal signal corresponding to the first synchronization signal, comprising: obtaining a cosine signal generated by a phase-locked loop; using the cosine signal to perform an orthogonal demodulation process on the first synchronization signal to obtain the first orthogonal signal, and performing a second orthogonal demodulation process on the second synchronization signal to obtain a second orthogonal signal corresponding to the second synchronization signal, comprising: performing a phase shift process on the cosine signal to obtain a sine signal generated by the phase-locked loop; using the sine signal to perform an orthogonal demodulation process on the second synchronization signal to obtain the second orthogonal signal; Determining a reference signal corresponding to the initial signal based on the first orthogonal signal and the second orthogonal signal; The reference signal is periodically sampled to obtain a PAM4 signal corresponding to the initial signal.

2. The PAM4 signal modulation method according to claim 1, characterized in that: The performing serial-to-parallel conversion on the initial signal to obtain a synchronized first synchronization signal and a second synchronization signal comprises: Performing tapping processing on the initial signal to obtain a first tapped signal and a second tapped signal, wherein the first tapped signal and the second tapped signal are alternately arranged in the initial signal; The first tapped signal and the second tapped signal are subjected to waveform shaping processing to obtain the first synchronization signal and the second synchronization signal.

3. The PAM4 signal modulation method according to claim 2, characterized in that: The step of performing waveform shaping processing on the first tap signal and the second tap signal to obtain the first synchronization signal and the second synchronization signal comprises: Data sampling is performed on the first tap signal and the second tap signal, and signal alignment is performed on the sampled first tap signal and the sampled second tap signal to obtain the aligned first synchronization signal and the second synchronization signal, wherein the signal alignment is used to align the clock periods of the sampled first tap signal and the sampled second tap signal.

4. The PAM4 signal modulation method according to claim 1, characterized in that: The determining, based on the first orthogonal signal and the second orthogonal signal, a reference signal corresponding to the initial signal comprises: The first orthogonal signal and the second orthogonal signal are multiplied to obtain the reference signal.

5. The PAM4 signal modulation method according to claim 1, characterized in that: The periodically sampling the reference signal to obtain a PAM4 signal corresponding to the initial signal includes: Divide the reference signal into 12 equal parts according to the period, wherein the first time interval of the divided reference signal is 1 / 12 of the second time interval of the reference signal; Using the output pulse signal, sampling the divided reference signal to obtain a candidate signal, wherein the pulse signal is output according to the first time interval; Perform amplitude sampling on the candidate signal to obtain the PAM4 signal.

6. The PAM4 signal modulation method according to claim 5, characterized in that: The method of using the output pulse signal to sample the divided reference signal to obtain a candidate signal includes: The pulse signal and the divided reference signal are multiplied to obtain the candidate signal.

7. The PAM4 signal modulation method according to claim 5, characterized in that: The method of using the output pulse signal to sample the divided reference signal to obtain a candidate signal includes: The pulse signal and the switch gate are used to control the conduction of the divided reference signal to obtain the candidate signal.

8. The PAM4 signal modulation method according to claim 5, characterized in that: The amplitude sampling of the candidate signal to obtain the PAM4 signal includes: Sampling the candidate signal at a center position to obtain multiple level values; The multiple level values ​​are maintained for a preset time interval to obtain the PAM4 signal, wherein the preset time interval is a time interval of the pulse signal.

9. The PAM4 signal modulation method according to claim 5, characterized in that: The frequency of the initial signal is f, the pulse width of the initial signal is 1 / 2f, the bit rate of the initial signal is 2f, the first time interval is 1 / 24f, the pulse width of the PAM4 signal is 1 / 12f, and the bit rate of the PAM4 signal is 24f.

10. A modulation system for a PAM4 signal, characterized in that: It includes a serial-to-parallel conversion circuit, a phase-locked loop module, a first multiplication module, a second multiplication module, a third multiplication module, a sampling gate circuit, an interval single pulse circuit, and a sampling and holding circuit. The serial-to-parallel conversion circuit is used to tap the input initial signal and output two synchronous signals, wherein the two synchronous signals include a first synchronous signal and a second synchronous signal; The first multiplication module is connected to the serial-to-parallel conversion circuit and the phase-locked loop module, and is used to multiply the first synchronization signal output by the serial-to-parallel conversion circuit and the cosine signal output by the phase-locked loop module to obtain a first orthogonal signal; The second multiplication module is connected to the serial-to-parallel conversion circuit and the phase-locked loop module, and is used to multiply the second synchronization signal output by the serial-to-parallel conversion circuit and the sinusoidal signal output by the phase-locked loop module to obtain a second orthogonal signal; The third multiplication module is connected to the first multiplication module and the second multiplication module, and is used to multiply the first orthogonal signal and the second orthogonal signal to obtain a reference signal; The sampling gate circuit is connected to the third multiplication module and is used to divide the reference signal into periods; The interval single pulse circuit is connected to the sampling gate circuit and is used to input a pulse signal to the sampling gate circuit, and the pulse signal is used to sample the divided reference signal to obtain a candidate signal; The sample-and-hold circuit is connected to the sampling gate circuit and is used to perform amplitude sampling on the candidate signal to obtain the PAM4 signal.

11. The PAM4 signal modulation system according to claim 10, characterized in that: The modulation system of the PAM4 signal also includes a phase shift module, which is connected to the phase-locked loop module and the second multiplication module. The phase shift module is used to shift the cosine signal of the phase-locked loop module to obtain the sine signal, and input the sine signal into the second multiplication module.

12. The PAM4 signal modulation system according to claim 10, characterized in that: The serial-to-parallel conversion module includes a tapping circuit, and the tapping circuit is used to tap the initial signal in an alternate manner to obtain a first tapped signal and a second tapped signal.

13. The PAM4 signal modulation system according to claim 12, characterized in that: The serial-to-parallel conversion module further includes a sampling and shaping circuit, and the sampling and shaping circuit is used to perform signal alignment on the first tapped signal and the second tapped signal to obtain the aligned first synchronization signal and the second synchronization signal.

14. The PAM4 signal modulation system according to claim 13, characterized in that: The clock frequencies of the tapping circuit, the sampling shaping circuit and the phase-locked loop are all f, and the clock frequencies of the sampling gate circuit, the interval single pulse circuit and the sampling and holding circuit are all 12f.

15. A modulation device for a PAM4 signal, characterized in that: include: An acquisition unit, used for acquiring an input initial signal; A conversion unit, configured to perform serial-to-parallel conversion on the initial signal to obtain a synchronized first synchronization signal and a second synchronization signal; a demodulation unit, configured to perform a first orthogonal demodulation process on the first synchronization signal to obtain a first orthogonal signal corresponding to the first synchronization signal, comprising: acquiring a cosine signal generated by a phase-locked loop; performing an orthogonal demodulation process on the first synchronization signal using the cosine signal to obtain the first orthogonal signal, and performing a second orthogonal demodulation process on the second synchronization signal to obtain a second orthogonal signal corresponding to the second synchronization signal, comprising: performing a phase shift process on the cosine signal to obtain a sine signal generated by the phase-locked loop; performing an orthogonal demodulation process on the second synchronization signal using the sine signal to obtain the second orthogonal signal; a determining unit, configured to determine a reference signal corresponding to the initial signal based on the first orthogonal signal and the second orthogonal signal; The sampling unit is used to periodically sample the reference signal to obtain a PAM4 signal corresponding to the initial signal.

16. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program implements the steps of the method according to any one of claims 1 to 9 when executed by a processor.

17. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 9 are implemented.

18. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 9 are implemented.

Images