A constant power output system and method

Abstract

The present invention discloses a constant power output system and method, including: a bias circuit, a first multiplier, a second multiplier, a first logic control circuit and a second logic control circuit, wherein in a first control state, the first multiplier is connected to the bias circuit and the second multiplier is disconnected from the bias circuit; in a second state, the first multiplier is disconnected from the bias circuit; in a third state, the first multiplier is connected to the bias circuit and the second multiplier is connected to the bias circuit; and an output stage circuit is connected to the second logic control circuit and an output signal. The present invention innovatively adopts a redundant design method, which can effectively avoid random defects in process manufacturing and greatly improve product yield.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a constant power output system and method. Background Art

[0002] A constant output power circuit is a circuit that can output constant power to the outside, and the output power is not affected by power supply voltage fluctuations or load changes. It is commonly used in the power control part of industrial control systems. Constant output power circuits often use multiple feedback branches to sample the output voltage and output current respectively, and input them into the multiplier to obtain output power information, and then maintain the output power constant through a negative feedback loop. Among them, high-precision, wide-range analog multipliers are key components of constant power circuits. Since the collector current (Ic) and collector-emitter voltage (Vbe) of a bipolar junction transistor (BJT) have an intrinsic exponential relationship, it is very convenient to convert voltage addition into current multiplication, so it is often used in the design of such analog multipliers.

[0003] However, compared with traditional metal oxide semiconductor field effect transistors (MOSFET), bipolar transistors are still not mature enough in process manufacturing, especially at more advanced technology nodes. Therefore, in the case of large-scale application of bipolar transistors, chips often suffer yield loss due to random defects. This random defect is often manifested in the manufacture of several bipolar transistors, in which a very small number of devices will have problems such as too low Beta value, insufficient gain, port short circuit or even functional failure, while most transistors meet the manufacturing standards. This will greatly reduce the chip yield. Summary of the invention

[0004] In order to solve this problem, the present invention proposes a constant power output system.

[0005] include:

[0006] A bias circuit provides the bias voltage and current required by the circuit;

[0007] A first multiplier is connected to the bias circuit and performs multiplication operation on the input analog signal according to the bias voltage and current provided by the bias circuit;

[0008] a second multiplier connected in parallel with the first multiplier;

[0009] a first logic control circuit, controlling in a first state that the first multiplier is connected to the bias circuit and the second multiplier is disconnected from the bias circuit; in a second state, the first multiplier is disconnected from the bias circuit; and in a third state, the first multiplier is connected to the bias circuit and the second multiplier is connected to the bias circuit;

[0010] a second logic control circuit, controlling in a first state that the first multiplier is connected to the output stage circuit and the second multiplier is disconnected from the output stage circuit; in a second state, the first multiplier is disconnected from the output stage circuit and the second multiplier is connected to the output stage circuit; in a third state, the first multiplier is connected to the output stage circuit and the second multiplier is connected to the output stage circuit;

[0011] The output stage circuit is connected to the second logic control circuit and the output signal.

[0012] Optionally, also include:

[0013] A current feedback branch and a fourth logic control circuit, wherein the current feedback branch is connected to the output stage circuit and feeds back the current of the output stage circuit to the fourth logic control circuit, and the fourth logic control circuit is connected to the first multiplier and the second multiplier;

[0014] In the first state, the current feedback of the first multiplier is turned on and the current feedback of the second multiplier is turned off; in the second state, the current feedback of the first multiplier is turned off and the current feedback of the second multiplier is turned on; in the third state, the current feedback of the first multiplier is turned on and the current feedback of the second multiplier circuit is turned on.

[0015] Optionally, also include:

[0016] A voltage feedback branch and a third logic circuit, wherein the voltage feedback branch is connected to the output end of the output stage and feeds back the voltage of the output stage to the third logic circuit, and the third logic circuit is connected to the first multiplier and the second multiplier;

[0017] In the first state, the voltage feedback of the first multiplier is turned on and the voltage feedback of the second multiplier is turned off; in the second state, the voltage feedback of the first multiplier is turned off and the voltage feedback of the second multiplier is turned on; in the third state, the voltage feedback of the first multiplier is turned on and the voltage feedback of the second multiplier circuit is turned on.

[0018] Optionally, also include:

[0019] The bias circuit includes:

[0020] A first operational amplifier and a second operational amplifier; a first MOS transistor, whose gate is connected to the output of the first operational amplifier, and whose drain / source is connected to the first current source; a second MOS transistor, whose gate is connected to the output of the second operational amplifier, and whose drain / source is connected to the second current source; a first resistor, whose first end is connected to the negative input terminal of the first operational amplifier and the drain / source of the first MOS transistor, and whose second end is connected to the negative input terminal of the second operational amplifier and the drain / source of the second MOS transistor.

[0021] Optionally, the first multiplier circuit includes: a first bipolar transistor, whose collector and base are connected to the first logic control circuit, and whose emitter is connected to the first output end of the bias circuit; a second bipolar transistor, whose collector and base are connected to the first logic control circuit, and whose emitter is connected to the second output end of the bias circuit; a first current mirror; a sixth bipolar transistor, whose collector is connected to the first current mirror, whose base is connected to the emitter of the first bipolar transistor, and whose emitter is connected to the first current mirror through the second logic control circuit; a seventh bipolar transistor, whose collector is connected to the first current mirror, whose base is connected to the emitter of the second bipolar transistor, and whose emitter is connected to the second current mirror through the second logic control circuit;

[0022] The second multiplier circuit includes: a third bipolar transistor, whose collector and base are connected to the first logic control circuit; a fourth bipolar transistor, whose collector and base are connected to the first logic control circuit; a first current mirror; a fifth bipolar transistor, whose collector is connected to the first current mirror, whose base is connected to the emitter of the third bipolar transistor, and whose emitter is connected to the second current mirror through the second logic control circuit; an eighth bipolar transistor, whose collector is connected to the first current mirror, whose base is connected to the emitter of the fourth bipolar transistor, and whose emitter is connected to the second current mirror through the second logic control circuit.

[0023] Optionally, the first logic control circuit is composed of a first MOS transistor switch connected between the first multiplier and the bias circuit and a second MOS transistor switch connected to the second multiplier. Specifically, the first MOS transistor switch is connected between the collector and the bias circuit of the first bipolar transistor and the second bipolar transistor. The second MOS transistor switch is connected between the collector and the bias circuit of the third bipolar transistor and the fourth bipolar transistor.

[0024] Optionally, the second logic control circuit is composed of a third MOS transistor switch connected between the first multiplier and the second current source and a second MOS transistor switch connected between the second multiplier and the second current source. Specifically, the third MOS transistor switch is connected between the emitters of the fifth bipolar transistor and the eighth bipolar transistor and the second current mirror. The fourth MOS transistor switch is connected between the collectors of the sixth bipolar transistor and the seventh bipolar transistor and the bias circuit.

[0025] Optionally, the output stage circuit includes a third current source, which is connected between the first current mirror and ground; a third MOS transistor, whose source is connected to a high level, whose gate is connected to the output of the first current mirror, and whose drain is connected to the second current mirror; and a fourth MOS transistor, whose source is connected to a high level, whose gate is connected to the output of the first current mirror, and whose drain is the output terminal.

[0026] Optionally, the output end is further connected to a load resistor, a first end of the load resistor is grounded, and a second end is connected to the drain of the fourth MOS transistor;

[0027] The voltage feedback branch includes a first feedback resistor connected between the drain of the fourth MOS transistor and the positive input terminal of the second operational amplifier.

[0028] Optionally, also include:

[0029] A test unit, used for testing output power;

[0030] The control unit is used to adjust the working states of the first logic control circuit and the second logic control circuit according to the output power.

[0031] Optionally, a method for a constant power output system to perform constant power output comprises the steps of:

[0032] Setting the first logic control circuit and the second logic control circuit to work in a third state;

[0033] Testing the output power, if it is consistent with the preset value of the third state, then the test ends; otherwise, setting the first logic control circuit and the second logic control circuit to work in the first state or the second state;

[0034] The test output power ends when it is consistent with the first state preset value or the second state preset value, otherwise an error is reported.

[0035] Compared with the existing solutions, the present invention has the following advantages:

[0036] (1) The innovative use of redundant design methods can effectively avoid random defects in process manufacturing and greatly improve product yield. At the same time, the redundant part not only participates in the circuit function by default, that is, when there are no random defects in the device, but also makes the circuit more robust and stable, avoiding the waste of area and power consumption of the redundant part in general redundant design.

[0037] (2) In the redundant design method, in addition to the redundant design of the core components, other peripheral auxiliary circuits can be shared among multiple redundant components, saving the overall circuit area and design scale, while reducing power consumption.

[0038] (3) By utilizing the convenient switch circuit design, each redundant core can be independently in working / non-working state and can be controlled by digital logic signals, with high circuit versatility and flexibility.

[0039] (4) By utilizing circuit design and testing methods, we can avoid and compensate for process defects, improve chip yield, avoid the situation where the chip design process is hindered by process optimization, and accelerate the progress of chip research and development. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The above and other objects, features and advantages of the present invention will become more apparent through a more detailed description of exemplary embodiments of the present invention in conjunction with the accompanying drawings, wherein like reference numerals generally represent like components throughout the exemplary embodiments of the present invention.

[0041] Figure 1 It is a structural schematic diagram of a constant power output system of the present invention;

[0042] Figure 2 A circuit diagram of an embodiment of a constant power output system of the invention;

[0043] Figure 3 A circuit diagram of another embodiment of a constant power output system of the invention. DETAILED DESCRIPTION

[0044] The preferred embodiments of the present invention will be described in more detail below. Although the preferred embodiments of the present invention are described below, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments set forth herein.

[0045] like Figure 1 As shown, a constant power output system of the present invention includes: a bias circuit 110, which provides a bias voltage and current required by the circuit;

[0046] A first multiplier 120 is connected to the bias circuit 110 and performs a multiplication operation on the input analog signal according to the bias voltage and current provided by the bias circuit 110;

[0047] A second multiplier 130 connected in parallel with the first multiplier 120;

[0048] The first logic control circuit 140 controls the first multiplier 120 to be connected to the bias circuit 110 and the second multiplier 130 to be disconnected from the bias circuit 110 in the first state; the first multiplier 120 to be disconnected from the bias circuit 110 in the second state; and the first multiplier 120 to be connected to the bias circuit 110 and the second multiplier 130 to be connected to the bias circuit 110 in the third state;

[0049] The second logic control circuit 150 controls that in the first state, the first multiplier 120 is connected to the output, and the second multiplier 130 is disconnected from the output stage circuit 160; in the second state, the first multiplier 120 is disconnected from the output stage circuit 160, and the second multiplier 130 is connected to the output stage circuit 160; in the third state, the first multiplier 120 is connected to the output stage circuit 160, and the second multiplier 130 is connected to the output stage circuit 160;

[0050] The output stage circuit 160 is connected to the second logic control circuit 150 and the output signal.

[0051] like Figure 2 As shown, in one embodiment, it also includes: a voltage feedback branch for providing feedback to stabilize the output voltage. By detecting the output voltage and feeding it back to the operational amplifier, the input voltage is adjusted to ensure the output voltage is stable. A current feedback branch for providing feedback to stabilize the output current. By detecting the output current and feeding it back to the operational amplifier, the input current is adjusted to ensure the output current is stable.

[0052] Specifically, it includes a current feedback branch 180 and a fourth logic circuit 185. The current feedback branch 180 is connected to the output stage circuit 160 to feed back the current of the output stage circuit 160 to the fourth logic circuit 185. The fourth logic circuit 185 is connected to the first multiplier 120 and the second multiplier 130.

[0053] In the first state, the current feedback of the first multiplier 120 is turned on and the current feedback of the second multiplier 130 is turned off; in the second state, the current feedback of the first multiplier 120 is turned off and the current feedback of the second multiplier 130 is turned on; in the third state, the current feedback of the first multiplier 120 is turned on and the current feedback of the second multiplier 130 is turned on.

[0054] In one embodiment, the voltage feedback branch 190 and the third logic circuit 195, the voltage feedback branch 190 is connected to the output end of the output stage circuit 160, and the voltage of the output stage circuit 160 is fed back to the third logic circuit 195, and the third logic circuit 195 is connected to the first multiplier 120 and the second multiplier 130.

[0055] In the first state, the voltage feedback of the first multiplier 120 is turned on, and the voltage feedback of the second multiplier 120 is turned off; in the second state, the voltage feedback of the first multiplier 120 is turned off, and the voltage feedback of the second multiplier 130 is turned on; in the third state, the voltage feedback of the first multiplier 120 is turned on, and the voltage feedback of the second multiplier 130 is turned on.

[0056] The bias circuit 110 is used to provide the bias voltage and current required by the circuit. It includes two operational amplifiers and a resistor Rs for stabilizing the circuit operating point. The operational amplifier adjusts the base voltage of the bipolar transistor in the multiplier to ensure that the transistor operates in the correct area. In one embodiment, the bias circuit includes: a first operational amplifier 210 and a second operational amplifier 220; a first MOS transistor 211, whose gate is connected to the output of the first operational amplifier 210 and whose drain / source is connected to the first current source 230; a second MOS transistor 221, whose gate is connected to the output of the second operational amplifier 220 and whose drain / source is connected to the second current source 240; a first resistor Rs, whose first end is connected to the negative input of the first operational amplifier 210 and the drain / source of the first MOS transistor 211, and whose second end is connected to the negative input of the second operational amplifier 220 and the drain / source of the second MOS transistor 221.

[0057] The analog multiplier is specifically: a multiplier based on bipolar transistors, which performs multiplication of analog signals. In this embodiment, it is composed of four bipolar transistors Q1, Q2, Q3, and Q4. By adjusting the base voltage, the multiplication of the input signal is realized. The input current is multiplied by Q1, Q2 and Q3, Q4, and the output result is a current or voltage signal.

[0058] In one embodiment, the first multiplier 120 includes: a first bipolar transistor Q1, whose collector and base are connected to the first logic control circuit, and whose emitter is connected to the first output terminal of the bias circuit 110; a second bipolar transistor Q2, whose collector and base are connected to the first logic control circuit, and whose emitter is connected to the second output terminal of the bias circuit 110; a first current mirror 310; a sixth bipolar transistor Q6, whose collector is connected to the first current mirror 310, whose base is connected to the emitter of the first bipolar transistor Q1, and whose emitter is connected to the first current mirror 210 through the second logic control circuit; a seventh bipolar transistor 76, whose collector is connected to the first current mirror, whose base is connected to the emitter of the second bipolar transistor Q2, and whose emitter is connected to the second current source through the second logic control circuit;

[0059] The second multiplier 130 circuit includes: a third bipolar transistor Q3, whose collector and base are connected to the first logic control circuit; a fourth bipolar transistor Q4, whose collector and base are connected to the first logic control circuit; a first current mirror 310; a fifth bipolar transistor Q5, whose collector is connected to the first current mirror 310, whose base is connected to the emitter of the third bipolar transistor Q3, and whose emitter is connected to the second current mirror through the second logic control circuit; an eighth bipolar transistor Q8, whose collector is connected to the first current mirror 310, whose base is connected to the emitter of the fourth bipolar transistor Q4, and whose emitter is connected to the second current mirror through the second logic control circuit.

[0060] In one embodiment, the first logic control circuit is composed of a first MOS transistor switch EAb connected between the first multiplier and the bias circuit and a second MOS transistor switch Ebb connected to the second multiplier. Specifically, the first MOS transistor switch is connected between the collectors of the first bipolar transistor Q1 and the second bipolar transistor Q2 and the bias circuit. The second MOS transistor switch is connected between the collectors of the third bipolar transistor Q3 and the fourth bipolar transistor Q4 and the bias circuit.

[0061] In one embodiment, the second logic control circuit is composed of a third MOS transistor switch EB connected between the first multiplier and the second current source and a second MOS transistor switch EA connected between the second multiplier and the second current source. Specifically, the third MOS transistor switch is connected between the emitters of the fifth bipolar transistor Q5 and the eighth bipolar transistor Q8 and the second current mirror. The fourth MOS transistor switch is connected between the collectors of the sixth bipolar transistor Q6 and the seventh bipolar transistor Q7 and the bias circuit.

[0062] The output stage provides the final output signal of the circuit. It is composed of a MOSFET and a current source Ictrl. The working state of the output stage is adjusted to ensure that the output voltage and current meet the requirements. In one embodiment, the output stage circuit includes a third current source, which is connected between the first current mirror and the ground; a third MOS transistor, whose source is connected to a high level, whose gate is connected to the output of the first current mirror, and whose drain is connected to the second current mirror; and a fourth MOS transistor, whose source is connected to a high level, whose gate is connected to the output of the first current mirror, and whose drain is the output terminal.

[0063] In one embodiment, a load resistor Rload is further connected to the output end. The output end is further connected to the load resistor, a first end of the load resistor is grounded, and a second end is connected to the drain of the fourth MOS transistor;

[0064] The voltage feedback branch includes a first feedback resistor connected between the drain of the fourth MOS transistor and the positive input terminal of the second operational amplifier.

[0065] In one embodiment, it further includes:

[0066] A test unit, used for testing output power;

[0067] The control unit is used to adjust the working states of the first logic control circuit and the second logic control circuit according to the output power.

[0068] The present invention also provides a method for the above-mentioned constant power output system to perform constant power output, which comprises the steps of:

[0069] Setting the first logic control circuit and the second logic control circuit to work in a third state;

[0070] Testing the output power, if it is consistent with the preset value of the third state, then the test ends; otherwise, setting the first logic control circuit and the second logic control circuit to work in the first state or the second state;

[0071] The test output power ends when it is consistent with the first state preset value or the second state preset value, otherwise an error is reported.

[0072] Specifically, the first logic control circuit and the second logic control circuit are set to work in a first state, and the output power is tested. If it is consistent with the preset value of the first state, the process ends, otherwise;

[0073] The first logic control circuit is set to work in the second state, and the output power is tested. If it is consistent with the preset value of the second state, the test ends, otherwise an error is reported.

[0074] The present invention has the following advantages:

[0075] (1) The innovative use of redundant design methods can effectively avoid random defects in process manufacturing and greatly improve product yield. At the same time, the redundant part not only participates in the circuit function by default, that is, when there are no random defects in the device, but also makes the circuit more robust and stable, avoiding the waste of area and power consumption of the redundant part in general redundant design.

[0076] (2) In the redundant design method, in addition to the redundant design of the core components, other peripheral auxiliary circuits can be shared among multiple redundant components, saving the overall circuit area and design scale, while reducing power consumption.

[0077] (3) By utilizing the convenient switch circuit design, each redundant core can be independently in working / non-working state and can be controlled by digital logic signals, with high circuit versatility and flexibility.

[0078] (4) By utilizing circuit design and testing methods, we can avoid and compensate for process defects, improve chip yield, avoid the situation where the chip design process is hindered by process optimization, and accelerate the progress of chip research and development.

[0079] (5) Effectively avoid random defects in process manufacturing and greatly improve product yield.

[0080] (6) Controlling the redundancy range saves the overall circuit area and design scale, avoiding a sharp increase in power consumption. The redundant cores can be independently controlled by digital logic signals, improving system flexibility.

[0081] (7) It avoids the situation where the chip design process is hindered by process optimization and accelerates the progress of chip research and development.

[0082] The above invention circuit first needs to build a traditional constant output power circuit, including an analog multiplier based on a bipolar transistor (BJT), an output stage circuit, a bias circuit, and a logic control circuit. The bias and logic control circuit is mainly responsible for providing the necessary voltage / current bias and some digital logic control functions for the analog multiplier and the output stage circuit, and its output signals are respectively connected to the analog multiplier and the output stage circuit. The output stage circuit is responsible for driving the external load resistor and providing it with constant power. Its input signal comes from the output end of the analog multiplier and is controlled by it, and the output current feedback branch is sent to the input end of the analog multiplier. In addition, the analog multiplier also directly receives the voltage feedback signal from the output port, and obtains the final output power information together with the current feedback signal, and uses a negative feedback loop to maintain its stability.

[0083] On this basis, in order to solve the yield problem mentioned above, redundant core design needs to be further added. It mainly introduces multiple (two in the figure as an example) core modules with the same function (called multiplier core A / B in the figure) in the analog multiplier based on bipolar transistors (BJT), and inserts a corresponding number of switch control circuits between it and the bias and logic control circuit, voltage / current feedback branch and output stage circuit. It is necessary to ensure that all switch circuits can be independently controlled by digital logic signals so that any redundant core can work independently or collaboratively.

[0084] The embodiments of the present invention have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments.

Claims

1. A constant power output system, characterized in that: include: A bias circuit provides the bias voltage and current required by the circuit; A first multiplier is connected to the bias circuit and performs multiplication operation on the input analog signal according to the bias voltage and current provided by the bias circuit; a second multiplier connected in parallel with the first multiplier; A first logic control circuit controls the first multiplier to be connected to the bias circuit and the second multiplier to be disconnected from the bias circuit in a first state; In the second state, the first multiplier is disconnected from the bias circuit, and in the third state, the first multiplier is connected to the bias circuit and the second multiplier is connected to the bias circuit; a second logic control circuit, controlling in a first state that the first multiplier is connected to the output stage circuit and the second multiplier is disconnected from the output stage circuit; and in a second state that the first multiplier is disconnected from the output stage circuit and the second multiplier is connected to the output stage circuit; In the third state, the first multiplier is connected to the output stage circuit, and the second multiplier is connected to the output stage circuit; An output stage circuit, connected to the second logic control circuit and the output signal; Also includes: A current feedback branch and a fourth logic control circuit, wherein the current feedback branch is connected to the output stage circuit and feeds back the current of the output stage circuit to the fourth logic control circuit, and the fourth logic control circuit is connected to the first multiplier and the second multiplier; In the first state, the current feedback of the first multiplier is turned on and the current feedback of the second multiplier is turned off; in the second state, the current feedback of the first multiplier is turned off and the current feedback of the second multiplier is turned on; in the third state, the current feedback of the first multiplier is turned on and the current feedback of the second multiplier is turned on; Also includes: A voltage feedback branch and a third logic circuit, wherein the voltage feedback branch is connected to the output end of the output stage and feeds back the voltage of the output stage to the third logic circuit, and the third logic circuit is connected to the first multiplier and the second multiplier; In the first state, the voltage feedback of the first multiplier is turned on and the voltage feedback of the second multiplier is turned off; in the second state, the voltage feedback of the first multiplier is turned off and the voltage feedback of the second multiplier is turned on; in the third state, the voltage feedback of the first multiplier is turned on and the voltage feedback of the second multiplier circuit is turned on.

2. The constant power output system according to claim 1, characterized in that: The bias circuit includes: A first operational amplifier and a second operational amplifier; a first MOS transistor, whose gate is connected to the output of the first operational amplifier, and whose drain / source is connected to the first current source; a second MOS transistor, whose gate is connected to the output of the second operational amplifier, and whose drain / source is connected to the second current source; a first resistor, whose first end is connected to the negative input terminal of the first operational amplifier and the drain / source of the first MOS transistor, and whose second end is connected to the negative input terminal of the second operational amplifier and the drain / source of the second MOS transistor.

3. The constant power output system according to claim 1, characterized in that: The first multiplier circuit includes: a first bipolar transistor, whose collector and base are connected to the first logic control circuit, and whose emitter is connected to the first output end of the bias circuit; a second bipolar transistor, whose collector and base are connected to the first logic control circuit, and whose emitter is connected to the second output end of the bias circuit; a first current mirror; a sixth bipolar transistor, whose collector is connected to the first current mirror, whose base is connected to the emitter of the first bipolar transistor, and whose emitter is connected to the second current mirror through the second logic control circuit; a seventh bipolar transistor, whose collector is connected to the first current mirror, whose base is connected to the emitter of the second bipolar transistor, and whose emitter is connected to the second current mirror through the second logic control circuit; The second multiplier circuit includes: a third bipolar transistor, whose collector and base are connected to the first logic control circuit; a fourth bipolar transistor, whose collector and base are connected to the first logic control circuit; a first current mirror; a fifth bipolar transistor, whose collector is connected to the first current mirror, whose base is connected to the emitter of the third bipolar transistor, and whose emitter is connected to the second current mirror through the second logic control circuit; an eighth bipolar transistor, whose collector is connected to the first current mirror, whose base is connected to the emitter of the fourth bipolar transistor, and whose emitter is connected to the second current mirror through the second logic control circuit.

4. The constant power output system according to claim 3, characterized in that: The first logic control circuit is composed of a first MOS transistor switch connected between the first multiplier and the bias circuit and a second MOS transistor switch connected between the second multiplier and the second bipolar transistor; the first MOS transistor switch is connected between the collectors of the first bipolar transistor and the second bipolar transistor and the bias circuit; the second MOS transistor switch is connected between the collectors of the third bipolar transistor and the fourth bipolar transistor and the bias circuit.

5. The constant power output system according to claim 4, characterized in that: The second logic control circuit is composed of a third MOS transistor switch connected between the first multiplier and the second current source and a second MOS transistor switch connected between the second multiplier and the second current source. The third MOS transistor switch is connected between the emitters of the fifth bipolar transistor and the eighth bipolar transistor and the second current mirror. The fourth MOS transistor switch is connected between the emitters of the sixth bipolar transistor and the seventh bipolar transistor and the second current mirror.

6. The constant power output system according to claim 3, characterized in that: The output stage circuit includes a third current source, which is connected between the first current mirror and the ground; a third MOS transistor, whose source is connected to a high level, whose gate is connected to the output of the first current mirror, and whose drain is connected to the second current mirror; and a fourth MOS transistor, whose source is connected to a high level, whose gate is connected to the output of the first current mirror, and whose drain is the output terminal.

7. The constant power output system according to claim 6, characterized in that: The output end is also connected to a load resistor, a first end of the load resistor is grounded, and a second end is connected to the drain of the fourth MOS transistor; The voltage feedback branch includes a first feedback resistor connected between the drain of the fourth MOS transistor and the positive input terminal of the second operational amplifier.

8. The constant power output system according to claim 1, characterized in that: Also includes: A test unit, used for testing output power; The control unit is used to adjust the working states of the first logic control circuit and the second logic control circuit according to the output power.

9. A method for performing constant power output using the constant power output system of claim 8, characterized in that: Includes steps: Setting the first logic control circuit and the second logic control circuit to work in a third state; Testing the output power, if it is consistent with the preset value of the third state, then the test ends; otherwise, setting the first logic control circuit and the second logic control circuit to work in the first state or the second state; The test output power ends when it is consistent with the first state preset value or the second state preset value, otherwise an error is reported.

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