Complex multiplication implementation method for parameter serial and parallel mixed input

Abstract

The invention discloses a parameter serial and parallel mixed input complex multiplication implementation method, which is implemented by adopting a complex multiplier circuit, and the complex multiplier circuit comprises a serial input cache unit, a parallel input cache unit, a real number multiplication unit and a real number addition / subtraction unit. The method comprises the specific implementation steps that S1, serial input complex number parameters and parallel input complex number parameters are sequentially input from a serial input cache unit and a parallel input cache unit respectively; s2, the serial input complex parameters and the parallel input complex parameters are subjected to combined calculation through a real number multiplication unit and a real number addition / subtraction unit; and S3, outputting a real part and an imaginary part of a complex multiplication result in sequence in a serial mode. Compared with a traditional and optimized triple multiplier version complex multiplication operation circuit, only a small number of registers are additionally arranged, latch resources are conditionally selected, and the complex multiplication operation circuit has obvious advantages in hardware resource consumption.

Description

Technical Field

[0001] The present invention relates to the technical field of digital signal processing, and particularly to a method for implementing complex multiplication operations with a hybrid serial and parallel input of parameters. Background Art

[0002] Complex multiplication operation is an important basic operation in computer data processing, and its purpose is to calculate the product of two input complex numbers and output the result. Complex multiplication operations are widely used in data processing fields such as digital communication and signal processing.

[0003] Currently, there are two existing implementation schemes of complex multipliers based on hardware description languages, namely the traditional four-multiplier and three-multiplier schemes. The traditional four-multiplier scheme requires four real multipliers and two real adder / subtractors, while the three-multiplier scheme requires three real multipliers and five real adder / subtractors. Both of these two implementation schemes support pipelined operations under the condition that the selected real multipliers and adder / subtractors support pipelining. Through in-depth analysis of these two schemes, it can be seen that the three-multiplier implementation scheme saves one real multiplier at the cost of adding three real adder / subtractors, and the overall resources are not saved much. Instead, it will consume additional logic resources in FPGAs.

[0004] Although the existing two implementation schemes do not consume much hardware resources, since complex multiplication operations, as a basic operation, are likely to be instantiated very frequently in a design, and the resources consumed will increase exponentially as the number of complex operation instances in the design increases, it is still necessary to explore an implementation method that can save resources in complex multiplication operations. Summary of the Invention

[0005] To solve the above problems, the present invention provides a method for implementing complex multiplication operations with a hybrid serial and parallel input of parameters, which is implemented by a complex multiplier circuit. The complex multiplier circuit includes: a serial input buffer unit, a parallel input buffer unit, a real multiplier unit, and a real adder / subtractor unit. The specific implementation steps include: S1. Sequentially input the serial input complex number parameter and the parallel input complex number parameter into the serial input buffer unit and the parallel input buffer unit respectively; S2. Combine and calculate the serial input complex number parameter and the parallel input complex number parameter through the real multiplier unit and the real adder / subtractor unit; S3. Output the real part and the imaginary part of the complex multiplication result in sequence in a serial form, wherein, represents the real part of the serial input complex number parameter Represents the imaginary part of a serially input complex parameter, Represents the real part of a parallel input complex parameter, Represents the imaginary part of a parallel input complex parameter, with a superscript Indicates that the currently input parameter is the th set of parameters in a sequence of continuously input parameters, Is an imaginary flag, indicating The value of, which is added in front of the imaginary part of a complex number in a complex number expression to identify the imaginary part.

[0006] Furthermore, the complex multiplier circuit further includes a circuit input interface unit, specifically including: a serial complex input interface, a parallel complex input interface, and a real / imaginary part flag signal interface.

[0007] Furthermore, in step S1, the serially input complex parameter Is input sequentially in beats according to the synchronous clock rhythm, starting with the real part And then the imaginary part At the same time, a flag signal Indicates whether the current clock at the serial complex input interface presents the real part Or the imaginary part Of the serially input complex parameter: a low level represents the real part , and a high level represents the imaginary part ; The serially input complex parameter Is sequentially delayed by 2 beats after input, and the delayed output signal and the serially input complex parameter Jointly form a third-order serially input parameter cache , , ; The flag signal Is sequentially delayed by 2 beats after input, and the delayed output signal and the flag signal Jointly form a third-order real / imaginary part identification signal cache , , ; The real part And the imaginary part Of the parallel input complex parameter Are input into the parallel input complex interface simultaneously according to the synchronous clock when the flag signal Is 0, and the parameter data input in the previous beat is kept unchanged when the flag signal Is 1.

[0008] Furthermore, the serial input buffer unit is composed of two-level registers and is used to sequentially cache the serially input complex parameter according to the synchronous clock rhythm, specifically: When When it is at a low level, the serial input complex number is input from the serial complex input interface The real part of , the first-stage register holds the imaginary part of the serial input complex number parameter input in the previous cycle And its corresponding flag signal , at this time, the flag signal in the first-stage register The value of is 1'b1, and the second-stage register holds the real part of the serial input complex number parameter in the previous cycle And its corresponding flag signal , at this time, the flag signal in the second-stage register The value of is 1'b0; When Is at a high level, the serial input complex number parameter is input from the serial complex input interface The imaginary part of , the first-stage register holds the real part of the current serial input complex number parameter And its corresponding flag signal , at this time, the flag signal in the first-stage register The value of is 1'b0, and the second-stage register holds the imaginary part of the serial input complex number parameter input in the previous cycle And its corresponding flag signal , at this time, the flag signal in the second-stage register The value of is 1'b1.

[0009] Furthermore, the parallel input buffer unit is composed of a first-stage register, which is used to cache the input parallel input complex number parameter according to the synchronous clock beat. Specifically: When Is at a low level, the real part And the imaginary part Of the parallel input complex number parameter are input from the parallel input complex interface and latched into the register. At this time, the register should output the real part And the imaginary part Of the previous parallel input complex number parameter, and output the real part And the imaginary part Of the currently input parallel input complex number parameter in the next cycle ; When Is at a high level, the register holds and outputs the real part And the imaginary part Of the parallel input complex number parameter input in the previous cycle.

[0010] Furthermore, the real number multiplication unit is composed of two parallel real number multipliers A and real number multiplier B, and The signal multiplier synchronous shift-order register Constitute; among them, Signal multiplier synchronous shift register The shift order is the number of delay beats of the real multiplier operation, Signal multiplier synchronous shift register The input end is connected to the flag signal at the output end of the second-stage register in the serial input buffer unit bit.

[0011] Furthermore, the input end of the real multiplier A is connected to the output of the real part register of the parallel input buffer unit and the serial input complex parameter output by the first-stage register of the serial input buffer unit , specifically: When the flag signal stored in the first-stage register of the serial input buffer unit has a low level (0) value, the two input ends of the real multiplier A are respectively the real part of the parallel input complex parameter and the real part of the serial input complex parameter ; When the flag signal stored in the first-stage register of the serial input buffer unit has a high level (1) value, the two input ends of the real multiplier A are respectively the real part of the parallel input complex parameter and the imaginary part of the serial input complex parameter .

[0012] Furthermore, among the two input ends of the real multiplier B, one input end is connected to the output end of the imaginary part register of the parallel input buffer unit, and the other input end selects to connect to the input end of the serial input buffer unit or the serial complex value output by the second-stage register according to the value of the flag signal stored in the first-stage register of the serial input buffer unit , specifically: When the flag signal stored in the first-stage register of the serial input buffer unit has a low level, the input end of the real multiplier B connected to the output end of the imaginary part register of the parallel input buffer unit is the imaginary part of the parallel input complex parameter , and the other input end of the real multiplier B selects to connect to the serial input complex parameter at the input end of the serial input buffer unit , and at this time, the input at this input end is the imaginary part of the serial input complex parameter ; When the flag signal stored in the first-stage register of the serial input buffer unit has a high level, the input end of the real multiplier B connected to the output end of the imaginary part register of the parallel input buffer unit is still the imaginary part of the parallel input complex parameter , , another input terminal of the real multiplier B is selectively connected to the serial input complex parameter output from the second-stage register of the serial input buffer unit , and at this time, the real part of the serial input complex parameter is input to this input terminal .

[0013] Furthermore, the real adder / subtractor unit is composed of a real adder / subtractor and a signal adder / subtractor synchronous shift-order register . Among them, the shift order of the signal adder / subtractor synchronous shift-order register is the same as the number of operation delay beats of the real adder / subtractor, and its input terminal is connected to the output terminal of the signal multiplier synchronous shift-order register ; the two parameter input ports of the real adder / subtractor are respectively connected to the output ports of the two real multipliers of the real multiplication unit, and are controlled by the signal level value at the output terminal of the signal multiplier synchronous shift-order register of the real multiplication unit. Specifically: When the signal level value at the output terminal of the signal multiplier synchronous shift-order register is high level, an addition operation is performed; When the signal level value at the output terminal of the signal multiplier synchronous shift-order register is low level, a subtraction operation is performed.

[0014] Furthermore, when the operation delay of the real multiplier is beats and the operation delay of the real adder / subtractor is beats, the total operation delay of the complex multiplication operation is beats.

[0015] The present invention provides a method for implementing complex multiplication operation with serial and parallel hybrid input of parameters, which is applicable to the scenario where the data throughput rate is less than or equal to half of the synchronous clock frequency, and has the following beneficial effects: 1. Low hardware resource consumption. The traditional complex multiplication operation circuit requires 4 real multipliers and 2 real adder / subtractor circuits, while the optimized three-multiplier version circuit also requires 3 real multipliers and 5 real adder circuits. The complex multiplication operation circuit of the present invention only requires 2 real multipliers, 1 real adder / subtractor circuit, two shift registers with a 1-bit width, and a small number of conditional selection latches. Compared with the traditional and optimized three-multiplier version complex multiplication operation circuits, the usage of real multipliers is reduced by 1 / 2, and the usage of real adder circuits is reduced by more than 1 / 2. Only a small amount of additional register and conditional selection latch resources are added, showing obvious advantages in hardware resource consumption.

[0016] 2. The increase in operation latency is not obvious. The traditional complex multiplication operation circuit requires clock cycles of operation latency, and the three-multiplier version complex multiplication operation circuit requires clock cycles of operation latency. The complex multiplication circuit of the present invention requires clock cycles of operation latency. Compared with the traditional design, the increase in operation latency is not obvious.

[0017] 3. The increase in interface complexity is not obvious. The input ends of the traditional and three-multiplier version complex multiplication operation circuits require two parallel complex parameter input interfaces, and the output end requires one parallel complex result interface. The input end of the complex multiplication circuit of the present invention requires one parallel complex parameter interface, one serial complex parameter interface, and a flag signal representing the real part / imaginary part. The output end requires one serial complex parameter interface and a flag signal representing the real part / imaginary part. Compared with the traditional and three-multiplier version complex multiplier operation circuits, the interface complexity only lies in replacing one output and one input parallel complex parameter with a serial complex parameter and a flag signal representing the real part / imaginary part.

[0018] 4. Support for pipelining operation. The input of each stage of operation of the complex multiplication circuit of the present invention is only connected to the output of the immediately adjacent previous stage of operation, which ensures support for pipelining operation in design.

[0019] 5. Strong reusability and low implementation difficulty. The structure of the complex multiplication circuit of the present invention is similar to that of the traditional complex multiplication circuit, equivalent to half of the traditional complex multiplication circuit structure with an additional 2 shift registers, 2 cache latches, and 2 conditional latches, with low implementation difficulty. In addition to processing standard unsigned integers and signed integers, this circuit can also process highly mature IEEE754 standard floating-point numbers, and even can use custom numerical adder / subtractor modules and multiplication modules according to requirements, with great flexibility and ease of use. Description of the Drawings

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the accompanying drawings required for the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on the structures shown in these drawings.

[0021] Figure 1 This is the top-level principle block diagram of the complex multiplication operation provided by the present invention; Figure 2 This is the schematic diagram of the input data stream provided by the present invention. Detailed implementation manners

[0022] It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0023] The following will detail the implementation method of the present invention in conjunction with the accompanying drawings. What is described is only part of the embodiments, not all embodiments. For the purpose of clarity, the representations and descriptions unrelated to the present invention are omitted in the drawings and the description.

[0024] In order to have a clearer understanding of the technical features, objectives, and beneficial effects of the present invention, the following will detail the technical solutions of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all embodiments, and should not be construed as limiting the scope of the present invention that can be implemented. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present invention.

[0025] The present invention provides a method for implementing complex multiplication operations with a hybrid serial and parallel input of parameters, which is implemented using a complex multiplier circuit. The complex multiplier circuit includes: a serial input buffer unit, a parallel input buffer unit, a real number multiplication unit, and a real number addition / subtraction unit.

[0026] The specific implementation steps include, as Figure 1 shown, the multiplication operation of signed integers can consume only 1 clock cycle when using a hardware multiplier, and the addition / subtraction operation of signed integers can also be achieved with only 1 clock cycle by using logic circuits. Therefore and both take the value of 1: The serial input complex parameters are input from the input port and sequentially delayed by 2 beats. The delayed output signal and the serial input complex on the input port jointly form a third-order serial input parameter cache 、 、 . The real part / imaginary part identification signal sequence is delayed by two beats, and the delayed output signal and the real part / imaginary part identification signal on the input port jointly form a third-order real part / imaginary part identification signal buffer. , , . The left operand of multiplier A is fixedly connected to the parallel input complex imaginary part output after being delayed by one beat according to the synchronous clock. , according to the signal value, select or and connect it to the right operand of multiplier A after being delayed by one beat. The real part of the parallel input complex number is fixedly connected to the left operand of multiplier B after being delayed by one beat, while the serial input buffer is fixedly connected to the right operand of multiplier B. The output result of multiplier A is connected to the left operand of the adder / subtractor, and the output result of multiplier B is connected to the right operand of the adder / subtractor. The identification signal buffer is connected to the addition / subtraction selection signal interface of the adder / subtractor after being delayed by beats. The output end of the adder / subtractor is connected to the output port of the top-level complex multiplication circuit. The identification signal buffer after being delayed by beats is then connected to the output port of the top-level complex multiplication circuit after being delayed by beats, and is used as the real part / imaginary part identification of the output result.

[0027] As Figure 2 shown, in step S1, the serial input complex number parameter (the superscript represents the element index number of the input complex number sequence) is input in sequence by beats according to the synchronous clock rhythm, first the real part and then the imaginary part . At the same time, the flag signal is used to indicate whether the current clock presents the real part or the imaginary part of the serial input complex number parameter: a low level indicates the real part , and a high level indicates the imaginary part ; The real part and the imaginary part (the superscript represents the element index number of the input complex number sequence) of the parallel input complex number parameter are input according to the synchronous clock when the flag signal is 0, and the parameter data input in the previous beat is kept unchanged when the flag signal is 1; Among the above, represents the real part of the serial input complex number parameter, Represents the imaginary part of a serially input complex parameter, Represents the real part of a parallelly input complex parameter, Represents the imaginary part of a parallelly input complex parameter, superscript Represents that the currently input parameter is the th set of parameters in a sequence of continuously input parameters, Is the imaginary number flag, indicating that The value is added in front of the imaginary part of the complex number in a complex expression to identify the imaginary part.

[0028] The circuit input for each clock cycle is a serially input complex parameter and a flag bit indicating the real or imaginary part , as well as a parallelly input complex parameter . At the even-numbered beats of the synchronous clock, A low level is established, and the real part of the serially input complex number is established at the serial input port , while the real part of the parallelly input complex number is established at the parallel input port and the imaginary part ; at the odd-numbered beats of the synchronous clock, A high level is established, and the imaginary part of the serially input complex number is established at the serial input port , while the real part of the parallelly input complex number established in the previous beat is maintained at the parallel input port and the imaginary part [[ID=XXX]]

[0029] The serial input buffer unit consists of two-level registers and is used to sequentially buffer the serially input complex parameter according to the synchronous clock beats. According to the different values of the flag signal IF n , the distribution of the serially input complex parameter buffered in the two-level registers is also different. Specifically, let the currently input serially input complex parameter be the Nth serially input complex parameter in the sequence input,

[0030] When IF n is at a low level, the serial complex input interface maintains the real part of the current serially input complex parameter s N , The first-level register maintains the imaginary part of the previous serially input complex parameter and its corresponding flag signal The second-level register maintains the real part of the previous serially input complex parameter and its corresponding flag signal

[0031] When IF n is at a high level, the serial complex input interface maintains the imaginary part of the current serially input complex parameter The first-level register maintains the real part of the current serially input complex parameter and its corresponding flag signal The second - stage register holds the imaginary part of the previous serial - input complex parameter and its corresponding flag signal

[0032] The parallel - input buffer unit is composed of a first - stage register, which is used to cache the input parallel - input complex parameter according to the synchronous clock beat. According to the different values of the flag signal IF n The operation method of the register in this unit is also different. Specifically, let the currently input parallel - input complex parameter be the Nth parallel complex parameter of the sequence input

[0033] When IF n is at a low level, the register of the parallel - input buffer unit samples the real part N and the imaginary part of the current parallel - input complex parameter p and latches them in the next clock cycle. At this time, the register outputs the real part N-1 and the imaginary part of the previous parallel - input complex p

[0034] When IF n is at a high level, the register of the parallel - input buffer unit holds and outputs the real part N and the imaginary part of the parallel - input complex parameter p latched in the previous clock cycle

[0035] The real - number multiplier unit is composed of two parallel real - number multipliers A and B and a multiplier synchronous shift - order register ST of the flag signal IF IF，M ; among them, the shift order of the multiplier synchronous shift - order register ST of the IF signal IF，M is the same as the operation delay beats of the real - number multiplier, and its input terminal is connected to the IF signal output by the second - stage register of the serial - input buffer unit

[0036] The input terminal of the real - number multiplier A is connected to the real - part register of the parallel - input buffer unit and the second - stage register of the serial - input buffer unit. The input - terminal state is different according to the value of the IF signal pif[1] output by the first - stage register of the serial - input buffer unit. Specifically When the value of the IF signal pif[1] output by the first - stage register of the serial - input buffer unit is at a high level, the two input terminals of the real - number multiplier A are respectively the real part of the parallel - input complex parameter and the real part When the value of the IF signal pif[1] output by the first-stage register of the serial input buffer unit is low, the two input terminals of the real multiplier A are respectively the real part of the parallel input complex parameter and the imaginary part of the serial input complex parameter The input terminal of the real multiplier B is connected to the imaginary part register of the parallel input buffer unit and the serial complex parameter value output by the first-stage register of the serial input buffer unit. Specifically: When the value of the IF signal pif[1] output by the first-stage register of the serial input buffer unit is low, the two input terminals of the real multiplier B are respectively the imaginary part of the parallel input complex parameter and the imaginary part of the serial input complex parameter When the value of the IF signal pif[1] output by the first-stage register of the serial input buffer unit is high, the two input terminals of the real multiplier B are respectively the imaginary part of the parallel input complex parameter and the real part of the serial input complex parameter The real adder / subtractor unit consists of a real adder / subtractor and an adder / subtractor synchronous shift-order register ST of the flag signal IF IF，A constitutes, where the input terminal of the adder / subtractor synchronous shift-order register ST of the IF signal IF，A is connected to the output terminal of the multiplier synchronous shift-order register ST of the IF signal IF，M Assume that the operation delay of the real adder / subtractor is a beats, then the shift order of the adder / subtractor synchronous shift-order register ST of the IF signal IF，A is a. The two parameter input ports of the real adder / subtractor are respectively connected to the output ports of the two real multipliers of the real multiplication unit, and are controlled by the d signal level value of the output terminal of the multiplier synchronous shift-order register ST of the IF signal of the real multiplication unit IF，M Specifically: When the signal at the output terminal of the multiplier synchronous shift-order register ST of the IF signal IF，M is high, an addition operation is performed; When the signal at the output terminal of the multiplier synchronous shift-order register ST of the IF signal IF，M is low, a subtraction operation is performed. When the operation delay of the real multiplier is m beats and the operation delay of the real adder / subtractor is a beats, the total delay of the complex multiplication operation is 2 + m + a beats. The result of the entire complex multiplication operation circuit is sequentially output from the output port of the real adder / subtractor, and the signal level value at the output terminal of the adder / subtractor synchronous shift-order register ST of the IF signal IF，A identifies whether the value at the output terminal is the real part or the imaginary part of the complex multiplication result. Specifically: When ST IF，A the output signal of IF，A is at a low level, the result at the output of the real number adder / subtractor is the real part of the complex multiplication result; When ST IF，A the output signal of IF，A is at a high level, the result at the output of the real number adder / subtractor is the imaginary part of the complex multiplication result.

[0037] Considering that the calculation delay of the signed integer multiplier is 1 clock cycle, the calculation delay of the signed integer adder / subtractor is 1 clock cycle, and the shifting operations of the shift register are all executed in a pipelined manner, so the delay from input to output of the data is clock cycles.

[0038] The input signal interface of each stage of operation of the present invention is only connected to the output signal interface of the previous stage of operation, and there is no cross-level signal cross-connection. Therefore, this complex multiplication circuit supports pipelined operation.

[0039] The present invention only requires 2 real number multipliers, 1 real number adder / subtractor, two shift registers with a bit width of 1 bit, and a small number of conditional selection latches. Compared with the traditional and optimized three-multiplier complex multiplication operation circuit, the usage of real number multipliers is reduced by 1 / 2, the usage of real number adders is reduced by more than 1 / 2, and only a small amount of additional register and conditional selection latch resources are added, which has obvious advantages in terms of hardware resource consumption.

[0040] The present invention adapts to different bit-width calculation scenarios by simply changing the signal bit widths of the integer multiplier, adder / subtractor, and corresponding interfaces, without the need for major changes to the circuit structure design, nor the need to change and maintain the program code. Therefore, it does not affect the reuse of the circuit in other application scenarios.

[0041] The above are only the preferred embodiments of the present invention. It should be understood that the present invention is not limited to the form disclosed herein, should not be regarded as excluding other embodiments, but can be used in various other combinations, modifications, and environments, and can be changed within the scope of the concept described herein through the above teachings or the techniques or knowledge in related fields. And the changes and modifications made by those skilled in the art that do not depart from the spirit and scope of the present invention shall all be within the protection scope of the appended claims of the present invention.

Claims

1. A method for implementing complex multiplication operations with serial and parallel hybrid input of parameters, characterized in that Implemented by a complex multiplier circuit, the complex multiplier circuit includes: a serial input buffer unit, a parallel input buffer unit, a real number multiplication unit, and a real number addition / subtraction unit; The specific implementation steps include: S1. Input the serial input complex parameter and the parallel input complex parameter into the serial input buffer unit and the parallel input buffer unit in sequence and ; S2. Respectively perform combined calculations on the serially input complex parameters and the parallelly input complex parameters through a real number multiplication unit and a real number addition / subtraction unit; S3. Sequentially output the real part and the imaginary part of the complex multiplication result in a serial form in sub-beats, Among the above, represents the real part of the serially input complex parameter, represents the imaginary part of the serially input complex parameter, represents the real part of the parallelly input complex parameter, represents the imaginary part of the parallelly input complex parameter, and the superscript represents that the currently input parameter is the th group of parameters in the continuously input parameter sequence, is the imaginary flag, indicating the value, which is added in front of the imaginary part of the complex number in the complex expression to identify the imaginary part.

2. The method for implementing complex multiplication operation with parameter serial and parallel hybrid input according to claim 1, characterized in that The complex multiplier circuit further includes a circuit input interface unit, specifically including: a serial complex input interface, a parallel complex input interface, and a real / imaginary part flag signal interface.

3. The method for implementing complex multiplication operation with serial and parallel hybrid input of parameters according to claim 2, characterized in that, In step S1, a complex parameter is serially input in the order of the real part first and then the imaginary part in sync with the clock beats in sequence. At the same time, a flag signal indicates whether the current clock at the serial complex input interface presents the real part or the imaginary part of the serially input complex parameter : a low level represents the real part and a high level represents the imaginary part ; After the serially input complex parameter is input, it is sequentially delayed by 2 beats. The delayed output signal and the serially input complex parameter are combined to form a third-order serially input parameter cache , , , ; The flag signal is sequentially delayed by 2 beats after input. The delayed output signal and the flag signal are combined to form a third-order real / imaginary part identification signal cache , , ; Parallel input complex parameter The real part of And the imaginary part In the flag signal When it is 0, they are simultaneously input into the parallel input complex interface according to the synchronous clock, and in the flag signal When it is 1, the parameter data input in the previous cycle remains unchanged.

4. The method for implementing complex multiplication operation with serial and parallel hybrid input of parameters according to claim 2, characterized in that, The serial input buffer unit is composed of two-stage registers and is used to sequentially buffer the serial input complex parameters according to the synchronous clock beats, specifically: when When it is low, the serial input complex number is input from the serial complex input interface. The real part of The first register holds the imaginary part of the serial input complex parameter input in the previous shot. and its corresponding signal , at this time the flag signal in the first level register The value is 1'b1, and the second-level register holds the real part of the complex parameter serially input in the previous beat. and its corresponding signal , at this time the flag signal in the second-level register The value of is 1'b0; when When the level is high, the serial input complex parameters are input from the serial complex input interface. The imaginary part The first register holds the real part of the current serial input complex parameter. and its corresponding signal , at this time the flag signal in the first level register The value is 1'b0, and the second-level register holds the imaginary part of the serial input complex parameter input in the previous beat and its corresponding signal , at this time the flag signal in the second-level register The value is 1'b1.

5. The method for implementing complex multiplication operation with serial and parallel hybrid input of parameters according to claim 4, characterized in that, The parallel input buffer unit is composed of one-stage registers and is used to buffer the input parallel input complex parameters according to the synchronous clock beats, specifically: When is at a low level, the real part and the imaginary part of the parallel input complex parameter input from the parallel input complex interface are latched into the register. At this time, the register should output the real part and the imaginary part of the previous parallel input complex parameter, and output the real part and the imaginary part of the currently input parallel input complex parameter in the next clock cycle; When is at a high level, the register holds and outputs the real part and the imaginary part of the parallel input complex parameter input in the previous cycle.

6. The method for implementing complex multiplication operation with serial and parallel hybrid input of parameters according to claim 4, characterized in that The real number multiplication unit consists of two parallel real number multipliers A and real number multiplier B, and a signal multiplier synchronous shift order register ; among them, a signal multiplier synchronous shift order register has a shift order equal to the number of delay beats of the real number multiplier operation, a signal multiplier synchronous shift order register has its input end connected to the flag signal bit at the output end of the second-stage register in the serial input buffer unit.

7. The method for implementing complex multiplication operation with serial and parallel hybrid input of parameters according to claim 6, characterized in that The input end of the real multiplier A is connected to the real part register output of the parallel input buffer unit and the serial input complex parameter output from the first-stage register of the serial input buffer unit. Specifically: When the flag signal stored in the first-stage register of the serial input buffer unit has a low level (0), the two input terminals of the real multiplier A are respectively the real part of the parallel input complex parameter and the real part of the serial input complex parameter ; When the flag signal stored in the first-stage register of the serial input buffer unit has a high level (1), the two input terminals of the real multiplier A are respectively the real part of the parallel input complex parameter and the imaginary part of the serial input complex parameter .

8. The method for implementing complex multiplication operation with parameter serial and parallel hybrid input according to claim 6, characterized in that Of the two input terminals of the real multiplier B, one input terminal is connected to the output terminal of the imaginary part register of the parallel input buffer unit, and the other input terminal is connected to the input terminal of the serial input buffer unit or the serial complex value output from the second-stage register according to the value of the flag signal stored in the first-stage register of the serial input buffer unit, specifically: ​ When the flag signal stored in the first-stage register of the serial input buffer unit has a low level value, the input terminal of the real multiplier B connected to the output terminal of the imaginary part register of the parallel input buffer unit is the imaginary part of the parallel input complex parameter , and the other input terminal of the real multiplier B is selected to connect to the serial input complex parameter at the input terminal of the serial input buffer unit , and at this time, the imaginary part of the serial input complex parameter is input at this input terminal ; When the flag signal stored in the first-stage register of the serial input buffer unit has a high level value, the input terminal of the real multiplier B connected to the output terminal of the imaginary part register of the parallel input buffer unit is still the imaginary part of the parallel input complex parameter , and the other input terminal of the real multiplier B is selected to be connected to the serial input complex parameter output by the second-stage register of the serial input buffer unit , and at this time, the input of this input terminal is the real part of the serial input complex parameter .

9. The method for implementing complex multiplication operation with serial and parallel hybrid input of parameters according to claim 1, characterized in that The real number addition / subtraction unit consists of a real number adder / subtractor and a signal addition / subtraction synchronous shift order register and is configured such that the signal addition / subtraction synchronous shift order register has the same shift order as the operation delay beats of the real number adder / subtractor, and its input terminal is connected to the output terminal of the signal multiplier synchronous shift order register ; the two parameter input ports of the real number adder / subtractor are respectively connected to the output ports of the two real number multipliers of the real number multiplication unit, and are controlled by the signal level value at the output terminal of the signal multiplier synchronous shift order register specifically as follows: ​ When the output terminal of the signal multiplier synchronous shift register has a high signal level value, an addition operation is performed; ​ When the output terminal of the signal multiplier synchronous shift register is at a low signal level value, a subtraction operation is performed. ​ 10. The method for implementing complex multiplication operation with parameter serial and parallel hybrid input according to claim 1, wherein When the operation delay of the real multiplier is beats and the operation delay of the real adder / subtractor is beats, the total delay of the complex multiplication operation is beats.

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