Compilation method, electronic device and storage medium

Abstract

The present disclosure provides a compilation method, an electronic device and a storage medium, comprising: obtaining a first code for processing a tensor object, which is composed of tensor intermediate representation instructions included in a first container, and the structured control flow instructions include a second container for describing a control instruction flow of a nested loop or a loop judgment, so that the first code has a recursive container structure, and the first container and the second container have the same structure; converting the first code into a second code composed of machine intermediate representation instructions, the machine intermediate representation instructions are included in a third container, and the machine intermediate representation instructions have a one-to-one mapping relationship with an assembly language; converting the second code into an assembly code, realizing design and development with high-level tensor abstraction, and obtaining high-performance assembly code after compilation, thereby improving programming efficiency, and the compiled assembly code can meet the development requirements of computers based on high-level language programming in various application scenarios, thereby improving development performance.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of processor technology, and more specifically, to a compilation method, an electronic device, and a storage medium. Background Art

[0002] With the development of more general computing scenarios such as artificial intelligence and scientific computing, higher requirements are placed on the computing power, processing efficiency, bandwidth, etc. of processor chips. How to achieve software and hardware collaborative design for high-performance electronic devices and provide high-performance electronic devices has become an important research direction. Summary of the invention

[0003] The embodiments of the present disclosure provide a compilation method, an electronic device, and a storage medium for implementing design and development based on high-level tensor abstraction, compiling to obtain high-performance assembly code, and improving programming efficiency.

[0004] According to a first aspect of the present disclosure, a compilation method is provided, comprising: obtaining a first code for processing a tensor object, wherein the first code is composed of at least one tensor intermediate representation instruction included in a first container, wherein at least one tensor intermediate representation instruction includes a structured control flow instruction, and the structured control flow instruction includes a second container for describing a control instruction flow of a nested loop or a loop judgment, so that the first code has a recursive container structure, wherein the first container and the second container have the same structure; converting the first code into a second code composed of machine intermediate representation instructions, wherein the machine intermediate representation instructions are included in one or more third containers, and the machine intermediate representation instructions have a one-to-one mapping relationship with the assembly language; and converting the second code into assembly code.

[0005] According to some embodiments of the present disclosure, before converting the first code into a second code composed of machine intermediate representation instructions, the compilation method also includes: performing a compilation optimization process on the first code, wherein the compilation optimization process includes: searching for unused resources in the first code; and removing instructions declaring unused resources from the first code, and using the first code after removing the instructions declaring unused resources as the optimized first code for conversion into the second code.

[0006] According to some embodiments of the present disclosure, before converting the first code into a second code composed of machine intermediate representation instructions, the compilation method also includes: for a resource declaration instruction in at least one tensor intermediate representation instruction, determining the life cycle of the resource declared by the resource declaration instruction, wherein the life cycle is represented by the first use time and the last use time of the resource; and allocating a physical storage address to the resource according to the life cycle of the resource.

[0007] According to some embodiments of the present disclosure, converting a first code into a second code composed of machine intermediate representation instructions includes: performing an equivalent transformation on tensor intermediate representation instructions in the first code to generate corresponding machine intermediate representation instructions.

[0008] According to some embodiments of the present disclosure, converting a first code into a second code composed of machine intermediate representation instructions also includes: in the process of performing equivalent transformation on the tensor intermediate representation instructions in the first code, allocating a temporary storage address to the equivalent transformation process according to the allocated physical storage address, wherein the temporary storage address is only valid during the equivalent transformation process.

[0009] According to some embodiments of the present disclosure, before converting the second code into assembly code, the compilation method also includes: performing a compilation optimization process on the second code, wherein the compilation optimization process includes: searching for unused resources in the second code; and removing instructions declaring unused resources from the second code, and using the second code after removing the instructions declaring unused resources as the optimized second code for conversion into assembly code.

[0010] According to some embodiments of the present disclosure, at least one tensor intermediate representation instruction also includes: a resource declaration instruction for declaring resource storage space, a tensor operation instruction for performing computational operations on tensors, a scalar computation instruction, and miscellaneous instructions, wherein the miscellaneous instructions include order-preserving instructions.

[0011] According to some embodiments of the present disclosure, the instructions in the third container are only allowed to have a jump instruction at the end, and the jump instruction allows jumping to the first machine intermediate representation instruction in any third container in the second code.

[0012] According to some embodiments of the present disclosure, the assembly code obtained by converting the second code is used to perform parallel calculations on tensor objects.

[0013] According to a second aspect of the present disclosure, an electronic device is also provided, which includes a processor and a non-volatile memory, wherein program code is stored in the non-volatile memory, and when the program code is executed by the processor, the processor executes the steps of the compilation method according to the present disclosure.

[0014] According to a third aspect of the present disclosure, a non-transitory computer-readable storage medium is also provided, on which computer-readable instructions are stored. When the computer-readable instructions are executed by a processor, the processor executes the steps of the compilation method according to the present disclosure.

[0015] The compilation method, electronic device, and storage medium provided in some embodiments of the present disclosure can compile the first code for processing the tensor object, and finally obtain the assembly code for execution. By using the compilation method, electronic device, and storage medium according to the present disclosure, it is possible to implement design and development with high-level tensor abstraction, and obtain high-performance assembly code after compilation, thereby improving programming efficiency. Moreover, the compiled assembly code can meet the development requirements of computers based on high-level language programming in various application scenarios, thereby improving development performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0017] Figure 1 A schematic flow chart of a compilation method according to an embodiment of the present disclosure is shown;

[0018] Figure 2 A schematic architecture diagram of a first code according to an embodiment of the present disclosure is shown;

[0019] Figure 3 A schematic diagram showing compiling a first code into an assembly code according to an embodiment of the present disclosure is shown;

[0020] Figure 4 Another schematic diagram showing compiling a first code into an assembly code according to an embodiment of the present disclosure;

[0021] Figure 5 A schematic block diagram of an electronic device according to an embodiment of the present disclosure is shown;

[0022] Figure 6 A schematic diagram of the architecture of an exemplary electronic device according to an embodiment of the present disclosure is shown;

[0023] Figure 7 A schematic block diagram of a storage medium according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0024] The technical solutions in the embodiments of the present disclosure will be described clearly and completely below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0025] In addition, as shown in the present disclosure and claims, unless the context clearly indicates an exception, the words "a", "an", "a kind" and / or "the" do not specifically refer to the singular, but may also include the plural. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, the words "include" or "comprise" and the like mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects, that is, it can be understood as "at least including but not limited to". The words "connect" or "connected" and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0026] Flowcharts are used herein to illustrate the steps of the method according to the embodiments of the present disclosure. It should be understood that the preceding or succeeding steps are not necessarily performed in order. Instead, the various steps may be processed in reverse order or simultaneously. At the same time, other operations may also be added to these processes.

[0027] It is understood that the professional terms, nouns, etc. described herein have meanings known to those skilled in the art. To facilitate understanding of the disclosed solution, the terms that may be involved in at least some embodiments of the disclosed solution are explained as follows.

[0028] Tensor is a multi-dimensional array data structure. In the field of deep learning, the dimensions of input data, intermediate data processed during deep learning, and output data are flexible and not exact, so a flexible data form is needed to describe various types of data, which gives rise to the concept of tensor. In the field of deep learning, all data to be calculated are stored and exist in the form of tensors. If the data is not in the form of tensors, it needs to be converted into the data structure of tensors first.

[0029] Artificial Intelligence (AI) operators can refer to tensor calculations performed in the AI ​​framework. These calculations are called operators. They are the core components of the AI ​​framework. As an example, it can be the attention operator in a neural network, etc. Its calculation process involves the calculation operations of query tensor (QTensor), key tensor (K Tensor) and value tensor (V Tensor).

[0030] With the development of more general computing scenarios such as artificial intelligence and scientific computing, higher requirements are placed on the computing power, processing efficiency, bandwidth, etc. of processor chips. How to achieve software and hardware collaborative design for high-performance electronic devices and provide high-performance electronic devices has become an important research direction.

[0031] In the related art, electronic devices used for tensor calculations are usually developed based on high-level languages, such as Compute Unified Device Architecture (CUDA) language, Open Computing Language (OpenCL) and other languages. Such high-level languages ​​are based on C or C++ languages, and add new language extensions, such as keywords, macro definitions, etc. These language extensions are used to support specific hardware features. These high-level language programming methods can provide convenient kernel development for computing devices (e.g., heterogeneous computing platforms) and provide high-performance computing services.

[0032] However, the development method based on high-level languages ​​has limitations in certain areas and cannot meet all design and development needs. As an example, in the early stages of hardware development, it is necessary to complete some test programs to verify the design of the hardware. However, at this time, the compiler for the high-level language is not ready, and the design verification cannot be performed directly based on the high-level language. As another example, in the hardware use stage, for applications with demanding performance requirements, high-level language programming cannot fully tap the potential of the hardware. Faced with the situation where the above-mentioned high-level language cannot meet the needs, developers can only carry out design and development through the low-level assembly language programming method. However, the development efficiency of assembly-based programming is low, and it is difficult to generate a large amount of code. Developers need to pay attention to the details of the underlying instructions and manually allocate resources, which is very restrictive.

[0033] In view of the technical problem that the electronic device that performs tensor calculations as described above, the design and development based on high-level languages ​​cannot meet the development requirements in some cases (for example, in the early stages of hardware development or in applications with demanding performance requirements), the present disclosure provides a compilation method, an electronic device, and a storage medium, which can realize design and development based on high-level tensor abstractions, and directly obtain high-performance assembly code after compilation, thereby improving programming efficiency, and the assembly code obtained after compilation can meet the development requirements of computers based on high-level language programming in various application scenarios, thereby improving development performance. In addition, design and development based on high-level tensor abstractions can isolate the impact of changes in instruction set architecture (ISA) on the software framework in the early stage of hardware-software co-design. Furthermore, using the compilation method provided by the present disclosure, developers only need to focus on the intermediate representation of tensor abstractions without having to pay attention to assembly language, which can effectively avoid the limitations faced by programming methods of high-level languages ​​and assembly languages.

[0034] Next, an implementation scheme for the compilation method according to an embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.

[0035] Figure 1 FIG. 1 shows a schematic flow chart of a compilation method according to an embodiment of the present disclosure. Figure 1 As shown, the compiling method according to the embodiment of the present disclosure includes steps S101-S103.

[0036] As an example, the compilation method provided in the present disclosure may be applicable to an electronic device that performs tensor calculations. As some examples, the electronic device may be implemented as a graphics processing unit (GPU). In addition, the electronic device may also be implemented in other forms, such as general-purpose graphics processing units (GPGPU), neural network processing units (NPU), tensor processing units (TPU), etc., which are not listed one by one here. It is understandable that the electronic device mentioned in this article may also include other components required to implement the target processing function, such as a central processing unit CPU, a memory, a communication interface, etc., which are not repeated here.

[0037] First, in step S101, a first code for processing a tensor object is obtained, wherein the first code is composed of at least one tensor intermediate representation instruction (TIR) ​​included in a first container, wherein at least one tensor intermediate representation instruction includes a structured control flow instruction, and the structured control flow instruction includes a second container for describing a control instruction flow of a nested loop or loop judgment, so that the first code has a recursive container structure, wherein the first container and the second container have the same structure. As an example, the present disclosure Figure 2 An exemplary organizational structure of the first code is shown, wherein a first code form with a recursive container structure is shown, wherein the tensor intermediate representation instructions in the first code are organized and managed by multiple containers of the same structure to form the above-mentioned recursive container structure. The first code organized in this structural form makes the logical relationship between the instructions clearer, which is conducive to compilation optimization and is also more conducive to conversion into a second code composed of machine intermediate representation instructions in subsequent steps, which will be described in detail below.

[0038] According to some embodiments of the present disclosure, the first code obtained is composed of tensor intermediate representation instructions, which are used to process and calculate tensor objects, for example, to perform program design and development with high-level tensor abstraction to cope with the design stage that cannot be completed by high-level languages ​​in the early stages of hardware development or in applications with demanding performance, and at the same time avoid directly writing assembly code. As an application example, the above-mentioned program design and development can refer to kernel design and development, which refers to a program executed on a processor such as a GPU or other dedicated processor.

[0039] Furthermore, in the first code, the tensor intermediate representation instruction is included in the first container, thereby managing the tensor intermediate representation instruction in a containerized manner, avoiding the simple code generation method of directly processing the string. In addition, the tensor intermediate representation instruction includes a structured control flow instruction, and the structured control flow instruction includes a second container for describing the control instruction flow of the nested loop or loop judgment, so that the first code has a recursive container structure.

[0040] For ease of understanding, Figure 2 Schematic diagram of the first code according to an embodiment of the present disclosure is shown. It can be understood that, Figure 2 The form of the first code in is only illustrative, and the first code obtained in step S101 may be in any form of a container structure that satisfies the above recursive formula to achieve the required design and development functions.

[0041] like Figure 2As shown, all tensor intermediate representation instructions of the first code (shown as multiple instructions "Instruction" and loop instructions "Loop") are included in container 1 (Region 1), so that the instruction code is managed in a containerized manner. The specific form of the instruction "Instruction" will be described below. Next, for the structured control flow instructions in the tensor intermediate representation instructions that are used to describe nested loops (for example, loop instructions "Loop") or control instruction flows that are used to describe loop judgments (for example, judgment instructions "If"), the structured control flow instructions include a second container, that is, another second container includes the instructions corresponding to the structured control flow instructions. In addition, in an embodiment according to the present disclosure, the first container and the second container have the same structure.

[0042] like Figure 2 As shown, for the loop instruction Loop included in container 1 (Region 1), it further includes container 2 (Region 2), and container 2 (Region 2) is used to organize and manage the tensor intermediate representation instructions corresponding to the loop instruction Loop. Figure 2 It is shown in FIG. 1 that the Loop instruction consists of three instructions “Instruction” and one judgment instruction “If”.

[0043] Next, if the container 2 (Region 2) also includes the above structured control flow instructions, it may further include another container with the same structure. Figure 2 As shown, the container 2 (Region 2) corresponding to the Loop instruction also includes a judgment instruction "If". The judgment instruction If, as a structured control flow instruction, includes its corresponding container 3 (Region 3). The container 3 (Region 3) includes the tensor intermediate representation instruction corresponding to the judgment instruction If (shown as three instructions "Instruction"), and so on.

[0044] The first code organized in the above-mentioned containerized management form can realize a recursive container structure and can express nested loops and complex control flows of loops and judgments, which is conducive to more conveniently and intuitively converting TIR instructions into machine intermediate representation (MIR) instructions one by one in the subsequent compilation stage.

[0045] Next reference Figure 1, in step S102, the first code is converted into a second code composed of machine intermediate representation instructions, wherein the machine intermediate representation instructions are included in one or more third containers, and the machine intermediate representation instructions (MIR instructions) have a one-to-one mapping relationship with the assembly language. It can be understood that in the compilation method according to the present disclosure, the instruction code has two abstraction levels, the first level is a first code designed and developed based on a high-level tensor abstraction, which includes TIR instructions for describing operations on Tensor objects, and then, the TIR instructions are converted into a second code of the second level, which includes the converted MIR instructions, and the MIR instructions have a one-to-one mapping relationship with the assembly language or machine language, and are used to generate assembly-level instructions.

[0046] Further, as described above, the first code form of containerized management satisfies the recursive container structure, and the MIR instructions of the second level are included in one or more third containers similar to the basic blocks in the compiler, which requires that the MIR instructions in the third container are only allowed to have jump instructions at the end, and the jump instructions are allowed to jump to the first machine intermediate representation instruction in any third container in the second code. For example, the third container can be understood as the concept of machine basic block (MBB). That is, the jump instruction can jump to the first instruction in any basic block. In the second code, the connection between containers and the instruction jump characterize the instruction control flow (i.e., jump) relationship.

[0047] According to some embodiments of the present disclosure, several equivalent transformations can be performed between the container of the TIR instruction and the container of the MIR instruction, that is, the TIR instruction is converted into one or more MIR instructions one by one while maintaining the correctness of the structure of the container and the mathematical calculation. The specific conversion process will be described below in conjunction with the accompanying drawings.

[0048] Next reference Figure 1 , in step S103, the second code is converted into assembly code. Since the machine intermediate representation instructions in the second code have a one-to-one mapping relationship with the assembly language, the second code can be directly printed as assembly code (Assembly) through, for example, the Print() function for execution. As an example, for the generated assembly code, a machine code can be first generated by an assembler, and the generated file can be represented as an object file, and then a linker can be used to convert the object file into an executable file for execution by an electronic device.

[0049] According to some embodiments of the present disclosure, the assembly code obtained by converting the second code is used to perform parallel calculations on tensor objects. This is because the first code used to generate the assembly code is itself used to process tensor objects, and the amount of computation of tensor calculations is generally large. It is mapped to different computing units for parallel processing, which can be understood as a multi-threaded parallel computing process. Therefore, after the TIR instructions in the first code are converted to MIR instructions and further converted to assembly code, it automatically maps these tensor calculations with large amounts of data to different address spaces for parallel computing. Therefore, the assembly code obtained by the compilation method provided according to the embodiment of the present disclosure is ultimately processed in a parallel computing process. In other words, the compilation method provided according to the embodiment of the present disclosure can generate high-performance parallel programs in the form of assembly language.

[0050] By using the compilation method according to the embodiment of the present disclosure, the first code obtained by designing and developing with high-level tensor abstraction can be converted into assembly code to complete the required design function. After compilation, high-performance assembly code is obtained, which improves programming efficiency. Developers only need to focus on the intermediate representation of tensor abstraction without paying attention to assembly language, which can effectively avoid the limitations faced by high-level languages ​​and assembly language programming methods. Moreover, the compiled assembly code can meet the development needs of computers based on high-level language programming in various application scenarios, improve development performance and realize parallel computing. In addition, designing and developing with high-level tensor abstraction can isolate the impact of ISA changes on the software framework in the early stage of hardware-software collaborative design.

[0051] According to some embodiments of the present disclosure, at least one tensor intermediate representation instruction in the first code may include the structured control flow instruction for describing the control instruction flow of nested loops or loop judgments, and the structured control flow instruction may be a loop instruction Loop and a judgment instruction If. Such instructions include one or more containers Region, so that nested loops and complex control flows of loops and judgments can be expressed in the first code.

[0052] According to some embodiments of the present disclosure, at least one tensor intermediate representation instruction in the first code may also include other types of instructions (for example, Figure 2In the structured control flow instructions, all tensor intermediate representation instructions other than structured control flow instructions are represented as instructions "Instruction"). For example, instructions "Instruction" may include resource declaration instructions for declaring resource storage space, tensor operation instructions for performing calculation operations on tensors, scalar calculation instructions, and other miscellaneous instructions required for the design. For example, miscellaneous instructions may include order preservation instructions (Fence), etc. As an example, resource declaration instructions include tensor resource declaration instructions, scalar resource declaration instructions, and synchronization resource declaration instructions. Tensor operation instructions include tensor multiplication instructions, tensor convolution instructions, and tensor movement instructions.

[0053] It is understandable that the above-mentioned tensor intermediate representation instructions can be various operation instructions for implementing tensor processing, and are not limited to the types described above. The developer can expand them into various required instruction codes, and only needs to make them satisfy the above-mentioned recursive container structure so as to be converted into MIR instructions one by one. It can be seen that, using the compilation method provided in accordance with the present disclosure, the developer only needs to provide the first code developed and designed by the high-level tensor abstraction, that is, only focusing on the intermediate representation of the tensor abstraction without paying attention to the assembly language, and can avoid the limitations faced by the programming methods of high-level languages ​​and assembly languages ​​at the same time, which will reduce the difficulty of code design for developers, without having to pay attention to the underlying assembly language, and avoid the various design details that the underlying assembly language needs to pay attention to, greatly improving programming efficiency.

[0054] According to some embodiments of the present disclosure, before converting the first code into a second code composed of machine intermediate representation instructions, the compilation method further includes: performing a compilation optimization process on the first code. The compilation optimization process may include: finding unused resources in the first code; and removing instructions declaring unused resources from the first code, and using the first code after removing the instructions declaring unused resources as the optimized first code for conversion into the second code.

[0055] According to the first code of the embodiment of the present disclosure, more resource objects may be involved. For example, developers can use tensor resource declaration instructions, scalar resource declaration instructions, synchronous resource declaration instructions, etc. to declare more resources to be processed. As an example, the tensor resource declaration instruction can be described as Tensor A (Shape, Layout, DataType, AddressSpace), which indicates that a tensor resource Tensor A is declared, and its size (Shape), layout (Layout), data type (DataType) and address space (AddressSpace) are specified. Then, there may also be some tensor operation instructions in the first code for performing tensor operations such as convolution and movement on the tensor resource Tensor A therein.

[0056] It is understandable that before converting the first code into the second code, the first code can be optimized by, for example, a PassManager in a compiler. Specifically, the optimization process can include removing invalid code (Dead Code Elimination Pass). This optimization step traverses the first code, finds resources that are not used after declaration, removes instructions that declare the unused resources from the first code, and uses the first code after removing the instructions that declare the unused resources as the optimized first code for conversion into the second code. As an example, the tensor resource TensorA declared above may not be used in subsequent processing. Therefore, it can be seen that this declared tensor resource is invalid. Therefore, the code declaring Tensor A (Tensor A(Shape, Layout, DataType, AddressSpace)) can be removed from the first code, thereby achieving the effect of simplifying the code, avoiding code redundancy, and improving compilation efficiency.

[0057] According to some embodiments of the present disclosure, the above-mentioned compilation optimization process may also include compilation optimization processing such as constant folding, expression simplification, loop expansion, etc. For example, developers may optimize the first code according to actual application requirements, which is not limited here.

[0058] According to some embodiments of the present disclosure, before converting the first code into a second code composed of machine intermediate representation instructions, the compilation method also includes: for a resource declaration instruction in at least one tensor intermediate representation instruction, determining the life cycle of the resource declared by the resource declaration instruction, wherein the life cycle is represented by the first use time and the last use time of the resource; and allocating a physical storage address to the resource according to the life cycle of the resource.

[0059] In the compilation method provided according to the present disclosure, it is possible to perform resource allocation for TIR instructions, for example, perform resource allocation (Resource Allocation Pass) for the optimized second code. As an example, the life cycle of the resources declared by each resource declaration instruction in the first code can be analyzed by a resource allocation algorithm, so that physical resource allocation is performed according to the life cycle. The life cycle (def-use chain) is represented by the first use time and the last use time of the resource. Therefore, according to the compilation method provided according to the present disclosure, the actual physical storage address can be allocated according to the life cycle, and the physical address allocated for the resource can be recycled or reused outside the life cycle of the resource for other resource allocations. This can effectively improve the resource utilization of the storage space. Since the compilation method of the present disclosure is suitable for electronic devices that perform tensor calculations, where the computational complexity of tensor calculations is usually large, effectively improving the resource utilization of the storage space is particularly critical for tensor calculations.

[0060] According to some embodiments of the present disclosure, converting the first code into a second code composed of machine intermediate representation instructions includes: performing an equivalent transformation on the tensor intermediate representation instructions in the first code to generate corresponding machine intermediate representation instructions. Using the compilation method according to the embodiment of the present disclosure, the first code of TIR instructions managed in a container-type structure can be converted into MIR instructions one by one. For example, a TIR instruction can generate one or more MIR-level instruction abstractions through mathematical equivalent transformation. The generated MIR instructions are included in one or more MBB containers. The instructions in the MBB container are only allowed to have a jump instruction at the end. The jump instruction allows jumping to the first machine intermediate representation instruction in any third container. The generated MIR instructions in the MBB container structure have a one-to-one mapping relationship with the assembly language.

[0061] For ease of description, the process of converting the above-mentioned TIR-level instructions to MIR-level instructions is represented as a Lower() process, and each TIR instruction can predefine its corresponding Lower() function. As an example, the Lower function can be described as Lower (MIR pointer). Therefore, the above-mentioned conversion process of converting TIR-level instructions to MIR-level instructions can be represented as a process of converting the TIR instruction to a MIR instruction using the Lower() function predefined for each TIR instruction.

[0062] As an example, Figure 3 FIG. 1 shows a schematic diagram of compiling a first code into an assembly code according to an embodiment of the present disclosure. Figure 3 In the figure, it is shown that Figure 2The process of converting the TIR instruction in the first code into the MIR instruction organized according to the MBB container structure is shown.

[0063] Specifically, Figure 3 As shown, the first TIR instruction in container 1 (the instruction shown by the diagonal shadow) is converted into three MBB containers ( Figure 3 , which are respectively shown as 9 MIR instructions ("MIR instructions (MachineInstruction)" shown by diagonal shadows) consisting of basic block container 1 (MBB 1), basic block container 2 (MBB 2) and basic block container 3 (MBB 3)). It can be understood that for each TIR instruction, a Lower function can be defined accordingly so as to convert it into a MIR instruction during the compilation stage. For other instructions in the first code, they can be converted into MIR instructions one by one in a similar manner, and the description will not be repeated here.

[0064] In addition, precisely because the TIR instructions in the first code according to the embodiment of the present disclosure are organized and managed in a container-type recursive structure, the logical relationship is clear during the conversion into MIR-level instructions, and they can be quickly and one by one converted into machine intermediate representation instructions, thereby improving compilation efficiency.

[0065] According to some embodiments of the present disclosure, converting a first code into a second code composed of machine intermediate representation instructions also includes: in the process of performing equivalent transformation on the tensor intermediate representation instructions in the first code, allocating a temporary storage address to the equivalent transformation process according to the allocated physical storage address, wherein the temporary storage address is only valid during the equivalent transformation process.

[0066] It is understandable that in the above-mentioned conversion process from TIR instructions to MIR instructions, some temporary storage space may be required. The scope of these temporary storage spaces will not exceed the current instruction, that is, they are only used in the Lower process, and the allocated temporary storage space becomes invalid after the Lower process is executed. Therefore, according to the compilation method disclosed in the present invention, in the Lower process, the physical storage space allocated for the first code can be first obtained, and then temporary resource allocation can be performed in the Lower stage.

[0067] According to the embodiment of the present disclosure, the resource allocation process is carried out in two stages. The first stage is to perform a resource allocation algorithm on the TIR level instructions to perform actual physical address allocation according to the life cycle (def-use chain) of the resources. In the second stage, temporary storage address allocation is performed in the process of converting the first code composed of TIR instructions into the second code composed of MIR instructions. According to the physical address of the above resource allocation, the resource allocation required for the subsequent assembly code generation can be automatically completed. Therefore, the compilation method according to the present disclosure does not require programmers to manually write assembly code for resource allocation, thereby improving programming development efficiency.

[0068] According to some embodiments of the present disclosure, before converting the second code into assembly code, the compilation method further includes: performing a compilation optimization process on the second code, wherein the compilation optimization process includes: finding unused resources in the second code; and removing instructions that declare unused resources from the second code, and using the second code after removing the instructions that declare unused resources as the optimized second code for conversion into assembly code. The optimization process for the second code is similar to the optimization process for the first code above, and will not be repeated here.

[0069] As a specific example, Figure 4 Another schematic diagram of compiling a first code into an assembly code according to an embodiment of the present disclosure is shown, which shows the overall execution flow of compiling the code using the compilation method according to an embodiment of the present disclosure.

[0070] refer to Figure 4 In step S401, a tensor code (TensorProgram) composed of tensor intermediate representation instructions is obtained, that is, it can correspond to the above-mentioned first code. As an example, the development code can be written by the developer according to the above-mentioned container-type recursive structure, which includes, for example, the structured control flow instructions for describing the control instruction flow of nested loops or loop judgments, resource declaration instructions for declaring resource storage space, tensor operation instructions for performing calculation operations on tensors, and other miscellaneous instructions required for the design, which are not limited here.

[0071] Next, in S402, the obtained tensor code is processed by PassManager to obtain an optimized tensor code (Optimized Tensor Program). For example, PassManager can be the optimization process for removing invalid code (Dead Code Elimination Pass) and the resource allocation process (Resource Allocation Pass) described above. It can be understood that other types of Pass processing can also be performed in step S402, which is not limited here.

[0072] In step S403, the optimized tensor code is converted into a machine code (Machine Program) composed of machine intermediate representation instructions using the Lower function, and the machine code corresponds to the second code. The machine code is composed of the MIR instructions described above and is included in one or more MBB containers, and the MIR instructions in the MBB container correspond one-to-one to the assembly language.

[0073] In step S404, the machine code in step S403 is optimized by PassManager, for example, invalid codes are removed to obtain optimized machine code (Optimized Machine Program).

[0074] Finally, in step S405, the optimized machine code is printed through the Print() function to obtain assembly code (Assembly). The assembly code can perform parallel calculations on tensor objects.

[0075] By using the compilation method according to the embodiment of the present disclosure, the first code obtained by designing and developing with high-level tensor abstraction can be converted into assembly code to complete the required design function. After compilation, high-performance assembly code is obtained, which improves programming efficiency. Developers only need to focus on the intermediate representation of tensor abstraction without paying attention to assembly language, which can effectively avoid the limitations faced by high-level languages ​​and assembly language programming methods. Moreover, the compiled assembly code can meet the development needs of computers based on high-level language programming in various application scenarios, improve development performance and realize parallel computing. In addition, designing and developing with high-level tensor abstraction can isolate the impact of ISA changes on the software framework in the early stage of hardware-software collaborative design.

[0076] According to a second aspect of the present disclosure, an electronic device is also provided. Figure 5 A schematic block diagram of an electronic device according to an embodiment of the present disclosure is shown. Figure 5 As shown, the electronic device 200 according to an embodiment of the present disclosure may include a processor 201 and a non-transitory memory 202. The non-transitory memory 202 stores program code, and when the program code is executed by the processor 201, the processor 201 executes the steps of the compilation method according to the present disclosure.

[0077] As an example, the electronic device according to the present disclosure may be implemented as any one of a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), an NPU (Neural network Processing Unit), a DPU (Deep learning Processing Unit), an APU (Accelerated Processing Unit), and a GPGPU (General-Purpose computing on Graphics Processing Unit), and may also be any conventional processor, etc. For example, the processor here may refer to a processor chip capable of parallel computing.

[0078] The non-transitory memory 202 stores a computer-readable code, which, when executed by the processor 201, can cause the processor to implement the steps of the compilation method according to some embodiments of the present disclosure. The non-transitory memory 202 can also be any suitable type of memory. As an example, by executing the computer-readable code in the non-transitory memory 202, the processor can implement the steps of the compilation method described above in conjunction with the accompanying drawings.

[0079] It is understandable that the electronic device according to the embodiment of the present disclosure can also be implemented as any form of computing device or processor for performing tensor calculations, etc., without limitation herein, and can compile the first code designed and developed with high-level tensor abstraction according to the compilation method described above, and obtain high-performance assembly code capable of parallel computing. The specific steps performed by the electronic device according to the embodiment of the present disclosure can refer to the above description of the compilation method according to the present disclosure, and will not be repeated here.

[0080] Figure 6 The schematic diagram of the architecture of an exemplary electronic device according to an embodiment of the present disclosure is shown. The electronic device in the embodiment of the present disclosure may be any one of the above-mentioned GPU, TPU, NPU, DPU, APU, and GPGPU. Figure 6 The electronic device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0081] For example, Figure 6As shown, in some examples, the electronic device 300 includes a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 301, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 302 or a program loaded from a storage device 308 to a random access memory (RAM) 303. Various programs and data required for the operation of the computer system are also stored in RAM 303. The processing device 301, ROM 302, and RAM 303 are connected to each other via a bus 304. An input / output (I / O) interface 305 is also connected to the bus 304.

[0082] For example, the following components may be connected to the I / O interface 305: an input device 306 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 307 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 308 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 309 including a network interface card such as a LAN card, a modem, etc. The communication device 309 may allow the electronic device 300 to communicate with other devices wirelessly or by wire to exchange data, performing communication processing via a network such as the Internet. A drive 310 is also connected to the I / O interface 305 as needed. Removable media 311, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., are installed on the drive 310 as needed, so that a computer program read therefrom can be installed into the storage device 309 as needed. Although Figure 6 The electronic device 300 including various devices is shown, but it should be understood that it is not required to implement or include all the devices shown. More or fewer devices may be implemented or included instead.

[0083] For example, the electronic device 300 may further include a peripheral interface (not shown in the figure), etc. The peripheral interface may be various types of interfaces, such as a USB interface, a lightning interface, etc. The communication device 309 may communicate with a network and other devices through wireless communication.

[0084] For example, according to an embodiment of the present disclosure, the process described above with reference to the flowchart may be implemented as a computer software program.For example, an embodiment of the present disclosure includes a computer program product including a computer program carried on a non-transitory computer-readable medium.

[0085] According to a third aspect of the present disclosure, a non-transitory computer-readable storage medium is also provided, on which computer-readable instructions are stored. When the computer-readable instructions are executed by a processor, the processor executes the steps of the compilation method according to the present disclosure.

[0086] Figure 7 Schematic block diagram of a storage medium according to an embodiment of the present disclosure is shown. Figure 7 As shown, a computer-readable storage medium 400 stores computer-readable instructions 401. When the computer-readable instructions 401 are executed by a processor, the compilation method described with reference to the above figures can be executed.

[0087] It should be noted that the computer-readable storage medium provided by the present disclosure may be, for example, (but not limited to) an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In an embodiment of the present disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program, which may be used by or in combination with an instruction execution system, device or device. The above-mentioned computer-readable medium may be contained in the above-mentioned electronic device, or may exist alone without being assembled into the electronic device.

[0088] The embodiments of the present disclosure provide a compilation method, an electronic device, and a storage medium for implementing design and development based on high-level tensor abstraction, compiling to obtain high-performance assembly code, and improving programming efficiency.

[0089] By using the compilation method, electronic device and storage medium provided by the present disclosure, the first code for processing the tensor object can be compiled, and finally the assembly code for execution can be obtained. By using the compilation method, electronic device and storage medium according to the present disclosure, it is possible to implement design and development with high-level tensor abstraction, and obtain high-performance assembly code after compilation, thereby improving programming efficiency, and the compiled assembly code can meet the development requirements of computers based on high-level language programming in various application scenarios, thereby improving development performance.

[0090] Those skilled in the art will appreciate that the contents disclosed in this disclosure may be subject to various modifications and improvements. For example, the various devices or components described above may be implemented by hardware, or by software, firmware, or a combination of some or all of the three.

[0091] In addition, although the present disclosure makes various references to certain units in a computing device or electronic device according to an embodiment of the present disclosure, any number of different units may be used and run on a client and / or server. The units are merely illustrative, and different aspects of a data transmission method, computing device, or electronic device may use different units.

[0092] Those skilled in the art will appreciate that all or part of the steps in the above data transmission method can be completed by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk. Optionally, all or part of the steps in the above embodiment can also be implemented using one or more integrated circuits. Accordingly, each module / unit in the above embodiment can be implemented in the form of hardware or in the form of a software functional module. The present disclosure is not limited to any particular form of combination of hardware and software.

[0093] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It should also be understood that terms such as those defined in common dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an idealized or highly formal sense, unless explicitly defined as such herein.

[0094] The above is an explanation of the present disclosure and should not be considered as a limitation thereof. Although several exemplary embodiments of the present disclosure are described, it will be readily understood by those skilled in the art that many modifications may be made to the exemplary embodiments without departing from the novel teachings and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure as defined in the claims. It should be understood that the above is an explanation of the present disclosure and should not be considered to be limited to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The present disclosure is defined by the claims and their equivalents.

Claims

1. A compiling method, characterized in that: The method comprises: Obtaining a first code for processing a tensor object, wherein the first code is composed of at least one tensor intermediate representation instruction included in a first container, wherein the at least one tensor intermediate representation instruction includes a structured control flow instruction, and the structured control flow instruction includes a second container for describing a control instruction flow of a nested loop or a loop judgment, so that the first code has a recursive container structure, wherein the first container and the second container have the same structure; converting the first code into a second code consisting of machine intermediate representation instructions, wherein the machine intermediate representation instructions are included in one or more third containers, and the machine intermediate representation instructions have a one-to-one mapping relationship with the assembly language; and The second code is converted into assembly code.

2. The method according to claim 1, characterized in that Before converting the first code into a second code consisting of machine intermediate representation instructions, the method further comprises: Performing a compilation optimization process on the first code, wherein the compilation optimization process includes: searching for unused resources in the first code; and The instruction declaring the unused resource is removed from the first code, and the first code after the instruction declaring the unused resource is removed is used as the optimized first code for conversion into the second code.

3. The method according to claim 1, characterized in that Before converting the first code into a second code consisting of machine intermediate representation instructions, the method further comprises: For a resource declaration instruction in the at least one tensor intermediate representation instruction, determining a life cycle of a resource declared by the resource declaration instruction, wherein the life cycle is represented by a first use time and a last use time of the resource; and A physical storage address is allocated to the resource according to the life cycle of the resource.

4. The method according to claim 3, characterized in that The converting the first code into a second code consisting of machine intermediate representation instructions comprises: Perform an equivalent transformation on the tensor intermediate representation instruction in the first code to generate a corresponding machine intermediate representation instruction.

5. The method according to claim 4, characterized in that The converting the first code into a second code consisting of machine intermediate representation instructions further comprises: In the process of performing equivalent transformation on the tensor intermediate representation instruction in the first code, a temporary storage address is allocated to the equivalent transformation process according to the allocated physical storage address, wherein the temporary storage address is only valid during the equivalent transformation process.

6. The method according to claim 1, characterized in that Before converting the second code into assembly code, the method further includes: Performing a compilation optimization process on the second code, wherein the compilation optimization process includes: searching for unused resources in the second code; and The instruction declaring the unused resource is removed from the second code, and the second code after the instruction declaring the unused resource is removed is used as the optimized second code for conversion into the assembly code.

7. The method according to claim 1, characterized in that The at least one tensor intermediate representation instruction also includes: a resource declaration instruction for declaring a resource storage space, a tensor operation instruction for performing calculation operations on a tensor, a scalar calculation instruction, and miscellaneous instructions, wherein the miscellaneous instructions include order preservation instructions.

8. The method according to claim 1, characterized in that The instructions in the third container are only allowed to have a jump instruction at the end, and the jump instruction allows jumping to the first machine intermediate representation instruction in any third container in the second code.

9. The method according to claim 1, characterized in that: The assembly code obtained by converting the second code is used to perform parallel calculations on the tensor object.

10. An electronic device, characterized in that: The electronic device comprises a processor and a non-transitory memory, wherein the non-transitory memory stores a program code, and when the program code is executed by the processor, the processor executes the steps of the compiling method according to any one of claims 1 to 9.

11. A non-transitory computer-readable storage medium having computer-readable instructions stored thereon, wherein when the computer-readable instructions are executed by a processor, the processor is caused to perform the steps of the compilation method according to any one of claims 1 to 9.

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