Back contact solar cell, battery module and photovoltaic system

Abstract

The present invention is applicable to the technical field of solar cells, and provides a back-contact solar cell, a battery assembly and a photovoltaic system. The back-contact solar cell comprises: a silicon substrate, the silicon substrate having a back side and a front side arranged relatively; a P-type doped polysilicon layer, located in a first region on the back side of the silicon substrate; an N-type doped polysilicon layer, located in a second region on the back side of the silicon substrate, and the first region is different from the second region; a P-type doped inner expansion layer, formed inside the silicon substrate and arranged close to the P-type doped polysilicon layer; an N-type doped inner expansion layer, formed inside the silicon substrate and arranged close to the N-type doped polysilicon layer; wherein the depth of the P-type doped inner expansion layer is greater than the depth of the N-type doped inner expansion layer. The back-contact solar cell provided by the present invention sets the depth of the P-type doped inner expansion layer to be greater than the depth of the N-type doped inner expansion layer, and increasing the depth of the P-type doped inner expansion layer can improve the emitter current collection efficiency of the back-contact solar cell, thereby improving the battery efficiency.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular to a back-contact solar cell, a cell assembly and a photovoltaic system. Background Art

[0002] Solar cell power generation is a sustainable source of clean energy. It uses the photovoltaic effect of semiconductor pn junction to convert sunlight into electrical energy, and the conversion efficiency is an important indicator of solar cell performance. IBC (Interdigitated back contact) solar cells, also known as interdigitated back contact cells, have positive and negative electrodes designed on the back of the cell, so that the front surface is completely free from the shading of metal grid lines, eliminating the optical loss caused by the shading of metal grid lines. At the same time, the electrode width can be designed to be wider than the current one, reducing the series resistance loss, thereby greatly improving the cell conversion efficiency. In addition, due to the design of no electrode on the front of the cell, the product appearance is more beautiful and suitable for a variety of application scenarios.

[0003] In the prior art, a staggered P region and N region are formed on the back side of a back-contact solar cell. Usually, when the P-type doped polysilicon layer in the P region and the N-type doped polysilicon layer in the N region are prepared, the P-type doped polysilicon layer will form a P-type doped inner expansion layer inside the silicon wafer, and the N-type doped polysilicon layer will form an N-type doped inner expansion layer inside the silicon wafer. For ease of processing, the depths of the P-type doped inner expansion layer and the N-type doped inner expansion layer are usually roughly equal, which will result in low emitter current collection efficiency, thereby affecting the battery efficiency. Summary of the invention

[0004] The present invention provides a back-contact solar cell, aiming to solve the problem in the prior art that the depths of a P-type doped inner diffusion layer and an N-type doped inner diffusion layer are equal, the emitter current collection efficiency is low, and thus the cell efficiency is affected.

[0005] The present invention is implemented by providing a back contact solar cell, comprising:

[0006] A silicon substrate having a back surface and a front surface arranged opposite to each other;

[0007] A P-type doped polysilicon layer located in a first region on the back side of the silicon substrate;

[0008] An N-type doped polysilicon layer is located in a second region on the back side of the silicon substrate, and the first region is different from the second region;

[0009] A P-type doped inner expansion layer is formed inside the silicon substrate and is disposed close to the P-type doped polysilicon layer;

[0010] An N-type doped inner expansion layer is formed inside the silicon substrate and is disposed close to the N-type doped polysilicon layer;

[0011] Wherein, the depth of the P-type doped inner extension layer is greater than the depth of the N-type doped inner extension layer.

[0012] Preferably, the ratio of the depth of the P-type doped inner extension layer to the depth of the N-type doped inner extension layer is 1-4 and is not equal to 1.

[0013] Preferably, the ratio of the depth of the P-type doped inner extension layer to the depth of the N-type doped inner extension layer is 1-2 and is not equal to 1.

[0014] Preferably, the depth of the P-type doped inner extension layer is 30 to 800 nm; the depth of the N-type doped inner extension layer is 10 to 600 nm.

[0015] Preferably, the width of the P-type doped inner extension layer is greater than the width of the N-type doped inner extension layer.

[0016] Preferably, the ratio of the width of the P-type doped inner extension layer to the width of the N-type doped inner extension layer is 1-2 and is not equal to 1.

[0017] Preferably, the volume of the P-type doped inner extension layer is greater than the volume of the N-type doped inner extension layer.

[0018] Preferably, the ratio of the volume of the P-type doped inner extension layer to the volume of the N-type doped inner extension layer is 1-2 and is not equal to 1.

[0019] Preferably, the thickness of the N-type doped polysilicon layer is greater than the thickness of the P-type doped polysilicon layer.

[0020] Preferably, the ratio of the thickness of the N-type doped polysilicon layer to the thickness of the P-type doped polysilicon layer is 1-2 and is not equal to 1.

[0021] Preferably, the ratio of the thickness of the N-type doped polysilicon layer to the thickness of the P-type doped polysilicon layer is 1 to 1.5, and is not equal to 1.

[0022] Preferably, it also includes:

[0023] a first passivation layer disposed between the P-type doped inner diffusion layer and the P-type doped polysilicon layer, wherein the first passivation layer contains a P-type dopant;

[0024] a second passivation layer disposed between the N-type doped inner diffusion layer and the N-type doped polysilicon layer, wherein the second passivation layer contains an N-type dopant;

[0025] The doping concentration of the P-type dopant in the first passivation layer is less than the doping concentration of the N-type dopant in the second passivation layer.

[0026] Preferably, the doping concentration of the P-type dopant of the P-type doped inner extension layer is less than the doping concentration of the N-type dopant of the N-type doped inner extension layer.

[0027] The present invention also provides a battery assembly, comprising the above-mentioned back-contact solar cell.

[0028] The present invention also provides a photovoltaic system, comprising the above-mentioned battery assembly.

[0029] An embodiment of the present invention provides a back-contact solar cell, in which the depth of a P-type doped inner expansion layer is set to be greater than the depth of an N-type doped inner expansion layer. On the premise that the depth of the N-type doped inner expansion layer remains unchanged and the depth requirement of the N-type doped inner expansion layer is not affected, the depth of the P-type doped inner expansion layer is increased, and the emitter current collection efficiency of the back-contact solar cell can be improved, thereby improving the battery efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A schematic diagram of a back-contact solar cell provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0032] An embodiment of the present invention provides a back-contact solar cell, in which the depth of a P-type doped inner expansion layer is set to be greater than the depth of an N-type doped inner expansion layer. On the premise that the depth of the N-type doped inner expansion layer remains unchanged and the depth requirement of the N-type doped inner expansion layer is not affected, the depth of the P-type doped inner expansion layer is increased, and the emitter current collection efficiency of the back-contact solar cell can be improved, thereby improving the battery efficiency.

[0033] Please refer to Figure 1 , an embodiment of the present invention provides a back contact solar cell, comprising:

[0034] A silicon substrate 1, wherein the silicon substrate 1 has a back surface and a front surface that are arranged opposite to each other;

[0035] A P-type doped polysilicon layer 2, located in a first region on the back side of the silicon substrate 1;

[0036] The N-type doped polysilicon layer 4 is located in a second region on the back side of the silicon substrate 1, and the first region is different from the second region;

[0037] A P-type doped inner extension layer 3 is formed inside the silicon substrate 1 and is disposed close to the P-type doped polysilicon layer 2;

[0038] An N-type doped inner expansion layer 5, which is formed inside the silicon substrate 1 and is disposed close to the N-type doped polysilicon layer 4;

[0039] The depth d3 of the P-type doped inner extension layer 3 is greater than the depth d4 of the N-type doped inner extension layer 5 .

[0040] like Figure 1 As shown, the back side of the silicon substrate 1 is the lower side, and the front side is the upper side. The dotted line L1 and the dotted line L2 are only used to distinguish the first area from the second area, and do not actually exist in the back contact solar cell. Figure 1 , the area on the left side of the dotted line L1 is the first area, the area on the right side of the dotted line L2 is the second area, and the first area and the second area are different areas. The P-type doped polysilicon layer 2 is located in the first area on the back side of the silicon substrate 1, and the N-type doped polysilicon layer 4 is located in the second area on the back side of the silicon substrate 1; the P-type doped polysilicon layer 2 is located in the area on the left side of the dotted line L1 on the back side of the silicon substrate 1; the N-type doped polysilicon layer 4 is located in the area on the right side of the dotted line L2 on the first side of the silicon substrate 1.

[0041] In the embodiment of the present invention, the silicon substrate 1 may be an N-type silicon substrate or a P-type silicon substrate.

[0042] In the embodiment of the present invention, the depth d3 of the P-type doped inner expansion layer 3 is the distance from the back of the silicon substrate 1 to the bottom of the P-type doped inner expansion layer 3, and the depth d4 of the N-type doped inner expansion layer 5 is the distance from the back of the silicon substrate 1 to the bottom of the N-type doped inner expansion layer 5. The back contact solar cell sets the depth d3 of the P-type doped inner expansion layer 3 to be greater than the depth d4 of the N-type doped inner expansion layer 5, and under the premise that the depth of the N-type doped inner expansion layer 5 remains unchanged and does not affect the depth of the N-type doped inner expansion layer 5, by increasing the depth of the P-type doped inner expansion layer 3, the emitter current collection efficiency of the back contact solar cell can be improved, thereby improving the battery efficiency.

[0043] In practical applications, the heat treatment temperature and time during the preparation of the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 4 can be adjusted so that after the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 4 are prepared, the depth d3 of the P-type doped inner expansion layer 3 is greater than the depth d4 of the N-type doped inner expansion layer 5, thereby effectively improving the battery efficiency. For example, controlling the heat treatment temperature of the P-type doped polysilicon layer 2 to be greater than the heat treatment temperature of the N-type doped polysilicon layer 4 or controlling the heat treatment time of the P-type doped polysilicon layer 2 to be greater than the heat treatment time of the N-type doped polysilicon layer 4 can both make the depth d3 of the P-type doped inner expansion layer 3 greater than the depth d4 of the N-type doped inner expansion layer 5; or, controlling the heat treatment temperature of the P-type doped polysilicon layer 2 to be greater than the heat treatment temperature of the N-type doped polysilicon layer 4 and controlling the heat treatment time of the P-type doped polysilicon layer 2 to be greater than the heat treatment time of the N-type doped polysilicon layer 4 can also make the depth d3 of the P-type doped inner expansion layer 3 greater than the depth d4 of the N-type doped inner expansion layer 5.

[0044] As an embodiment of the present invention, the ratio of the depth d3 of the P-type doped inner extension layer 3 to the depth d4 of the N-type doped inner extension layer 5 is 1-4 and is not equal to 1.

[0045] In this embodiment, the ratio of the depth d3 of the P-type doped inner expansion layer 3 to the depth d4 of the N-type doped inner expansion layer 5 is set to be greater than 1 and less than or equal to 4, which can not only improve the emitter current collection efficiency of the back contact solar cell and improve the battery efficiency, but also facilitate the control of the depth difference between the P-type doped inner expansion layer 3 and the N-type doped inner expansion layer 5, and facilitate the processing of the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 4.

[0046] For example, the ratio of the depth d3 of the P-type doped inner extension layer 3 to the depth d4 of the N-type doped inner extension layer 5 may be:

[0047] 1.01, or 1.08, or 1.1, or 1.15, or 1.2, or 1.25, or 1.3, or 1.35, or 1.4, or 1.45, or 1.5, or 1.55, or 1.6, or 1.65, or 1.7, or 1.75, or 1.8, or 1.85, or 1.9, or 1.92, or 2.0; or 2.2, or 2.3, or 2.5, or 2.6, or 2.9, or 3.0, or 3.5, or 3.7, or 3.8, or 3.9, or 4.0.

[0048] As an embodiment of the present invention, the ratio of the depth d3 of the P-type doped inner extension layer 3 to the depth d4 of the N-type doped inner extension layer 5 is 1-2.

[0049] In this embodiment, the ratio of the depth d3 of the P-type doped inner expansion layer 3 to the depth d4 of the N-type doped inner expansion layer 5 is set to be greater than 1 and less than or equal to 2, which can ensure that the depth d3 of the P-type doped inner expansion layer 3 and the depth d4 of the N-type doped inner expansion layer 5 are within a more appropriate range, which can not only improve the emitter current collection efficiency of the back contact solar cell, improve the battery efficiency, but also facilitate the processing of the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 4.

[0050] As an embodiment of the present invention, the depth d3 of the P-type doped inner extension layer 3 is 30-800 nm; the depth d4 of the N-type doped inner extension layer 5 is 10-600 nm.

[0051] For example, the depth d3 of the P-type doped inner extension layer 3 can be 30nm, or 50nm, or 80nm, or 100nm, or 150nm, or 180nm, or 220nm, or 250nm, or 280nm, or 300nm, or 350nm, or 400nm, or 450nm, or 500nm, or 560nm, or 600nm, or 650nm, or 680nm, or 700nm, or 720nm, or 780nm, or 800nm.

[0052] For example, the depth d4 of the N-type doped inner extension layer 5 may be 10 nm, 50 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 240 nm, 350 nm, 400 nm, 450 nm, 500 nm, 550 nm, or 600 nm.

[0053] As an embodiment of the present invention, the width of the P-type doped inner extension layer 3 is greater than the width of the N-type doped inner extension layer 5 .

[0054] In this embodiment, the width of the P-type doped inner expansion layer 3 is greater than the width of the N-type doped inner expansion layer 5, so that the area of ​​the P-type doped inner expansion layer 3 can be greater than the area of ​​the N-type doped inner expansion layer 5, the area of ​​the P-type doped inner expansion layer 3 can be increased, and the emitter current collection efficiency of the back contact solar cell can be further improved, thereby improving the battery efficiency. Specifically, the width of the P-type doped polysilicon layer 2 can be increased, thereby increasing the width of the P-type doped inner expansion layer 3 formed by the diffusion of the P-type doped polysilicon layer 2 into the silicon substrate 1, that is, the width of the P-type doped polysilicon layer 2 is greater than the width of the N-type doped polysilicon layer 4.

[0055] As an embodiment of the present invention, the ratio of the width of the P-type doped inner expansion layer 3 to the width of the N-type doped inner expansion layer 5 is 1 to 2, and is not equal to 1, which can ensure that the width of the P-type doped inner expansion layer 3 and the width of the N-type doped inner expansion layer 5 are kept within a suitable range, maintain a high battery efficiency, and facilitate the preparation of the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 4. Among them, the width of the P-type doped inner expansion layer 3 corresponds to the width of the P-type doped polysilicon layer 2, and the width of the N-type doped inner expansion layer 5 corresponds to the width of the N-type doped polysilicon layer 4. The width of the P-type doped inner expansion layer 3 can be changed accordingly by adjusting the width of the P-type doped polysilicon layer 2, and the width of the N-type doped inner expansion layer 5 can be changed accordingly by adjusting the width of the N-type doped polysilicon layer 4. The width of the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 4 can be flexibly set according to actual conditions.

[0056] As an embodiment of the present invention, the volume of the P-type doped inner extension layer 3 is greater than the volume of the N-type doped inner extension layer 5 .

[0057] In this embodiment, the volume of the P-type doped inner expansion layer 3 is greater than the volume of the N-type doped inner expansion layer 5, so that the volume of the P-type doped inner expansion layer 3 can be greater than the volume of the N-type doped inner expansion layer 5, the volume of the P-type doped inner expansion layer 3 can be increased, and the emitter current collection efficiency of the back contact solar cell can be further improved, thereby improving the battery efficiency. Specifically, the width or depth of the P-type doped polysilicon layer 2 can be increased, thereby increasing the volume of the P-type doped inner expansion layer 3 formed by the diffusion of the P-type doped polysilicon layer 2 into the silicon substrate 1, that is, the volume of the P-type doped polysilicon layer 2 is greater than the volume of the N-type doped polysilicon layer 4.

[0058] As an embodiment of the present invention, the ratio of the volume of the P-type doped inner extension layer 3 to the volume of the N-type doped inner extension layer 5 is 1-2, and is not equal to 1.

[0059] In this embodiment, the ratio of the volume of the P-type doped inner expansion layer 3 to the volume of the N-type doped inner expansion layer 5 is greater than 1 and less than or equal to 2, which can ensure that the volume of the P-type doped inner expansion layer 3 and the volume of the N-type doped inner expansion layer 5 are kept within a suitable range, maintain a high battery efficiency, and facilitate the preparation of the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 4. Among them, the width of the P-type doped inner expansion layer 3 corresponds to the width of the P-type doped polysilicon layer 2, the width of the N-type doped inner expansion layer 5 corresponds to the width of the N-type doped polysilicon layer 4, the depth d3 of the P-type doped inner expansion layer 3 corresponds to the heat treatment temperature and heat treatment time of the P-type doped polysilicon layer 2, and the depth d4 of the N-type doped inner expansion layer 5 corresponds to the heat treatment temperature and heat treatment time of the N-type doped polysilicon layer 4. Therefore, under the premise that the depth d3 of the P-type doped inner extension layer 3 is greater than the depth d4 of the N-type doped inner extension layer 5, the width of the P-type doped polysilicon layer 2 is set to be greater than or equal to the width of the N-type doped polysilicon layer 4, so that the volume of the P-type doped inner extension layer 3 can be greater than the volume of the N-type doped inner extension layer 5.

[0060] As an embodiment of the present invention, it also includes:

[0061] A first passivation layer 8 disposed between the P-type doped inner extension layer 3 and the P-type doped polysilicon layer 2, wherein the first passivation layer 8 contains a P-type dopant;

[0062] A second passivation layer 10 disposed between the N-type doped inner extension layer 5 and the N-type doped polysilicon layer 4, wherein the second passivation layer 10 contains an N-type dopant;

[0063] The doping concentration of the P-type dopant in the first passivation layer 8 is less than the doping concentration of the N-type dopant in the second passivation layer 10 .

[0064] In this embodiment, the passivation layer 8 is specifically a silicon dioxide passivation layer. By providing the first passivation layer 8 and the second passivation layer 10, and the doping concentration of the P-type dopant of the first passivation layer 8 is less than the doping concentration of the N-type dopant of the second passivation layer 10, the impurity gettering effect of the N region is improved, thereby improving the battery efficiency.

[0065] As an embodiment of the present invention, the doping concentration of the P-type dopant of the P-type doped inner extension layer 3 is lower than the doping concentration of the N-type dopant of the N-type doped inner extension layer 5 , which can further enhance the gettering effect of the N region.

[0066] As an embodiment of the present invention, the thickness of the N-type doped polysilicon layer 4 is greater than the thickness of the P-type doped polysilicon layer 2 .

[0067] In this embodiment, under the premise that the thickness d1 of the N-type doped polysilicon layer 4 remains unchanged and the effect of the N-type doped polysilicon layer 4 is not affected, the thickness d2 of the P-type doped polysilicon layer 2 is reduced, thereby reducing the etching difficulty of the P-type doped polysilicon and the difficulty of the patterning process, and facilitating the patterning process of the P-type doped polysilicon; moreover, reducing the thickness d2 of the P-type doped polysilicon layer 2 can reduce the difficulty of boron diffusion, which is beneficial to the boron diffusion process and facilitates the preparation of a P-type doped polysilicon layer 2 with a higher concentration; moreover, the thickness d1 of the N-type doped polysilicon layer 4 is greater than the thickness d2 of the P-type doped polysilicon layer 2, and the N-type doped polysilicon is thicker than the P-type doped polysilicon layer 2, which can enhance the passivation effect and improve the battery efficiency. Moreover, since the back contact solar cell first prepares the P-type doped polysilicon layer 2 on the entire surface and then prepares the N-type doped polysilicon layer 4, when preparing the N-type doped polysilicon layer 4, it is necessary to first etch and remove the P-type doped polysilicon in the N region. Therefore, in this embodiment, by reducing the thickness of the P-type doped polysilicon layer 2 , the difficulty of etching the P-type doped polysilicon is reduced, and the P-type doped polysilicon in the N region is removed cleanly, which facilitates the preparation of the N-type doped polysilicon layer 4 .

[0068] As an embodiment of the present invention, the ratio of the thickness d1 of the N-type doped polysilicon layer 4 to the thickness d2 of the P-type doped polysilicon layer 2 is 1-2 and is not equal to 1.

[0069] In this embodiment, the ratio of the thickness d1 of the N-type doped polysilicon layer 4 to the thickness d2 of the P-type doped polysilicon layer 2 is greater than 1 and less than or equal to 2, which can reduce the etching difficulty of the P-type doped polysilicon layer 2, facilitate the patterning process of the P-type doped polysilicon layer 2, and facilitate the boron diffusion process, reduce the difficulty of boron diffusion, and facilitate the preparation of a higher concentration of the P-type doped polysilicon layer 2. Moreover, more importantly, it can prevent the metallization damage of the P-type doped polysilicon layer 2 from being too large or the contact resistance from being too large, thereby reducing the loss of battery efficiency.

[0070] For example, the ratio of the thickness d1 of the N-type doped polysilicon layer 4 to the thickness d2 of the P-type doped polysilicon layer 2 may be:

[0071] 1.01, or 1.05, or 1.1, or 1.15, or 1.2, or 1.25, or 1.3, or 1.35, or 1.4, or 1.45, or 1.5, or 1.55, or 1.6, or 1.65, or 1.7, or 1.75, or 1.8, or 1.85, or 1.9, or 1.92, or 2.

[0072] Optionally, when the ratio of d1 to d2 is 1 to 2, the thickness d1 of the N-type doped polysilicon layer 4 is 100nm to 600nm, and the thickness d2 of the P-type doped polysilicon layer 2 can be 50nm to 300nm. When d1 and d2 are within the above range, both the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 4 can easily achieve good doping effects, and both have good passivation effects, while ensuring that the metallization damage is small and the contact resistance is small, and the cost is relatively low; in addition, the etching difficulty of the P-type doped polysilicon can be reduced, which is convenient for the patterning process of the P-type doped polysilicon, and is conducive to the boron diffusion process, reducing the difficulty of boron diffusion, and facilitating the preparation of a high-concentration P-type doped polysilicon layer 2.

[0073] For example, the thickness d1 of the N-type doped polysilicon layer 4 may be 100 nm, or 105 nm, or 135 nm, or 145 nm, or 173 nm, or 185 nm, or 200 nm, or 240 nm, or 285 nm, or 300 nm, or 301 nm, or 342 nm, or 367 nm, or 370 nm, or 420 nm, or 456 nm, or 482 nm, or 500 nm, or 550 nm, or 570 nm, or 590 nm, or 600 nm.

[0074] For example, the thickness d2 of the P-type doped polysilicon layer 2 can be 50nm, or 45nm, or 52nm, or 60nm, or 66.7nm, or 73nm, or 81nm, or 90nm, or 92nm, or 100nm, or 112nm, or 133nm, or 144nm, or 175nm, or 190nm, or 211nm, or 243nm, or 270nm, or 282nm, or 296nm, or 300nm.

[0075] As an embodiment of the present invention, the ratio of the thickness d1 of the N-type doped polysilicon layer 4 to the thickness d2 of the P-type doped polysilicon layer 2 is 1-1.5 and is not equal to 1.

[0076] In this embodiment, the ratio of the thickness d1 of the N-type doped polysilicon layer 4 to the thickness d2 of the P-type doped polysilicon layer 2 is greater than 1 and less than or equal to 1.5. This can reduce the processing cost of the thickness d1 of the N-type doped polysilicon layer 4 and the P-type doped polysilicon layer 2, facilitate the patterning process of the P-type doped polysilicon, and is beneficial to the boron diffusion process and facilitates the preparation of a higher concentration of the P-type doped polysilicon layer 2; and can prevent the metallization damage of the P-type doped polysilicon layer 2 from being too large or the contact resistance from being too large, thereby reducing the loss of battery efficiency.

[0077] As an embodiment of the present invention, it also includes:

[0078] A first metal electrode 6, located in a first region on the back side of the silicon substrate 1 and in contact with the P-type doped polysilicon layer 2;

[0079] The second metal electrode 7 is located in the second region on the back side of the silicon substrate 1 and is in contact with the N-type doped polysilicon layer 42 .

[0080] In this embodiment, the depth of the metal crystals of the metal electrode entering the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 4 can be controlled by controlling the temperature and time during the metallization process. Preferably, the depth of the metal crystals of the first metal electrode 6 entering the P-type doped polysilicon layer 2 is greater than the depth of the metal crystals of the second metal electrode 7 entering the N-type doped polysilicon layer 4, which can improve the contact effect between the first metal electrode 6 and the P-type doped polysilicon layer 2, thereby improving the battery conversion efficiency.

[0081] As an embodiment of the present invention, the back-contact solar cell further includes a back passivation film layer 9 located on the surfaces of the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 4 to further improve the conversion efficiency of the back-contact solar cell.

[0082] As an embodiment of the present invention, the silicon substrate 1 is further provided with a groove 12 between the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 4. The P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 4 are physically isolated by the groove 12, which can further improve the isolation effect of the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 4, and further reduce the risk of short circuit or leakage. Among them, the width of the groove can be flexibly set according to actual needs and is not limited here.

[0083] As an embodiment of the present invention, the front side of the silicon substrate 1 has a suede structure (not shown), which can achieve a good light trapping effect and improve the conversion efficiency of the back contact solar cell. In addition, a front passivation anti-reflection film layer 11 can also be provided on the front side of the back contact solar cell to further improve the conversion efficiency of the back contact solar cell.

[0084] The embodiment of the present invention further provides a battery assembly, which includes the back-contact solar cell of the above embodiment. It should be noted that the battery assembly and the back-contact solar cell have the same or similar beneficial effects, and the relevant parts between the two can be referenced to each other. In order to avoid repetition, they will not be described here.

[0085] The embodiment of the present invention also provides a photovoltaic system, which includes the battery assembly of the above embodiment. It should be noted that the battery assembly has the same or similar beneficial effects as the back contact solar cell, and the relevant parts between the two can be referenced to each other. In order to avoid repetition, it will not be repeated here.

[0086] An embodiment of the present invention provides a back-contact solar cell, in which the depth of a P-type doped inner expansion layer is set to be greater than the depth of an N-type doped inner expansion layer. On the premise that the depth of the N-type doped inner expansion layer remains unchanged and the depth requirement of the N-type doped inner expansion layer is not affected, the depth of the P-type doped inner expansion layer is increased, and the emitter current collection efficiency of the back-contact solar cell can be improved, thereby improving the battery efficiency.

[0087] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A back contact solar cell, characterized in that: include: A silicon substrate, wherein the silicon substrate is an N-type silicon substrate, and the silicon substrate has a back side and a front side that are arranged opposite to each other; A P-type doped polysilicon layer located in a first region on the back side of the silicon substrate; An N-type doped polysilicon layer is located in a second region on the back side of the silicon substrate, and the first region is different from the second region; A P-type doped inner expansion layer is formed inside the silicon substrate and is disposed close to the P-type doped polysilicon layer; An N-type doped inner expansion layer is formed inside the silicon substrate and is disposed close to the N-type doped polysilicon layer; Wherein, the depth of the P-type doped inner extension layer is greater than the depth of the N-type doped inner extension layer.

2. The back contact solar cell according to claim 1, characterized in that: The ratio of the depth of the P-type doped inner extension layer to the depth of the N-type doped inner extension layer is 1-4 and is not equal to 1.

3. The back contact solar cell according to claim 1, characterized in that: The ratio of the depth of the P-type doped inner extension layer to the depth of the N-type doped inner extension layer is 1-2 and is not equal to 1.

4. The back contact solar cell according to claim 1, characterized in that: The depth of the P-type doped inner extension layer is 30-800 nm; the depth of the N-type doped inner extension layer is 10-600 nm.

5. The back contact solar cell according to claim 1, characterized in that: The width of the P-type doped inner extension layer is greater than the width of the N-type doped inner extension layer.

6. The back contact solar cell according to claim 5, characterized in that: The ratio of the width of the P-type doped inner extension layer to the width of the N-type doped inner extension layer is 1-2 and is not equal to 1.

7. The back contact solar cell according to claim 1, characterized in that: The volume of the P-type doped inner extension layer is greater than the volume of the N-type doped inner extension layer.

8. The back contact solar cell according to claim 7, characterized in that: The ratio of the volume of the P-type doped inner extension layer to the volume of the N-type doped inner extension layer is 1-2 and is not equal to 1.

9. The back contact solar cell according to claim 1, characterized in that: The thickness of the N-type doped polysilicon layer is greater than the thickness of the P-type doped polysilicon layer.

10. The back contact solar cell according to claim 9, characterized in that: The ratio of the thickness of the N-type doped polysilicon layer to the thickness of the P-type doped polysilicon layer is 1-2 and is not equal to 1.

11. The back contact solar cell according to claim 9, characterized in that: The ratio of the thickness of the N-type doped polysilicon layer to the thickness of the P-type doped polysilicon layer is 1 to 1.5, and is not equal to 1.

12. The back contact solar cell according to claim 1, characterized in that: Also includes: a first passivation layer disposed between the P-type doped inner diffusion layer and the P-type doped polysilicon layer, wherein the first passivation layer contains a P-type dopant; a second passivation layer disposed between the N-type doped inner diffusion layer and the N-type doped polysilicon layer, wherein the second passivation layer contains an N-type dopant; The doping concentration of the P-type dopant in the first passivation layer is less than the doping concentration of the N-type dopant in the second passivation layer.

13. The back contact solar cell according to claim 1, characterized in that: The doping concentration of the P-type dopant in the P-type doped inner extension layer is lower than the doping concentration of the N-type dopant in the N-type doped inner extension layer.

14. A battery assembly, characterized in that: A back-contact solar cell comprising the step of:

15. A photovoltaic system, characterized in that: Comprising the battery assembly as claimed in claim 14.

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