A SiC MOSFET crosstalk suppression circuit

Abstract

The present invention discloses a crosstalk suppression circuit for SiC MOSFET, which belongs to the field of power electronics technology and includes: a control circuit, an impedance network and an internal gate-source voltage extraction circuit. The internal gate-source voltage extraction circuit can obtain the voltage v across the gate-source capacitance of the SiC MOSFET. gsint , can correctly reflect the actual crosstalk waveform; the crosstalk suppression control circuit is based on v gsint The comparison result with the reference voltage is used to actively trigger the Miller capacitor C gd and the common source inductor L s The crosstalk suppression method of the invention can quickly and effectively suppress the Miller capacitance C gd and the common source inductor L s Crosstalk under action.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of power electronics, and more particularly relates to a crosstalk suppression circuit of a SiC MOSFET. BACKGROUND

[0002] Power semiconductor devices are the cornerstone of the development of power electronics technology, and provide a fundamental guarantee for efficient conversion of electric energy. The third-generation power semiconductor devices represented by SiC MOSFETs have advantages such as wide band gap, high electron mobility, and high thermal conductivity, and are widely used in rail transit, photovoltaic power generation, aerospace, and new energy vehicles.

[0003] Crosstalk refers to the problem that the high-speed operation of the SiC MOSFET of the active switch in the bridge circuit causes the gate-source voltage of the SiC MOSFET in the off state to change. This is because, under the rapid switching transient, the Miller capacitance C gd and the common-source inductance L s will cause crosstalk of the gate-source voltage under the action of the power side dv / dt and di / dt. When the gate-source voltage is lower than the minimum gate-source voltage allowed for safe operation of the device, it will cause the SiC MOSFET to break down and be damaged; when the gate-source voltage is higher than the threshold voltage for the device to turn on, it will cause the SiC MOSFET to be misdirected on or even cause a bridge arm to be directly on. Therefore, when designing the driving circuit, special attention needs to be paid to the crosstalk problem caused by the high-speed operation of the SiC MOSFET to ensure the reliability of the system.

[0004] At present, the gate driving circuit for suppressing crosstalk can be divided into the following two suppression methods: changing the gate driving voltage and changing the driving loop impedance. However, existing researches usually only aim at the crosstalk caused by C gd , and the crosstalk suppression of C gd will further aggravate the crosstalk caused by L s . In addition, existing crosstalk suppression research lacks the judgment of the type of crosstalk, and cannot actively switch the crosstalk suppression network of C gd and L s under the rapid switching transient of the SiC MOSFET. In summary, the existing crosstalk suppression method cannot effectively suppress the crosstalk under the action of C gd and L s . SUMMARY

[0005] In view of the defects of the prior art and the improvement needs, the application provides a crosstalk suppression circuit of a SiC MOSFET, which aims to distinguish and judge the crosstalk of C gd and L s , and simultaneously effectively realize the crosstalk suppression of C gd and L sCrosstalk suppression under the action of MOSFET can improve system reliability.

[0006] To achieve the above object, the present invention provides a crosstalk suppression circuit for SiC MOSFET, comprising: a control circuit, an impedance network and an internal gate-source voltage extraction circuit; the impedance network includes switch tubes S1, S2, S3, S4 and an inductor L c , the drain of S1 and the drain of S3 are connected to the positive voltage V cc , the source of S1 is connected to the drain of S2, the source of S3 is connected to the drain of S4, and the source of S2 and the source of S4 are connected to the negative voltage V ee , L c connected between the source of S1 and the source of S3, the source of S3 is connected to the gate of the crosstalked SiC MOSFET; the internal gate-source voltage extraction circuit is used to extract the voltage v across the internal gate-source capacitance of the crosstalked SiC MOSFET gsint ; During the crosstalk phase: if the crosstalked SiC MOSFET’s v gsint is lower than the turn-on reference voltage, the control circuit is used to turn on S1 and turn off S2, S3 and S4 to pass the positive voltage V cc and the inductor L c The high-resistance network provided is used to suppress the common-source inductance crosstalk. Otherwise, the control circuit is used to turn on S4 and turn off S1, S2 and S3 to build a low-resistance network to suppress the Miller capacitance crosstalk. In the crosstalk turn-off stage: if the v of the crosstalked SiC MOSFET gsint is higher than the shutdown reference voltage, the control circuit is used to turn on S2 and turn off S1, S3 and S4 to pass the negative voltage V ee and the inductor L c A high-resistance network is provided to suppress the common-source inductor crosstalk. Otherwise, the control circuit is used to turn on S4 and turn off S1, S2 and S3 to build a low-resistance network to suppress the Miller capacitor crosstalk.

[0007] Furthermore, the internal gate-source voltage extraction circuit includes: a first differential amplifier circuit, a second differential amplifier circuit, a third differential amplifier circuit and an addition and subtraction circuit; an external gate sampling resistor R is connected between the two input terminals of the first differential amplifier circuit. gext , the non-inverting input terminal is connected to the source of S3, and the inverting input terminal is connected to the gate of the crosstalked SiC MOSFET; the non-inverting input terminal of the second differential amplifier circuit is connected to the gate of the crosstalked SiC MOSFET, and the inverting input terminal is connected to the source of the crosstalked SiC MOSFET; the external source inductor L is connected between the two input terminals of the third differential amplifier circuit sext, the non-inverting input end of the add-subtract circuit is connected with the output end of the second differential amplification circuit, the inverting input end is connected with the output end of the first differential amplification circuit and the output end of the third differential amplification circuit, and the output end outputs v gsint .

[0008] Further, the gain of the first differential amplification circuit is R gint / R gext ; the gain of the second differential amplification circuit is 1; and the gain of the third differential amplification circuit is L s / L sext , wherein R gint is the internal gate resistance of the crosstalk SiC MOSFET, and L s is the common source inductance of the crosstalk SiC MOSFET.

[0009] Further, the add-subtract circuit comprises resistors R7, R8, R9, R f7 , R f8 and an operational amplifier U4; the inverting input end of the operational amplifier U4 is connected with the output end of the first differential amplification circuit through R9 and with the output end of the third differential amplification circuit through R8; the non-inverting input end of the operational amplifier U4 is connected with the output end of the second differential amplification circuit through R7 and grounded through R f7 ; R f8 is connected between the inverting input end and the output end of the operational amplifier U4, and R7=R8=R9=2R f7 =R f8 .

[0010] Further, the control circuit comprises a first comparator C1, a second comparator C2, a first logic AND gate AND1, a second logic AND gate AND2, a third logic AND gate AND3, a logic NOR gate NOR and a controller; the non-inverting input end of C1 is connected with an on reference voltage, the inverting input end is connected with v gsint , and the output end is connected with one input end of AND1; the other input end of AND1 is connected with an on crosstalk enable signal, and the output end outputs a signal for driving S1; the inverting input end of C2 is connected with an off reference voltage, the non-inverting input end is connected with v gsint , and the output end is connected with one input end of AND2; the other input end of AND2 is connected with an off crosstalk enable signal, and the output end outputs a signal for driving S2; the two input ends of the NOR gate are respectively connected with the output ends of AND1 and AND2, and the output end is connected with one input end of AND3; the other input end of AND3 is connected with a driving PWM signal S 4-1 , and the output end outputs a signal for driving S4; and the controller is used for outputting the on crosstalk enable signal, the off crosstalk enable signal and the driving PWM signal S4-1 and output drive S3.

[0011] Further, the output of AND1 is connected to the gate of S1 through a first gate driver; the output of AND2 is connected to the gate of S2 through a second gate driver; and the output of AND3 is connected to the gate of S4 through a fourth gate driver.

[0012] Further, the control circuit is further configured to determine the type of crosstalk; in the turn-on crosstalk stage, if the v gsint of the SiC MOSFET being crosstalked is lower than a turn-on reference voltage, it is determined that the crosstalk is common-source inductance crosstalk, otherwise, it is determined that the crosstalk is Miller capacitor crosstalk; in the turn-off crosstalk stage, if the v gsint of the SiC MOSFET being crosstalked is higher than a turn-off reference voltage, it is determined that the crosstalk is common-source inductance crosstalk, otherwise, it is determined that the crosstalk is Miller capacitor crosstalk.

[0013] Further, the turn-on reference voltage and the turn-off reference voltage satisfy:

[0014] V gsmin <V ref1 <V ee

[0015] V ee <V ref2 <V th

[0016] wherein, V ref1 is the turn-on reference voltage, V ref2 is the turn-off reference voltage, V gsmin is the minimum gate-source voltage of the SiC MOSFET, and V th is the threshold voltage of the SiC MOSFET in turn-on.

[0017] Overall, the above technical solutions conceived by the present application can achieve the following beneficial effects:

[0018] (1) A crosstalk suppression circuit for SiC MOSFET is provided, which takes into account that in the fast switching transient of SiC MOSFET, the Miller capacitor C gd and the common-source inductance L s will both cause crosstalk to the gate-source voltage of the device, and the crosstalk effects of C gd and L s are opposite and the required suppression methods are contradictory to each other, so it is necessary to accurately determine the type of crosstalk and automatically switch the corresponding crosstalk suppression impedance network, and the existing research lacks a method for determining the type of crosstalk, and also lacks common crosstalk suppression of C gd and L s ;

[0019] L s Under the action of di / dt, the gate-source voltage produces crosstalk, C gd Under the action of dv / dt, the gate-source voltage produces crosstalk, and there is a problem of di / dt and dv / dt stage overlap in the fast switching transient of the silicon carbide device, at this time, L s and C gd act together, v gsint is the final manifestation of L s and C gd crosstalk effect;

[0020] Based on this, a crosstalk suppression control method based on internal gate-source voltage threshold triggering is proposed, which determines the crosstalk reason according to the comparison result of the internal gate-source capacitor voltage v gsint and the reference voltage, and automatically switches the corresponding suppression impedance network, solves the problem of difficult crosstalk type determination in fast switching transient, and realizes common source inductance crosstalk suppression and Miller capacitor crosstalk suppression;

[0021] (2) The existing research directly tests the voltage v gsext between the gate and source pins of the silicon carbide device to reflect crosstalk, however, since v gsext contains the voltage of the gate parasitic resistance R gint , the voltage of the common source inductance L s and cannot correctly reflect the actual crosstalk waveform v gsint , directly using v gsext will lead to crosstalk misjudgment;

[0022] Based on this, the embodiment considers that the SiC MOSFET device is a voltage-controlled device, and determines that the voltage v gs across the gate-source capacitor C gsint correctly reflects the crosstalk; a SiC MOSFET internal gate-source voltage extraction circuit is proposed, which extracts the voltage v gs across the SiC MOSFET internal gate-source capacitor C gsint for determining the crosstalk type, which can accurately reflect the actual crosstalk waveform and be used for crosstalk type determination. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 The overall structure block diagram of the crosstalk suppression circuit of the SiC MOSFET provided by the embodiment of the application;

[0024] Figure 2 The circuit model diagram of the SiC MOSFET provided by the embodiment of the application;

[0025] Figure 3The internal gate-source voltage extraction circuit diagram provided by the embodiment of the present application is shown in the figure;

[0026] Figure 4 、 Figure 5 The two control subunits in the crosstalk suppression control circuit provided by the embodiment of the present application are respectively shown in the figures;

[0027] Figure 6 The impedance network circuit diagram provided by the embodiment of the present application is shown in the figure;

[0028] Figure 7 The key waveform diagram of the SiC MOSFET crosstalk suppression circuit provided by the embodiment of the present application is shown in the figure;

[0029] Figure 8 The equivalent driving circuit diagram of the SiC MOSFET turn-on transient provided by the embodiment of the present application is shown in the figure;

[0030] Figure 9 The equivalent driving circuit diagram of the SiC MOSFET turn-off transient, crosstalk suppression stage II, and crosstalk suppression stage III provided by the embodiment of the present application is shown in the figure;

[0031] Figure 10 The equivalent driving circuit diagram of the crosstalk suppression stage I provided by the embodiment of the present application is shown in the figure;

[0032] Figure 11 The equivalent driving circuit diagram of the crosstalk suppression stage IV provided by the embodiment of the present application is shown in the figure. DETAILED DESCRIPTION

[0033] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and should not be used to limit the present application. In addition, the technical features involved in each embodiment of the present application described below can be combined with each other as long as there is no conflict.

[0034] In the present application, the terms "first", "second", etc. (if any) in the present application and the accompanying drawings are used to distinguish similar objects, and do not necessarily describe a specific order or sequence.

[0035] Figure 1 The overall structure block diagram of the SiC MOSFET crosstalk suppression circuit provided by the embodiment of the present application is shown in the figure. Figure 1 , in combination with Figures 2-11 , the SiC MOSFET crosstalk suppression circuit in the present embodiment is described in detail.

[0036] The SiC MOSFET crosstalk suppression circuit includes a control circuit, an impedance network and an internal gate-source voltage extraction circuit.

[0037] The impedance network comprises switch tubes S1, S2, S3, S4 and an inductor L c The drain of S1 and the drain of S3 are connected to a positive voltage V cc The source of S1 is connected to the drain of S2, the source of S3 is connected to the drain of S4, and the source of S2 and the source of S4 are connected to a negative voltage V ee L c is connected between the source of S1 and the source of S3, and the source of S3 is connected to the gate of the SiC MOSFET subject to crosstalk.

[0038] The internal gate-source voltage extraction circuit is used to extract the voltage v gsint across the internal gate-source capacitance of the SiC MOSFET subject to crosstalk.

[0039] In the turn-on crosstalk phase: if v gsint of the SiC MOSFET subject to crosstalk is lower than a turn-on reference voltage, the control circuit is used to turn on S1 and turn off S2, S3 and S4, so as to provide a high-impedance network through the positive voltage V cc and the inductor L c to suppress the common-source inductance crosstalk, otherwise, the control circuit is used to turn on S4 and turn off S1, S2 and S3, so as to construct a low-impedance network to suppress the Miller capacitance crosstalk.

[0040] In the turn-off crosstalk phase: if v gsint of the SiC MOSFET subject to crosstalk is higher than a turn-off reference voltage, the control circuit is used to turn on S2 and turn off S1, S3 and S4, so as to provide a high-impedance network through the negative voltage V ee and the inductor L c to suppress the common-source inductance crosstalk, otherwise, the control circuit is used to turn on S4 and turn off S1, S2 and S3, so as to construct a low-impedance network to suppress the Miller capacitance crosstalk.

[0041] Referring to Figure 2 , the equivalent circuit model of the SiC MOSFET comprises: an internal gate resistance R gint , a gate parasitic inductance L g , a drain parasitic inductance L d , a common-source inductance L s , a Miller capacitance C gd , a gate-source capacitance C gs , a drain-source capacitance C gd , and a parasitic diode D.

[0042] Preferably, the embodiment of the present application provides an internal gate-source voltage extraction circuit, comprising: a first differential amplification circuit, a second differential amplification circuit, a third differential amplification circuit and a plus-minus circuit.

[0043] An external gate sampling resistor R is connected between the two input terminals of the first differential amplification circuit gext , the source of S3 is connected to the non-inverting input terminal, and the gate of the crosstalked SiC MOSFET is connected to the inverting input terminal.

[0044] The gate of the crosstalked SiC MOSFET is connected to the inverting input terminal of the second differential amplification circuit, and the source of the crosstalked SiC MOSFET is connected to the non-inverting input terminal.

[0045] An external source inductor L is connected between the two input terminals of the third differential amplification circuit sext , and the source of the crosstalked SiC MOSFET is connected to the non-inverting input terminal.

[0046] The non-inverting input terminal of the add-subtract circuit is connected to the output terminal of the second differential amplification circuit, the inverting input terminal is connected to the output terminals of the first differential amplification circuit and the third differential amplification circuit, and the output terminal outputs v gsint .

[0047] Specifically, referring to Figure 3 , the internal gate-source voltage extraction circuit includes: an external gate sampling resistor R gext , an external source inductor L sext , four high-speed operational amplifiers (U1, U2, U3, U4), 17 resistors (R1, R2, R3, R4, R5, R6, R7, R8, R9, R f1 , R f2 , R f3 , R f4 , R f5 , R f6 , R f7 , R f8 ).

[0048] R1, R2, R f1 , R f2 and U1 constitute the first differential amplification circuit; R3, R4, R f3 , R f4 and U2 constitute the second differential amplification circuit; R5, R6, R f5 , R f6 and U3 constitute the third differential amplification circuit; R7, R8, R9, R f7 , R f8 and U4 constitute the add-subtract circuit.

[0049] R gextis connected between the source of S3 and the gate of the SiC MOSFET subject to crosstalk. The source of S3 is connected to the non-inverting input of U1 through R1, the gate of the SiC MOSFET subject to crosstalk is connected to the inverting input of U1 through R2, the non-inverting input of U1 is connected to ground through R f1 , R f2 is connected between the inverting input and the output of U1.

[0050] The gate of the SiC MOSFET subject to crosstalk is connected to the non-inverting input of U2 through R3, the source of the SiC MOSFET subject to crosstalk is connected to the inverting input of U2 through R4, the non-inverting input of U2 is connected to ground through R f3 , R f4 is connected between the inverting input and the output of U2.

[0051] One end of L sext is connected to the non-inverting input of U3 through R5, the other end of L sext is connected to the inverting input of U3 through R6, the source of the SiC MOSFET subject to crosstalk is connected to the non-inverting input of U3 through R5, the non-inverting input of U3 is connected to ground through R f5 , R f6 is connected between the inverting input and the output of U3.

[0052] The inverting input of operational amplifier U4 is connected to the output of the first differential amplification circuit through R9 and to the output of the third differential amplification circuit through R8; the non-inverting input of operational amplifier U4 is connected to the output of the second differential amplification circuit through R7 and to ground through R f7 ; R f8 is connected between the inverting input and the output of operational amplifier U4. R7=R8=R9=2R f7 =R f8 . The output of operational amplifier U4 is v gsint .

[0053] Preferably, the gain of the first differential amplification circuit is R gint / R gext , i.e. let R1=R2, R f1 =R f2 , R f1 / R1=R gint / R gext . The gain of the second differential amplification circuit is 1, i.e. let R3=R4=R f3 =R f4 . The gain of the third differential amplification circuit is L s / L sext , i.e. let R5=R6, R f5 =R f6 and Rf5 / R5 = L s / L sext . Wherein, R gint is the internal gate resistance of the SiC MOSFET being crosstalked, L s is the common source inductance of the SiC MOSFET being crosstalked.

[0054] It should be noted that the internal gate-source voltage extraction circuit in the embodiment can also adopt other structures to extract the voltage v gs across the internal gate-source capacitance (i.e. C gsint ) of the SiC MOSFET being crosstalked.

[0055] Preferably, the embodiment of the present application provides a control circuit. Referring to Figure 5 , the control circuit comprises a first comparator C1, a second comparator C2, a first logic AND gate AND1, a second logic AND gate AND2, a third logic AND gate AND3, and a logic NOR gate NOR.

[0056] The non-inverting input terminal of C1 is connected with the turn-on reference voltage, the inverting input terminal is connected with v gsint , and the output terminal is connected with one input terminal of AND1; the other input terminal of AND1 is connected with the turn-on crosstalk enable signal, and the output terminal outputs the signal for driving S1.

[0057] The non-inverting input terminal of C2 is connected with the turn-off reference voltage, the inverting input terminal is connected with v gsint , and the output terminal is connected with one input terminal of AND2; the other input terminal of AND2 is connected with the turn-off crosstalk enable signal, and the output terminal outputs the signal for driving S2.

[0058] The two input terminals of NOR are respectively connected with the output terminals of AND1 and AND2, and one input terminal of AND3 is connected with the output terminal of NOR; the other input terminal of AND3 is connected with the driving PWM signal S 4-1 , and the output terminal outputs the signal for driving S4.

[0059] Further, the control circuit further comprises a controller, as shown in Figure 4 . The controller is used to output the turn-on crosstalk enable signal S Lon , the turn-off crosstalk enable signal S Loff , the driving PWM signal S 4-1 , and the signal P S3 for driving S3. The controller can be a DSP or an FPGA.

[0060] The output terminal of AND1 is connected with the gate of S1 through a first gate driver; the output terminal of AND2 is connected with the gate of S2 through a second gate driver; and the controller outputs P S3The output end of AND2 is connected to the gate of S3 through a third gate driver, and the output end of AND3 is connected to the gate of S4 through a fourth gate driver, as shown in Figure 6 Preferably, the switch tubes S1, S2, S3 and S4 are gallium nitride high electron mobility transistors (GaN HEMT).

[0061] In this embodiment, the control circuit is further configured to determine the type of crosstalk. Specifically, in the turn-on crosstalk stage, if the v gsint of the SiC MOSFET being crosstalked is lower than the turn-on reference voltage, it is determined as common-source inductance crosstalk, otherwise, it is determined as Miller capacitor crosstalk; in the turn-off crosstalk stage: if the v gsint of the SiC MOSFET being crosstalked is higher than the turn-off reference voltage, it is determined as common-source inductance crosstalk, otherwise, it is determined as Miller capacitor crosstalk.

[0062] Preferably, the turn-on reference voltage and the turn-off reference voltage satisfy:

[0063] V gsmin <V ref1 <V ee

[0064] V ee <V ref2 <V th

[0065] wherein V ref1 is the turn-on reference voltage, V ref2 is the turn-off reference voltage, V gsmin is the minimum gate-source voltage of the SiC MOSFET, and V th is the threshold voltage of the SiC MOSFET in turn-on state.

[0066] In this embodiment, the control of the crosstalk suppression circuit includes: in the turn-on crosstalk stage, controlling the common-source inductance L s crosstalk, in the turn-on crosstalk stage, controlling the Miller capacitor C gd crosstalk, in the turn-off crosstalk stage, controlling the Miller capacitor C gd crosstalk, and in the turn-off crosstalk stage, controlling the common-source inductance L s crosstalk.

[0067] In the turn-on crosstalk stage, under the control of suppressing the common-source inductance L s crosstalk, when the switch tube S1 is turned on and S2, S3 and S4 are turned off, a high-impedance gate loop is provided through V cc -S1-L c -Q, combined with the positive voltage V cc of the driving power supply, to suppress the negative crosstalk under the action of the common-source inductance L s .

[0068] Turn-on crosstalk stage suppresses Miller capacitance C gd Control of crosstalk, and turn-off crosstalk stage suppresses Miller capacitance C gd Control of crosstalk, and turn-off crosstalk stage suppresses Miller capacitance C ee Control of crosstalk, and turn-off crosstalk stage suppresses Miller capacitance C gd Control of crosstalk, and turn-off crosstalk stage suppresses Miller capacitance C

[0069] Turn-off crosstalk stage suppresses common-source inductance L s Control of crosstalk, and turn-off crosstalk stage suppresses Miller capacitance C ee Control of crosstalk, and turn-off crosstalk stage suppresses Miller capacitance C c Control of crosstalk, and turn-off crosstalk stage suppresses Miller capacitance C ee Control of crosstalk, and turn-off crosstalk stage suppresses Miller capacitance C s Control of crosstalk, and turn-off crosstalk stage suppresses Miller capacitance C

[0070] The specific working principle of the crosstalk suppression circuit of the SiC MOSFET in the embodiment of the application will be described in detail below. Figures 4-11 The working waveform of the crosstalk suppression circuit of the crosstalk SiC MOSFET is divided into eight stages, which are a driving turn-on stage, a turn-on clamping stage, a driving turn-off stage, a turn-off clamping stage, a crosstalk suppression stage I, a crosstalk suppression stage II, a crosstalk suppression stage III, and a crosstalk suppression stage IV, as shown in the figure. Among them, the driving turn-on stage, the turn-on clamping stage, the driving turn-off stage, and the turn-off clamping stage are the turn-on or turn-off process of the crosstalk SiC MOSFET, and do not need to be suppressed by crosstalk; the crosstalk suppression stages I-IV are the stages of being crosstalked, and are in the turn-off state, and need to be suppressed by the crosstalk suppression circuit of the SiC MOSFET.

[0071] As Figure 7 shown, the working waveform of the crosstalk suppression circuit of the crosstalk SiC MOSFET is divided into eight stages, which are a driving turn-on stage, a turn-on clamping stage, a driving turn-off stage, a turn-off clamping stage, a crosstalk suppression stage I, a crosstalk suppression stage II, a crosstalk suppression stage III, and a crosstalk suppression stage IV. Among them, the driving turn-on stage, the turn-on clamping stage, the driving turn-off stage, and the turn-off clamping stage are the turn-on or turn-off process of the crosstalk SiC MOSFET, and do not need to be suppressed by crosstalk; the crosstalk suppression stages I-IV are the stages of being crosstalked, and are in the turn-off state, and need to be suppressed by the crosstalk suppression circuit of the SiC MOSFET.

[0072] Driving turn-on stage [t0, t1]: in the driving PWM signal generated by the DSP or FPGA, the driving PWM signal P S3 of the switch S3 is high level, the driving PWM signal S 4-1 of the switch S4 is low level; the turn-on crosstalk enable signal S Lon and the turn-off crosstalk enable signal S Loff are all low level. In addition, as Figure 5 shown, the output P S1 of the first logic AND gate AND1 is low level, the output P S2 of the second logic AND gate AND2 is low level. The driving PWM signal S 4-1 of the switch S4 is low level, and the output PS4 is low level. Figure 8 As shown, the switch tube S3 is turned on, and the switch tubes S1, S2, and S4 are all kept off. cc -S3-R gext To charge the gate of SiC MOSFET, the internal gate-source voltage v gsint Start to rise, this stage until v gsint Rising to V cc Ends when.

[0073] Turn-on clamping phase [t1, t2]: SiC MOSFET internal gate-source voltage v gsint The positive voltage V of the driving power supply is clamped by the switch tube S3. cc , the switch tubes S1, S2, and S4 all remain off.

[0074] Driving off stage [t2, t3]: In the driving PWM signal generated by DSP or FPGA, the driving PWM signal S of the switch tube S4 is 4-1 The driving PWM signal P of the switch tube S3 is high. S3 Is low level. Turn on the crosstalk enable signal S Lon And turn off the crosstalk enable signal S Loff In addition, if Figure 5 As shown, the output P of the first logic AND gate AND1 S1 is low, the output P of the second logic AND gate AND2 S2 The low level P S1 With low level P S2 S output by NOR gate 4-2 The driving PWM signal S of the switch tube S4 is high. 4-1 The output P of the third logic AND gate AND3 is high. S4 is high level. Figure 9 As shown, the switch tube S4 is turned on, and the switch tubes S1, S2, and S3 are all kept off. ee -S4-R gext The gate of SiC MOSFET is discharged, and the internal gate-source voltage of SiC MOSFET v gsint Descend until v gsint Drop to the negative voltage of the driving power supply V ee This phase ends when

[0075] Turn-off clamping stage [t3, t4]: SiC MOSFET internal gate-source voltage v gsint The negative voltage V of the driving power supply is clamped by the switch tube S4. ee , the switch tubes S1, S2, and S3 all remain off.

[0076] Crosstalk suppression stage I [t4, t5]: the drive PWM signal S 4-1 of switch S4 is high, and the drive PWM signal P S3 of switch S3 is low. The turn-on crosstalk enable signal S Lon generated by the DSP or FPGA is high, and the turn-off crosstalk enable signal S Loff is low.

[0077] Under the turn-on crosstalk, the drain current i ds of power device Q changes, and the common-source inductance L s is affected to cause the discharge of the gate-source capacitance C gs , so that the voltage v gsint continuously decreases. As shown in FIG. 6, when the voltage v gsint is lower than the first reference voltage V ref1 , the output V C1 of the first comparator C1 is high, and after being ANDed with the turn-on crosstalk enable signal S Lon , the output P S1 of the first logic AND gate AND1 is high, so that the turn-on switch S1 is turned on. Since the turn-off crosstalk enable signal S Loff is low at this time, no matter whether the output V C2 of the second comparator C2 is high or low, the output P C2 of the second logic AND gate AND2 after being ANDed with S Loff is low, so that the switch S2 remains in the turn-off state. The switch S3 does not participate in the crosstalk suppression process, so that the switch S3 remains in the turn-off state.

[0078] The output P S1 of the first logic AND gate AND1 is high, the output P S2 of the second logic AND gate AND2 is low, the voltage S S1 outputted after the NOR gate is operated on P S2 and P 4-2 is low, even if the drive PWM signal S 4-1 of the switch S4 is high, but the output P 4-2 of the third logic AND gate AND3 after being ANDed with S 4-1 and S S4 is low, so that the switch S4 is turned off.

[0079] As shown in FIG. 7, the common-source inductance L s is suppressed by the turn-on crosstalk stage, and the control method of the crosstalk can realize that: the internal gate-source voltage v gsint is continuously decreased, the drain current i ref1 of the power device Q is continuously increased, and the common-source inductance L cc is continuously decreased.gsint Lower than the reference voltage V ref1 When S1 is turned on and S4 is turned off, switches S2 and S3 remain in the off state. cc To suppress the negative crosstalk in this stage, combined with the inductor L c The high-resistance gate loop constructed to suppress L s Crosstalk under action.

[0080] Crosstalk suppression phase II [t5, t6]: Turn on the crosstalk enable signal S Lon is high level; the drain-source voltage v of the power device Q ds Changes in the Miller capacitance C gd The displacement current is generated on the gate-source capacitance C gs Charging, so v gsint Start to rise. Figure 5 As shown, when v gsint Higher than the first reference voltage V ref1 When the output of the first comparator C1 is V C1 is low level, and the crosstalk enable signal S Lon After the AND phase, the first logic gate AND1 outputs P S1 = is low, so the switch tube S1 is turned off. Since the crosstalk enable signal S is turned off at this time Loff is low, regardless of the output V C2 Is it high or low, V C2 With S Loff The output P after the second logic AND gate AND2 S2 Both are low level, so the switch tube S2 remains in the off state. The switch tube S3 does not participate in the crosstalk suppression process, so the switch tube S3 remains in the off state.

[0081] The first logic AND gate AND1 outputs P S1 is low, the output P of the second logic AND gate AND2 S2 Is low level; P S1 With P S2 The output voltage S after the NOR gate 4-2 Is high level; S4 driving PWM signal S 4-1 is high level, high level S 4-2 With high level S 4-1 The output P after the third logic AND gate AND3 S4 It is high level, so the switch tube S4 is turned on.

[0082] like Figure 9 As shown, the Miller capacitance C is suppressed by turning on the crosstalk stage. gd The crosstalk control method can be achieved by:gsint Higher than the reference voltage V ref1 When S4 is turned on and S1 is turned off, switches S2 and S3 remain in the off state; a negative gate drive voltage V ee To suppress the forward crosstalk at this stage, the low-resistance gate loop constructed by the switch tube S4 is used to suppress C gd Crosstalk under action.

[0083] Turn-off clamping stage [t6, t7]: In the driving PWM signal generated by DSP or FPGA, the driving PWM signal S of the switch tube S4 is 4-1 The driving PWM signal P of the switch tube S3 is high. S3 Is low level. Turn on the crosstalk enable signal S Lon is low, turning off the crosstalk enable signal S Loff is low level. Figure 5 As shown, the first logic AND gate AND1 outputs P S1 is low, so the switch tube S1 remains off; the output P of the second logic AND gate AND2 S2 is low level, so the switch tube S2 remains off; the driving PWM signal P of the switch tube S3 S3 is low level, so the switch tube S3 remains off; the low level P S1 With P S2 After passing through the NOR gate, the output S 4-2 Is high level; S4 driving PWM signal S 4-1 is high level, high level S 4-2 With high level S 4-1 The output P after the third logic AND gate AND3 S4 It is at a high level, so the switch tube S4 remains on.

[0084] Crosstalk suppression phase III [t7, t8]: In the driving PWM signal generated by DSP or FPGA, the driving PWM signal S of the switch tube S4 is 4-1 The driving PWM signal P of the switch tube S3 is high. S3 Is low level. Turn on the crosstalk enable signal S Lon is low, turning off the crosstalk enable signal S Loff is high level.

[0085] Under the off crosstalk, the drain-source voltage v of the power device Q ds Changes in the Miller capacitance C gd The displacement current generated on the gate-source capacitance C gs discharge, so v gsint Start to descend. Figure 5 As shown, when v gsint Lower than the second reference voltage V ref2When the output of the second comparator C2 is V C2 is low level, and turns off the crosstalk enable signal S Loff After the AND phase, the second logic gate AND2 outputs P S2 = is low level, so the switch tube S2 remains in the off state. Lon is low, regardless of the output V C1 Is it high or low, V C1 With S Lon The output P after the first logic AND gate AND1 S1 Both are low level, so the switch tube S1 remains in the off state. The switch tube S3 does not participate in the crosstalk suppression process, so the switch tube S3 remains in the off state.

[0086] The voltage P output by the first logic AND gate AND1 S1 is low, the output P of the second logic AND gate AND2 S2 Is low level; P S1 With P S2 After passing through the NOR gate, the output S 4-2 Is high level; S4 driving PWM signal S 4-1 is high level, high level S 4-2 With high level S 4-1 The output P after the third logic AND gate AND3 S4 It is at a high level, so the switch tube S4 remains on.

[0087] like Figure 9 As shown, the Miller capacitance C is suppressed by turning on the crosstalk stage. gd The crosstalk control method can be achieved by: gsint Lower than the reference voltage V ref2 When the switch S4 is turned on, the switches S1-S3 are kept off. The low-resistance gate loop constructed by the switch S4 is used to suppress the C gd Crosstalk under action.

[0088] Crosstalk suppression phase IV [t8, t9]: Turn off the crosstalk enable signal S Loff is high level; the drain current i of the power device Q ds Changes, acting on the common source inductance L s The voltage generated on the gate-source capacitance C gs Charging, so v gsint Start to rise. Figure 5 As shown, when v gsint Higher than the second reference voltage V ref2 When the output of the second comparator C2 is V C2 is high level, and turns off the crosstalk enable signal SLoff After the AND phase, the second logic gate AND2 outputs P S2 = is high, and the switch tube S2 is turned on. Since the crosstalk enable signal S Lon is low, regardless of the output V C1 Is it high or low, V C1 With S Lon The output P after the first logic AND gate AND1 S1 Both are low level, so the switch tube S1 remains in the off state. The switch tube S3 does not participate in the crosstalk suppression process, so the switch tube S3 remains in the off state.

[0089] The first logic AND gate AND1 outputs P S1 is low, the output P of the second logic AND gate AND2 S2 is high level; low level P S1 With high level P S2 After passing through the NOR gate, the output S 4-2 Is low level; even if the driving PWM signal S 4-1 is high level, S 4-2 With S 4-1 The output P after the third logic AND gate AND3 S4 It is at a low level, so the switch tube S4 is turned off.

[0090] like Figure 11 As shown, the common source inductance L is suppressed by turning on the crosstalk phase. s The crosstalk control method can be achieved by: gsint Higher than the second reference voltage V ref2 When S2 is turned on and S4 is turned off, the switches S1 and S3 remain in the off state. ee To suppress the forward crosstalk at this stage, combined with the inductor L c The high-resistance gate loop constructed to suppress L s Crosstalk under action.

[0091] Turn off clamping stage [t9,t 10 ]: Among the driving PWM signals generated by DSP or FPGA, the driving PWM signal S of the switch tube S4 is 4-1 The driving PWM signal P of the switch tube S3 is high. S3 Is low level. Turn on the crosstalk enable signal S Lon is low, turning off the crosstalk enable signal S Loff is low level. Figure 5 As shown, the first logic AND gate AND1 outputs P S1 is low, so the switch tube S1 remains off; the output P of the second logic AND gate AND2S2 is low, so the switch tube S2 is turned off; the driving PWM signal P S3 is low, so the switch tube S3 remains off; the low-level P S1 is high, so the switch tube S3 is turned on. S2 is outputted by the NOR gate NOR and is low. 4-2 is high; the driving PWM signal S 4-1 is high, so the switch tube S4 is turned on. 4-2 is high, so the switch tube S4 is turned on. 4-1 is outputted by the third logic AND gate AND3. S4 is high, so the switch tube S4 is turned on.

[0092] Referring to Figure 7 , at t 10 , the driving on process of the SiC MOSFET in the next cycle is started, which will not be described here again. It should be noted that, Figure 7 The internal gate-source voltage waveform shown in the above is only used to help understand the working principle of the present application, and does not represent the actual working waveform.

[0093] The SiC MOSFET crosstalk suppression circuit provided by the embodiment of the present application extracts the internal gate-source capacitance C gs of the SiC MOSFET gsint is used to determine the crosstalk type, instead of using the power device peripheral gate-source voltage v gsext , which can accurately reflect the actual crosstalk waveform and be used for the determination of the crosstalk type, so that the crosstalk reason can be accurately determined and the C gd or L s crosstalk suppression can be automatically triggered under the fast switching transient state.

[0094] Those skilled in the art will easily understand that the above description is only the preferred embodiment of the present application, and is not used to limit the present application, and any modification, equivalent replacement and improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A crosstalk suppression circuit for SiC MOSFET, characterized in that: include: control circuit, impedance network and internal gate-source voltage extraction circuit; The impedance network includes switches S1, S2, S3, S4 and an inductor L c , the drain of S1 and the drain of S3 are connected to the positive voltage V cc , the source of S1 is connected to the drain of S2, the source of S3 is connected to the drain of S4, and the source of S2 and the source of S4 are connected to the negative voltage V ee , L c Connected between the source of S1 and the source of S3, the source of S3 is connected to the gate of the SiC MOSFET that is crosstalked; The internal gate-source voltage extraction circuit is used to extract the voltage v across the internal gate-source capacitance of the crosstalked SiC MOSFET. gsint ; During the crosstalk phase, if the crosstalked SiC MOSFET’s v gsint is lower than the turn-on reference voltage, the control circuit is used to turn on S1 and turn off S2, S3 and S4 to pass the positive voltage V cc and the inductor L c A high-resistance network is provided to suppress the common-source inductor crosstalk. Otherwise, the control circuit is used to turn on S4 and turn off S1, S2 and S3 to build a low-resistance network to suppress the Miller capacitance crosstalk; During the crosstalk turn-off phase: If the crosstalked SiC MOSFET’s v gsint is higher than the shutdown reference voltage, the control circuit is used to turn on S2 and turn off S1, S3 and S4 to pass the negative voltage V ee and the inductor L c A high-resistance network is provided to suppress the common-source inductor crosstalk. Otherwise, the control circuit is used to turn on S4 and turn off S1, S2 and S3 to build a low-resistance network to suppress the Miller capacitance crosstalk; The internal gate-source voltage extraction circuit includes: a first differential amplifier circuit, a second differential amplifier circuit, a third differential amplifier circuit and an addition and subtraction circuit; An external gate sampling resistor R is connected between the two input terminals of the first differential amplifier circuit. gext , the non-inverting input is connected to the source of S3, and the inverting input is connected to the gate of the SiC MOSFET being crosstalked; The non-inverting input terminal of the second differential amplifier circuit is connected to the gate of the crosstalked SiC MOSFET, and the inverting input terminal is connected to the source of the crosstalked SiC MOSFET; The external source inductor L is connected between the two input terminals of the third differential amplifier circuit. sext , the non-inverting input terminal is connected to the source of the SiC MOSFET that is crosstalked; The non-inverting input terminal of the addition and subtraction circuit is connected to the output terminal of the second differential amplifier circuit, the inverting input terminal is connected to the output terminal of the first differential amplifier circuit and the output terminal of the third differential amplifier circuit, and the output terminal outputs v gsint .

2. The crosstalk suppression circuit for SiC MOSFET according to claim 1, wherein: The gain of the first differential amplifier circuit is R gint / R gext The gain of the second differential amplifier circuit is 1; the gain of the third differential amplifier circuit is L s / L sext , where R gint is the internal gate resistance of the SiC MOSFET affected by crosstalk, L s is the common-source inductance of the SiC MOSFET affected by crosstalk.

3. The crosstalk suppression circuit for SiC MOSFET according to claim 1, wherein: The addition and subtraction circuit includes: resistors R7, R8, R9, R f7 、R f8 and operational amplifier U4; The inverting input terminal of the operational amplifier U4 is connected to the output terminal of the first differential amplifier circuit through R9 and to the output terminal of the third differential amplifier circuit through R8; the non-inverting input terminal of the operational amplifier U4 is connected to the output terminal of the second differential amplifier circuit through R7 and to the output terminal of the third differential amplifier circuit through R8. f7 Ground; R f8 Connected between the inverting input and output of operational amplifier U4, R7=R8=R9=2R f7 =R f8 .

4. The crosstalk suppression circuit for SiC MOSFET according to any one of claims 1 to 3, wherein: The control circuit includes: a first comparator C1, a second comparator C2, a first logic AND gate AND1, a second logic AND gate AND2, a third logic AND gate AND3, a logic NOR gate NOR and a controller; The non-inverting input of C1 is connected to the turn-on reference voltage, and the inverting input is connected to v gsint , the output end is connected to one input end of AND1; the other input end of AND1 is connected to the crosstalk enable signal, and the output end outputs the signal that drives S1; The inverting input of C2 is connected to the shutdown reference voltage, and the non-inverting input is connected to v gsint , the output end is connected to one input end of AND2; the other input end of AND2 is connected to the crosstalk enable signal, and the output end outputs the signal that drives S2; The two input terminals of NOR are connected to the output terminals of AND1 and AND2 respectively, and the output terminal is connected to one input terminal of AND3; the other input terminal of AND3 is connected to the driving PWM signal S 4-1 , the output terminal outputs the signal that drives S4; The controller is used to output the crosstalk enable signal, the crosstalk enable signal and the driving PWM signal S 4-1 , and outputs the signal that drives S3.

5. The crosstalk suppression circuit for SiC MOSFET according to claim 4, wherein: The output end of AND1 is connected to the gate of S1 through a first gate driver; the output end of AND2 is connected to the gate of S2 through a second gate driver; and the output end of AND3 is connected to the gate of S4 through a fourth gate driver.

6. The crosstalk suppression circuit for SiC MOSFET according to claim 1, wherein: The control circuit is also used to determine the type of crosstalk; During the crosstalk phase, if the crosstalked SiC MOSFET’s v gsint If it is lower than the turn-on reference voltage, it is determined to be common-source inductance crosstalk; otherwise, it is determined to be Miller capacitance crosstalk; During the crosstalk turn-off phase: If the crosstalked SiC MOSFET’s v gsint If it is higher than the shutdown reference voltage, it is determined to be common-source inductor crosstalk; otherwise, it is determined to be Miller capacitor crosstalk.

7. The crosstalk suppression circuit for SiC MOSFET according to claim 1 or 6, wherein: The turn-on reference voltage and the turn-off reference voltage satisfy: In gsmin <V ref1 <V ee In ee <V ref2 <V th Among them, V ref1 is the turn-on reference voltage, V ref2 is the shutdown reference voltage, V gsmin is the minimum gate-source voltage of SiC MOSFET, V th is the threshold voltage for SiC MOSFET to turn on.

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