A constant power output system

Abstract

The application discloses a constant power output system, which comprises a MOS tube MP, a source electrode of the MOS tube MP inputs a load voltage Vbat, a drain electrode of the MOS tube MP outputs a load current Ibat, a first ADC module, which can convert the load voltage Vbat into a digital signal X, a second ADC module, which can convert the load current Ibat into a digital signal Y, the first ADC module and the second ADC module are b byte precision ADCs (b is an integer and b>0), a constant power module, the constant power module outputs a PWM signal to drive the MOS tube MP, and the constant power module adjusts a duty cycle D of the PWM signal according to the digital signal X and the digital signal Y to output a constant power P1, wherein D=Ton / T, Ton is a conduction time, and T is a period of the PWM signal.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of constant power output, and particularly relates to a constant power output system. BACKGROUND

[0002] In common direct current heating applications in which a resistance wire is used as a heating wire, in order to ensure the stability of heating, the power on the heating wire needs to be constant, while the voltage value on the heating wire varies in a large range, and the resistance of the heating wire also varies with temperature. In order to achieve constant power output, the voltage and current of the resistance wire need to be dynamically adjusted. Existing applications often use an MCU to monitor the power information of the heating wire to achieve constant power, but the cost of the MCU is high and the product scheme development is relatively complex. SUMMARY

[0003] The present application aims to at least solve one of the problems in the prior art, and provide a constant power output system which uses a pure hardware low-cost method to achieve high-precision constant power output.

[0004] The constant power output system according to the embodiments of the present application comprises a MOS tube MP, a source electrode of the MOS tube MP inputs a load voltage Vbat, and a drain electrode of the MOS tube MP outputs a load current Ibat.

[0005] A first ADC module is capable of converting the load voltage Vbat into a digital signal X.

[0006] A second ADC module is capable of converting the load current Ibat into a digital signal Y.

[0007] The first ADC module and the second ADC module are b-byte precision ADCs (b is an integer and b>0).

[0008] A constant power module outputs a PWM signal to drive the MOS tube MP, and adjusts the duty cycle D of the PWM signal according to the digital signal X and the digital signal Y to output a constant power P1.

[0009] Wherein D=Ton / T, Ton is the on time, and T is the period of the PWM signal.

[0010] According to some embodiments of the present application, the period T of the PWM signal is constant, and the constant power module adjusts the on time Ton of the PWM signal to adjust the duty cycle D of the PWM signal according to the digital signal X and the digital signal Y.

[0011] According to some embodiments of the present application, the on time Ton is constant, and the constant power module adjusts the period T of the PWM signal to adjust the duty cycle D of the PWM signal according to the digital signal X and the digital signal Y.

[0012] According to some embodiments of the present application, T = Z * CLK, CLK is the clock period of the first ADC module and the second ADC module or the clock period of the PWM signal, Z is the number of periods, and Z = D1 * D2 * X * Y / P1, and Z ≥ 2b, D1 is the resolution of the load voltage Vbat, D2 is the resolution of the load current Ibat;

[0013] Ton = K * CLK, K is a constant;

[0014] Then D = Ton / T = K / Z.

[0015] According to some embodiments of the present application, the constant K is in the range of 2 (b-1) ~ 2 (b+1) .

[0016] According to some embodiments of the present application, the first ADC module comprises a variable resistor R1, a resistor R2, a comparator comp, a digital circuit 1, one end of the variable resistor R1 inputs the load voltage Vbat, the other end of the variable resistor R1 is electrically connected with one end of the resistor R2 and one input end of the comparator comp respectively, the other end of the resistor R2 is grounded, the output end of the comparator comp is electrically connected with the input end of the digital circuit 1, and the output end of the digital circuit 1 outputs a digital signal X; the digital circuit 1 outputs n at the nth clock rising edge to set the resistance value of the variable resistor R1 to n * R (n is an integer that gradually increases, and 1 ≤ n ≤ 2b), wherein the reference voltage of the comparator comp is Vf, the resistor R2 = K1 * R (K1 is a constant), the resolution D1 = the reference voltage Vf / K1, and the digital signal X = n + K1.

[0017] According to some embodiments of the present application, the value of K1 is in the range of 2 b ~ 2 (b+1) .

[0018] According to some embodiments of the present application, the second ADC module comprises an adjustable current source, a sampling circuit, a comparison circuit and a digital circuit 2, the adjustable current source outputs a current I1, the input end of the adjustable current source inputs the load voltage Vbat, the sampling end of the sampling circuit is electrically connected with the drain of a MOS transistor MP, the output end of the adjustable current source and the output end of the sampling circuit are electrically connected with the input end of the comparison circuit respectively, the comparison circuit outputs a pulse signal by comparing the current I1 and the sampling current of the sampling circuit to control the digital circuit 2 to output a digital signal Y; the digital circuit 2 outputs m at the mth clock rising edge to set the current I1 of the adjustable current source to (K2 + m) uA, m is an integer that gradually increases, and 1 ≤ m ≤ 2 b , K2 is a constant, and Y = K2 + m.

[0019] According to some embodiments of the present application, the sampling circuit comprises MOS MS, operational amplifier A, MOS MN0, MOS MN1, MOS MN2, the amplification factor of the operational amplifier A is A1, the gate of the MOS MS inputs the PWM signal, the source of the MOS MS inputs the load voltage Vbat, the drain of the MOS MS is electrically connected with the source of the MOS MN0 and one input terminal of the operational amplifier A respectively, the other input terminal of the operational amplifier A inputs the load current Ibat, the output terminal of the operational amplifier A is electrically connected with the gate of the MOS MN0, the drain of the MOS MN0 is electrically connected with the drain of the MOS MN1, the gate of the MOS MN1 and the gate of the MOS MN2 respectively, the drain of the MOS MN2 is electrically connected with the input terminal of the comparison circuit, the amplification factor of the MOS MN2 relative to the MOS MN1 is A2; then the resolution D2=(A1*A2)uA, the output current I2 of the MOS MN2=load current Ibat / resolution D2=Ibat / (A1*A2).

[0020] According to some embodiments of the present application, the comparison circuit comprises a Schmitt trigger SCT, when the current I1>the current I2, the output of the Schmitt trigger SCT will jump from 0 to 1, so that the digital circuit 2 outputs the next digital signal Y.

[0021] The constant power output system according to the embodiments of the present application has at least the following beneficial effects: the present application does not need to use the high-cost MCU, but only needs to convert the load voltage Vbat and the load current Ibat into the digital signal X and the digital signal Y through the low-cost first ADC module and the second ADC module, and then generates the specific PWM signal to control the duty cycle D of the MOS MP through the digital algorithm on the constant power module to realize the output of the constant power P1; the duty cycle is controlled through the digital signal X and the digital signal Y, the logic is simple, and the adjustment and implementation are convenient, so that the present application has low cost and simple structure.

[0022] Additional aspects and advantages of the present application will be given in part in the following description, will become apparent in part from the following description, or will be learned by practice of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0023] The specific embodiments of the present application will be further described below in combination with the drawings;

[0024] Figure 1 is the principle block diagram of the constant power output circuit;

[0025] Figure 2 is the power supply principle diagram of the first ADC module;

[0026] Figure 3 is the power supply principle diagram of the second ADC module;

[0027] Figure 4 Constant power module logic diagram

[0028] Figure 5 Z value table DETAILED DESCRIPTION

[0029] This part will describe the specific embodiments of the present application in detail, the preferred embodiments of the present application are shown in the drawings, the role of the drawings is to supplement the description of the text part with graphics, so that people can intuitively and visually understand each technical feature and the overall technical scheme of the present application, but it cannot be understood as a limitation on the protection scope of the present application.

[0030] In the description of the present application, it should be understood that the orientation description, such as the orientation or position relationship indicated by up, down, front, back, left, right and the like, is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element indicated must have a particular orientation, be constructed and operated in a particular orientation, therefore it cannot be understood as a limitation on the present application.

[0031] In the description of the present application, several meanings are one or more, and the meaning of multiple is two or more, greater than, less than, more than, etc. are understood as not including the number, above, below, etc. are understood as including the number. If it is described as first, second, it is only for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features or implicitly indicating the sequence of indicated technical features.

[0032] Reference Figures 1 to 5 The constant power output system of the present application comprises a MOS tube MP, a first ADC module, a second ADC module and a constant power module, wherein the MOS tube MP can adopt a PMOS tube or an NMOS tube, the PMOS tube is convenient to drive and has lower cost, and the NMOS tube has higher efficiency. The source of the MOS tube MP inputs a load voltage Vbat, and the drain of the MOS tube MP outputs a load current Ibat; the first ADC module can convert the load voltage Vbat into a digital signal X; the second ADC module can convert the load current Ibat into a digital signal Y; the first ADC module and the second ADC module are b byte precision ADCs (b is an integer and b>0); the constant power module outputs a PWM signal to drive the MOS tube MP, and the constant power module adjusts the duty cycle D (D=Ton / T, T is the period of the PWM signal, and Ton is the on time) of the PWM signal according to the digital signal X and the digital signal Y to output a constant power P1.

[0033] In some embodiments, the period T of the PWM signal is constant, and the constant power module adjusts the on time Ton according to the digital signal X and the digital signal Y, so as to adjust the duty cycle D of the PWM signal.

[0034] In some embodiments, the on time Ton is constant, and the constant power module adjusts the period T of the PWM signal according to the digital signal X and the digital signal Y, so as to adjust the duty cycle D of the PWM signal. Preferably, the constant power module adjusts the number of periods Z according to the digital signal X and the digital signal Y, so as to adjust the period T, so that the duty cycle D of the PWM signal changes to output a constant power P1; T = Z * CLK, CLK is the clock period of the first ADC module and the second ADC module or the clock period of the PWM signal, the first ADC module, the second ADC module and the PWM signal can be the same clock or different clocks; wherein Z = D1 * D2 * X * Y / P1, and Z >= 2 b , D1 is the resolution of the load voltage Vbat, D2 is the resolution of the load current Ibat; Ton = K * CLK, K is a constant; D = Ton / T = K / Z is obtained.

[0035] The application does not need to use a high-cost MCU, but only needs to convert the load voltage Vbat and the load current Ibat into digital signals X and Y through low-cost first and second ADC modules, and generate a specific PWM signal through a digital algorithm on the constant power module to control the duty cycle D (D = K / Z, K is an empirical constant) of the MOS tube MP, so as to realize the output of a constant power P1, and the logic of the digital algorithm used is simple. In particular, the relationship between the number of periods Z and X * Y is defined as: Z = D1 * D2 * X * Y / P1, wherein D1 is the resolution of the load voltage Vbat, and D2 is the resolution of the load current Ibat, so that Z is proportional to X * Y, and when Z >= 2b, high-precision adjustment can be realized, the logic is simple, and adjustment and implementation are facilitated. Therefore, the application has low cost, simple structure, and simple and high-precision algorithm of the constant power module.

[0036] Taking an 8W constant power output as an example, P1 = 8W, wherein the accuracy of the first ADC module and the second ADC module is 7bit, i.e. b = 7, and the conversion of the digital signal is realized through 128 steps of comparison:

[0037] As Figure 2As shown in the figure, in some embodiments, the first ADC module includes a variable resistor R1, a resistor R2, a comparator comp, a digital circuit 1, and is composed of only a set of resistors, a comparator and a corresponding digital circuit, occupies a small chip area, and has low cost. One end of the variable resistor R1 inputs a load voltage Vbat, the other end of the variable resistor R1 is electrically connected to one end of the resistor R2 and one input end of the comparator comp respectively, the other end of the resistor R2 is grounded, the output end of the comparator comp is electrically connected to the input end of the digital circuit 1, and the output end of the digital circuit 1 outputs a digital signal X; the digital circuit 1 adopts an existing digital circuit, can output n at the nth clock rising edge to set the resistance value of the variable resistor R1 to n*R (n is an integer that gradually increases, and 1≤n≤128), wherein the reference voltage of the comparator comp is Vf, Vf=2.1V, the resistor R2=K1*R (K1 is a constant), then the resolution D1=reference voltage Vf / K1, and the digital signal X=n+K1.

[0038] Further, the value range of K1 is 2 b ~ 2 (b+1) , that is, 128~256, when in this range, the control accuracy is high. According to experience, K1=140 is adopted, at this time, the digital signal X=n+140, the resolution D1=0.015V, the actual voltage value Vbat is about D1*X=0.015*X, the range of the range is 2.115V~4.02V, and if it is necessary to change the range and accuracy of Vbat, the comparison reference voltage Vf or the resistor voltage division mode can be changed to achieve the change.

[0039] As shown in the figure, Figure 3 , the second ADC module includes an adjustable current source, a sampling circuit, a comparison circuit and a digital circuit 2, and is composed of only a current sampling, a comparator and a digital circuit, and occupies a very small chip area except for the power part. The adjustable current source outputs a current I1, the input end of the adjustable current source inputs a load voltage Vbat, the sampling end of the sampling circuit is electrically connected to the drain electrode of a MOS tube MP, the output end of the adjustable current source and the output end of the sampling circuit are electrically connected to the input end of the comparison circuit respectively, the comparison circuit outputs a pulse signal by comparing the current I1 and the sampling current of the sampling circuit to control the digital circuit 2 to output a digital signal Y; the digital circuit 2 outputs m at the mth clock rising edge to set the current I1 of the adjustable current source to (K2+m)uA, m is an integer that gradually increases, and 1≤m≤128, K2 is a constant, then Y=K2+m. According to experience, K2=50 is adopted, then I1=(50+m)Ua, and Y=50+m.

[0040] In some embodiments, the sampling circuit comprises a MOS tube MS, an operational amplifier A, a MOS tube MN0, a MOS tube MN1, a MOS tube MN2, the amplification factor of the operational amplifier A is A1, A1 can be 300, the gate of the MOS tube MS inputs the PWM signal, the source of the MOS tube MS inputs the load voltage Vbat, the drain of the MOS tube MS is electrically connected with the source of the MOS tube MN0 and one input terminal of the operational amplifier A, the other input terminal of the operational amplifier A inputs the load current Ibat, the output terminal of the operational amplifier A is electrically connected with the gate of the MOS tube MN0, the drain of the MOS tube MN0 is electrically connected with the drain of the MOS tube MN1, the gate of the MOS tube MN1 and the gate of the MOS tube MN2, the drain of the MOS tube MN2 is electrically connected with the input terminal of the comparison circuit, the amplification factor of the MOS tube MN2 relative to the MOS tube MN1 is A2, A2 can be 100; then the resolution D2=(A1*A2)uA=30000uA=30mA, the output current I2 of the MOS tube MN2=load current Ibat / resolution D2=Ibat / (A1*A2)=Ibat / 30000. In some embodiments, the comparison circuit comprises a Schmitt trigger SCT, when the current I1>the current I2, the output of the Schmitt trigger SCT will jump from 0 to 1, so that the digital circuit 2 outputs the next digital signal Y. The actual load current Ibat is about D2*Y=30Ma*Y, the range of the load current Ibat is 1.53A-5.34A, if it is needed to change the range and the accuracy of the load current Ibat, the current sampling ratio A1, A2 and the constant K2 can be changed to achieve the change.

[0041] The derivation process of the relationship between the clock cycle number Z of the PWM signal and X*Y is as follows:

[0042] When the MOS tube MP is turned on, the transient power P0 is:

[0043] P0=Ibat*Vbat=(D1*Y)*(D2*X)=D1*D2*X*Y

[0044] Since the period T of the PWM signal=Z*CLK, the on time Ton is fixed as K*CLK, then the output constant power P1(average power) is:

[0045] P1=P0*Ton / T=D1*D2*K*X*Y / Z

[0046] Let α=D1*D2*K, the relationship between the clock cycle number Z of the PWM signal and X*Y can be derived as follows:

[0047] Z=α*XY / P1.

[0048] Among them, the value range of the constant K is 2 (b-1) ~2(b+1) i.e. 64-256, at which time higher precision can be achieved.

[0049] In the present design, D1=15mV, D2=30mA, K=128, P1=8W, so the above formula can be simplified in the present design as:

[0050] Z=0.0072*XY, Z>=128.

[0051] The digital circuit adjusts the period of the PWM according to the value of Z, i.e. constant power output can be achieved.

[0052] In some embodiments, the value of Z can be set by looking up the table of XY, which can reduce the design area of the digital circuit. Taking the present design as an example, Z takes an integer value, X=140+n, the value range of X is 141-268, Y=50+m, the value range of Y is 51-178, so the value range of XY is 7191-47704. The Z value lookup table of the present design of 8W constant power is shown in Table 1, the value range of Z is 128-339, the XY step corresponding to each integer step of Z is 138.89, the XY value corresponding to between Z and Z+1 is taken as the corresponding on period number of Z, the digital circuit takes the period of PWM according to the table in Table 2, i.e. 8W constant output can be achieved. Figure 5 Figure 5

[0053] In addition, reducing the range and precision of the first ADC module and the second ADC module can multiply the number of XY lookup table, which is specific to the design.

[0054] Those skilled in the art can understand that the above preferred modes can be freely combined and superimposed without conflict.

[0055] The above is only the preferred embodiment of the present application, and does not limit the patent scope of the present application, any equivalent structural transformation made under the inventive concept of the present application, or direct or indirect application in other related technical fields is included in the patent protection scope of the present application.​​

Claims

1. A constant power output system, comprising: a MOS transistor MP, a source of the MOS transistor MP inputting a load voltage Vbat, a drain of the MOS transistor MP outputting a load current Ibat; a first ADC module capable of converting the load voltage Vbat into a digital signal X; a second ADC module capable of converting the load current Ibat into a digital signal Y; the first ADC module and the second ADC module are b-bit precision ADCs, b is an integer and b>0; a constant power module, the constant power module outputs a PWM signal to drive the MOS transistor MP, and the constant power module adjusts a duty cycle D of the PWM signal according to the digital signal X and the digital signal Y to output a constant power P1; wherein D=Ton / T, Ton is the on time, and T is the period of the PWM signal; the on time Ton is constant, and the constant power module adjusts the period T of the PWM signal according to the digital signal X and the digital signal Y to adjust the duty cycle D of the PWM signal; T=Z*CLK, CLK is a clock cycle of the first ADC module and the second ADC module or a clock cycle of a PWM signal, Z is a cycle number, and Z=D1*D2*X*Y / P1, and Z≥2 b D1 is a resolution of a load voltage Vbat, and D2 is a resolution of a load current Ibat. Ton=K*CLK, K is a constant; then D=Ton / T=K / Z.

2. The constant power output system of claim 1, wherein: The constant K has a value in the range of 2 （b-1） ~2 （b +1） .

3. The constant power output system of claim 1, wherein: the first ADC module comprises a variable resistor R1, a resistor R2, a comparator comp, and a digital circuit 1, one end of the variable resistor R1 inputs the load voltage Vbat, the other end of the variable resistor R1 is electrically connected to one end of the resistor R2 and one input terminal of the comparator comp respectively, the other end of the resistor R2 is grounded, the output terminal of the comparator comp is electrically connected to the input terminal of the digital circuit 1, and the output terminal of the digital circuit 1 outputs the digital signal X; the digital circuit 1 outputs n at the nth clock rising edge to set the resistance value of the variable resistor R1 to n*R, n is an integer that increases step by step, and 1≤n≤2b, wherein the reference voltage of the comparator comp is Vf, the resistor R2=K1*R, K1 is a constant, then the resolution D1=reference voltage Vf / K1, and the digital signal X=n+K1.

4. The constant power output system of claim 3, wherein: K1 has a value in the range of 2 b ~2 （b+1） .

5. The constant power output system of claim 1, wherein: the second ADC module comprises an adjustable current source, a sampling circuit, a comparison circuit, and a digital circuit 2, the adjustable current source outputs a current I1, the input terminal of the adjustable current source inputs the load voltage Vbat, the sampling end of the sampling circuit is electrically connected to the drain of the MOS transistor MP, the output terminal of the adjustable current source and the output terminal of the sampling circuit are electrically connected to the input terminals of the comparison circuit respectively, the comparison circuit outputs a pulse signal by comparing the current I1 and the sampling current of the sampling circuit to control the digital circuit 2 to output the digital signal Y; The digital circuit 2 outputs m at the mth clock rising edge, sets the current I1 of the adjustable current source to (K2+m)uA, m is an integer which is gradually increased, and 1≤m≤2 b , K2 is a constant, then Y=K2+m.

6. The constant power output system of claim 5, wherein: The sampling circuit comprises a MOS tube MS, an operational amplifier A, a MOS tube MN0, a MOS tube MN1, a MOS tube MN2, the amplification factor of the operational amplifier A is A1, the gate of the MOS tube MS inputs the PWM signal, the source of the MOS tube MS inputs the load voltage Vbat, the drain of the MOS tube MS is electrically connected with the source of the MOS tube MN0 and one input end of the operational amplifier A respectively, the other input end of the operational amplifier A inputs the load current Ibat, the output end of the operational amplifier A is electrically connected with the gate of the MOS tube MN0, the drain of the MOS tube MN0 is electrically connected with the drain of the MOS tube MN1, the gate of the MOS tube MN1 and the gate of the MOS tube MN2 respectively, the drain of the MOS tube MN2 is electrically connected with the input end of the comparison circuit, the amplification factor of the MOS tube MN2 relative to the MOS tube MN1 is A2, the resolution D2=(A1*A2)uA, the output current I2 of the MOS tube MN2=the load current Ibat / the resolution D2=Ibat / (A1*A2).

7. The constant power output system of claim 6, wherein: The comparison circuit comprises a Schmitt trigger SCT, when the current I1>I2, the output of the Schmitt trigger SCT will jump from 0 to 1, so that the digital circuit 2 outputs the next digital signal Y.

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