Electronic storage device and data transmission method thereof

Abstract

This invention provides an electronic storage device and its data transmission method. The electronic storage device includes: a processor for creating and executing multiple parallel instructions, including a query instruction, a read registration instruction, a write registration instruction, a read operation instruction, and a write operation instruction; and a memory electrically connected to the processor, the memory being used to respond to a read registration instruction to write target read data into a read buffer, and to respond to a write registration instruction to perform garbage collection on the target write address. During the memory's instruction response process, the processor continuously sends query instructions to the memory to query the memory's instruction status; when a read registration instruction is completed, the processor executes a read operation instruction, and when a write registration instruction is completed, it executes a write operation instruction. This invention can fully utilize the system's multi-task parallel processing capabilities and improve the read and write performance of the storage device.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to an electronic storage device and a data transmission method thereof. Background Art

[0002] The eMMC storage chip is composed of an ARM CPU as a controller and NAND Flash. The ARM CPU runs the controller software, usually called firmware. The main functions of the firmware are to manage bad blocks, GC, early warning, improve performance and life of NAND Flash, and ensure the reliable use of NAND Flash.

[0003] As CPU speed continues to increase, the speed requirements for peripheral storage devices are also getting higher and higher. The CMDQ (Command Queue) function of storage devices, mainly eMMC, has been widely used. However, due to the inappropriate configuration and algorithm of the host CPU processing CMDQ task queue, the CMDQ performance is poor, which limits the data transmission performance of the storage device. Therefore, there is room for improvement. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide an electronic storage device and a data transmission method thereof, so as to solve the problem in the prior art that the command queue task queue configuration and algorithm inappropriately limit the data transmission performance of the storage device.

[0005] To achieve the above objectives and other related objectives, the present invention provides an electronic storage device, comprising:

[0006] A processor, comprising a plurality of processing cores, the processor is used to create a plurality of instructions, which are executed in parallel by different processing cores, the instructions comprising a query instruction, a read register instruction, a write register instruction, a read operation instruction, and a write operation instruction; and

[0007] A memory, for responding to the read register instruction to write the target read data into the read buffer, and responding to the write register instruction to perform garbage collection processing on the target write address;

[0008] Wherein, during the process of the memory responding to the instruction, the processor continuously sends the query instruction to the memory to query the instruction status of the memory;

[0009] The processor executes the read operation instruction when the read register instruction is completed, and executes the write operation instruction when the write register instruction is completed.

[0010] In an embodiment of the present invention, the memory is further configured to simultaneously respond to a plurality of the read operation instructions to simultaneously read a plurality of different target read data from the read buffer.

[0011] In an embodiment of the present invention, the memory is further configured to simultaneously respond to a plurality of the write operation instructions so as to simultaneously write a plurality of different host data into corresponding target write addresses.

[0012] In one embodiment of the present invention, during the process of the memory responding to the read operation instruction and / or the write operation instruction, the processor continues to send the query instruction to the memory to obtain a task identifier of task completion, and the task identifier is used to bind a new instruction.

[0013] In one embodiment of the present invention, the memory includes:

[0014] A command queue unit, for receiving and managing a plurality of instructions sent by the processor, and binding the instructions with task identifiers;

[0015] A read acceleration unit, used for writing target read data into the read buffer;

[0016] The write acceleration unit is used to write target write data from the write buffer into the target write address.

[0017] In one embodiment of the present invention, each of the processing cores is allowed to process multiple threads simultaneously.

[0018] In one embodiment of the present invention, the first processing core of the processor executes the read registration instruction and the write registration instruction respectively through two threads, the second processing core of the processor is used to execute the query instruction, the third processing core of the processor is used to execute the read operation instruction, and the fourth processing core of the processor is used to execute the write operation instruction.

[0019] The present invention also provides a data transmission method for an electronic storage device, comprising:

[0020] Sending a read register instruction and / or a write register instruction to the memory by the processor;

[0021] Responding to the read register instruction through the memory to write the target read data into the read buffer, and responding to the write register instruction to perform garbage collection processing on the target write address;

[0022] In the process that the memory responds to the read registration instruction and the write registration instruction, the processor continuously sends a query instruction to the memory to query the instruction state of the memory;

[0023] The processor executes a read operation instruction when the read register instruction is completed, and executes a write operation instruction when the write register instruction is completed.

[0024] In one embodiment of the present invention, the step of responding to the read register instruction through the memory to write the target read data into the read buffer includes:

[0025] Binding the task identifier to the read registration instruction through a command queue unit;

[0026] The target read data is written into the read buffer through the read acceleration unit.

[0027] In one embodiment of the present invention, the process of executing the step of executing the read operation instruction by the processor when the read registration instruction is completed, and executing the write operation instruction when the write registration instruction is completed, includes:

[0028] The processor continuously sends the query instruction to the memory to obtain a task identifier of a completed task, where the task identifier is used to bind a new instruction.

[0029] As described above, an electronic storage device and a data transmission method thereof of the present invention have the following beneficial effects: the present invention can give full play to the multi-task parallel processing capability of the system and maximize the command queue read and write performance of the storage device.

[0030] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0032] Figure 1 Shown is a structural schematic diagram of an electronic storage device provided by the present invention.

[0033] Figure 2 Shown is a schematic diagram of the structure of a memory in an embodiment of the present invention.

[0034] Figure 3 It is a schematic diagram of the command queue registration strategy in the prior art.

[0035] Figure 4 Shown is a schematic diagram of the command queue registration strategy provided by the present invention.

[0036] Figure 5 Shown is a flow chart of a data transmission method of an electronic storage device provided by the present invention.

[0037] Figure 6 Display as Figure 5 A flowchart of a specific implementation of step S200 is shown in FIG.

[0038] Component number description:

[0039] 100. Processor;

[0040] 200, memory; 210, micro control unit; 220, flash memory unit; 230, command queue unit; 240, write acceleration unit; 250, read acceleration unit; 260, error correction unit 260; 270, storage unit; 280, memory unit; 290, communication unit; 2100, serial port output unit;

[0041] 300 , memory module; 400 , peripheral interface module; 500 , memory card; 600 , power supply; 700 , first interface; 800 , second interface 800 . DETAILED DESCRIPTION

[0042] The following is an explanation of the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the features in the following embodiments and the embodiments can be combined with each other without conflict. It should also be understood that the terms used in the embodiments of the present invention are intended to describe specific embodiments, rather than to limit the scope of protection of the present invention. The test methods for which specific conditions are not specified in the following examples are usually carried out under conventional conditions or according to the conditions recommended by the manufacturers.

[0043] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the limiting conditions for the implementation of the present invention, so they have no substantial technical significance. Any modification of the structure, change in the proportional relationship, or adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the effects and purposes that can be achieved by the present invention. At the same time, the terms such as "upper", "lower", "left", "right", "middle" and "one" quoted in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. The change or adjustment of their relative relationship should also be regarded as the scope of the implementation of the present invention without substantially changing the technical content.

[0044] See also Figures 1 to 6 The present invention provides an electronic storage device and a data transmission method thereof, and proposes a solution to the performance bottleneck of reading and writing data in actual use of the CMDQ (Command Queue) function of storage devices such as eMMC. Based on actual needs, the SOC CPU manufacturer and the underlying hardware design and firmware logic of the storage device are coordinated to solve the bottleneck problem encountered in the data transmission process, and the maximum performance effect can be exerted. The following is a detailed description through specific embodiments.

[0045] See also Figure 1 The present invention provides an electronic storage device, which may include a processor 100 and a memory 200. The processor 100 may be a multi-core processor, and a plurality of independent processing cores may be integrated on the processor chip, and each processing core may have a hyperthreading processing capability, so each processing core allows multiple threads to be processed simultaneously. The memory 200 may be electrically connected to the processor 100. In this embodiment, when data is transmitted, first, the processor 100 may be used to create a plurality of parallel instructions, for example, including query instructions, read register instructions, write register instructions, read operation instructions, and write operation instructions. The memory 200 may be used to respond to the read register instruction to write the target read data into the read buffer, or to respond to the write register instruction to perform garbage collection on the target write address. In the process of the memory 200 responding to the read register instruction and the write register instruction, the processor 100 continuously sends a query instruction to the memory 200 to query whether the read register instruction and the write register instruction are completed, and after the read register instruction or the write register instruction is completed, the processor 100 executes the corresponding read operation instruction or write operation instruction. The memory 100 can be used to respond to multiple read operation instructions at the same time to read multiple different target read data from the read buffer at the same time. The memory 100 can also be used to respond to multiple write operation instructions at the same time to write multiple different host data to the corresponding target write addresses at the same time. It can be seen that the processor 100 can decompose different command queue instructions and tasks to give full play to the multi-task parallel processing capability of the device, thereby maximizing the read and write performance of the storage device.

[0046] See also Figure 1In one embodiment of the present invention, the electronic storage device further includes a memory module 300, a peripheral interface module 400, a memory card 500, a power supply 600, a first interface 700, and a second interface 800. Among them, the SD card 500 is electrically connected to the processor 100 and can be used to store the data transmission management program of the entire electronic storage device. The memory module 300 is electrically connected to the processor 100 and can be used to run the data transmission management program. The peripheral interface module 400 is electrically connected to the processor 100 and can be used for external devices. The power supply 600 can be used to supply power to the processor 100, the memory 200, and the memory module 300. The first interface 700 can be the serial port output of the processor 100. The second interface 800 can be the serial port output of the memory 200.

[0047] See also Figure 2 In one embodiment of the present invention, the memory 200 may include a microcontroller unit 210 and a flash memory unit 220. The microcontroller unit 210 may be an MCU (Memory Controller Unit, microprocessor) based on the RISC-V architecture. RISC-V is an open source instruction set architecture known for its simplicity, modularity and scalability. The microcontroller unit 210 may be used to execute the firmware of the memory 200, manage read and write operations, error handling, and communicate with the processor 100. The flash memory unit 220 is the main storage medium (NAND Flash) in the memory 200. The flash memory unit 220 is divided into different logical blocks and pages, which can be used to store user data and firmware. For example, the flash memory unit 220 can be divided into buffers such as CODE0 / 1, FFU0 / 1, Tablex, and DATAxxx. CODE0 / 1 may be a code buffer, which can be used to store firmware code or control programs. FFU0 / 1 may be a storage area for a firmware functional unit. Tablex may be used to store a mapping table. DATAxxx may be a plurality of buffers or partitions for storing user data. In this embodiment, the flash memory unit 220 is provided with an independent read buffer and write buffer. The read buffer and write buffer are designed to be physically separated and can be executed in parallel, thereby reducing the waiting time between operations and improving the overall data transmission speed and system response efficiency.

[0048] In one embodiment of the present invention, the memory 200 further includes a command queue unit 230, a write acceleration unit 240, a read acceleration unit 250, and an error correction unit 260. The command queue unit 230 is electrically connected to the micro control unit 210. The error correction unit 260 is electrically connected to the flash memory unit 220. The write acceleration unit 240 is electrically connected between the command queue unit 230 and the error correction unit 260. The read acceleration unit 250 is also electrically connected between the command queue unit 230 and the error correction unit 260. In this embodiment, the command queue unit 230 is a CMDQ Engine (Command Queue Engine), which can be used to manage and optimize the command execution process and improve the efficiency and response speed of the storage device. The command queue unit 230 can receive and store multiple commands from the processor 100, such as read, write, erase and other instructions, and organize these commands into queues for management according to certain strategies. The write acceleration unit 240 can be a WDMA Engine (Write Direct Memory Access Engine), which can be used to accelerate the data writing process. When the system needs to write data to the flash memory unit 220, the write acceleration unit 240 can bypass the micro control unit 210 through direct memory access technology and efficiently transfer the data directly from the write buffer to the specified storage address. The read acceleration unit 250 can be an RDMA Engine (Read Direct Memory Access Engine), which can be used to accelerate the data reading process. When the system needs to read data, the read acceleration unit 250 can also bypass the micro control unit 210 through direct memory access technology and directly transfer the data in the storage medium to the read buffer or directly to the system memory. The write acceleration unit 240 and the read acceleration unit 250 can reduce the intervention of the micro control unit 210, reduce the delay of read and write operations, and improve the reading and writing speed.

[0049] In one embodiment of the present invention, the processor 100 sends a read registration instruction to the micro control unit 210. When the Task ID (task identifier) ​​of the CMD44 read task is received and bound by the command queue unit 230, the target read data can be pre-processed by the read acceleration unit 250 and written into the read buffer. Therefore, when the subsequent micro control unit 210 receives the CMD46 read operation instruction, the target read data can be quickly read out. Similarly, the processor 100 sends a write registration instruction to the micro control unit 210. When the Task ID of the CMD44 write task is received by the command queue unit 230, the target write address can be pre-garbage collected (pre-Garbage Collection), and the invalid data on the target write address can be moved away and cleared in advance. Therefore, when the subsequent micro control unit 210 receives the CMD47 write operation instruction, it can be written into the corresponding address through the write acceleration unit 240, which can improve the speed of writing data.

[0050] See also Figure 2 In one embodiment of the present invention, the memory 200 also includes a storage unit 270, a memory unit 280, a communication unit 290 and a serial port output unit 2100. The storage unit 270, the memory unit 280 and the communication unit 290 are electrically connected to the microcontroller unit 210, respectively. The storage unit 270 can be used to store the initial loading program of the firmware. The initial loading program is the code that is first executed when the device is started, which is responsible for initializing the system and loading more complex firmware into the memory unit 280. The storage unit 270 is the memory when the firmware is running, and is used to store dynamic data and program code. The communication unit 290 is a data interface that complies with the JEDEC (Joint Electron Device Engineering Council) protocol. The communication unit 290 can be used to support efficient communication between the processor 100 and the memory 200.

[0051] See also Figure 3 In the prior art, the command queue registration strategy of the memory 200 firmware is serial execution, that is, the command queue registration, query preparation, and execution steps are executed in sequence, and each step needs to wait for the previous step to be completed before the next step can be executed. Therefore, this serial mode limits the parallel potential of the command queue and cannot fully utilize its performance advantages in multi-tasking processing, resulting in limited overall data transmission speed.

[0052] See also Figure 4, the present invention proposes a new command queue registration strategy that can be executed in parallel. In one embodiment of the present invention, the processor 100 is a multi-core hyperthreading processor that can process multiple threads at the same time. For example, a dedicated thread (Thread) continuously queries the command queue through the CMD13 instruction (i.e., the query instruction) whether the Task ID registered by CMD44 / CMD45 is ready at the memory 200 end. This step is performed asynchronously, does not block subsequent operations, and improves the response speed. Another thread quickly registers through the CMD44 / CMD45 instruction, that is, quickly registers the Task ID to the command queue through the read registration instruction / write registration instruction, which is parallel to the query step. The read execution instruction and the write execution instruction can be separated into two independent CPU threads, one responsible for performing the read operation through CMD46, and the other for performing the write operation through CMD47. This parallel processing mechanism greatly improves the execution efficiency of the command queue and allows multiple read and write tasks to be performed simultaneously. After the TaskID of the completed operation can be queried through CMD13, it can be quickly fed back to the processor 100. Then the processor 100 can register a new Task ID again through CMD44 / CMD45, forming an efficient task cycle and continuously promoting data transmission.

[0053] In one embodiment of the present invention, the existing command queue registration strategy is implemented as shown in Table 1. It can be seen that according to the JEDEC protocol, the command queue can register a maximum of 32 task IDs at the same time. Table 1 shows that a single processing core and a single thread are executed, and read commands are not distinguished from write commands. Commands are executed serially. Therefore, only one Task ID in the Ready state can be executed at a time, resulting in a large bottleneck in the overall performance of the storage device.

[0054] Table 1 Existing command queue registration policy execution table

[0055]

[0056] In one embodiment of the present invention, the new command queue registration strategy provided by the present invention is executed as shown in Table 2. Table 2 shows multi-CPU core, hyperthread Thread execution. The registration strategy shown in Table 2 is also that a maximum of 32 tasks TaskID can be registered, multiple Task IDs can be registered at the same time, and read commands and write commands can be executed separately using different threads. Then, a CMD13 query instruction is continuously executed through an independent thread to confirm the status of each task Task ID, so as to promptly notify the execution of the memory 200 and the Task ID registration of the processor 100. In this embodiment, the first processing core of the processor 100 executes the read registration instruction and the write registration instruction respectively through two threads (CPU1 Thread1 and CPU1 Thread2), the second processing core (CPU2 Thread1) is used to execute the query instruction, the third processing core (CPU3 Thread1) is used to execute the read operation instruction, and the fourth processing core (CPU4 Thread1) is used to execute the write operation instruction.

[0057] Table 2 New command queue registration strategy execution table of the present invention

[0058]

[0059] Further, according to Table 2, the memory 100 is used to respond to multiple read operation instructions at the same time to read multiple different target read data from the read buffer at the same time. The memory 100 is also used to respond to multiple write operation instructions at the same time to write multiple different host data to the corresponding target write addresses at the same time.

[0060] See also Figure 5 The present invention also provides a data transmission method for an electronic storage device, which can be applied to the above-mentioned electronic storage device and may include the following steps:

[0061] Step S100, sending a read registration instruction and / or a write registration instruction to the memory through the processor;

[0062] Step S200, responding to the read register instruction through the memory to write the target read data into the read buffer, and responding to the write register instruction to perform garbage collection processing on the target write address;

[0063] Step S300: In the process of the memory responding to the read registration instruction and the write registration instruction, the processor continuously sends a query instruction to the memory to query the instruction state of the memory;

[0064] Step S400: When the read registration instruction is completed, the processor executes the read operation instruction, and when the write registration instruction is completed, the processor executes the write operation instruction.

[0065] In one embodiment of the present invention, when step S100 is executed, a read register instruction and / or a write register instruction is sent to the memory 200 by the processor 100. Specifically, the processor 100 is a multi-core hyperthreading processor that can process multiple threads simultaneously. The read register instruction can represent a CMD44 / CMD45 read operation and a corresponding target read address parameter. The write register instruction can represent a CMD44 / CMD45 write operation and a corresponding target write address parameter. A thread of the processor 100 simultaneously creates multiple CMD44 / CMD45 read operations and / or simultaneously creates multiple CMD44 / CMD45 write operations.

[0066] In one embodiment of the present invention, when step S200 is executed, the memory 200 responds to the read register instruction to write the target read data into the read buffer, and responds to the write register instruction to perform garbage collection on the target write address. Specifically, the memory 200 may include a micro control unit 210, a flash memory unit 220, a command queue unit 230, a write acceleration unit 240, and a read acceleration unit 250. Among them, the flash memory unit 220 is provided with an independent read buffer and a write buffer, and the read buffer and the write buffer are physically separated and can be executed in parallel.

[0067] See also Figure 6 In one embodiment of the present invention, when executing step S200, the following steps may be included:

[0068] Step S210, binding the task identifier with the read registration instruction through the command queue unit;

[0069] Step S220: Write the target read data into the read buffer through the read acceleration unit.

[0070] In one embodiment of the present invention, when executing step S210-step S220, specifically, when the micro control unit 210 receives the read registration instruction, a unique task identifier can be quickly registered in the command queue (Command Queue, CMDQ) through the command queue unit 230 to bind the task identifier to the read registration command. Then, the target read data is written into the read buffer according to the target read address parameter through the read acceleration unit 250.

[0071] Furthermore, when the microcontroller unit 210 receives a write register instruction, a unique task identifier can be quickly registered in the command queue (CMDQ) through the command queue unit 230 to bind another task identifier to the write register command. Then, garbage collection is performed on the target write address to remove and clear invalid data on the target write address.

[0072] In one embodiment of the present invention, when step S300 is executed, that is, in the process of the memory responding to the read register instruction and the write register instruction, the processor continuously sends a query instruction to the memory to query the instruction status of the memory. Specifically, before the read and write operations are formally executed, a query instruction (such as CMD13) is continuously sent to the memory 200 through an independent thread of the processor 100 to monitor the execution status of the read and write register instructions in real time. Thereby, the processor 100 dynamically adjusts subsequent operations according to the real-time feedback of the memory 200, thereby improving the flexibility and efficiency of task scheduling.

[0073] In one embodiment of the present invention, when step S400 is executed, the processor executes the read operation instruction when the read register instruction is completed, and executes the write operation instruction when the write register instruction is completed. When the query result shows that the read and write register instructions are ready, the processor 100 immediately executes the actual read operation instruction (CMD46) to obtain data from the read buffer, or executes the write operation instruction (CMD47) to write data from the write buffer to the target write address.

[0074] In one embodiment of the present invention, during the execution of step S400, the processor 100 is further included in continuously sending query instructions to the memory 200 to obtain the task identifier of the completed task. Specifically, the Task ID of the completed operation can be queried through CMD13 and can be quickly fed back to the processor 100. Then the processor 100 can register a new Task ID again through CMD44 / CMD45 and bind a new command, thereby forming an efficient task cycle and continuously promoting data transmission.

[0075] In particular, according to an embodiment of the present invention, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present invention includes a computer program product, which includes a computer program carried on a computer readable medium, and the computer program includes a computer program for executing the method shown in the flowchart.

[0076] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architecture, functions and operations of the systems, methods and application structures according to various embodiments of the present invention. Among them, each box in the flowchart or block diagram can represent a module, a program segment, or a part of a code, and the above-mentioned module, program segment, or a part of the code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of boxes in the block diagram or flowchart, can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0077] The modules involved in the embodiments of the present invention may be implemented by software or hardware, and the modules described may also be arranged in a processor. The names of these modules do not, in some cases, limit the modules themselves.

[0078] The present invention also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor of a computer, the computer executes the above-mentioned method for analyzing the state data of a storage chip. The computer-readable storage medium may be included in the electronic storage device described in the above embodiment, or may exist independently without being assembled into the electronic storage device.

[0079] The present invention also provides a computer program product or a computer program, which includes a computer instruction stored in a computer-readable storage medium. A processor of a computer device reads the computer instruction from the computer-readable storage medium, and the processor executes the computer instruction, so that the computer device executes the analysis method of the storage chip status data provided in each of the above embodiments.

[0080] In summary, the present invention provides an electronic storage device and a data transmission method thereof, which can give full play to the multi-task parallel processing capability of the device, thereby maximizing the read and write performance of the storage device. The present invention solves the problem that the CMDQ performance of the storage device is limited due to the limitation of the host CPUOS end and the serial execution waiting of the registered Task Ready time. At the same time, the present invention also optimizes the CMDQ hardware design of the eMMC master control end, and realizes that the firmware's processing mechanism for CMDQ can quickly respond to CMDQ read and write data requests and parallelly process multiple task sites.

[0081] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. An electronic storage device, characterized in that: include: A processor, comprising a plurality of processing cores, each of the processing cores allowing for simultaneous processing of a plurality of threads, the processor being configured to create a plurality of instructions which are executed in parallel by different processing cores, the instructions comprising a query instruction, a read register instruction, a write register instruction, a read operation instruction, and a write operation instruction; as well as A memory, for responding to the read register instruction to write the target read data into the read buffer, and responding to the write register instruction to perform garbage collection processing on the target write address; Wherein, during the process of the memory responding to the instruction, the processor continuously sends the query instruction to the memory to query the instruction status of the memory; The processor executes the read operation instruction when the read registration instruction is completed, and executes the write operation instruction when the write registration instruction is completed; The memory is also used to respond to a plurality of the read operation instructions at the same time, so as to read a plurality of different target read data from the read buffer at the same time; The memory is also used to respond to a plurality of the write operation instructions simultaneously to simultaneously write a plurality of different host data into corresponding target write addresses; The first processing core of the processor executes the read registration instruction and the write registration instruction respectively through two threads, the second processing core of the processor is used to execute the query instruction, the third processing core of the processor is used to execute the read operation instruction, and the fourth processing core of the processor is used to execute the write operation instruction.

2. The electronic storage device according to claim 1, characterized in that During the process that the memory responds to the read operation instruction and / or the write operation instruction, the processor continues to send the query instruction to the memory to obtain a task identifier of a completed task, and the task identifier is used to bind a new instruction.

3. The electronic storage device according to claim 1, characterized in that The memory comprises: A command queue unit, for receiving and managing a plurality of instructions sent by the processor, and binding the instructions with task identifiers; A read acceleration unit, used for writing target read data into the read buffer; The write acceleration unit is used to write target write data from the write buffer into the target write address.

4. A data transmission method for an electronic storage device, characterized in that: include: Sending a read register instruction and / or a write register instruction to a memory through a processor, wherein a first processing core of the processor executes the read register instruction and the write register instruction respectively through two threads; Responding to the read register instruction through the memory to write the target read data into the read buffer, and responding to the write register instruction to perform garbage collection processing on the target write address; In the process that the memory responds to the read register instruction and the write register instruction, the processor continuously sends a query instruction to the memory to query the instruction state of the memory, wherein the second processing core of the processor is used to execute the query instruction; When multiple read registration instructions are completed, the processor simultaneously responds to multiple read operation instructions to simultaneously read multiple different target read data from the read buffer, and when multiple write registration instructions are completed, the processor simultaneously responds to multiple write operation instructions to simultaneously write multiple different host data to corresponding target write addresses, wherein the third processing core of the processor is used to execute the read operation instructions, and the fourth processing core of the processor is used to execute the write operation instructions.

5. The data transmission method of the electronic storage device according to claim 4, characterized in that: The step of responding to the read register instruction through the memory to write the target read data into the read buffer comprises: Binding the task identifier to the read registration instruction through a command queue unit; The target read data is written into the read buffer through the read acceleration unit.

6. The data transmission method of the electronic storage device according to claim 4, characterized in that: The process of executing the step of executing the read operation instruction by the processor when the read registration instruction is completed, and executing the write operation instruction when the write registration instruction is completed, includes: The processor continuously sends the query instruction to the memory to obtain a task identifier of a completed task, where the task identifier is used to bind a new instruction.

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