Address updating device and method, processor and chip

Abstract

The present disclosure relates to an address update device and method, a processor, and a chip. The address update device includes: an address update unit, a page table update source, a memory address management unit, and a memory. The address update unit receives an update request from the page table update source. The update request includes a virtual address and a first physical address corresponding to the virtual address. The address update unit updates the page table information corresponding to the memory and the memory address management unit respectively, which is used to describe the mapping relationship between the virtual address and the first physical address, according to the obtained update request. In the embodiments of the present disclosure, by introducing the address update unit, the page table information in the memory and the page table information of the memory address management unit are directly updated by the address update unit as hardware, reducing the software-hardware interaction during system operation, simplifying the page table update process, and improving the system operation efficiency.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technologies, and in particular, to an address update device and method, a processor, and a chip. Background Art

[0002] In compiled executable code, if it involves a processor accessing an instruction or data, a virtual address will be provided for the accessed instruction or data, and a page table that records the mapping relationship between the virtual address and the physical address in the memory address management unit will be queried, so as to convert the virtual address into a physical address and access the instruction or data from the memory.

[0003] The page table update of the memory address management unit is completed by software (such as a driver). The software will write the updated page table into the memory, and then initiate an invalidation operation to the memory address management unit to notify the memory address management unit that the page table is outdated. In this way, after receiving a new request, the memory address management unit will re-fetch the page table from the memory and finally cache it in the on-chip cache of the memory address management unit.

[0004] However, when the hardware needs to update the page table, it will first notify the software how to allocate the page table through the software-hardware interface, then the software writes it into the memory, and then notifies the memory address management unit to re-fetch the page table from the memory. For a high-performance processor, this process consumes a relatively long time and will affect the overall performance of the processor. Summary of the Invention

[0005] The present disclosure proposes an address update technical solution.

[0006] According to one aspect of the present disclosure, there is provided an address update device, where the address update device includes: an address update unit, a page table update source, a memory address management unit, and a memory; the address update unit receives an update request from the page table update source, and the update request includes a virtual address and a first physical address corresponding to the virtual address; the address update unit updates the page table information corresponding to the memory and the memory address management unit respectively according to the obtained update request, and the page table information is used to describe the mapping relationship between the virtual address and the first physical address.

[0007] In a possible implementation, the address update unit updates the page table information corresponding to the memory and the memory address management unit respectively according to the obtained update request, including: the address update unit sends a first virtual address request carrying the virtual address to the memory address management unit according to the virtual address carried in the update request; the memory address management unit generates a read request for accessing the memory according to the first virtual address request; the address update unit intercepts the read request and sends the first physical address to the memory address management unit; the address update unit obtains a second physical address from the page table update source, and writes the page table information for describing the mapping relationship between the virtual address and the first physical address into the storage location indicated by the second physical address in the memory.

[0008] In a possible implementation, the address update unit updates the page table information corresponding to the memory and the memory address management unit respectively according to the obtained update request, including: the address update unit waits for the page table update source to send an update request, and generates the page table information to be updated according to the unprocessed update request obtained earlier; the address update unit intercepts the read request from the memory address management unit, and the read request is used to access the memory; the address update unit compares the read request with the page table information to be updated to obtain a comparison result; the address update unit updates the page table information to be updated and the page table information corresponding to the memory and the memory address management unit respectively in response to the comparison result indicating that there is the same virtual address in the read request and the page table information to be updated.

[0009] In a possible implementation, the address update unit is further configured to feedback an update result to the page table update source, and the update result is used to indicate that the address update unit has completed the update of the memory and the memory address management unit.

[0010] In a possible implementation, the address update unit sends a first virtual address request carrying the virtual address to the memory address management unit according to the virtual address carried in the update request, including: the address update unit sends a first virtual address request carrying a first identifier and the virtual address to the memory address management unit; the read request includes the virtual address and the first identifier, and the first identifier is used to indicate that the source category of the virtual address is the update request; the address update unit intercepts the read request, including: the address update unit intercepts the read request in response to the read request including the first identifier.

[0011] In a possible implementation, when the page table information includes a multi-level page table, the address update unit obtains a second physical address from the page table update source, and writes the page table information used to describe the mapping relationship between the virtual address and the first physical address into the storage location indicated by the second physical address in the memory, including: the address update unit sends a physical address request to the page table update source, and the physical address request includes a third identifier for indicating the page table level; the address update unit receives the second physical address fed back by the page table update source, and the second physical address corresponds to the third identifier; the address update unit writes the page table information of the level indicated by the third identifier into the storage location indicated by the second physical address in the memory according to the second physical address corresponding to each third identifier.

[0012] In a possible implementation, the memory address management unit receives a second virtual address request from the page table update source, and the second virtual address request carries a virtual address and a second identifier; in response to the memory address management unit identifying that the source category of the virtual address is other category requests other than the update request according to the second identifier, the memory address management unit returns the first physical address corresponding to the virtual address to the page table update source.

[0013] In a possible implementation, in response to the read request sent by the memory address management unit including a second identifier, the address update unit transparently forwards the read request from the memory address management unit to the memory; the address update unit transparently forwards the return result of the memory in response to the read request to the memory address management unit, and the second identifier is used to indicate that the source category of the virtual address of the read request is other category requests other than the update request.

[0014] In a possible implementation, when the memory address management unit receives the first virtual address request, it queries the virtual address carried in the first virtual address request in the cache of the memory address management unit; if the virtual address is not queried in the cache of the memory address management unit, it allocates space for storing page table information for the first virtual address request in the cache; or, if the virtual address is queried in the cache of the memory address management unit, it clears the associated space of the virtual address in the cache and allocates space for storing page table information for the first virtual address request in the cache.

[0015] According to one aspect of the present disclosure, an address update method is provided. The method is applied to the address update device, and the address update device includes: an address update unit, a page table update source, a memory address management unit, and a memory. The method includes: the address update unit receives an update request from the page table update source, and the update request includes a virtual address and a first physical address corresponding to the virtual address; the address update unit updates the page table information corresponding to the memory and the memory address management unit respectively according to the obtained update request, and the page table information is used to describe the mapping relationship between the virtual address and the first physical address.

[0016] In a possible implementation manner, the address update unit updates the page table information corresponding to the memory and the memory address management unit respectively according to the obtained update request, including: the address update unit sends a first virtual address request carrying the virtual address to the memory address management unit according to the virtual address carried in the update request; the memory address management unit generates a read request for accessing the memory according to the first virtual address request; the address update unit intercepts the read request and sends the first physical address to the memory address management unit; the address update unit obtains a second physical address from the page table update source, and writes the page table information for describing the mapping relationship between the virtual address and the first physical address into the storage location indicated by the second physical address in the memory.

[0017] In a possible implementation manner, the address update unit updates the page table information corresponding to the memory and the memory address management unit respectively according to the obtained update request, including: the address update unit waits for the page table update source to send an update request, and generates page table information to be updated according to the unprocessed update request obtained previously; the address update unit intercepts a read request from the memory address management unit, and the read request is used to access the memory; the address update unit compares the read request with the page table information to be updated to obtain a comparison result; the address update unit updates the page table information to be updated and the page table information corresponding to the memory and the memory address management unit respectively in response to the comparison result indicating that there is the same virtual address in the read request and the page table information to be updated.

[0018] In a possible implementation manner, the method further includes: the address update unit feeds back an update result to the page table update source, and the update result is used to represent that the address update unit has completed the update of the memory and the memory address management unit.

[0019] In a possible implementation, the address update unit sends a first virtual address request carrying the virtual address to the memory address management unit according to the virtual address carried in the update request, including: the address update unit sends a first virtual address request carrying a first identifier and the virtual address to the memory address management unit; the read request includes the virtual address and the first identifier, and the first identifier is used to indicate that the source category of the virtual address is the update request; the address update unit intercepts the read request, including: the address update unit intercepts the read request in response to the read request including the first identifier.

[0020] In a possible implementation, when the page table information includes multi-level page tables, the address update unit obtains a second physical address from the page table update source, and writes the page table information for describing the mapping relationship between the virtual address and the first physical address into the storage location indicated by the second physical address in the memory, including: the address update unit sends a physical address request to the page table update source, and the physical address request includes a third identifier for indicating the page table level; the address update unit receives the second physical address fed back by the page table update source, and the second physical address corresponds to the third identifier; the address update unit writes the page table information of the level indicated by the third identifier into the storage location indicated by the second physical address in the memory according to the second physical address corresponding to each third identifier.

[0021] In a possible implementation, the method further includes: the memory address management unit receives a second virtual address request from the page table update source, and the second virtual address request carries a virtual address and a second identifier; in response to the memory address management unit identifying that the source category of the virtual address is other category requests other than the update request according to the second identifier, the memory address management unit returns the first physical address corresponding to the virtual address to the page table update source.

[0022] In a possible implementation, the method further includes: the address update unit transparently forwards the read request from the memory address management unit to the memory in response to the read request sent by the memory address management unit including the second identifier; the address update unit transparently forwards the return result of the memory in response to the read request to the memory address management unit, and the second identifier is used to indicate that the source category of the virtual address of the read request is other category requests other than the update request.

[0023] In a possible implementation, the method further includes: when the memory address management unit receives the first virtual address request, query the virtual address carried in the first virtual address request in the cache of the memory address management unit; in the case where the virtual address is not found in the cache of the memory address management unit, allocate space for storing page table information for the first virtual address request in the cache; or, in the case where the virtual address is found in the cache of the memory address management unit, clear the associated space of the virtual address in the cache, and allocate space for storing page table information for the first virtual address request in the cache.

[0024] According to one aspect of the present disclosure, there is provided a processor, which includes the address update device as described above.

[0025] According to one aspect of the present disclosure, there is provided a chip, which includes the processor as described above.

[0026] According to one aspect of the present disclosure, there is provided a computer-readable storage medium, on which computer program instructions are stored, and when the computer program instructions are executed by a processor, the above method is implemented.

[0027] In the embodiments of the present disclosure, the address update device includes: an address update unit, a page table update source, a memory address management unit, and a memory; the address update unit receives an update request from the page table update source, and the update request includes a virtual address and a first physical address corresponding to the virtual address; the address update unit updates the page table information corresponding to the memory and the memory address management unit respectively according to the obtained update request, and the page table information is used to describe the mapping relationship between the virtual address and the first physical address. In this way, by introducing the address update unit, the page table information in the memory and the page table information of the memory address management unit are directly updated by the address update unit as hardware, reducing the software-hardware interaction during system operation, simplifying the page table update process, and improving the system operation efficiency.

[0028] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and do not limit the present disclosure. Other features and aspects of the present disclosure will become clear according to the following detailed description of exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification. These drawings show embodiments consistent with the present disclosure and are used together with the specification to explain the technical solutions of the present disclosure.

[0030] Figure 1 A block diagram showing an address update device according to an embodiment of the present disclosure.

[0031] Figure 2 A schematic diagram showing an address update device according to an embodiment of the present disclosure.

[0032] Figure 3 A schematic diagram showing an address update method according to an embodiment of the present disclosure.

[0033] Figure 4 A block diagram showing an electronic device according to an embodiment of the present disclosure. Detailed implementation manners

[0034] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the drawings denote elements having the same or similar functions. Although various aspects of the embodiments are shown in the drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0035] The special term "exemplary" herein means "serving as an example, embodiment or illustration". Any embodiment described as "exemplary" herein need not be construed as superior to or better than other embodiments.

[0036] The term "and / or" herein merely describes an association relationship of associated objects and means that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the term "at least one" herein means any one of a plurality or any combination of at least two of a plurality. For example, including at least one of A, B, and C may represent any one or more elements selected from the set composed of A, B, and C.

[0037] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following detailed implementation manners. Those skilled in the art should understand that the present disclosure can also be implemented without some specific details. In some instances, methods, means, elements and circuits well known to those skilled in the art are not described in detail so as to highlight the gist of the present disclosure.

[0038] Figure 1 A block diagram showing an address update device according to an embodiment of the present disclosure, as Figure 1As shown in the figure, the address update device includes: an address update unit 1, a page table update source 2, a memory address management unit 3, and a memory 4; the address update unit 1 is connected to the page table update source 2, and the address update unit 1 receives an update request from the page table update source 2, and the update request includes a virtual address and a first physical address corresponding to the virtual address; the address update unit 1 is connected between the memory address management unit 3 and the memory 4, and the address update unit 1 updates the page table information corresponding to the memory 4 and the memory address management unit 3 respectively according to the obtained update request, and the page table information is used to describe the mapping relationship between the virtual address and the first physical address.

[0039] In a possible implementation manner, the address update unit 1, the page table update source 2, and the memory address management unit 3 can be implemented by a circuit board card or an integrated circuit composed of general analog components, digital circuit components, etc. The present disclosure does not limit the specific implementation manners of the address update unit 1, the page table update source 2, and the memory address management unit 3.

[0040] In a possible implementation manner, the memory 4 can be composed of semiconductor storage units, such as including random access memory (RAM), read only memory (ROM), erasable programmable read only memory (EPROM), static random access memory (SRAM), dynamic random access memory (DRAM), flash memory, etc. The embodiments of the present disclosure do not limit the specific form of the memory 4.

[0041] In a possible implementation manner, the page table update source 2 is used to generate an update request, and the update request is used to change the page table information in the memory address management unit 3 and the memory 4, and the page table information can be used to describe the mapping relationship between the virtual address and the first physical address. Optionally, the page table information may include N (N≥1) virtual addresses and a first physical address corresponding to each virtual address. For example, the virtual address VA1 corresponds to the first physical address PA1, the virtual address VA2 corresponds to the first physical address PA2, and so on, and the virtual address VAN corresponds to the first physical address PAN. Among them, the virtual address is the logical address used by the program code during operation, and the program code can access the memory 4 through the virtual address instead of directly accessing the first physical address of the memory 4.

[0042] Optionally, the page table update source 2 may respond to the page table update requirements of the upstream software and generate an update request for changing the page table information in the memory address management unit 3 and the memory 4. For example, assume that a certain thread requests more memory space. The thread may instruct the page table update source 2 to generate a page table update request to change the page table information in the memory address management unit 3 and the memory 4, and allocate the first physical address occupied by other threads (such as invalid historical threads) to the virtual address of this thread.

[0043] Optionally, the page table update source 2 may also respond to the page table update requirements of the upstream hardware and generate an update request for changing the page table information in the memory address management unit 3 and the memory 4. For example, assume that a device driver changes the value of a certain hardware register. Since this change will affect the physical address associated with the register, it is necessary to update the page table information in the memory address management unit 3 and the memory 4 to reflect this change. The hardware may send a timing signal to the page table update source 2 to instruct the page table update source 2 to generate a page table update request to change the page table information in the memory address management unit 3 and the memory 4, and update the corresponding first physical address for the virtual address of this hardware register.

[0044] It should be understood that the page table update source 2 may respond to the page table update requirements of the upstream software (or hardware) and generate an update request for changing the page table information in the memory address management unit 3 and the memory 4, and the embodiments of the present disclosure do not limit this.

[0045] In a possible implementation manner, the memory address management unit 3 may store the currently latest page table information for describing the mapping relationship between the virtual address and the first physical address, be responsible for mapping the virtual address to the first physical address, and provide a hardware mechanism for memory access permission check (for example, it can query in the page table information whether there is a corresponding first physical address for the access request carrying a certain virtual address to determine whether the access request has memory access permission), so as to improve the memory usage efficiency and the security of the system. The memory address management unit 3 may also provide operation interfaces such as application and release of the memory 4 for user programs.

[0046] Optionally, the memory address management unit 3 may include a cache, and the cache is a high-speed memory with a faster data access speed than the memory 4, such as including a cache (Cache). In the cache of the memory address management unit 3, the page table information for describing the mapping relationship between the virtual address and the first physical address may be stored. Among them, the page table information cached by the memory address management unit 3 may be partial page table information of the page table information stored in the memory 4 (such as the latest page table information expected to be used recently), or may be all the page table information stored in the memory 4, and the present disclosure does not limit this.

[0047] In the example, the virtual address can be queried according to the page table information cached in the memory address management unit 3. If the first physical address required by the virtual address is in the cache, the first physical address can be directly returned; if the first physical address required by the virtual address is not in the cache, an access to the memory 4 can be initiated.

[0048] In a possible implementation, the address update unit 1 can be respectively connected to the page table update source 2, the memory address management unit 3, and the memory 4, and is configured to receive an update request carrying the virtual address and the first physical address corresponding to the virtual address from the page table update source 2, and update the page table information of the memory 4 and the memory address management unit 3 according to the received update request, so that the page table information has the mapping relationship between the virtual address and the first physical address indicated by the update request.

[0049] In this way, when the page table update source 2 has page table mappings that need to be updated to the memory address management unit 3 and the memory 4, the new page table information can be first updated to the address update unit 1, and then the address update unit 1 updates the new page table information to the memory 4 and the memory address management unit 3.

[0050] For the scenario where the hardware needs to update the page table, in the related art, the software is first notified through the software-hardware interface on how to allocate the page table, and then the software writes the page table information into the memory 4, and then the memory address management unit 3 is notified to re-obtain the page table information. This process in the related art consumes too much time due to the synchronization between software and hardware and the access to the memory, which will affect the performance of the processor. However, in the address update device of the present disclosure embodiment, by introducing the address update unit 1, the page table information in the memory 4 and the page table information of the memory address management unit 3 are directly updated by the address update unit 1 as hardware, reducing the software-hardware interaction during system operation (the address update unit 1 obtains the update request on how to allocate the page table initiated by the hardware via the page table update source 2), simplifying the page table update process, and improving the system operation efficiency.

[0051] Figure 2 The schematic diagram showing the address update device according to the embodiment of the present disclosure is as Figure 2As described above, during the process of the memory address management unit 3 accessing the memory 4, it will pass through the address update unit 1. For regular memory accesses (e.g., access requests unrelated to address updates), the address update unit 1 will transparently pass them to the memory 4, and the results returned by the memory 4 will also be transparently passed back to the memory address management unit 3. For address update requests initiated by the page table update source 2, the address update unit 1 will intercept them and return the page table information updated by the previous page table update source 2. In this way, the memory address management unit 3 will obtain the updated page table information. At the same time, the address update unit 1 will write the new page table information into the memory 4, so that there is also a copy of the new page table information in the memory 4 for subsequent use by software or other memory address management units 3.

[0052] The following takes Figure 2 as an example to exemplarily illustrate the update process of the address update device according to the embodiments of the present disclosure.

[0053] In a possible implementation manner, the address update unit 1 updates the page table information corresponding to the memory 4 and the memory address management unit 3 respectively according to the obtained update request, including: the address update unit 1 sends a first virtual address request carrying the virtual address to the memory address management unit 3 according to the virtual address carried in the update request; the memory address management unit 3 generates a read request for accessing the memory 4 according to the first virtual address request; the address update unit 1 intercepts the read request and sends the first physical address to the memory address management unit 3 to implement the update of the memory address management unit 3; the address update unit 1 obtains a second physical address from the page table update source 2, and writes the page table information describing the mapping relationship between the virtual address and the first physical address into the storage location indicated by the second physical address in the memory 4 to implement the update of the memory 4; the address update unit 1 feeds back an update result to the page table update source 2, and the update result is used to indicate that the address update unit 1 has completed the update of the memory 4 and the memory address management unit 3.

[0054] By introducing the address update unit 1 in the address update device according to the embodiments of the present disclosure, the page table information in the memory 4 and the page table information of the memory address management unit 3 are directly updated by the address update unit 1 as hardware, which simplifies the page table information update process. For update requirements from various hardware modules obtained via the page table update source 2, there is no longer a need for synchronization between software and hardware (e.g., it does not involve processes such as notifying software through a software-hardware interface how to allocate page tables, writing by software into the memory 4, and then notifying the memory address management unit 3 to re-obtain the page tables), reducing the software-hardware interaction during system operation and improving the address update efficiency.

[0055] Exemplarily, such as Figure 2As shown in S1, the page table update source 2 can send an update request to the address update unit 1. The update request may include a virtual address and its corresponding first physical address. Among them, the update request may be a table creation request indicating to establish a mapping relationship between a new virtual address and the first physical address in the memory address management unit 3 and the memory 4, or a request to change the mapping relationship between the virtual address and the first physical address in the memory address management unit 3 and the memory 4. The present disclosure does not limit this.

[0056] For example, assume that the update request sent by the page table update source 2 carries the virtual address VA and the first physical address PA. If the virtual address VA is not recorded in the memory address management unit 3 and the memory 4, the update request is a table creation request, requesting to establish a mapping relationship between the virtual address VA and the physical address PA; if the virtual address VA has been recorded in the memory address management unit 3 and the memory 4, but the first physical address corresponding to the virtual address VA is not the first physical address PA, the update request is a change request, requesting to change the mapping relationship between the virtual address VA and other physical addresses to the mapping relationship between the virtual address VA and the first physical address PA.

[0057] The address update unit 1 can receive the update request from the page table update source 2. The update request carries the virtual address and the first physical address corresponding to the virtual address. The address update unit 1 can retain the first physical address and, as Figure 2 shown in S2, generate a first virtual address request according to the received virtual address, and send the first virtual address request carrying the virtual address to the memory address management unit 3.

[0058] In a possible implementation manner, the address update unit 1 sends a first virtual address request carrying the virtual address to the memory address management unit 3 according to the virtual address carried in the update request, including: the address update unit 1 generates a first identifier according to the virtual address carried in the update request; the address update unit 1 sends a first virtual address request carrying the first identifier and the virtual address to the memory address management unit 3; by setting the first identifier, it is convenient for the memory address management unit 3 to quickly identify that the received first virtual address request is a request related to address update.

[0059] Exemplarily, since the first virtual address request is generated based on the update request from the page table update source 2, in order to indicate that the source of the virtual address carried in the first virtual address request is the virtual address in the update request, the address update unit 1 can generate a first identifier for the virtual address, used to mark that the source category of the virtual address is an update request for updating the page table information in the memory address management unit 3 and the memory 4. Then, in Figure 2In S2, the address update unit 1 may send a first virtual address request carrying a first identifier and a virtual address to the memory address management unit 3.

[0060] In this way, when the page table update source 2 initiates an update request to the cache of the memory address management unit 3, it will first notify the address update unit 1. The address update unit 1 will send a first virtual address request to the memory address management unit 3. Such a first virtual address request needs to have a first identifier to distinguish that this first virtual address request is not an ordinary virtual address request, but a first virtual address request related to page table update.

[0061] Among them, various virtual address requests received by the memory address management unit 3 may have an identification information to distinguish different types of virtual address requests. For example, a first virtual address request carrying a first identifier (for example, the first identifier is 1) is used to represent a request related to address update; a second virtual address request carrying a second identifier (for example, the second identifier is 0) is used to represent other types of requests unrelated to address update. Among them, the first identifier and the second identifier may be a combination of at least one or more of numbers, letters, and symbols. The present disclosure does not limit this.

[0062] In a possible implementation manner, when the memory address management unit 3 receives the first virtual address request, it queries the virtual address carried in the first virtual address request in the cache of the memory address management unit 3; in the case where the virtual address is not found in the cache of the memory address management unit 3, it allocates space for storing page table information for the first virtual address request in the cache; or, in the case where the virtual address is found in the cache of the memory address management unit 3, it clears the associated space of the virtual address in the cache and allocates space for storing page table information for the first virtual address request in the cache.

[0063] Among them, when the memory address management unit 3 allocates space for storing page table information in the cache, it can mark this cache space for storing page table update information, which is convenient for subsequent page table updates and reduces the probability of other data occupying this space.

[0064] In this way, the memory address management unit 3 can not only create page table information representing the mapping relationship between the virtual address and the first physical address, but also change the mapping relationship between the existing virtual address and the first physical address in the cache, and can be applied to more scenarios.

[0065] Such as Figure 2As shown in S3, the memory address management unit 3 may generate a read request for accessing the memory 4 according to the first virtual address request. For example, when the memory address management unit 3 receives the first virtual address request, it may query and judge in the on-chip cache. Since this virtual address is a newly created virtual address and the on-chip cache of the memory address management unit 3 cannot find the corresponding first physical address for this virtual address, according to the process in the related art, the memory address management unit 3 will send a read request to the memory 4 to read the page table information in the memory 4 to obtain its corresponding first physical address.

[0066] In the embodiment of the present disclosure, the read request generated by the memory address management unit 3 according to the first virtual address request includes the virtual address and the first identifier, and the first identifier is used to indicate that the source category of the virtual address is the update request, so that the subsequent address update unit 1 can intercept the read request according to the first identifier.

[0067] It should be understood that although the read request is for sending to the memory 4, the actual transmission path allows the address update unit 1 to intercept. Whether the address update unit 1 actually intercepts the read request can be determined according to the actual application scenario, and the embodiment of the present disclosure does not limit this.

[0068] In a possible implementation manner, as Figure 2 shown in S4, the address update unit 1 intercepts the read request in response to the read request including the first identifier, and sends the first physical address to the memory address management unit 3 to implement the update of the memory address management unit 3.

[0069] For example, after the address update unit 1 receives the read request from the memory address management unit 3, it will judge according to the first identifier carried in the read request that the read request is a request related to address update. For such a read request related to address update, the address update unit 1 will intercept its access to the memory 4, and at the same time will return the first physical address to the memory address management unit 3, that is, the first physical address carried in the request information in S1 as Figure 2 shown, to implement the update of the memory address management unit 3. In this way, when the subsequent memory address management unit 3 receives the second virtual address request carrying the second identifier and the virtual address, it can query the first physical address corresponding to the virtual address.

[0070] As Figure 2 shown in S5, the address update unit 1 will send a physical address request to the page table update source 2. This physical address request requires the address update unit 1 to feedback a second physical address, and the purpose of this second physical address is to tell the address update unit 1 the position in the memory 4 where the mapping relationship information between the virtual address and the physical address established by the previous page table update source 2 needs to be stored. AsFigure 2 As shown in S6, after obtaining the second physical address, the address update unit 1 initiates a write operation to the memory 4, and writes the mapping relationship between the virtual address and the physical address established by the page table update source 2 to the position indicated by the second physical address in the memory 4.

[0071] After the writing is completed, as Figure 2 shown in S7, the address update unit 1 has updated the new page table mapping relationship to the memory address unit 3 and the memory 4, and can feedback the update result indicating that the page table update has been completed to the page table update source 2.

[0072] In an embodiment of the present disclosure, the address update unit 1 may update the page table information of the memory 4 and the memory address management unit 3 in an actively triggered manner according to the obtained update request; or, the address update unit 1 may also passively wait for the page table update source 2 to send an update request. The address update unit 1 may store the unupdated page table information. Each time the address update unit 1 receives a read request from the memory address management unit 3, it may compare the read request with the stored unupdated page table information, and when the virtual address carried in the read request meets the requirements in the unupdated page table information, update the page table information of the memory 4 and the memory address management unit 3, and delete the content related to the virtual address from the unupdated page table information.

[0073] Exemplarily, the address update unit 1 updates the page table information corresponding to the memory 4 and the memory address management unit 3 according to the obtained update request, including: the address update unit 1 waits for the page table update source 2 to send an update request, and generates the page table information to be updated according to the previously obtained unprocessed update request; the address update unit 1 intercepts the read request from the memory address management unit 3, and the read request is used to access the memory 4; the address update unit 1 compares the read request with the page table information to be updated to obtain a comparison result; the address update unit 1 responds to the comparison result indicating that there is the same virtual address in the read request and the page table information to be updated, updates the page table information to be updated (for example, deletes the updated virtual address from the page table information to be updated), and the page table information corresponding to the memory 4 and the memory address management unit 3 respectively; the address update unit 1 feeds back the update result to the page table update source 2, and the update result is used to represent that the address update unit 1 has completed the update of the memory 4 and the memory address management unit 3.

[0074] In this way, through the page table information to be updated, while waiting for the page table update source 2 to send an update request, the address update unit 1 can process the unprocessed update requests that have been obtained before, which can ensure the timely and continuous update of the page table information, and reduce the probability of update delay caused by waiting for a new update request. Moreover, by comparing the read request with the page table information to be updated, the address update unit 1 can accurately determine which read requests can be processed immediately, which can reduce unnecessary memory access waiting, reduce system overhead, and improve system operation efficiency.

[0075] It should be understood that the address update unit 1 updates the page table information corresponding to the memory 4 and the memory address management unit 3 respectively according to the obtained update request. It can either adopt an active trigger method to trigger the update of the memory address management unit 3 or passively wait for the page table update source 2 to send an access request. The embodiments of the present disclosure do not limit this, and can be set according to the implemented application scenarios.

[0076] In a possible implementation manner, as Figure 2 shown in S8, the page table update source 2 is connected to the memory address management unit 3. The memory address management unit 3 receives a second virtual address request from the page table update source 2. The second virtual address request carries a virtual address and a second identifier. In response to the memory address management unit 3 identifying that the source category of the virtual address is other category requests other than the update request according to the second identifier, the memory address management unit 3 returns the first physical address corresponding to the virtual address to the page table update source 2.

[0077] Exemplarily, after receiving the update result fed back by the address update unit 1, the page table update source 2 may send a second virtual address request carrying a virtual address and a second identifier to the memory address management unit 3, and read the first physical address corresponding to the virtual address in the second virtual address request from the cache of the memory address management unit 3. The second identifier is used to indicate that the source category of the virtual address is other category requests other than the update request.

[0078] For example, after the page table update is completed, the cache of the memory address management unit 3 stores the latest page table information representing the mapping relationship between the virtual address and the first physical address. For example, the page table information includes the virtual address A and the first physical address A corresponding to the virtual address. The memory address management unit 3 receives a second virtual address request carrying the virtual address A and the second identifier. When the memory address management unit 3 recognizes the second identifier in the second virtual address request, it can know that the second virtual address request is a request unrelated to the address update, and can query the virtual address A in the page table information in the cache, and find that the virtual address A corresponds to the first physical address A, and can return the first physical address A to the page table update source 2.

[0079] In this way, after receiving the notification that the page table update is completed, the page table update source 2 can send a virtual second virtual address request to the memory address management unit 3, or can notify other hardware modules or software that the mapping relationship is available.

[0080] In the above update process, if multi-level page tables are involved, in Figure 2 S3 as shown, the address update unit 1 will send multiple physical address requests to the page table update source 2. In a possible implementation manner, when the page table information includes multi-level page tables, the address update unit 1 obtains a second physical address from the page table update source 2, and writes the page table information used to describe the mapping relationship between the virtual address and the first physical address into the storage location indicated by the second physical address in the memory 4, including: the address update unit 1 sends a physical address request to the page table update source 2, and the physical address request includes a third identifier for indicating the page table level; the address update unit 1 receives the second physical address fed back by the page table update source 2, and the second physical address corresponds to the third identifier; the address update unit 1 writes the page table information of the level indicated by the third identifier into the storage location indicated by the second physical address in the memory 4 according to the second physical address corresponding to each third identifier.

[0081] Optionally, the physical address request sent by the address update unit 1 to the page table update source 2 can carry multiple different-level third identifiers at a time. The page table update source 2 can receive multiple third identifiers at a time, and feedback all the second physical addresses corresponding to all levels to the address update unit 1 according to the multiple third identifiers. The address update unit 1 can write the page table information of the level indicated by the third identifier into the storage location indicated by the second physical address in the memory 4 according to the second physical address corresponding to each third identifier.

[0082] Optionally, the address update unit 1 sends multiple physical address requests to the page table update source 2. Each physical address request can carry a third identifier for indicating the page table level at a time, and the number of sending times is determined by the level of the multi-level page table; the address update unit 1 receives the second physical address fed back by the page table update source 2 each time, and the second physical address is the second physical address corresponding to the third identifier generated by the page table update source 2 according to the physical address request carrying the third identifier; the address update unit 1 writes the page table information of the level indicated by the third identifier into the storage location indicated by the second physical address in the memory 4 according to the second physical address corresponding to each third identifier.

[0083] It should be understood that during the interaction between the address update unit 1 and the page table update source 2, each physical address request can carry one or more third identifiers at a time, and different third identifiers can correspond to different page table levels. The embodiments of the present disclosure do not limit the specific interaction method between the address update unit 1 and the page table update source 2, and can be set according to the actual application scenario.

[0084] By setting up a multi-level page table, the memory space can be optimized, the memory utilization rate can be improved, a larger virtual address space can be supported, and the address conversion speed can be increased.

[0085] For example, if there is a multi-level page table in the memory address management unit 3, the address update unit 1 needs to send physical address requests to the page table update source 2 multiple times because the establishment of each level of the page table requires an available second physical address. At the same time, in order for the address update unit 1 to know which level of the page table the currently established page table belongs to, each physical address request sent by the address update unit 1 includes a third identifier for indicating the page table level. The page table update source 2 can generate a second physical address corresponding to the third identifier according to the physical address request carrying the third identifier.

[0086] For example, the multi-level page table can include M levels (M>1), and the address update unit 1 can send M physical address requests to the page table update source 2.

[0087] The first physical address request 1 sent by the address update unit 1 to the page table update source 2 can carry a third identifier 1 for indicating the first-level list. The page table update source 2 can generate a second physical address 1 corresponding to the third identifier 1 according to the physical address request 1 carrying the third identifier 1, which is used to indicate the position in the memory 4 where the first-level page table information is written. The page table update source 2 can feedback the second physical address 1 corresponding to the third identifier 1 to the address update unit 1, and the address update unit 1 writes the first-level page table information into the position of the second physical address 1 in the memory 4 according to the second physical address 1, realizing the update of the first-level page table information in the memory 4.

[0088] Similarly, the second physical address request 2 sent by the address update unit 1 to the page table update source 2 for the first time can carry a third identifier 2 for indicating the second-level list. The page table update source 2 can generate a second physical address 2 corresponding to the third identifier 2 according to the physical address request 2 carrying the third identifier 2, which is used to indicate the position in the memory 4 where the second-level page table information is written. The page table update source 2 can feedback the second physical address 2 corresponding to the third identifier 2 to the address update unit 1, and the address update unit 1 writes the second-level page table information into the position of the second physical address 2 in the memory 4 according to the second physical address 2, realizing the update of the second-level page table information in the memory 4.

[0089] By analogy, the physical address request M sent by the address update unit 1 to the page table update source 2 for the M-th time can carry a third identifier M for indicating the M-th level list. The page table update source 2 can generate a second physical address M corresponding to the third identifier M according to the physical address request M carrying the third identifier M, which is used to indicate the position in the memory 4 where the M-th level page table information is written. The page table update source 2 can feedback the second physical address M corresponding to the third identifier M to the address update unit 1. The address update unit 1 writes the M-th level page table information to the position of the second physical address M in the memory 4 according to the second physical address M, so as to realize the update of the M-th level page table information in the memory 4.

[0090] In a possible implementation manner, when the page table information includes multi-level page tables, the read request generated by the memory address management unit 3 for accessing the memory 4 may further include a third identifier for indicating the page table level information. When the address update unit 1 receives a read request carrying the first identifier and the third identifier, it will intercept the read request according to the first identifier and prevent it from being sent to the memory 4. At the same time, according to the third identifier indicating the page table level information, the page table content updated by the page table update source 2 (such as the first physical address corresponding to the virtual address) is returned to the on-chip cache of the memory address management unit 3.

[0091] Among them, according to the working process of the memory address management unit 3, assuming that the multi-level page table is a three-level page table, the memory address management unit 3 can sequentially send read requests carrying the third identifier to the address update unit 1. For example, the third identifier carried by the first read request is used to represent the first-level page table PC, the third identifier carried by the second read request is used to represent the second-level page table PD, and the third identifier carried by the third read request is used to represent the third-level page table PD. The address update unit 1 will return the first physical address to the memory address management unit 3 according to the page table information issued by the page table update source 2 for describing the mapping relationship between the virtual address and the first physical address. At the same time, the address update unit 1 can record the second physical address for the memory address management unit 3 to access the memory 4 according to the physical address request, and initiate a write operation on the second physical address. The write data can come from the first physical address of the page table update source 2. In this way, the page table information of the page table update source 2 will be synchronized to the memory 4 and the memory address management unit 3.

[0092] In a possible implementation manner, in response to the read request sent by the memory address management unit 3 including a second identifier, the address update unit 1 transparently transmits the read request from the memory address management unit 3 to the memory 4, and the address update unit 1 transparently transmits the return result of the memory 4 in response to the read request to the memory address management unit 3. The second identifier is used to indicate that the source category of the virtual address of the read request is other category requests other than the update request.

[0093] In this way, an address update unit 1 is introduced between the memory address management unit 3 and the memory 4. Its function is to identify the read requests sent by the memory address management unit 3 to the memory 4. If the read request contains the second identifier, it indicates a normal read request, and the source category of the virtual address of this read request is other category requests other than the update request. The address update unit 1 can release the read request carrying the second identifier, transparently transmit the read request from the memory address management unit 3 to the memory 4, and let it perform the normal memory 4 reading operation. If the read request contains the first identifier, it indicates a read request related to page table update, and the address update unit 1 can intercept it. The address update unit 1 not only improves the address update efficiency but also does not affect the operations unrelated to address update between the memory address management unit 3 and the memory 4.

[0094] Among them, when the memory address management unit 3 sends a read request to the address update unit 1, the included first identifier or second identifier can be used to distinguish whether the read request is a request related to page table update. Further, the read request may further include a third identifier for indicating which level of page table update request the read request is. The present disclosure does not limit the specific forms of the first identifier to the third identifier.

[0095] In summary, the address update device according to the embodiments of the present disclosure may include: an address update unit 1, a page table update source 2, a memory address management unit 3, and a memory 4. Among them, the page table update source 2 may be connected to the memory address management unit 3 and the address update unit 1, and the address update unit 1 is connected between the memory address management unit 3 and the memory 4. The address update unit 1 receives an update request from the page table update source 2, and the update request includes a virtual address and a first physical address corresponding to the virtual address; the address update unit 1 generates a first identifier according to the virtual address carried in the update request; the address update unit 1 sends a first virtual address request carrying the first identifier and the virtual address to the memory address management unit 3; the memory address management unit 3 generates a read request for accessing the memory 4 according to the first virtual address request, and the read request includes the virtual address and the first identifier, and the first identifier is used to indicate that the source category of the virtual address is the update request, so that the address update unit 1 can intercept the read request carrying the first identifier according to the first identifier and send the first physical address to the memory address management unit 3 to implement the update of the memory address management unit 3; the address update unit 1 sends a physical address request to the page table update source 2 to obtain a second physical address from the page table update source 2, and write the page table information describing the mapping relationship between the virtual address and the first physical address into the storage location indicated by the second physical address in the memory 4 to implement the update of the memory 4; then, the address update unit 1 feeds back an update result to the page table update source 2, and the update result is used to indicate that the address update unit 1 has completed the update of the memory 4 and the memory address management unit 3.

[0096] After the update is completed, the page table update source 2 can send a second virtual address request carrying the virtual address and a second identifier to the memory address management unit 3, and read the first physical address corresponding to the virtual address in the second virtual address request from the cache of the memory address management unit 3. The second identifier is used to indicate that the source category of the virtual address is other category requests other than the update request.

[0097] Thus, for the scenario where the hardware needs to update the page table, compared with the related art where the software is first notified how to allocate the page table through the software-hardware interface, and then the software writes the page table information into the memory 4, and then the memory address management unit 3 is notified to re-obtain the page table information. This process in the related art consumes too much time due to the synchronization between software and hardware and accessing the memory, which will affect the performance of the processor. In the address update device according to the embodiments of the present disclosure, by introducing the address update unit 1, the page table information in the memory 4 and the page table information of the memory address management unit 3 are directly updated by the address update unit 1 as hardware, reducing the software-hardware interaction during system operation (the address update unit 1 obtains the update request for how to allocate the page table initiated by the hardware via the page table update source 2), simplifying the page table update process, and improving the system operation efficiency.

[0098] It can be understood that the above-mentioned various method embodiments mentioned in the present disclosure can be combined with each other to form combined embodiments without violating the principle logic. Due to space limitations, the present disclosure will not elaborate further. Those skilled in the art can understand that in the above methods of the specific implementation manner, the specific execution order of each step should be determined according to its function and possible internal logic.

[0099] In addition, the present disclosure also provides an address update method, a processor, a chip, an electronic device, a computer-readable storage medium, and a program, all of which can be used to implement any address update scheme provided by the present disclosure. The corresponding technical solutions and descriptions can be referred to the corresponding records in the method part and will not be elaborated further.

[0100] Figure 3 A schematic diagram showing an address update method according to an embodiment of the present disclosure, as Figure 3 shown, the method is applied to the address update device, and the address update device includes: an address update unit 1, a page table update source 2, a memory address management unit 3, and a memory 4; the method includes: in step S31, the address update unit 1 receives an update request from the page table update source 2, and the update request includes a virtual address and a first physical address corresponding to the virtual address; in step S32, the address update unit 1 updates the page table information corresponding to the memory 4 and the memory address management unit 3 respectively according to the obtained update request, and the page table information is used to describe the mapping relationship between the virtual address and the first physical address.

[0101] In a possible implementation, step S32 may include: The address update unit 1 sends a first virtual address request carrying the virtual address to the memory address management unit 3 according to the virtual address carried in the update request; The memory address management unit 3 generates a read request for accessing the memory 4 according to the first virtual address request; The address update unit 1 intercepts the read request and sends the first physical address to the memory address management unit 3; The address update unit 1 obtains a second physical address from the page table update source 2 and writes the page table information describing the mapping relationship between the virtual address and the first physical address into the storage location indicated by the second physical address in the memory 4.

[0102] In a possible implementation, step S32 may include: The address update unit 1 waits for the page table update source 2 to send an update request and generates the page table information to be updated according to the unprocessed update request obtained previously; The address update unit 1 intercepts the read request from the memory address management unit 3, and the read request is used to access the memory 4; The address update unit 1 compares the read request with the page table information to be updated to obtain a comparison result; The address update unit 1 updates the page table information to be updated and the page table information corresponding to the memory 4 and the memory address management unit 3 respectively in response to the comparison result indicating that there is the same virtual address in the read request and the page table information to be updated.

[0103] In a possible implementation, the method further includes: The address update unit 1 feeds back an update result to the page table update source 2, and the update result is used to represent that the address update unit 1 has completed the update of the memory 4 and the memory address management unit 3.

[0104] In a possible implementation, that the address update unit 1 sends a first virtual address request carrying the virtual address to the memory address management unit 3 according to the virtual address carried in the update request includes: The address update unit 1 sends a first virtual address request carrying a first identifier and the virtual address to the memory address management unit 3; The read request includes the virtual address and the first identifier, and the first identifier is used to indicate that the source category of the virtual address is the update request; That the address update unit 1 intercepts the read request includes: The address update unit 1 intercepts the read request in response to the read request including the first identifier.

[0105] In a possible implementation, when the page table information includes a multi-level page table, the address update unit 1 obtains a second physical address from the page table update source 2, and writes the page table information for describing the mapping relationship between the virtual address and the first physical address into the storage location indicated by the second physical address in the memory 4, including: the address update unit 1 sends a physical address request to the page table update source 2, and the physical address request includes a third identifier for indicating the page table level; the address update unit 1 receives the second physical address fed back by the page table update source 2, and the second physical address corresponds to the third identifier; the address update unit 1 writes the page table information of the level indicated by the third identifier into the storage location indicated by the second physical address in the memory 4 according to the second physical address corresponding to each third identifier.

[0106] In a possible implementation, the method further includes: the memory address management unit 3 receives a second virtual address request from the page table update source 2, and the second virtual address request carries a virtual address and a second identifier; in response to the memory address management unit 3 identifying that the source category of the virtual address is other category requests other than the update request according to the second identifier, the memory address management unit 3 returns the first physical address corresponding to the virtual address to the page table update source 2.

[0107] In a possible implementation, the method further includes: in response to the read request sent by the memory address management unit 3 including a second identifier, the address update unit 1 transparently forwards the read request from the memory address management unit 3 to the memory 4; the address update unit 1 transparently forwards the return result of the memory 4 in response to the read request to the memory address management unit 3, and the second identifier is used to indicate that the source category of the virtual address of the read request is other category requests other than the update request.

[0108] In a possible implementation, the method further includes: when the memory address management unit 3 receives the first virtual address request, it queries the virtual address carried by the first virtual address request in the cache of the memory address management unit 3; when the virtual address is not queried in the cache of the memory address management unit 3, it allocates space for storing page table information for the first virtual address request in the cache; or, when the virtual address is queried in the cache of the memory address management unit 3, it clears the associated space of the virtual address in the cache and allocates space for storing page table information for the first virtual address request in the cache.

[0109] In some embodiments, the functions or modules included in the apparatus provided by the embodiments of the present disclosure can be used to execute the methods described in the above method embodiments. The specific implementation can refer to the description of the above method embodiments. For the sake of brevity, it will not be repeated here.

[0110] The embodiments of the present disclosure also propose a processor, and the processor includes the address update device as described above.

[0111] The embodiments of the present disclosure also propose a chip, and the chip includes the processor as described above.

[0112] The embodiments of the present disclosure also propose a computer-readable storage medium, on which computer program instructions are stored. When the computer program instructions are executed by a processor, the above methods are implemented. The computer-readable storage medium can be a volatile or non-volatile computer-readable storage medium.

[0113] The embodiments of the present disclosure also propose an electronic device, including: a processor; a memory for storing instructions executable by the processor; wherein, the processor is configured to call the instructions stored in the memory to execute the above methods.

[0114] The embodiments of the present disclosure also provide a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in the processor of an electronic device, the processor in the electronic device executes the above methods.

[0115] The electronic device can be provided as a terminal, a server or other forms of devices, such as a user equipment (UE), a mobile device, a user terminal, a terminal, a cellular phone, a cordless phone, a personal digital assistant (PDA), a handheld device, a computing device, a vehicle-mounted device, a wearable device, etc.

[0116] Figure 4 A block diagram of an electronic device 1900 according to an embodiment of the present disclosure is shown. For example, the electronic device 1900 can be provided as a server or a terminal device. Referring to Figure 4 , the electronic device 1900 includes a processing component 1922, which further includes one or more processors. Any processor can include the address update device as described above, and memory resources represented by a memory 1932 for storing instructions executable by the processing component 1922, such as application programs. The application programs stored in the memory 1932 can include one or more modules each corresponding to a set of instructions. In addition, the processing component 1922 is configured to execute instructions to execute the above methods.

[0117] The electronic device 1900 may also include a power supply component 1926 configured to perform power management of the electronic device 1900, a wired or wireless network interface 1950 configured to connect the electronic device 1900 to a network, and an input / output interface 1958. The electronic device 1900 may operate based on an operating system stored in the memory 1932, such as the Microsoft server operating system (Windows Server TM ), the graphical user interface-based operating system launched by Apple Inc. (Mac OS X TM ), the multi-user and multi-process computer operating system (Unix TM ), the free and open-source Unix-like operating system (Linux TM ), the open-source Unix-like operating system (FreeBSD TM ) or the like.

[0118] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as the memory 1932 including computer program instructions, and the above computer program instructions can be executed by the processing component 1922 of the electronic device 1900 to complete the above method.

[0119] The present disclosure may be a system, a method, and / or a computer program product. The computer program product may include a computer-readable storage medium having thereon computer-readable program instructions for causing a processor to implement various aspects of the present disclosure.

[0120] A computer-readable storage medium may be a tangible device that can retain and store instructions for use by an instruction execution device. A computer-readable storage medium may be, for example, (but is not limited to) an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples (non-exhaustive list) of the computer-readable storage medium include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disc (DVD), a memory stick, a floppy disk, a mechanical encoding device, such as a punched card or raised structures in grooves having instructions stored thereon, and any suitable combination of the foregoing. The computer-readable storage medium used herein is not construed as an instantaneous signal itself, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagated through a waveguide or other transmission medium (e.g., an optical pulse through an optical fiber cable), or an electrical signal transmitted through a wire.

[0121] The computer-readable program instructions described herein can be downloaded to various computing / processing devices from a computer-readable storage medium or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network may include copper transmission cables, optical fiber transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium in each computing / processing device.

[0122] The computer program instructions for performing the operations of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages such as Smalltalk, C++, etc., and conventional procedural programming languages such as the "C" language or similar programming languages. The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, executed as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., through the Internet using an Internet service provider). In some embodiments, by using the state information of the computer-readable program instructions to customize an electronic circuit, such as a programmable logic circuit, a field-programmable gate array (FPGA), or a programmable logic array (PLA), the electronic circuit can execute the computer-readable program instructions to implement various aspects of the present disclosure.

[0123] Aspects of the present disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0124] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that the instructions, when executed by the processor of the computer or other programmable data processing apparatus, create an apparatus that implements the functions / acts specified in one or more boxes of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, a programmable data processing apparatus, and / or other devices to operate in a particular manner, so that the computer-readable medium storing the instructions comprises a manufacture, which includes instructions that implement various aspects of the functions / acts specified in one or more boxes of the flowchart and / or block diagram.

[0125] The computer-readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other devices so that a series of operational steps are performed on the computer, other programmable data processing apparatus, or other devices to produce a computer-implemented process such that the instructions executed on the computer, other programmable data processing apparatus, or other devices implement the functions / acts specified in one or more boxes of the flowchart and / or block diagram.

[0126] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram may represent a module, a segment of a program, or a portion of an instruction, and the module, segment of a program, or portion of an instruction includes one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions noted in the boxes may occur in a different order than noted in the figures. For example, two consecutive boxes may in fact be executed substantially in parallel, or they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each box in the block diagrams and / or flowcharts, and combinations of boxes in the block diagrams and / or flowcharts, can be implemented by a dedicated hardware-based system that performs the specified functions or acts, or by a combination of dedicated hardware and computer instructions.

[0127] The computer program product can be implemented specifically in the form of hardware, software, or a combination thereof. In an alternative embodiment, the computer program product is embodied as a computer storage medium. In another alternative embodiment, the computer program product is embodied as a software product, such as a Software Development Kit (SDK), etc.

[0128] The above descriptions of the various embodiments tend to emphasize the differences between the various embodiments. Their similarities or likenesses can be referred to each other. For the sake of brevity, they are not elaborated herein.

[0129] Those skilled in the art can understand that in the above methods of the specific embodiments, the writing order of each step does not mean a strict execution order and does not impose any limitation on the implementation process. The specific execution order of each step should be determined according to its function and possible internal logic.

[0130] In addition, in each embodiment of the present application, the functional modules can be integrated together to form an independent part, or each module can exist alone, or two or more modules can be integrated to form an independent part.

[0131] The above has described the embodiments of the present disclosure. The above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations are obvious to those of ordinary skill in the art in the technical field without departing from the scope and spirit of the described embodiments. The choice of terms used herein is intended to best explain the principles of the embodiments, the practical application, or the improvement of the technology in the market, or to enable other ordinary skill in the art in the technical field to understand the embodiments disclosed herein.

Claims

1. An address updating device, characterized in that: The address updating device comprises: an address updating unit, a page table updating source, a memory address management unit, and a memory; The address updating unit receives an update request from the page table update source, wherein the update request includes a virtual address and a first physical address corresponding to the virtual address; The address updating unit updates page table information corresponding to the memory and the memory address management unit respectively according to the acquired update request, wherein the page table information is used to describe a mapping relationship between the virtual address and the first physical address; wherein the address updating unit intercepts a read request sent by a memory address management unit and sends the first physical address to the memory address management unit, the read request corresponding to the virtual address; The address updating unit writes page table information used to describe a mapping relationship between the virtual address and the first physical address into the memory.

2. The address updating device according to claim 1, characterized in that: The address updating unit updates the page table information corresponding to the memory and the memory address management unit respectively according to the acquired update request, including: The address updating unit sends a first virtual address request carrying the virtual address to the memory address management unit according to the virtual address carried in the update request; The memory address management unit generates a read request for accessing the memory according to the first virtual address request; The address updating unit intercepts the read request and sends the first physical address to the memory address management unit; The address updating unit obtains a second physical address from the page table update source, and writes page table information describing a mapping relationship between the virtual address and the first physical address into a storage location indicated by the second physical address in the memory.

3. The address updating device according to claim 1, characterized in that: The address updating unit updates the page table information corresponding to the memory and the memory address management unit respectively according to the acquired update request, including: The address update unit waits for the page table update source to send an update request, and generates to-be-updated page table information according to the previously acquired unprocessed update request; The address updating unit intercepts a read request from the memory address management unit, wherein the read request is used to access the memory; The address updating unit compares the read request with the page table information to be updated to obtain a comparison result; In response to the comparison result indicating that the read request and the page table information to be updated have the same virtual address, the address update unit updates the page table information to be updated and the page table information corresponding to the memory and the memory address management unit respectively.

4. The address updating device according to claim 2 or 3, characterized in that: The address update unit is further used to feed back an update result to the page table update source, where the update result is used to indicate that the address update unit has completed the update of the memory and the memory address management unit.

5. The address updating device according to claim 2, characterized in that: The address updating unit sends a first virtual address request carrying the virtual address to the memory address management unit according to the virtual address carried in the update request, including: The address updating unit sends a first virtual address request carrying a first identifier and the virtual address to the memory address management unit; The read request includes the virtual address and the first identifier, wherein the first identifier is used to indicate that the source category of the virtual address is the update request; The address updating unit intercepts the read request, comprising: In response to the read request containing the first identifier, the address update unit intercepts the read request.

6. The address updating device according to claim 2, characterized in that: In the case where the page table information includes a multi-level page table, the address updating unit obtains a second physical address from the page table update source, and writes the page table information used to describe the mapping relationship between the virtual address and the first physical address into a storage location indicated by the second physical address in the memory, including: The address updating unit sends a physical address request to the page table update source, where the physical address request includes a third identifier for indicating a page table level; The address updating unit receives a second physical address fed back by the page table update source, where the second physical address corresponds to the third identifier; The address updating unit writes the page table information of the level indicated by the third identifier into the storage location indicated by the second physical address in the memory according to the second physical address corresponding to each third identifier.

7. The address updating device according to claim 2 or 3, characterized in that: The memory address management unit receives a second virtual address request from the page table update source, where the second virtual address request carries a virtual address and a second identifier; In response to the memory address management unit identifying, according to the second identifier, that the source category of the virtual address is a request of another category other than the update request, the memory address management unit returns the first physical address corresponding to the virtual address to the page table update source.

8. The address updating device according to claim 2 or 3, characterized in that: The address updating unit transmits the read request from the memory address management unit to the memory in response to the read request sent by the memory address management unit including the second identifier; The address update unit transparently transmits the return result of the memory in response to the read request to the memory address management unit, and the second identifier is used to indicate that the source category of the virtual address of the read request is other category requests other than the update request.

9. The address updating device according to claim 2, characterized in that: The memory address management unit receives the first virtual address request, and searches the cache of the memory address management unit for the virtual address carried in the first virtual address request; In the case where the virtual address is not found in the cache of the memory address management unit, allocating space for storing page table information in the cache for the first virtual address request; or, When the virtual address is found in the cache of the memory address management unit, the associated space of the virtual address is cleared in the cache, and space for storing page table information is allocated in the cache for the first virtual address request.

10. An address updating method, characterized in that: The method is applied to an address updating device, which includes: an address updating unit, a page table updating source, a memory address management unit, and a memory; The method comprises: The address updating unit receives an update request from the page table update source, wherein the update request includes a virtual address and a first physical address corresponding to the virtual address; The address updating unit updates page table information corresponding to the memory and the memory address management unit respectively according to the acquired update request, wherein the page table information is used to describe a mapping relationship between the virtual address and the first physical address; wherein the address updating unit intercepts a read request sent by a memory address management unit and sends the first physical address to the memory address management unit, the read request corresponding to the virtual address; The address updating unit writes page table information used to describe a mapping relationship between the virtual address and the first physical address into the memory.

11. A processor, characterized in that: The processor comprises the address updating device according to any one of claims 1 to 9.

12. A chip, characterized in that: The chip includes the processor of claim 11.

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