A chip design method and device for multiple projects

Abstract

The present invention provides a chip design method and device for multiple projects, including: determining a project set, the project set including at least two chip projects; obtaining a physical layout of an integrated chip that realizes the requirements of all chip projects in the project set through the first stage of design; obtaining an integrated bare chip produced according to the physical layout of the integrated chip; and planning the packaging of the integrated bare chip according to the requirements of each chip project in the project set to obtain a chip that meets the requirements of the chip project. The present invention can realize that multiple projects share a set of mask plates, thereby reducing the total manufacturing cost.

Description

Technical Field

[0001] The present invention relates to the field of chip design, and in particular to a chip design method and device for multiple projects. Background Art

[0002] ASIC (Application Specific Integrated Circuit) chips are widely used in modern electronic systems. The design of ASIC chips generally includes three stages, namely:

[0003] The first stage includes a demand analysis of the chip project to determine the functions, performance requirements, and application scenarios that the chip needs to achieve. Then, based on the demand analysis, the chip's architecture design, logic design, integrated design, and physical design are carried out in sequence to obtain a physical layout that can be used for production and manufacturing.

[0004] In the second stage, the chip is produced through a series of process steps according to the physical layout of the designed chip. The chip at this time is usually called a bare die.

[0005] In the third stage, the bare die is packaged to obtain the chip we usually see.

[0006] The cost of ASIC chips is very low after mass production, but its early design and development costs and production costs are extremely expensive. Among them, the one-time plate making cost of the mask plate used in the photolithography process in the second stage of production is very high.

[0007] Due to differences in customer needs and technical indicators, units engaged in the first phase of design tasks often have multiple similar chip projects under development at the same time. For example, if six chip projects are carried out at the same time, if each chip project has to go through the above three stages, it will have to go through six production and manufacturing processes, and six mask plate making fees will need to be paid, which is a considerable expense for units engaged in the first phase of design tasks. How to reduce the production cost in the chip design process is a problem that is expected to be solved. Summary of the invention

[0008] The purpose of the present invention is to provide a chip design method and device for multiple projects, so as to solve the problem of high production cost in the prior art.

[0009] The technical solution provided by the present invention is as follows:

[0010] A chip design method for multiple projects includes: determining a project set, the project set including at least two chip projects;

[0011] Through the design of the first stage, a physical layout of an integrated chip that realizes the requirements of all chip projects in the project set is obtained;

[0012] Obtaining an integrated bare chip produced according to the physical layout of the integrated chip;

[0013] According to the requirements of each chip project in the project collection, plan the packaging of the integrated die to obtain a chip that meets the requirements of the chip project.

[0014] In some embodiments, through the first stage of design, a physical layout of an integrated chip that realizes the requirements of all chip projects in the project set is obtained, including:

[0015] Design each chip project in the project set respectively to obtain a design result of each chip project, where the design result is a requirement analysis result, an architecture design result, a logic design result, a comprehensive design result, or a physical design result;

[0016] The design results of all chip projects in the project collection are integrated, and the physical layout of the integrated chip is obtained based on the integrated results.

[0017] In some embodiments, the fusion is a simple merge or a multiplexed merge.

[0018] In some embodiments, the fusion is multiplexing merging, and the multiplexing merging includes at least one of the following methods:

[0019] Input and output port multiplexing, merging of modules with the same function, and macro unit multiplexing.

[0020] In some embodiments, multiplexing of macrocells is accomplished by selecting macrocells with the highest demand and / or that meet all project requirements.

[0021] In some embodiments, multiplexing of input and output ports is achieved through a multiplexer and a control signal for controlling the multiplexer.

[0022] In some embodiments, the level of the control signal of the multiplexer is controlled by a programmable device.

[0023] In some embodiments, the control signal of the multiplexer is connected to the input port of the integrated chip, and the level of the control signal is determined according to application requirements during packaging.

[0024] In some embodiments, the control signal of the multiplexer is connected to the input port of the integrated chip, which is packaged outside the chip during packaging. When it is used, the level of the control signal is determined at the application board level according to the requirements of the application.

[0025] The present invention also provides a chip design device for multiple projects, comprising:

[0026] A project set determination module is used to determine a project set, where the project set includes at least two chip projects;

[0027] A design planning module is used to obtain a physical layout of an integrated chip that meets the requirements of all chip projects in the project set through the first stage of design;

[0028] A production planning module, used to obtain an integrated bare chip produced according to a physical layout of the integrated chip;

[0029] The packaging planning module is used to plan the packaging of the integrated bare die according to the requirements of each chip project in the project collection to obtain a chip that meets the requirements of the chip project.

[0030] Compared with the prior art, the chip design method and device for multiple projects provided by the present invention can at least bring the following beneficial effects:

[0031] 1. The present invention combines the designs of multiple applications / functions and designs them all at once on the same ASIC chip for production, thereby reducing the number of designs in the first stage and the number of productions in the second stage, improving design and production efficiency and reducing production costs.

[0032] 2. When carrying out different application / function merging designs, the present invention can adopt different strategies according to different types of designs to achieve optimal design and production cost control and improve design and production flexibility.

[0033] 3. The present invention adopts the same set of processes for design and production for different applications and functions, thereby improving the consistency and reliability of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The preferred implementation modes will be described below in a clear and understandable manner in conjunction with the accompanying drawings to further illustrate the above-mentioned characteristics, technical features, advantages and implementation methods of a chip design method and device for multiple projects.

[0035] Figure 1 is a flow chart of an embodiment of a chip design method for multiple projects of the present invention;

[0036] Figure 2 is a schematic structural diagram of an embodiment of a chip design device for multiple projects of the present invention;

[0037] Figure 3 is a schematic diagram of the design of each single-chip project in one embodiment of the present invention;

[0038] Figure 4 It is a schematic diagram of simply merging the designs of various single-chip projects in one embodiment of the present invention;

[0039] Figure 5 It is a schematic diagram of multiplexing the input and output ports of each single-chip project in one embodiment of the present invention. DETAILED DESCRIPTION

[0040] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the specific implementation methods of the present invention will be described below with reference to the accompanying drawings. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings and other implementation methods can be obtained based on these drawings without creative work.

[0041] In order to simplify the drawings, only the parts related to the present invention are schematically shown in each figure, and they do not represent the actual structure of the product. In addition, in order to simplify the drawings and facilitate understanding, in some figures, only one of the parts with the same structure or function is schematically drawn or marked. In this article, "one" not only means "only one", but also means "more than one".

[0042] In one embodiment of the present invention, Figure 1 As shown, a chip design method for multiple projects includes:

[0043] Step S1000 determines a project set, where the project set includes at least two chip projects.

[0044] The elements in the project set can be determined manually, or the candidate projects can be selected by machine according to certain principles and then manually adjusted and decided. Usually, chip projects with similar functions can be selected to form a project set. The requirements of chip projects with similar functions are relatively similar, and the probability of design reuse in the first stage is higher, which can reduce the design cost of the first stage.

[0045] Step S2000 obtains a physical layout of an integrated chip that realizes the requirements of all chip projects in the project set through the first stage of design.

[0046] The first stage of design includes project demand analysis, logic design, integrated design and physical design of the chip. Some complex chips also include chip architecture design. Demand analysis refers to determining the functions and performance to be achieved by the chip based on market or user needs. The task of logic design is to refine the chip functions into logic circuits and use hardware description language (HDL) to describe the behavior and function of the circuits. The task of integrated design is to convert HDL code into physical circuits. Physical design is to determine the physical layout and connection of the physical circuit to obtain the physical layout for chip manufacturing.

[0047] The first phase design of multiple chip projects can be carried out at the same time. It can be integrated from the demand analysis, or from the chip architecture design, logic design, integrated design or physical design. This mainly depends on the progress of each chip project. For example, if chip project 1 and chip project 2 are both in the demand analysis stage, and it is necessary to design an integrated chip that meets the requirements of chip project 1 and chip project 2, then it can be integrated from the demand analysis, and then the logic design, integrated design and physical design are carried out according to the fusion results of the demand analysis (that is, the demand analysis results of the integrated chip) to obtain the physical layout of the integrated chip. For another example, if chip project 1 and chip project 2 both have mature FPGA designs, and in order to reduce costs, the FPGA design needs to be converted into a functionally equivalent ASIC design, at this time, the first phase design of chip project 1 and chip project 2 can be carried out independently to obtain their respective physical design results; then the physical design results of chip project 1 and chip project 2 are integrated to obtain the physical layout of the integrated chip.

[0048] Step S3000 obtains an integrated bare chip produced according to the physical layout of the integrated chip.

[0049] Specifically, the manufacturing of integrated chips is planned, and the physical layout of the integrated chips is delivered to the manufacturer for manufacturing. After the second phase of design, the manufacturer produces the corresponding bare chips according to the physical layout of the integrated chips. This bare chip that integrates the requirements of multiple chip projects is called an integrated bare chip, and the integrated bare chip is delivered to the designer.

[0050] The second stage of design refers to the production of chips by manufacturers through a series of process steps according to the physical layout. For manufacturers, only one set of mask plates need to be made, and only one production is required according to the physical layout of the integrated chip. There is no need to make multiple sets of mask plates, and there is no need to produce multiple times according to the physical layout of multiple chips, which greatly reduces the production cost.

[0051] In addition, the number of bare chips required to be produced should not be less than the sum of the number of chips produced for all single-chip projects, which makes it easier to meet the minimum chip quantity requirements required for manufacturing and helps reduce costs.

[0052] Step S4000 plans the packaging of the integrated bare die according to the requirements of each chip project in the project set to obtain a chip that meets the requirements of each single chip project.

[0053] Although the integrated bare die integrates the functions of multiple chip projects, different packages are used to make the packaged chips meet the requirements of each single chip project, thus obtaining chips for each chip project. The number of different packages depends on the requirements of each chip project.

[0054] In this embodiment, the requirements of multiple single-chip projects are integrated into one chip (i.e., an integrated chip), and then the integrated chip is used for tape-out production. Multiple single-project chips are then realized through different packages based on the obtained bare chips. Only one production is required during the entire design process, and only one set of mask plates need to be made, which greatly reduces the production cost compared to traditional methods.

[0055] In one embodiment, step S2000 includes:

[0056] Step S2100 designs each chip project in the project set respectively to obtain a design result of each chip project, where the design result is a requirement analysis result, an architecture design result, a logic design result, a comprehensive design result, or a physical design result;

[0057] Step S2200 integrates the design results of all chip projects in the project set, and obtains the physical layout of the integrated chip according to the integrated results.

[0058] For example, perform demand analysis and logic design on each chip project in turn to obtain the logic design results of each chip project; merge the logic design results of all chip projects to obtain the logic design results of the integrated chip; perform comprehensive design and physical design based on the logic design results of the integrated chip to obtain the physical layout of the integrated chip.

[0059] In one embodiment, the fusion in step S2200 is a simple merge.

[0060] Simply combine the design results of all chip projects in the project set without integrating the design results of each project. This process makes integration simple and helps shorten the design time.

[0061] In this way, in the design of the integrated chip, the input port is equal to the sum of the input ports of each chip project, the output port is equal to the sum of the output ports of each chip project, and the design of the integrated chip is equal to the sum of the designs of each chip project.

[0062] In one embodiment, the fusion in step S2200 is multiplexing merging.

[0063] Integrate the design results of all chip projects in the project collection, that is, reuse and merge. Reuse and merge include but are not limited to the following methods: input and output port reuse, merging of modules with the same function, and macro unit reuse. The specific reuse measures can be adopted according to different strategies according to the design needs.

[0064] Taking input and output port multiplexing as an example, input port multiplexing refers to the multiplexing of the input ports of multiple single-chip projects to the input ports of the integrated chip, and output port multiplexing refers to the multiplexing of the output ports of multiple single-chip projects to the output ports of the integrated chip. Compared with simple merging, input multiplexing can reduce the number of input ports of the integrated chip. Similarly, output multiplexing can reduce the number of output ports of the integrated chip. Input and output port multiplexing can be multiplexing of some ports or multiplexing of the maximum number of ports.

[0065] The merging of modules with the same function means that when the same functional design exists in different chip projects, only one design can be retained and the duplicate design can be removed, which can reduce the chip cost.

[0066] Different chip projects may use the same macrocells in different functional designs. The number of macrocells used can be reduced through macrocell reuse and some auxiliary designs. Macrocells are usually large in area, and reducing the number of macrocells is conducive to reducing chip area, thereby reducing chip costs.

[0067] Compared with simple merging, this embodiment integrates the resources used in the design of various chip projects, including input and output port multiplexing, macro unit multiplexing and merging of modules with the same function, thereby reducing chip costs.

[0068] Macrocell multiplexing includes memory multiplexing and / or phase-locked loop (PLL) multiplexing and / or multiplexing of other IPs (e.g., ADC / DAC converters). Memory multiplexing can be achieved by reserving a memory with large storage space. PLL multiplexing can be achieved by allowing the PLL to generate the required high-frequency clock and then using a frequency division circuit to generate the required low-frequency clock; PLL multiplexing can also be achieved by configuring the PLL to obtain all the clocks required for multiple projects.

[0069] In summary, macrocell reuse is achieved by selecting macrocells with the highest demand and / or those that meet the needs of all chip projects.

[0070] For example, if project 1 requires a 1Mbyte SRAM and project 2 requires a 5Mbyte SRAM, when multiplexing and merging, only one 5Mbyte SRAM needs to be retained, which can meet the needs of both projects.

[0071] For example, Project 1 requires a 1MHz clock and Project 2 requires a 100KHz clock. When multiplexing and merging, only one PLL macro unit is used to generate a 1MHz clock, which is then divided to obtain a 100KHz clock. This meets the needs of both projects while saving one PLL macro unit.

[0072] In one embodiment, input and output port multiplexing is achieved through a multiplexer and a control signal for controlling the multiplexer.

[0073] In one embodiment, the level of the control signal of the multiplexer is controlled by a programmable device, which includes but is not limited to an efuse device, an OTP device, and an MTP device.

[0074] In one embodiment, the control signal of the multiplexer is connected to the input port of the integrated chip, and the level of the control signal is determined according to application requirements during packaging.

[0075] In one embodiment, the control signal of the multiplexer is connected to the port of the integrated chip and packaged outside the chip during packaging. When it is used, the level of the control signal is determined at the application board level according to the application requirements.

[0076] In one embodiment of the present invention, Figure 2 As shown, a chip design device for multiple projects includes:

[0077] The project set determination module 100 is used to determine a project set, where the project set includes at least two chip projects;

[0078] The design planning module 200 is used to obtain a physical layout of an integrated chip that meets the requirements of all chip projects in the project set through the first stage of design;

[0079] A production planning module 300 is used to obtain an integrated bare chip produced according to a physical layout of the integrated chip;

[0080] The packaging planning module 400 is used to plan the packaging of the integrated bare die according to the requirements of each chip project in the project set to obtain a chip that meets the requirements of the chip project.

[0081] In one embodiment, the design planning module includes:

[0082] A single-project design unit is used to design each chip project in the project set respectively to obtain a design result of each chip project, where the design result is a requirement analysis result, an architecture design result, a logic design result, a comprehensive design result, or a physical design result;

[0083] The integration unit is used to fuse the design results of all chip projects in the project collection and obtain the physical layout of the integrated chip based on the fusion results.

[0084] In one embodiment, the fusion is a simple merge or a multiplex merge.

[0085] In one embodiment, the fusion is multiplexing and merging, and the multiplexing and merging includes at least one of the following methods: input and output port multiplexing, merging of same functional modules, and macro unit multiplexing.

[0086] In one embodiment, the reuse of macrocells is accomplished by selecting macrocells with the highest demand and / or that meet all project requirements.

[0087] In one embodiment, a multiplexer is further included, and the multiplexer multiplexes the input and output ports according to a control signal for controlling the multiplexer.

[0088] In one embodiment, a programmable device is further included, and the programmable device controls the level of the control signal of the multiplexer.

[0089] In one embodiment, the control signal of the multiplexer is connected to the input port of the integrated chip, and the level of the control signal is determined according to application requirements during packaging.

[0090] In one embodiment, the control signal of the multiplexer is connected to the input port of the integrated chip, which is packaged outside the chip during packaging.

[0091] It should be noted that the embodiments of the chip design device for multiple projects provided by the present invention and the embodiments of the chip design method for multiple projects provided above are based on the same inventive concept and can achieve the same technical effects. Therefore, other specific contents of the embodiments of the chip design device for multiple projects can refer to the contents of the embodiments of the chip design method for multiple projects provided above.

[0092] The present invention also provides a specific application, which adopts the aforementioned chip design method for multiple projects, as follows:

[0093] There are 6 chip projects for realizing interface protocol conversion, namely: Project 1: Convert interface protocol A to interface protocol B; Project 2: Convert interface protocol A to interface protocol C; Project 3: Convert interface protocol B to interface protocol A; Project 4: Convert interface protocol B to interface protocol C; Project 5: Convert interface protocol C to interface protocol A; Project 6: Convert interface protocol C to interface protocol B. For example, the three interface protocols AC are serial communication protocols SPI, I2C, and UART.

[0094] According to the traditional design method, six designs are needed to meet the above application requirements respectively, six first-stage designs need to be completed, and six chips need to be produced and packaged.

[0095] Based on the chip design method for multiple projects proposed in this application, the implementation is as follows:

[0096] 1) Determine a project set: The set obtained by bringing together the above 6 chip projects is called a project set.

[0097] 2) To obtain the logic design result of the integrated chip corresponding to the project set, you can do the following:

[0098] Method 1:

[0099] Design each chip project and get the logic design result of the corresponding project. For example, project 1: get design 1, input port IN1 and output port OUT1. The logic design of the 6 projects is as follows Figure 3 The input port IN1 is not limited to one input interface signal, but can also be a collection of multiple input interface signals; the input ports IN2 to IN6 and the output ports OUT1 to OUT6 can be understood in the same way.

[0100] Physically combine the logic design results of all chip projects as the logic design results of the integrated chip, such as Figure 4 shown.

[0101] In this method, the input and output ports of the integrated chip are equal to the sum of the input and output ports of the six single-project chips, and the design of the integrated chip is equal to the sum of the designs of the six single-project chips.

[0102] Method 2:

[0103] Design is performed for each chip project to obtain the logic design result of the corresponding project; the logic design results of all chip projects in the project set are reused and merged to obtain the logic design result of the integrated chip that realizes the functions of all chip projects.

[0104] For example, analyze the area size, IP core, and IO (input and output) of Design 1, Design 2, Design 3, Design 4, Design 5, and Design 6. If the analysis result shows that all designs have a relatively small area, a large number of input and output ports, and no IP core reuse, then only the reuse of input and output ports needs to be considered.

[0105] Assume that the selected merging strategy is to reuse the input and output ports. The merging diagram is as follows: Figure 5 S2, S1, and S0 are introduced as programmable input selection interfaces, corresponding to 8 codes. The first six codes are selected in the example to correspond to six designs respectively. In actual applications, any six codes can be selected as needed.

[0106] like Figure 5As shown, the level of the S0-S2 signal is controlled by the programmable device efuse (electronic fuse), and the input multiplexer and the output multiplexer are controlled by the S0-S2 signal to realize the connection between the input port of the integrated chip and one of the six input ports (IN1-IN6), and the connection between the output port of the integrated chip and one of the six output ports (OUT1-OUT6). The programming data can be written to the efuse through the JTAG (Joint Test Group, used for boundary scan testing) in the original design.

[0107] You can also use a one-time programmable device OTP (One Time Program) or a multi-time programmable device MTP (Multi-time Program) to control the level of the S0-S2 signal. Efuse uses fuse technology, OTP uses anti-fuse technology, efuse and OTP can only be programmed once, and MTP can be programmed multiple times.

[0108] Alternatively, the S0-S2 signals may be connected to the input port of the integrated chip, and in the subsequent packaging process, they may be connected to a high level or a low level according to the application requirements.

[0109] The S0-S2 signals can also be packaged outside the chip, and in specific applications, they can be connected to a high level or a low level on an application-level PCB board according to actual application needs.

[0110] 3) Perform comprehensive design, physical design, and electrical property verification on the obtained integrated chip logic design. If the verification is correct, produce the corresponding integrated bare chip according to the physical layout of the integrated chip.

[0111] 4) According to the requirements of the single chip project, the integrated bare chips are packaged separately to obtain chips that meet the requirements of the single chip project.

[0112] It should be noted that the input and output ports of the aforementioned integrated chip are the pins seen inside the chip. If some of the pins are packaged outside the chip, they become the pins seen outside the chip, otherwise they can only be the pins inside the chip.

[0113] Take the integrated bare chip obtained by method 1 as an example, its input ports include IN1~IN6, and its output ports include OUT1~OUT6. Assuming that 100 chips of project 1 are to be obtained, 100 integrated bare chips are selected, and the IN1 port and OUT1 port of each integrated bare chip are packaged outside the chip, so that the chip obtained by packaging is the chip of project 1. Assuming that 200 chips of project 2 are to be obtained, 200 integrated bare chips are selected, and the IN2 port and OUT2 port of each integrated bare chip are packaged outside the chip, so that the chip obtained by packaging is the chip of project 2. Chips of other projects are obtained by packaging in the same way.

[0114] According to method 2 Figure 5 Take the integrated bare chip obtained in the example as an example, its input port is IN, and its output port is OUT. If you want to get the chip of project 1, you can package the IN and OUT ports outside the chip, and set S2-S0 to 000 through JTAG. The chip obtained by packaging is the chip of project 1. If you want to get the chip of project 2, in addition to packaging the IN and OUT ports outside the chip, you can also set S2-S0 to 001 through JTAG. The chip obtained by packaging is the chip of project 2. And so on, you can get the chips of other projects through packaging.

[0115] if Figure 5 If the efuse device in the project is replaced with an MTP device, the chip originally packaged as project 1 can be flexibly converted into a chip of other projects by reprogramming S2-S0.

[0116] If Figure 5 If the S2-S0 signal in the chip is directly packaged outside the chip, all chip projects can share the package, and the level of the S2-S0 signal can be controlled on the application-level PCB board according to the needs of the actual application to meet the needs of the corresponding application.

[0117] In this embodiment, by integrating the requirements of multiple single-chip projects into one chip (i.e., an integrated chip), all designs can be completed at one time, thereby improving design efficiency. Then, according to one integrated chip, only one production is required, which greatly reduces the total mask plate making cost compared with the traditional method. The produced integrated bare chip can be used for any application scenario of the design, and then multiple single-project chips can be realized through packaging, which can flexibly meet the number of chips required for different application scenarios.

[0118] It should be noted that the above embodiments can be freely combined as needed. The above are only preferred embodiments of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be regarded as the protection scope of the present invention.

Claims

1. A chip design method for multiple projects, characterized in that: include: Determine a project set, wherein the project set includes at least 2 chip projects; Through the design of the first stage, a physical layout of an integrated chip that realizes the requirements of all chip projects in the project set is obtained; Obtaining an integrated bare chip produced according to the physical layout of the integrated chip; According to the requirements of each chip project in the project set, planning the packaging of the integrated bare chip to obtain a chip that meets the requirements of the chip project; The physical layout of an integrated chip that realizes the requirements of all chip projects in the project set is obtained through the design of the first stage, including: Designing each chip project in the project set respectively to obtain a design result of each chip project, wherein the design result is a demand analysis result, an architecture design result, a logic design result, a comprehensive design result, or a physical design result; The design results of all chip projects in the project set are integrated, and the physical layout of the integrated chip is obtained according to the integrated results; the integration is a simple integration or a multiplexing integration.

2. The chip design method for multiple projects according to claim 1, characterized in that: The multiplexing and merging includes at least one of the following methods: Input and output port multiplexing, merging of modules with the same function, and macro unit multiplexing.

3. The chip design method for multiple projects according to claim 2, characterized in that: Macrocell reuse is achieved by selecting macrocells with the highest demand and / or that meet the needs of all chip projects.

4. The chip design method for multiple projects according to claim 2, characterized in that: The input and output port multiplexing is achieved through a multiplexer and a control signal for controlling the multiplexer.

5. The chip design method for multiple projects according to claim 4, characterized in that: The level of the control signal of the multiplexer is controlled by a programmable device.

6. The chip design method for multiple projects according to claim 4, characterized in that: The control signal of the multiplexer is connected to the input port of the integrated chip, and the level of the control signal is determined according to application requirements during packaging.

7. The chip design method for multiple projects according to claim 4, characterized in that: The control signal of the multiplexer is connected to the port of the integrated chip and packaged outside the chip during packaging. When it is used, the level of the control signal is determined at the application board level according to the application requirements.

8. A chip design device for multiple projects, characterized in that: include: A project set determination module, used to determine a project set, wherein the project set includes at least two chip projects; A design planning module, used to obtain a physical layout of an integrated chip that realizes the requirements of all chip projects in the project set through the first stage of design; A production planning module, used to obtain an integrated bare chip produced according to the physical layout of the integrated chip; A packaging planning module, used to plan the packaging of the integrated bare die according to the requirements of each chip project in the project set, so as to obtain a chip that meets the requirements of the chip project; The design planning module includes: A single project design unit, used to design each chip project in the project set respectively, and obtain a design result of each chip project, wherein the design result is a demand analysis result, an architecture design result, a logic design result, a comprehensive design result, or a physical design result; The integration unit is used to merge the design results of all chip projects in the project set, and obtain the physical layout of the integrated chip according to the fusion results; the fusion is a simple merger or a multiplexed merger.

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