Weight writing method of multi-resistance state resistive random access memory and circuit system thereof

Abstract

In order to improve the speed of weight write verification, the invention designs a two-step write verification scheme. In the second step of writing, the scheme needs to read the resistance value of the MLC unit after each write is completed, and establish a lookup table of the relationship between each resistance state and the number of pulses to achieve each resistance state. When the storage unit is initially written, the lookup table is read and the corresponding number of pulses is transmitted to the unit, which greatly reduces the number of read verifications and reduces system energy consumption.

Description

Technical Field

[0001] The present invention relates to the field of in-memory computing technology, and in particular to a weight writing method of a multi-resistance state resistive random access memory and a circuit system thereof. Background Art

[0002] Nowadays, deep learning is one of the areas of interest for hardware and software researchers. In order to achieve accurate and efficient learning processes, deep neural networks (DNNs) have become a powerful solution for various tasks such as image classification, speech recognition, and language translation. In order to achieve high accuracy of DNNs, larger network scales and deeper network depths are required. Inevitably, as the scale of DNNs continues to grow, higher computational loads are added. The traditional von Neumann computing architecture uses a design in which the processor and memory are separated. Therefore, when performing high-density computing, the data movement between storage and computing consumes a lot of resources and is difficult to cope with the demand for high computing power. Computing in Memory is a new computing architecture that uses physical laws such as Ohm's law and Kirchhoff's current law to perform analog computing in the memory array, integrating storage units with computing units, avoiding large amounts of data movement, thereby improving computing speed and energy efficiency, and breaking through the bottleneck of the memory wall in the von Neumann architecture.

[0003] At present, various types of new memories have been studied as synaptic devices for CIM applications, such as resistive random access memory (RRAM), phase change memory (PCM), Flash, and ferroelectric field effect transistors (FeFET). Among them, the in-memory computing architecture based on RRAM devices is one of the mainstream directions explored by academia and industry. The resistance of RRAM is controlled by the amount of charge flowing through it. Based on this characteristic, we can use its high and low resistance states to store information. Existing research further realizes the multi-level storage capability of RRAM, which can store multiple bits of information in each storage cell, further improve storage density and computing efficiency, and realize high-performance, low-power in-memory computing systems. However, compared with traditional binary data storage, multi-level resistive synaptic devices require a tighter distribution of unit conductance, because any deviation in unit conductance value may affect the result of analog-to-digital conversion (ADC) quantization. Therefore, it is more challenging to linearly space each state in the conductance mechanism, and higher requirements are placed on the weight-accurate write verification scheme of resistive memory cells at the circuit level.

[0004] MLC (Multi-level cell) operation has been verified at the device level. According to the enhancement and suppression tests of RRAM, multiple resistance states can be achieved by adjusting the pulse width or pulse amplitude, but the design implications of MLC at the circuit and system levels remain to be explored. Currently, only a few studies in the literature have explored the application of MLC at the circuit level, and most of the work is focused on the readout circuit. There are few studies on the precise tuning of MLC at the storage array level. The main weight write verification schemes are step-by-step approximation write, pulse width modulation write, and preset write termination. The flow chart of the step-by-step approximation write scheme is shown in the figure below. Figure 1 As shown in Figure (a), a series of gradually increasing or decreasing voltage pulses are used for step-by-step adjustment. After each adjustment, a read operation is performed to confirm that the expected state has been achieved. However, multiple iterative writes are required, and the verification process takes a long time. The pulse width modulation write process, such as Figure 1 As shown in Figure (b), the resistance change is finely controlled by adjusting the width (duration) of the voltage pulse. This method can flexibly adjust the pulse width and amplitude according to the programming strategy, but it has high requirements for the control circuit, requiring precise and reliable voltage and time control circuits, and this method usually rewrites the RRAM cell after it is completely reset or set during the write iteration process, which will affect the performance and life of the cell; the preset write termination first sets an expected target resistance range, and then interrupts the write process if the resistance value reaches or exceeds the range. Although this method can quickly adjust the resistance value to the target area, the control of the write interruption circuit is relatively complex, and the interruption conditions are relatively fixed. When the write weight needs to be changed, the circuit structure needs to be readjusted, and it is not universal.

[0005] In the prior art, when the resistance value of MLC is detected, a readout circuit is needed to read out the current or voltage on the MLC. The output value of the readout circuit indirectly represents the resistance value of the MLC, so the accuracy of the readout circuit is also crucial for the accurate writing of the MLC resistance value. The readout circuit is generally implemented by a sense amplifier or an ADC. The sense amplifier reads the 0 or 1 stored in the RRAM, but cannot accurately read out the storage value in the multi-resistance storage unit. The ADC has high accuracy, but its area and energy consumption are too large. If an external device is used for readout and reprogramming, the readout time is slow and additional pin allocation is required. Summary of the invention

[0006] In view of the problems existing in the prior art, the present invention provides a weight writing circuit system for a multi-resistance state resistive random access memory, characterized in that: the circuit system comprises: an RRAM array, a driving circuit, a control module, a current-to-voltage module and an ADC module;

[0007] The current-to-voltage module converts the current value output by the source line of the RRAM array into a voltage value during the reading phase, amplifies the voltage, and then transmits the voltage to the input end of the ADC module;

[0008] The ADC module is used to read the voltage value output by the current-to-voltage module, convert it into a digital output, and then transmit it to the control module;

[0009] The control module is provided with a resistance state-pulse number correspondence lookup table; the control module controls the input of the write voltage and the read voltage of the RRAM array by the driving circuit according to the resistance state-pulse number correspondence lookup table.

[0010] Preferably, one RRAM and one NMOS transistor of the RRAM array are connected in series to form a multi-resistance state resistive storage cell MLC with a 1T1R structure.

[0011] Preferably, the gates of the MOS tubes in all 1T1R units in the same row of the RRAM array are uniformly connected to a word line, and the word line is connected to a word line write voltage (V_write) and a ground through a switch circuit; the top electrode terminal of the RRAM in all 1T1R units in the same row of the RRAM array is connected to a bit line, and the bit line is connected to two write voltages (V_write1 and V_write2) and a read voltage (V_read) through a switch circuit; the sources of the MOS tubes in all 1T1R units in the same column of the RRAM array are uniformly connected to a source line, and the source line is connected to two write voltages (V_write1 and V_write2), the current-to-voltage module, and gnd through a switch circuit.

[0012] Preferably, the ADC module is constructed based on an optimized comparator circuit and a threshold inverse quantization (TIQ) comparator, and is used to read the voltage value output by the current-to-voltage module, convert it into a digital output, and then transmit it to the control module.

[0013] Preferably, the ADC module comprises: a comparator module and an encoder; the comparator module comprises: a threshold inverse quantization (TIQ) comparator, a double-tail comparator and a control circuit.

[0014] The present invention also provides a method for writing a weight, the method comprising the following steps:

[0015] S1: performing an initialization operation on the RRAM array to set the RRAM array to a lowest resistance state;

[0016] S2: the control module performs a coarse write on an MLC of the RRAM array according to the resistance state-pulse number correspondence lookup table;

[0017] S3: After the rough writing is completed, a read verification is performed; the control module verifies whether the MLC is written into the corresponding resistance state range according to the read data of the ADC module. If it is written into the corresponding resistance state range, it jumps to the next MLC to cycle the above operations. If it does not enter the target weight value range, it is necessary to fine-tune the resistance value.

[0018] Preferably, in step S3, the resistance fine-tuning is specifically as follows: further adjusting the resistance of the MLC, first determining whether its resistance is lower than the minimum value of the resistance state or higher than the maximum value of the resistance state; if it is lower than the minimum value of the resistance state, then sending two RESET pulses with smaller amplitude to the bit line of the unit through the control module before reading; if it is higher than the maximum value of the resistance state, then inputting 2 cycles of SET pulses with smaller amplitude to the bit line of the unit for fine-tuning.

[0019] Preferably, if writing is not successful after iterating steps S1-S3 for a preset number of times, the program jumps to the next unit for writing and outputs a write failure signal, thereby traversing all MLC units and completing the resistance writing of the entire RRAM array.

[0020] Compared with the prior art solutions, the present invention has at least the following beneficial effects:

[0021] 1) The present invention innovatively implements an on-chip precise read-write circuit system based on multi-resistance state resistive memory. Based on the optimized ADC design, combined with the on-chip digital control module established by the lookup table containing the relationship between each resistance state and the number of pulses and the verification scheme, the memory cell resistance can be quickly written to the specified range within a limited number of cycles through two amplitude pulse voltages, and the voltage detection readout circuit is used to overcome the potential logic ambiguity, thereby realizing the compact distribution of resistance state resistance, improving the weight writing speed, and reducing the power consumption of reading verification;

[0022] 2) Optimize the ADC design of the readout circuit to reduce the power consumption and area of ​​the ADC while meeting the reading accuracy, and use multiplexing technology to improve the use efficiency of the ADC and further reduce power consumption;

[0023] 3) A lookup table of the relationship between each resistance state and the number of pulses to achieve each resistance state is established in the digital control module. When initially writing to a unit, the lookup table is read and the corresponding number of pulses is transmitted to the unit, which greatly reduces the number of read verifications and reduces system energy consumption;

[0024] 4) Through two different write pulse amplitudes, the resistance value of the MLC is first quickly written to the vicinity of the target resistance value through a pulse with a larger amplitude, and then the MLC resistance value is fine-tuned through a pulse with a smaller amplitude, the target weight is quickly written to the MLC, and a compact distribution of the resistive state is achieved;

[0025] 5) The two pulse voltages with different amplitudes are controlled by digital control circuits and transmission gate switches, and the circuit structure is relatively simple. Compared with the pulse width modulation circuit, the use of many MOS tubes is reduced, and the circuit complexity and power consumption are reduced;

[0026] 6) A lookup table that can flexibly adjust the relationship between each resistance state and the number of pulses that realize each resistance state, as well as the resistance range of each resistance state, is adaptable to resistive memory with various characteristics and has universality and scalability. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a simplified flow chart of a step-by-step approach writing scheme and a simplified flow chart of a step-by-step approach writing scheme in the prior art; wherein, (a) is a simplified flow chart of a step-by-step approach writing scheme in the prior art, and (b) is a simplified flow chart of a pulse width modulation writing scheme in the prior art;

[0028] Figure 2 1 is a LTD and LTP characteristic curve of the RRAM cell of the present invention and a schematic diagram of the 1T1R cell structure; wherein (a) is the LTD and LTP characteristic curve of the RRAM cell of the present invention, and (b) is a schematic diagram of the 1T1R cell structure of the present invention;

[0029] Figure 3 is a diagram of the architecture of the writing circuit system of the present invention;

[0030] Figure 4 It is a schematic diagram of a 16*16 1T1R array and a driving circuit of the present invention;

[0031] Figure 5 It is a schematic diagram of the structure of Flash ADC of the present invention;

[0032] Figure 6 It is a schematic diagram of the corresponding relationship between each resistance state and the number of pulses and each voltage of the present invention;

[0033] Figure 7 It is a flowchart of the writing verification workflow of the present invention. Specific embodiments

[0034] The technical solution of the present invention is further described below with reference to the accompanying drawings and through specific implementation methods.

[0035] The technology of the present invention, based on a 16*16 1T1R array built on a multi-resistance RRAM device model, proposes a two-step write weight write verification scheme, designs an accurate read and write verification circuit for the multi-resistance RRAM array, and adopts a voltage detection readout circuit to overcome potential logical ambiguity, thereby realizing a compact distribution of multi-resistance resistors, greatly improving the weight write speed and reducing the power consumption of read verification.

[0036] The present invention provides a writing circuit diagram for a multi-resistance RRAM. Figure 2 As shown in Figure (a), according to the LTD and LTP characteristic curves of the RRAM cell, the RRAM cell resistance can show resistance variability under the SET pulse or RESET pulse, and the writing and adjustment of the RRAM resistance value can be realized based on this characteristic. The circuit diagram is based on the 1T1R cell to build a memristor array, as shown in Figure 2 As shown in Figure (b), a RRAM and an NMOS transistor are connected in series to form a 1T1R resistive memory cell. The word line connected to the gate of the transistor controls the on and off of the 1T1R cell. The specific operation is determined by the pulse signal on the bit line. The SET pulse or RESET pulse provided at the bit line end can adjust the resistance of the RRAM cell.

[0037] The overall circuit system architecture diagram is as follows: Figure 3 As shown, it consists of RRAM array, driving circuit, control module, current-to-voltage module and ADC module. The specific construction steps are as follows:

[0038] S1: First, a 16*16 1T1R array (taking 16*16 as an example) was built based on the multi-resistance RRAM model and CMOS. The specific structure is as follows Figure 4 As shown. The gates of the MOS tubes in all 1T1R cells in the same row are uniformly connected to the word line (WL), and the WL end is connected to the word line write voltage (V_write) and ground (gnd) through a switch circuit. The top electrode end of the RRAM in all 1T1R cells in the same row is connected to the bit line (BL), and the BL end is connected to two write voltages (V_write1 and V_write2) and a read voltage (V_read) through a switch circuit. The source electrodes of the MOS tubes in all 1T1R cells in the same column are uniformly connected to the source line (SL), and the SL end is connected to two write voltages (V_write1 and V_write2), ADC, and gnd through a switch circuit.

[0039] S2: Use data selectors and transmission gates to build bit line (BL) drivers, word line (WL) drivers, and source line (SL) drivers on the periphery of the array. These three drivers are responsible for selecting a cell in the array and turning on switches corresponding to different input voltages according to control signals at different stages, transmitting different pulse voltages to a cell to complete weight writing and adjustment.

[0040] S3: Design a current-to-voltage module based on an operational amplifier and a resistor network. During the reading phase, the current value output from the SL terminal is converted into a voltage value, amplified, and then transmitted to the ADC input terminal.

[0041] S4: Build an 8-bit FLASH-ADC module based on the optimized comparator circuit and threshold inverse quantization (TIQ) comparator (structure as shown in Figure 5 As shown), it is used to read the voltage value output by the current-to-voltage module and convert it into a digital output, which is then transmitted to the control module;

[0042] S5: Write a control module based on Verilog language, write the resistance state information of each MLC unit in the control module in advance, establish a lookup table of two corresponding relationships between each resistance state and the number of pulses required for each resistance state to achieve, and each resistance state and its resistance state range (corresponding relationship diagram, such as Figure 6 As shown in the figure), write the weight writing scheme for initial writing and subsequent verification. When working and writing the verification scheme, the control signal of each module is output, so that each module can complete the reading, writing and verification work, and quickly write the weight.

[0043] like Figure 7 The figure shows the writing verification workflow of the present invention. When writing, the cells in the 16*16 array are written and verified one by one. First, the entire array is initialized to set, that is, all cells are selected through WL, BL and SL drivers, that is, all switches connected to the V_write pulse voltage at the WL end are opened through the WL driver, all switches connected to the V_write1 pulse voltage at the SL end are opened through the SL driver, and all switches connected to the gnd voltage at the BL end are opened through the BL driver, and all cells are set to set all RRAMs to the lowest resistance state;

[0044] Then, the rough writing starts from the MLC of the first row and the first column. First, the switch between the first row WL0 and V_WL_write is closed by the WL driver, and a high level is input to the WL end of all the MLCs in the first row to turn on the transistor. The first row BL0 is selected by the BL driver, and the switch connected to V_write1 is closed, and a write pulse (V_write1) is input to the BL0 end. At the same time, the SL driver is responsible for closing the switch connected to gnd at the SL0 end of the first column to select and write to the first row and the first column. The remaining columns SL1 to SL15 close the switches connected to V_write1 to prevent interference with the resistance values ​​of the remaining columns of MLC. Finally, according to the corresponding relationship between each resistance state and the number of pulses to achieve the resistance state in the lookup table, the control module counts, and after reaching the number of pulses to achieve the resistance state, the switch connected to V_write1 at the BL0 end, the switch connected to gnd at the SL0 end, and the switches connected to V_write1 at SL1 to SL15 are disconnected.

[0045] After the rough write is completed, a read verification is performed. The WL0 end maintains the closed state of the switch between V_WL_write, and the control module controls the BL driver to close the switch connected to BL0 and V_read. The SL0 end closes the switch connected to the ADC module, and SL1 to SL15 remain in the open state. The read current obtained by V_read acting on the MCL unit will be converted into a suitable voltage by the current-to-voltage module and transmitted to the ADC module for reading. Then the control module verifies whether the MLC is written into the corresponding resistance state range based on the read data of the ADC. If it is written into the corresponding resistance state range, it jumps to the next unit and repeats the above operation. If it does not enter the target weight value range, it is necessary to fine-tune the resistance value.

[0046] To further adjust the resistance of the MLC, first determine whether its resistance is lower than the minimum value of the resistance state or higher than the maximum value of the resistance state. If it is lower than the minimum value of the resistance state, two fine-tuning reset pulses with smaller amplitudes are sent to the BL end of the unit through the control module before reading. The specific operation is as follows: the WL driver closes the switch between the first row WL0 and V_WL_write to turn on the transistor. The first row BL0 is selected by the BL driver, and the switch connected to V_write2 is closed, and a write pulse (V_write2) is input to the BL0 end. At the same time, the SL driver is responsible for closing the switch connected to gnd at the SL0 end of the first column, and the switches connected to V_write2 in the remaining columns SL1 to SL15 are closed. The control module counts and sends two V_write2 pulses to the unit, then turns off the switch connected to V_write2 at BL0, the switch connected to gnd at the SL0 end, and the switches connected to V_write1 at SL1 to SL15, and enters the reading stage. If it is higher than the maximum value of the resistance state, two cycles of set pulses with a smaller amplitude are input to the BL end of the unit for fine-tuning. The specific operation is as follows: WL drives to close the switch between the first row WL0 and V_WL_write. The first column SL0 is selected by the SL drive, and the switch connected to V_write2 is closed, and a write pulse (V_write2) is input to the SL0 end. At the same time, the BL driver is responsible for closing the switch connected to gnd in the first row, counting through the control module, and after sending two V_write2 pulses to the unit, the switch connecting SL0 to V_write2 and the switch connected to gnd at the BL0 end are turned off to enter the reading phase. After 20 iterations in the above manner, if the writing is not successful, jump to the next unit for writing, and output a write failure signal. In this way, all units are traversed to complete the resistance writing of the entire array.

[0047] In order to improve the weight write verification speed, the present invention designs a two-step write verification scheme. In the second step of writing, the resistance value of the MLC unit needs to be read after each write is completed, which requires the ADC module to respond quickly and convert the read analog quantity into a digital quantity. Flash-ADC can effectively realize the fast sampling and processing of high-speed signals due to its high-speed conversion capability, and is very suitable for the storage and calculation unit readout circuit. However, the power consumption of Flash-ADC increases significantly with the increase of resolution. In order to achieve lower delay and lower power consumption, the present invention adopts an improved Flash-ADC structure, including a TIQ (threshold inverter quantization) comparator, a control circuit and a double-tail (DT) comparator system architecture, which reduces the number of comparators by half, reduces power consumption and design area, and also has the advantage of low delay of the traditional Flash-ADC structure.

[0048] The preferred embodiments of the present invention are described in detail above. However, the present invention is not limited to the specific details in the above embodiments. Within the technical concept of the present invention, a variety of simple modifications can be made to the technical solution of the present invention, and these simple modifications all belong to the protection scope of the present invention.

[0049] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not further describe various possible combinations.

[0050] In addition, various embodiments of the present invention may be arbitrarily combined, and as long as they do not violate the concept of the present invention, they should also be regarded as the contents disclosed by the present invention.

Claims

1. A weight writing circuit system of a multi-resistance state resistive random access memory, characterized in that: The circuit system includes: an RRAM array, a driving circuit, a control module, a current-to-voltage module and an ADC module; The current-to-voltage module converts the current value output by the source line of the RRAM array into a voltage value during the reading phase, amplifies the voltage, and then transmits the voltage to the input end of the ADC module; The ADC module is used to read the voltage value output by the current-to-voltage module and convert it into a digital output, which is then transmitted to the control module; the ADC module includes: a comparator module and an encoder; the comparator module includes: a threshold inverse quantization TIQ comparator, a double-tail comparator and a control circuit; The control module is provided with a resistance state-pulse number correspondence lookup table; the control module performs a rough write on an MLC of the RRAM array according to the resistance state-pulse number correspondence lookup table, and performs a read verification after the rough write is completed; the control module verifies whether the MLC is written into the corresponding resistance state resistance value range according to the read data of the ADC module, and if it is written into the corresponding resistance state range, it jumps to the next MLC to cycle the above operation, and if it does not enter the target weight value range, it is necessary to perform resistance fine adjustment.

2. The circuit system according to claim 1, characterized in that: One RRAM and one NMOS transistor of the RRAM array are connected in series to form a multi-resistance state resistive storage cell MLC with a 1T1R structure.

3. The circuit system according to claim 1, characterized in that: The gates of the MOS tubes in all 1T1R units in the same row of the RRAM array are uniformly connected to a word line, and the word line is connected to a word line write voltage V_write and ground through a switch circuit; The top electrode terminals of the RRAMs in all 1T1R cells in the same row of the RRAM array are connected to bit lines, and the bit lines are connected to two write voltages V_write1 and V_write2 and a read voltage V_read through a switch circuit; The sources of the MOS tubes in all 1T1R units in the same column of the RRAM array are uniformly connected to a source line, and the source line is connected to two write voltages V_write1 and V_write2, gnd and the current-to-voltage module through a switch circuit.

4. The circuit system according to claim 1, characterized in that: The ADC module is constructed based on an optimized comparator circuit and a threshold inverse quantization TIQ comparator, and is used to read the voltage value output by the current-to-voltage module, convert it into a digital output, and then transmit it to the control module.

5. A method for writing circuit system weights using any one of claims 1 to 4, characterized in that: The method comprises the following steps: S1: performing an initialization operation on the RRAM array to set the RRAM array to a lowest resistance state; S2: the control module performs a coarse write on an MLC of the RRAM array according to the resistance state-pulse number correspondence lookup table; S3: After the rough writing is completed, a read verification is performed; the control module verifies whether the MLC is written into the corresponding resistance state range according to the read data of the ADC module. If it is written into the corresponding resistance state range, it jumps to the next MLC to cycle the above operations. If it does not enter the target weight value range, it is necessary to fine-tune the resistance value.

6. The writing method according to claim 5, characterized in that: In step S3, the resistance fine-tuning is specifically as follows: further adjusting the resistance of the MLC, first determining whether its resistance is lower than the minimum value of the resistance state or higher than the maximum value of the resistance state; if it is lower than the minimum value of the resistance state, then sending two RESET pulses with smaller amplitudes to the bit line of the unit where the resistance is located through the control module before reading; if it is higher than the maximum value of the resistance state, then inputting 2 cycles of SET pulses with smaller amplitudes to the bit line of the unit where the resistance is located for fine-tuning.

7. The writing method according to claim 6, characterized in that: If writing is not successful after iterating steps S1-S3 for a preset number of times, the next unit is jumped to write and a write failure signal is output. In this way, all MLC units are traversed to complete the resistance writing of the entire RRAM array.

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