Process method for low voltage super junction mosfet

Abstract

The application provides a process method of a low-voltage super-junction MOSFET, which comprises the following steps: forming an epitaxial layer of a first conductive type on a substrate of the first conductive type; forming a bulk region of a second conductive type on the surface of the epitaxial layer by means of ion implantation, and then performing thermal diffusion promotion on the bulk region; forming a hard mask layer and a photoresist layer on the bulk region; opening the photoresist layer by lithography to define the forming position of a gate trench, and then forming an opening on the hard mask layer to the epitaxial layer by means of anisotropic etching, etching the epitaxial layer at the bottom of the opening to form a first gate trench by taking the hard mask layer as a mask, and making the first gate trench extend downward through the bulk region from the upper surface of the epitaxial layer; performing etching on the epitaxial layer in the vertical direction of the extending direction of the first gate trench to form a second gate trench, so that the second gate trench is recessed into the hard mask layer; and forming an ion implantation protection layer on the surface of the gate trench. The application can avoid the connection of the bulk region and the columnar bulk region in the channel region during the ion implantation on the columnar bulk region.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a process method of low-voltage super-junction MOSFET. BACKGROUND

[0002] Before the process of forming pillar region by column region implantation, a hard mask layer is generally deposited as a mask template. The general etching method is to etch the hard mask layer to form an opening, and then etch Si to form a trench. Due to the large implantation energy of the column region implantation and the inclined sidewall of the hard mask layer, the body region and the column region are finally connected together in the channel region during the column region implantation, so that the device has no channel, thereby causing the device to fail.

[0003] Figure 1 A schematic diagram of a conventional hard mask layer structure and a schematic diagram of a device formed by the structure are shown in the figure, in which the body region and the column region are connected in the channel region.

[0004] Taking an N-type super-junction-trench gate as an example, the reference numerals are as follows: 101-highly doped N-type substrate, 102-N-type epitaxial layer / N-type drift region 103-P pillar implantation region, 104-gate dielectric layer, 105-gate polysilicon, 106-P-type body region, 107-P-type heavily doped implantation, 108-N-type heavily doped implantation, 109-contact hole, 110-interlayer dielectric layer, 111-gate terminal metal layer, 211-source-terminal-body-terminal metal layer, and 112-drain terminal metal layer.

[0005] To solve the above problems, a new process method of low-voltage super-junction MOSFET is needed. SUMMARY

[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a process method of low-voltage super-junction MOSFET, which is used to solve the problem that the body region and the column region are connected together in the channel region in the prior art, so that the device has no channel, thereby causing the device to fail.

[0007] To achieve the above-mentioned purposes and other related purposes, the present application provides a process method of low-voltage super-junction MOSFET, which comprises:

[0008] Step one, epitaxially forming a first conductive type epitaxial layer on a first conductive type substrate;

[0009] Step two, forming a second conductive type body region on the surface of the epitaxial layer by ion implantation, and then performing thermal diffusion promotion on the body region;

[0010] Step three, forming a hard mask layer and a photoresist layer on the body region; photoetching the photoresist layer to define the formation position of the gate trench, and then forming an opening on the hard mask layer to the epitaxial layer by anisotropic etching, and etching the epitaxial layer at the bottom of the opening to form the first gate trench by taking the hard mask layer as a mask, wherein the first gate trench extends downward from the upper surface of the epitaxial layer and passes through the body region;

[0011] Step four, etching the epitaxial layer in the vertical direction of the extension direction of the first gate trench to form a second gate trench, so that the second gate trench is recessed into the hard mask layer;

[0012] Step five, forming an ion implantation protection layer on the surface of the gate trench, taking the hard mask layer as a mask for ion implantation, and taking the ion implantation protection layer as a mask for ion implantation, and forming a columnar body region of the second conductive type at the bottom of the gate trench by self-aligned implantation, wherein the columnar body region does not form contact with the body region;

[0013] Step six, removing the ion implantation protection layer and the hard mask layer, and forming a gate dielectric layer in the gate trench; and forming a gate polysilicon layer to fill the remaining gate trench;

[0014] Step seven, forming a source heavily doped region above the body region on both sides of the gate trench, forming an insulating dielectric layer on the gate polysilicon layer, forming a contact hole on the source heavily doped region, and performing a heavily doped implantation on the body region below the contact hole, and forming a heavily doped region by thermal diffusion, and activating the impurity implantation of the heavily doped implantation;

[0015] Step eight, forming a conductive metal to fill the contact hole, and then forming a source, body region, and drain metal layer.

[0016] Preferably, the first conductive type in step one is N-type, and the second conductive type is P-type.

[0017] Preferably, the first conductive type in step one is P-type, and the second conductive type is N-type.

[0018] Preferably, the doping concentration of the epitaxial layer in step one is 5e15-1e17 cm-3.

[0019] Preferably, the material of the hard mask layer in step three is silicon dioxide.

[0020] Preferably, the second gate trench in step four is recessed into the hard mask layer by 300-700 angstroms.

[0021] Preferably, in step five, a sacrificial oxide layer is formed by thermal oxidation to repair defects formed by the gate trench etching, and the sacrificial oxide layer serves as an ion implantation protection layer.

[0022] Preferably, in step five, boron ions are used for ion implantation to form the P-type pillar region at the bottom of the gate trench.

[0023] Preferably, the pillar region in step five is formed by multiple ion implantations.

[0024] Preferably, the implantation dose of the boron ions in step five is 1e12-1e13cm-2, and the implantation energy is 50-4000KeV.

[0025] Preferably, in step six, the sacrificial oxide layer and the hard mask layer are removed in the same wet etching.

[0026] Preferably, the material of the gate dielectric layer in step six is silicon dioxide.

[0027] Preferably, the method for forming the gate dielectric layer in step six includes: forming a first gate silicon oxide layer by low-temperature thermal oxidation; depositing a TEOS silicon oxide layer as a second gate oxide layer, and then performing rapid annealing to densify the TEOS silicon oxide layer.

[0028] Preferably, the temperature of the low-temperature thermal oxidation in step six is 800-930 degrees Celsius, and the processing time is less than 30 minutes.

[0029] Preferably, the thickness of the first gate silicon oxide layer in step six is 100-400 angstroms.

[0030] Preferably, the contact hole in step seven is formed by photolithography and etching.

[0031] Preferably, after the contact hole is formed by photolithography and etching in step seven, a belt implantation is performed on the remaining photoresist to form the source end heavily doped region.

[0032] As described above, the process method of the low-voltage super-junction MOSFET of the present application has the following beneficial effects:

[0033] The present application can avoid the body region and the pillar region being connected together in the channel region during the pillar region implantation. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 A low-voltage super-junction MOSFET schematic diagram is shown as prior art;

[0035] Figure 2 A process flow schematic diagram of the present application is shown;

[0036] Figure 3 A schematic diagram showing the formation of the body region of the present application;

[0037] Figure 4 A schematic diagram showing the formation of the gate trench of the present application;

[0038] Figure 5 A schematic diagram showing the formation of the first gate trench of the present application;

[0039] Figure 6 A schematic diagram showing the formation of the second gate trench of the present application;

[0040] Figure 7 A schematic diagram showing the formation of the ion implantation protection layer on the surface of the gate trench of the present application;

[0041] Figure 8 A schematic diagram showing the formation of the second conductivity type pillar region on the bottom of the gate trench of the present application by self-aligned implantation;

[0042] Figure 9 A schematic diagram showing the removal of the ion implantation protection layer and the hard mask layer of the present application;

[0043] Figure 10 A schematic diagram showing the formation of the gate dielectric layer and the gate polysilicon layer in the gate trench of the present application;

[0044] Figure 11 A schematic diagram showing the formation of the heavily doped region of the present application;

[0045] Figure 12 A schematic diagram showing the formation of the source terminal, the body region terminal metal layer, and the drain terminal metal layer of the present application. DETAILED DESCRIPTION

[0046] The present application is herein described, by way of example only, with reference to certain embodiments thereof. It is construed that persons skilled in the art can easily understand other advantages and functions of the present application from the contents disclosed in the present specification. The present application can be implemented or applied in other different embodiments, and the details in the present specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present application.

[0047] Reference is made to Figure 2 The present application provides a process method for a low-voltage super-junction MOSFET, comprising:

[0048] Step one, epitaxially forming a first conductivity type epitaxial layer 102 on a first conductivity type substrate 101;

[0049] In some embodiments, the first conductivity type in step one is N-type, and the second conductivity type is P-type.

[0050] In some embodiments, the first conductivity type in step one is P-type; and the second conductivity type is N-type.

[0051] In some embodiments, the doping concentration of the epitaxial layer 102 in step one is 5e15-1e17cm^-3.

[0052] Step two, forming a body region 106 of the second conductivity type on the surface of the epitaxial layer 102 by ion implantation, and then performing thermal diffusion promotion on the body region 106 to form a structure as shown in FIG. 2B. Figure 3 The thermal promotion process of the body region 106 is placed before the trench gate structure and the columnar region 103 implantation, preventing excessive lateral diffusion of the columnar region 103 under the thermal promotion process of the body region 106.

[0053] Step three, forming a hard mask layer 502 and a photoresist layer 501 on the body region 106; opening the photoresist layer 501 by lithography to define the formation position of the gate trench, and then forming an opening on the hard mask layer 502 to the epitaxial layer 102 by anisotropic etching to form a structure as shown in FIG. 3A. Figure 4 Etching the epitaxial layer 102 at the bottom of the opening with the hard mask layer 502 as a mask to form a first gate trench, which extends downward from the upper surface of the epitaxial layer 102 through the body region 106 to form a structure as shown in FIG. 3B. Figure 5

[0054] In some embodiments, the material of the hard mask layer 502 in step three is silicon dioxide.

[0055] Step four, etching the epitaxial layer 102 in the vertical direction of the extension direction of the first gate trench to form a second gate trench, so that the second gate trench is recessed into the hard mask layer 502 to form a structure as shown in FIG. 4A. Figure 6 This can avoid the connection of the body region 106 and the columnar region 103 in the channel region during the implantation of the columnar region 103;

[0056] In some embodiments, the second gate trench is recessed into the hard mask layer 502 by 300-700 angstroms in step four.

[0057] Step five, forming an ion implantation protection layer 202 on the surface of the gate trench to form a structure as shown in FIG. 5A. Figure 7 With the hard mask layer 502 as the mask for ion implantation and the ion implantation protection layer 202 as the mask layer for ion implantation, a columnar region 103 of the second conductivity type is formed at the bottom of the gate trench by self-aligned implantation, wherein the columnar region 103 does not form contact with the body region 106 to form a structure as shown in FIG. 5B. Figure 8

[0058] ​​In some embodiments, in step five, the hard mask layer 502 is reserved, and a sacrificial oxide layer is formed by thermal oxidation to repair defects caused by the gate trench etching, and the sacrificial oxide layer serves as the ion implantation protection layer 202.

[0059] In some embodiments, in step five, boron ions are used for ion implantation to form a P-type pillar region 103 at the bottom of the gate trench.

[0060] In some embodiments, the pillar region 103 in step five is formed by multiple ion implantations.

[0061] In some embodiments, the boron ion implantation dose in step five is 1e12-1e13cm-2, and the implantation energy is 50-4000KeV.

[0062] Step six, remove the ion implantation protection layer 202 and the hard mask layer 502 to form a structure as shown in Figure 9 , in which a gate dielectric layer 104 is formed in the gate trench; and a gate polysilicon layer 105 is formed to fill the remaining gate trench to form a structure as shown in Figure 10 .

[0063] In some embodiments, the sacrificial oxide layer and the hard mask layer 502 are removed in the same wet etching in step six, which can further save manufacturing costs.

[0064] In some embodiments, the material of the gate dielectric layer 104 in step six is silicon dioxide.

[0065] In some embodiments, the formation method of the gate dielectric layer 104 in step six includes: forming a first gate silicon oxide layer by low-temperature thermal oxidation; depositing a TEOS silicon oxide layer as a second gate oxide layer, and then performing rapid annealing to densify the TEOS silicon oxide layer.

[0066] In some embodiments, the low-temperature thermal oxidation in step six has a temperature of 800-930 degrees Celsius and a processing time of less than 30 minutes, which can reduce the thermal process introduced by thermal growth to cause lateral diffusion of the pillar region 103.

[0067] In some embodiments, the thickness of the first gate silicon oxide layer in step six is 100-400 angstroms.

[0068] Step seven, form a source heavy doped region 108 above the body region 106 on both sides of the gate trench, form an insulating dielectric layer 110 on the gate polysilicon layer 105, form a contact hole 109 on the source heavy doped region, and perform heavy doped implantation on the body region 106 below the contact hole, and form a heavy doped region 107 by thermal diffusion, and activate the impurity implantation of the heavy doped implantation to form a structure as shown in Figure 11 .

[0069] In some embodiments, the contact hole in step seven is formed by photolithography and etching.

[0070] In some embodiments, after the contact hole 109 is formed by photolithography and etching in step seven, the remaining photoresist is used for the implantation of the source heavily doped region 108.

[0071] In step eight, a conductive metal is formed to fill the contact hole, and then a metal layer 111 is formed on the source and body regions, and a metal layer 112 is formed on the drain region, to form a structure as shown in Figure 12 .

[0072] It should be noted that the diagrams provided in the embodiments only schematically illustrate the basic concepts of the present application, and thus only the components related to the present application are shown in the diagrams, rather than the number, shape and size of the components when actually implemented. The shapes, number and proportions of the components when actually implemented can be arbitrarily changed, and the layout of the components can be more complicated.

[0073] In summary, the present application can avoid the body region and the pillar region being connected together in the channel region when implanting the pillar region. Therefore, the present application effectively overcomes the disadvantages of the prior art and has a high industrial utilization value.

[0074] The above embodiments only illustratively explain the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical thought of the present application should be covered by the claims of the present application.

Claims

1. A method of fabricating a low voltage super junction MOSFET, characterized by, At least comprising: Step one, epitaxially forming a first conductive type epitaxial layer on a first conductive type substrate; Step two, forming a second conductive type bulk region on the surface of the epitaxial layer by ion implantation, and then performing thermal diffusion to advance the bulk region; Step three, forming a hard mask layer and a photoresist layer on the bulk region, opening the photoresist layer to define the formation position of the gate trench, and then forming an opening on the hard mask layer to the epitaxial layer by anisotropic etching, etching the epitaxial layer at the bottom of the opening to form a first gate trench with the hard mask layer as a mask, the first gate trench extending downward through the bulk region from the upper surface of the epitaxial layer; Step four, etching the epitaxial layer in the vertical direction of the extension direction of the first gate trench to form a second gate trench, so that the second gate trench is recessed into the hard mask layer; Step five, forming an ion implantation protection layer on the surface of the gate trench, using the hard mask layer as an ion implantation mask, and using the ion implantation protection layer as an ion implantation shielding layer, forming a second conductive type columnar region at the bottom of the gate trench by self-aligned implantation, wherein the columnar region does not form contact with the bulk region; Step six, removing the ion implantation protection layer and the hard mask layer, forming a gate dielectric layer in the gate trench, and forming a gate polysilicon layer to fill the remaining gate trench; Step seven, forming a source heavily doped region above the bulk region on both sides of the gate trench, forming an insulating dielectric layer on the gate polysilicon layer, forming a contact hole on the source heavily doped region, and performing a heavily doped implantation on the bulk region below the contact hole, and then performing thermal diffusion to form a heavily doped region, and activating the impurity implantation of the heavily doped implantation; Step eight, forming a conductive metal to fill the contact hole, and then forming a source, bulk region, and drain metal layer.

2. The method of manufacturing a low voltage super junction MOSFET of claim 1, wherein: The first conductive type in step one is N-type, and the second conductive type is P-type.

3. The method of manufacturing a low voltage super junction MOSFET of claim 1, wherein: The first conductive type in step one is P-type, and the second conductive type is N-type.

4. The method of manufacturing a low voltage super junction MOSFET of claim 1, wherein: The doping concentration of the epitaxial layer in step one is 5e15-1e17 cm^-3.

5. The method of manufacturing a low voltage super junction MOSFET of claim 1, wherein: The material of the hard mask layer in step three is silicon dioxide.

6. The method of manufacturing a low voltage super junction MOSFET of claim 1, wherein: The second gate trench in step four is recessed into the hard mask layer by 300-700 angstroms.

7. The method of manufacturing a low voltage super junction MOSFET of claim 1, wherein: In step five, a sacrificial oxide layer is formed by thermal oxidation while the hard mask layer is retained, defects formed by etching the gate trench are repaired by thermal oxidation, and the sacrificial oxide layer serves as an ion implantation protection layer.

8. The method of manufacturing a low voltage super junction MOSFET of claim 3, wherein: In step five, boron ions are used for ion implantation to form a P-type columnar region at the bottom of the gate trench.

9. The method of manufacturing a low voltage super junction MOSFET of claim 8, wherein: The columnar region in step five is formed by multiple ion implantations.

10. The method of manufacturing a low voltage super junction MOSFET of claim 9, wherein: The implantation dose of the boron ions in step five is 1e12-1e13 cm^-2, and the implantation energy is 50-4000 KeV.

11. The method of manufacturing a low voltage super junction MOSFET of claim 7, wherein: In step six, the sacrificial oxide layer and the hard mask layer are removed in the same wet etching process.

12. The method of manufacturing a low voltage super junction MOSFET of claim 1, wherein: The material of the gate dielectric layer in step six is silicon dioxide.

13. The method of manufacturing a low voltage super junction MOSFET of claim 12, wherein: The method for forming the gate dielectric layer in step six includes: forming a first gate oxide silicon layer by low temperature thermal oxidation; depositing a TEOS silicon oxide layer as a second gate oxide layer, and then performing rapid annealing to densify the TEOS silicon oxide layer.

14. The method of manufacturing a low voltage super junction MOSFET of claim 13, wherein: The temperature of the low temperature thermal oxidation in step six is 800-930 degrees Celsius, and the processing time is less than 30 minutes.

15. The method of manufacturing a low voltage super junction MOSFET of claim 13, wherein: The thickness of the first gate oxide silicon layer in step six is 100-400 angstroms.

16. The method of manufacturing a low voltage super junction MOSFET of claim 1, wherein: The contact hole in step seven is formed by photolithography and etching.

17. The method of manufacturing a low voltage super junction MOSFET of claim 16, wherein: The photoresist remaining after forming the contact hole in step seven by photolithography and etching is used for implantation with photoresist, to form the source end heavily doped region.

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