Afe chip with synchronous voltage sampling function and battery management system

Abstract

The application provides an AFE chip with a synchronous voltage sampling function and a battery management system, n AFE chips are connected in one-to-one correspondence with n battery units, and the first to the n AFE chips are in a cascaded daisy chain structure; wherein the ith AFE chip calculates the ith delay time tdi based on the time instant tit when the first broadcast command information is sent and the time instant tir when the response information is received, and also based on the first time T1; wherein 1≤i<n; the first time T1 represents the time difference between the time instant tn' when the n AFE chip receives the first broadcast command information and the time instant tnt when the response information is sent; the ith AFE chip executes the second broadcast command information after delaying the ith delay time tdi at the time instant when the second broadcast command information is received, and the n AFE chip executes the second broadcast command information starting from the time instant when the second broadcast command information is received; the second broadcast command information is a voltage sampling command, so as to realize the basic synchronization of the voltage sampling time instants of the n AFE chips.

Description

Technical Field

[0001] The present invention relates to the field of battery voltage management, and in particular to an AFE chip with a synchronous voltage sampling function and a battery management system. Background Art

[0002] In the field of battery management, such as Figure 1 As shown in the figure, the battery management system generally includes n AFE (Analog Front End) chips and n battery cells, where n is a natural number greater than 1, wherein the n AFE chips are connected one-to-one with the n battery cells to realize the monitoring of the corresponding battery cells. The n battery cells form a high-voltage battery pack with a positive terminal pack+ and a negative terminal pack-, which are used to power the back-end load. Among them, the first to the nth AFE chips are in the form of a cascaded daisy chain structure, and two adjacent AFE chips can communicate bidirectionally; but because it is serial communication, the time when each AFE chip receives the command information will be different. The AFE chip closer to the top of the daisy chain ( Figure 1 In the example, the later the n AFE chips are connected (with AFEn at the top of the daisy chain), the later they receive the command information. If the command information is a voltage sampling command, different AFE chips receive the command information at different times, which causes these n AFE chips to sample the voltage at different times. This inconsistent voltage sampling time leads to inaccurate parameters such as battery capacity calculated based on the sampled data, which in turn affects the health and life of the battery. Therefore, it is necessary to improve the problems existing in the existing technology. Summary of the Invention

[0003] In order to solve the above technical problems, the present invention provides an AFE chip and a battery management system with a synchronous voltage sampling function.

[0004] According to a first aspect of the present invention, an AFE chip with a synchronous voltage sampling function is provided, which is applied to a battery management system. The battery management system includes n battery cells, n AFE chips, and a main controller, where n is a natural number greater than 1. The n AFE chips are connected to the n battery cells in a one-to-one correspondence, and the first to nth AFE chips form a cascaded daisy chain structure. After receiving a first broadcast command message from the main controller, the first AFE chip sequentially sends the first broadcast command message to the second to nth AFE chips via cascade communication. Response messages from the nth to first AFE chips are sent to the main controller via cascade communication. The battery management system is characterized in that:

[0005] The i-th AFE chip comprises a transmission delay calculation module i, which calculates the i-th delay time tdi based on the time tit at which the i-th AFE chip sends the first broadcast command information and the time tir at which the i-th AFE chip receives the response information, and based on the first time T1; wherein 1≤i<n; the first time T1 represents the time difference between the time tnt at which the n-th AFE chip receives the first broadcast command information and the time at which the n-th AFE chip sends the response information thereof.

[0006] The i-th AFE chip further comprises a delay module i, which delays the i-th delay time tdi after the i-th AFE chip receives the second broadcast command information at a time, and the n-th AFE chip starts to execute the second broadcast command information at the time of receiving the second broadcast command information; the second broadcast command information is a voltage sampling command, so as to realize the basic synchronization of the voltage sampling time of the first to n-th AFE chips.

[0007] Optionally, the i-th delay time tdi=(T2-T1) / 2, wherein T2 is the time difference between the time tir and the time tit.

[0008] Optionally, the i-th AFE chip further comprises a register i, and the first time T1 is a preset time stored in the register i.

[0009] Optionally, after the i-th delay time tdi is obtained, the i-th delay time tdi is stored in the register i.

[0010] At the time at which the i-th AFE chip receives the second broadcast command information, the i-th delay time tdi is extracted from the register i and applied to the delay module i to determine the delay time of the delay module i.

[0011] Optionally, each AFE chip is internally provided with a number of analog-to-digital converters equal to the number of battery cells contained in the corresponding AFE chip, and each analog-to-digital converter is arranged corresponding to one battery cell, so as to realize the synchronous detection of the corresponding battery cell voltage.

[0012] The present invention also provides a battery management system, comprising n battery cells, n AFE chips, and a main controller, where n is a natural number greater than 1; the n AFE chips are connected one-to-one with the n battery cells, and the first to nth AFE chips form a cascaded daisy chain structure; after the first AFE chip receives a first broadcast command message from the main controller, it sequentially sends the first broadcast command message to the second to nth AFE chips via cascade communication; and the response message from the nth to the first AFE chip is sent to the main controller via cascade communication; the battery management system is characterized in that:

[0013] The i-th AFE chip further includes a delay module i, wherein the i-th AFE chip, upon receiving the second broadcast command information, delays for an i-th delay time tdi, and begins executing the second broadcast command information upon receiving the second broadcast command information by the n-th AFE chip. Wherein, 1≤i<n, and the second broadcast command information is a voltage sampling command, so as to achieve basic synchronization of voltage sampling times of the first to n-th AFE chips.

[0014] The i-th delay time tdi is generated based on the first broadcast command information.

[0015] Optionally, the i-th AFE chip includes a transmission delay calculation module i, which calculates the i-th delay time tdi based on the moment tit when the i-th AFE chip sends the first broadcast command information and the moment tir when the response information is received, and also based on the first time T1; wherein 1≤i<n; the first time T1 represents the time difference between the moment when the n-th AFE chip receives the first broadcast command information and the moment tnt when it sends its response information.

[0016] Optionally, the i-th delay time tdi=(T2-T1) / 2, wherein T2 is the time difference between the moment tir and the moment tit.

[0017] Optionally, the i-th AFE chip further includes a register i, and the first time T1 is a preset time and is stored in the register i.

[0018] Optionally, each AFE chip is internally provided with analog-to-digital converters whose number is equal to the number of cells contained in the battery unit corresponding to the AFE chip, and each analog-to-digital converter is provided corresponding to one cell to realize synchronous detection of the corresponding cell voltage.

[0019] The beneficial effects of the present invention include at least:

[0020] The present invention provides an AFE chip and a battery management system with a synchronous voltage sampling function. The battery management system includes n battery cells, n AFE chips, and a main controller, where n is a natural number greater than 1; the n AFE chips are connected to the n battery cells in a one-to-one correspondence, and the first to nth AFE chips are cascaded in a daisy chain structure; after the first AFE chip receives a first broadcast command message from the main controller, it sends the first broadcast command message to the second to nth AFE chips in sequence through cascade communication; the response message from the nth to the first AFE chip is sent to the main controller after cascade communication; wherein the i-th AFE chip is based on the time tit when it sends the first broadcast command message and the time tir when it receives the response message, and also based on the first time T1 Calculate the i-th delay time tdi; where 1≤i<n; the first time T1 represents the time difference between the moment when the n-th AFE chip receives the first broadcast command information and the moment tnt when it sends its response information; when the main controller sends the second broadcast command, the i-th AFE chip starts to execute the second broadcast command information after the i-th delay time tdi is delayed upon receiving the second broadcast command information, and the n-th AFE chip starts to execute the second broadcast command information upon receiving the second broadcast command information; the second broadcast command information is a voltage sampling command to achieve basic synchronization of the voltage sampling moments of the first to n-th AFE chips; through the synchronous voltage sampling, the accuracy of the battery parameters calculated based on the sampled data can be improved to avoid affecting the battery life or health status.

[0021] Furthermore, the i-th delay time tdi = (T2 - T1) / 2, where T2 is the time difference between time tir and time tit. The first time T1 can be set to a preset time to reduce the design difficulty of directly calculating the difference between the time when the n-th AFE chip sends the response information and the time when the n-th AFE chip receives the first broadcast command information.

[0022] Furthermore, each AFE chip is internally provided with analog-to-digital converters whose number is equal to the number of battery cells contained in the battery unit corresponding to the AFE chip. Each analog-to-digital converter is provided corresponding to a battery cell, and is used to realize synchronous detection of the corresponding battery cell voltage, thereby improving the accuracy of voltage sampling.

[0023] It should be noted that the foregoing general description and the following detailed description are merely exemplary and explanatory and are not restrictive of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A schematic diagram of a battery management system in the prior art is shown;

[0025] Figure 2A schematic diagram of a battery management system provided by the present application is shown;

[0026] Figure 3 A working schematic diagram of the present application for voltage sampling time synchronization is shown;

[0027] Figure 4 A schematic diagram of the internal structure of the AFE1 chip provided by the present application based on the principle in Figure 2

[0028] Figure 5 A schematic diagram of the battery management system provided by the present application based on the principle in Figure 2

[0029] Figure 6 A schematic diagram of the internal structure of the i-th AFE chip provided by the present application is shown. DETAILED DESCRIPTION

[0030] In order to facilitate the understanding of the present application, the present application will be described in more detail below with reference to the relevant drawings. The preferred embodiments of the present application are shown in the drawings. However, the present application can be realized in different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0031] The principle of the present application for realizing synchronous voltage sampling will be described below based on the structure in Figure 1 Figure 1 As shown in the figure, the battery management system further includes a main controller, which here includes an MCU and an AFE0 chip, the AFE0 chip is used to transmit the command information issued by the MCU to the n AFE chips cascaded behind, and transmit the response information of the n AFE chips to the MCU. Whether to set the AFE0 can be set according to the actual situation. After the first AFE chip receives the first broadcast command information from the main controller, the first broadcast command information is sent to the second to the n-th AFE chip in turn through cascaded communication; then, the response information of the n-th to the first AFE chip is sent to the main controller after cascaded communication.

[0032] Figure 2 A schematic diagram of the battery management system provided by the present application with synchronous voltage sampling function is shown, here taking the battery management system including four AFE chips as an example for description, that is, Figure 1 n in the present application is 4; Figure 2 ​​​In the figure, t1t represents the time when the chip AFE1 sends the first broadcast command information, t1r represents the time when the chip AFE4 receives the response information of the chip AFE1; similarly, t2t represents the time when the chip AFE2 sends the first broadcast command information, t2r represents the time when the chip AFE4 receives the response information of the chip AFE2; t3t represents the time when the chip AFE3 sends the first broadcast command information, t3r represents the time when the chip AFE4 receives the response information of the chip AFE3; t4t represents the time when the chip AFE4 sends the response information after receiving the first broadcast command information. Wherein, the chip AFE1 calculates the first delay time td1 based on the time t1t, t1r and the first time T1; the chip AFE2 calculates the second delay time td2 based on the time t2t, t2r and the first time T1; the chip AFE3 calculates the third delay time td3 based on the time t3t, t3r and the first time T1; wherein the first time T1 represents the time difference between t4t and the time when the chip AFE4 receives the first broadcast command information (for example, t4' represents the time).

[0033] Further, Figure 3 The figure shows a working schematic diagram of the voltage sampling time synchronization provided by the application, in which Figures 2-3 In the figure, t1, t2, t3 and t4 respectively represent the time when the chips AFE1 to AFE4 receive the second broadcast command information; the chip AFE1 starts to execute the second broadcast command information after a first delay time td1 after receiving the second broadcast command information at t1; similarly, the chip AFE2 starts to execute the second broadcast command information after a second delay time td2 after receiving the second broadcast command information at t2; the chip AFE3 starts to execute the second broadcast command information after a third delay time td3 after receiving the second broadcast command information at t3; the chip AFE4 starts to execute the second broadcast command information after receiving the second broadcast command information at t4; wherein the second broadcast command information is a voltage sampling command, and the first broadcast command information is a command different from the voltage sampling. Through the above setting, t1+td1=t2+td2=t3+td3=t4 can be realized, that is, the voltage sampling times of the chips AFE1 to AFE4 are basically consistent, thereby ensuring the accuracy of the battery parameters calculated according to the sampled data, and avoiding affecting the life or health state of the battery.

[0034] Further, Figure 4 The figure shows a schematic diagram of the internal structure of the AFE1 chip provided by the application, and the internal structures of AFE2 to AFE3 are the same as AFE1. Here, AFE1 is taken as an example for description, based on which Figure 4To further illustrate the principle of generating the first delay time td1, the first time T1 can be a preset time, or the time difference between the time t4t at which the chip AFE4 sends the response information and the time t4' at which it receives the first broadcast command information. Hereinafter, the first time T1 is taken as a preset time as an example, and the chip AFE1 is internally provided with a register 1, and the preset time is stored in the register 1; the chip AFE1 is also internally provided with a transmission delay calculation module 1, a clock module 1 and a delay module 1, the transmission delay calculation module 1 receives the time t1t at which the chip AFE1 sends the first broadcast command information and the time t1r at which it receives the response information of the chip AFE4; and extracts the first time T1 (the preset time, which can be set according to actual application, for example, it can be set to a time length close to equal to the time difference between the time t4t at which the chip AFE4 sends the response information and the time t4' at which it receives the first broadcast command information) from the register 1, the transmission delay calculation module 1 calculates the first delay time td1 based on t1r, t1t and the first time T1, specifically, td1 = (T2-T1) / 2, wherein T2 is the time difference between the time t1r and the time t1t; because the chip AFE4 needs a certain time to process after receiving the first broadcast command information before sending its response information, the processing time is included in the time period between t1r and t1t, and the processing time (the first time T1) needs to be considered when calculating the first delay time td1. The clock module 1 is used to generate a clock signal, and based on the clock signal, the corresponding time can be calculated, for example, for the time difference between t1r and t1t, the number of clock signal pulses passed can be used to calculate, and the corresponding time can be calculated by multiplying the clock signal period length and the number of pulses; other time calculations can also be calculated in this way. After the transmission delay calculation module 1 calculates the first delay time td1, it can be stored in the register 1, and after receiving the second broadcast command information at the time t1, that is, receiving the voltage sampling command, the first delay time td1 is extracted from the register 1, and the delay module 1 starts to execute the voltage sampling command after delaying the first delay time td1 at the time t1. It should be noted that, Figure 4 Only one embodiment is shown, and corresponding modifications can be made to achieve the same function.

[0035] Further, Figure 5 The battery management system with the function of synchronous voltage sampling is shown, and the specific working principle is the same as Figure 2 Here, it will not be described in detail.

[0036] Further, in order to increase the accuracy of voltage sampling, Figure 6A schematic diagram of the inside of the chip AFEj is shown, where 1≤j≤n; for example, the battery unit j includes m battery cells cell1, cell2,..., cellm-1, cellm; where the value of m can be set according to the actual application scenario, and m analog-to-digital converters ADC1, ADC2,..., ADCm-1, ADCm are correspondingly arranged inside the AFEj; the m analog-to-digital converters are arranged one-to-one with the m battery cells, for detecting the voltage of the corresponding battery cell. By arranging the analog-to-digital converter one-to-one with the battery cell, the present application can realize synchronous sampling of the m battery cells, and compared with the prior art in which multiple battery cells share one analog-to-digital converter ADC, the present application can realize sampling of the battery cell voltage at the same time, thereby improving the accuracy of voltage sampling.

[0037] In summary, the AFE chip with synchronous voltage sampling function and the battery management system provided by the present application include n battery units, n AFE chips and a main controller, where n is a natural number greater than 1; the n AFE chips are connected one-to-one with the n battery units, the first to the n-th AFE chips are in a cascaded daisy chain structure, and adjacent two AFE chips can communicate bidirectionally; after the first AFE chip receives the first broadcast command information from the main controller, the first broadcast command information is sequentially sent to the second to the n-th AFE chips through cascaded communication; the response information of the n-th to the first AFE chips is sent to the main controller after cascaded communication; wherein the i-th AFE chip is based on the time tit when the first broadcast command information is sent and the time tir when the response information is received, and also based on the first time T1 to calculate the i-th delay time tdi; where 1≤i<n; the first time represents the time difference between the time when the n-th AFE chip receives the first broadcast command information and the time tnt when the response information is sent; when the main controller sends the second broadcast command, the i-th AFE chip delays for the i-th delay time tdi after receiving the second broadcast command information at the time, and the n-th AFE chip starts to execute the second broadcast command information at the time of receiving the second broadcast command information; the second broadcast command information is a voltage sampling command, so as to realize the basic synchronization of the voltage sampling time of the first to the n-th AFE chips; through synchronous sampling of the voltage, the accuracy of the battery parameters calculated based on the sampled data can be improved, and the impact on the life or health status of the battery can be avoided.

[0038] Further, the i-th delay time tdi=(T2-T1) / 2, where T2 is the time difference between the time tir and the time tit, and the first time T1 can be set as a preset time, for reducing the design difficulty of directly calculating the difference between the time when the n-th AFE chip sends the response information and the time when the n-th AFE chip receives the first broadcast command information.

[0039] Further, each AFE chip is internally provided with a number of analog-to-digital converters equal to the number of battery cells contained in the AFE chip, each analog-to-digital converter corresponding to one battery cell setting, for realizing synchronous detection of the corresponding battery cell voltage and improving the accuracy of voltage sampling.

[0040] Finally, it should be noted that: obviously, the above embodiments are only examples for clearly illustrating the present application, and are not limitations on the embodiments. For ordinary skilled persons in the art, other different forms of changes or variations can be made on the basis of the above description. Here, it is not necessary and impossible to exhaust all the embodiments. The obvious changes or variations derived therefrom are still within the protection scope of the present application.

Claims

1. An AFE chip with a synchronous voltage sampling function, applied to a battery management system, the battery management system comprising n battery units, n AFE chips and a main controller, n being a natural number greater than 1; the n AFE chips are connected in one-to-one correspondence with the n battery units, the first to the n-th AFE chips being in a cascaded daisy chain structure; after the first AFE chip receives a first broadcast command information from the main controller, the first broadcast command information is sent to the second to the n-th AFE chips in turn through cascaded communication; the response information of the n-th to the first AFE chips is sent to the main controller after cascaded communication; characterized in that: the i-th AFE chip comprises a transmission delay calculation module i, which is based on the time tit at which the i-th AFE chip sends the first broadcast command information and the time tir at which the response information is received, and also based on a first time T1 to calculate an i-th delay time tdi; wherein 1≤i<n; the first time T1 represents the time difference between the time tnt at which the n-th AFE chip receives the first broadcast command information and the time at which the response information is sent; the i-th AFE chip further comprises a delay module i, after the i-th AFE chip receives a second broadcast command information at a time, the i-th delay time tdi is delayed through the delay module i, and the n-th AFE chip starts to execute the second broadcast command information at the time of receiving the second broadcast command information; the second broadcast command information is a voltage sampling command, so as to realize the basic synchronization of the voltage sampling time of the first to the n-th AFE chips. The i-th delay time tdi=(T2-T1) / 2, wherein T2 is the time difference between tir and tit.

2. The AFE chip of claim 1, wherein:

3. The AFE chip of claim 2, characterized in that: the i-th AFE chip further comprises a register i, and the first time T1 is a preset time stored in the register i. After obtaining the i-th delay time tdi, it is stored in the register i; 4. The AFE chip of claim 3, wherein: At the time when the i-th AFE chip receives the second broadcast command information, the i-th delay time tdi is extracted from the register i to act on the delay module i to determine the delay time of the delay module i. Each AFE chip is internally provided with a number of analog-to-digital converters equal to the number of battery cells contained in the corresponding battery unit, and each analog-to-digital converter is arranged corresponding to one battery cell, for realizing synchronous detection of the corresponding battery cell voltage.

5. The AFE chip of claim 1, wherein: ​ 6. A battery management system comprising n battery units, n AFE chips and a main controller, n being a natural number greater than 1; the n AFE chips are connected one by one with the n battery units, the first to the n-th AFE chips are in a cascaded daisy chain structure; after the first AFE chip receives a first broadcast command information from the main controller, the first broadcast command information is sent to the second to the n-th AFE chips in turn through cascaded communication; the response information of the n-th to the first AFE chips is sent to the main controller after cascaded communication; characterized in that: The i-th AFE chip further comprises a delay module i, the i-th AFE chip delays for i-th delay time tdi after receiving the second broadcast command information at the moment, and executes the second broadcast command information starting from the moment when the n-th AFE chip receives the second broadcast command information; wherein 1≤i<n, the second broadcast command information is a voltage sampling command, so as to realize the basic synchronization of the voltage sampling time of the first to the n-th AFE chips; Wherein, the i-th delay time tdi is generated based on the first broadcast command information.

7. The battery management system of claim 6, wherein: The i-th AFE chip comprises a transmission delay calculation module i, which calculates the i-th delay time tdi based on the moment tit when the i-th AFE chip sends the first broadcast command information and the moment tir when the response information is received, and also based on the first time T1; wherein the first time T1 represents the time difference between the moment when the n-th AFE chip receives the first broadcast command information and the moment tnt when the response information is sent.

8. The battery management system of claim 7, wherein: The i-th delay time tdi=(T2-T1) / 2, wherein T2 is the time difference between the moment tir and the moment tit.

9. The battery management system of claim 8, wherein: The i-th AFE chip further comprises a register i, and the first time T1 is a preset time stored in the register i.

10. The battery management system of claim 6, wherein: Each AFE chip is internally provided with a number of analog-to-digital converters equal to the number of battery cells contained in the corresponding AFE chip, each analog-to-digital converter corresponding to a battery cell setting for realizing synchronous detection of the corresponding battery cell voltage.

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