A motor active short circuit control method, device, system, vehicle and motor

Abstract

The present application provides a method, device, system, vehicle and motor for active short-circuit control of a motor. The method includes obtaining a bus overvoltage signal, a power chip signal and a main control chip signal, wherein the power chip signal includes a first detection signal and a second detection signal, and performing fault detection based on the bus overvoltage signal and the power chip signal. If the detection result is that a fault exists, a first fault signal is obtained based on the first detection signal and the bus overvoltage signal, and an enable control signal is obtained based on the main control chip signal and the first fault signal. Based on the enable control signal, the drive unit of the motor enters an open circuit protection mode, and a second fault signal is output according to the second detection signal and the bus overvoltage signal. An upper bridge control signal and a lower bridge control signal are obtained based on the main control chip signal and the second fault signal to control the opening or closing of the upper bridge switch device and the lower bridge switch device in the drive unit. The method solves the technical problem of directly shutting down the IGBT causing damage to the vehicle.

Description

Technical Field

[0001] The present application relates to the field of vehicle motor control technology, and in particular to a motor active short-circuit control method, device, system, vehicle and motor. Background Art

[0002] As electrification and intelligence become the mainstream direction of automobile research and development, the requirements for active vehicle safety are getting higher and higher. As the core component of electric vehicles, the motor controller is directly related to the power output safety of the vehicle, so it is necessary to carry out corresponding functional safety development of the automotive electronic control system. According to the vehicle safety goals, when a serious fault occurs in the motor controller, the motor power output is shut down to reduce its torque to zero. This can be achieved by shutting down the three-phase insulated gate bipolar transistor (IGBT).

[0003] However, if the IGBT is turned off directly while the car is driving, the higher speed of the motor will generate a larger braking torque. At the same time, the reverse electromotive force generated will cause current backflow through the freewheeling diode, which may endanger driving safety and components such as the vehicle power module, bus capacitor and battery.

[0004] Patent document CN111959278B describes a control system and method for actively shutting down the lower bridge arm of a motor controller. This method controls the lower bridge arm for active short-circuit protection to ensure that the active short-circuit function can be performed when the low-voltage side of the circuit loses power. Although this method can ensure the timeliness of active short-circuit in the event of a fault, there is a hidden danger of current backflow, which can damage vehicle components. Patent document CN218771277U describes a motor active short-circuit protection circuit. This patent describes a method for controlling the upper or lower bridge of a power device drive circuit to enter an active short-circuit mode through a power diagnostic circuit to avoid the technical problem of direct connection between the upper and lower bridges. However, the technical problem of current backflow is still not solved. Directly shutting down the IGBT will damage the vehicle components, thereby reducing the service life of the vehicle. Summary of the invention

[0005] In view of the shortcomings of the related technologies mentioned above, the present application provides a method, device, system, vehicle and motor for active short-circuit control of a motor to solve the technical problem that turning off the IGBT will cause damage to vehicle components.

[0006] The present application provides a method for active short-circuit control of a motor, the method comprising: obtaining a bus overvoltage signal, a power chip signal and a main control chip signal, the power chip signal comprising a first detection signal and a second detection signal, the first detection signal and the second detection signal having the same level type, and the second detection signal being obtained after the first detection signal; performing fault detection based on the bus overvoltage signal and the power chip signal, and if the detection result is that a fault exists, obtaining a first fault signal based on the first detection signal and the bus overvoltage signal; obtaining an enable control signal based on the main control chip signal and the first fault signal, and controlling a drive unit of the motor to enter an open circuit protection mode based on the enable control signal; outputting a second fault signal according to the second detection signal and the bus overvoltage signal, and obtaining an upper bridge control signal and a lower bridge control signal based on the main control chip signal and the second fault signal, so as to control the opening or closing of an upper bridge switch device and a lower bridge switch device in the drive unit, and the drive unit enters an active short-circuit mode.

[0007] In one embodiment of the present application, fault detection is performed based on the bus overvoltage signal and the power chip signal, including: if the bus overvoltage signal is at a high level, the bus overvoltage signal is abnormal; if the power chip signal is at a low level, the power chip signal is abnormal; if one of the bus overvoltage signal and the power chip signal is abnormal or both the bus overvoltage signal and the power chip signal are abnormal, the detection result is that a fault exists; if the detection result is that a fault exists, a first fault signal is obtained based on the first detection signal and the bus overvoltage signal, and a second fault signal is obtained based on the second detection signal and the bus overvoltage signal.

[0008] In one embodiment of the present application, the main control chip signal includes a driver chip enable signal, an upper bridge main control signal and a lower bridge main control signal. An enable control signal is obtained based on the main control chip signal and the first fault signal. Controlling the drive unit of the motor to enter an open circuit protection mode based on the enable control signal includes: inputting the driver chip enable signal and the first fault signal into a first AND gate circuit, and using the output result of the first AND gate circuit as the enable control signal, the first fault signal is a low level, and the enable control signal is a low level; controlling the drive unit based on the enable control signal so that the drive unit does not respond to a pulse width modulation control mode, and all upper bridge switch devices and all lower bridge switch devices in the drive unit are all turned off.

[0009] In one embodiment of the present application, the main control chip signal includes a driving chip enable signal, an upper bridge main control signal and a lower bridge main control signal. A second fault signal is output according to the second detection signal and the bus overvoltage signal. The lower bridge control signal is obtained based on the main control chip signal and the second fault signal, including: if the second detection signal is at a low level or the bus overvoltage signal is at a high level, at least one of the following is satisfied, then the second fault signal is output, and the second fault signal is at a low level; the lower bridge main control signal and the second fault signal are input into a NAND gate circuit, and the lower bridge control signal is obtained based on the output result of the NAND gate circuit, so as to control all lower bridge switch devices in the driving unit to be fully turned on based on the lower bridge control signal.

[0010] In one embodiment of the present application, the main control chip signal includes a driving chip enable signal, an upper bridge main control signal and a lower bridge main control signal, and a second fault signal is output according to the second detection signal and the bus overvoltage signal. The upper bridge control signal is obtained based on the main control chip signal and the second fault signal, including: if the second detection signal is a low level or the bus overvoltage signal is a high level, at least one of the following is satisfied, then the second fault signal is output, and the second fault signal is a low level; the upper bridge main control signal and the second fault signal are input into a second AND gate circuit, and the upper bridge control signal is obtained based on the output result of the second AND gate circuit, so as to control all upper bridge devices in the driving unit to be completely turned off based on the upper bridge control signal.

[0011] In one embodiment of the present application, after the upper bridge main control signal and the second fault signal are input into the second AND gate circuit, it also includes: inputting the output result of the second AND gate circuit and the lower bridge main control signal into a third AND gate circuit, and obtaining the upper bridge control signal based on the output result of the third AND gate circuit, so as to control all the upper bridge devices in the driving unit to be completely turned off based on the upper bridge control signal.

[0012] An embodiment of the present application also provides a motor active short-circuit control system, which includes a bus voltage acquisition unit, a bus voltage overvoltage detection unit, a drive unit, a main control unit, a power management unit and a short-circuit control circuit unit; the bus voltage acquisition unit is used to acquire the bus voltage; the bus voltage overvoltage detection unit is used to obtain a bus overvoltage signal based on the bus voltage, and if the bus voltage is overvoltage, the bus overvoltage signal is a high level; the drive unit is used to drive the gate voltage of the upper bridge switch device and the lower bridge switch device to control the opening or closing of the upper bridge switch device and the lower bridge switch device; the main control unit is used to send a main control chip signal to the short-circuit control circuit unit, and the main control chip signal includes a drive chip enable signal, an upper bridge main control signal and a lower bridge main control signal. signal; the power management unit is used to detect the power supply and send a power chip signal to the short-circuit control circuit unit. If the power supply fails, the power chip signal is at a low level. The power chip signal includes a first detection signal and a second detection signal. The first detection signal and the second detection signal have the same level type, and the second detection signal is sent after the first detection signal; the short-circuit control circuit unit is used to obtain an enable control signal, an upper bridge control signal and a lower bridge control signal based on the main control chip signal, the power chip signal and the bus overvoltage signal, and send the enable control signal, the upper bridge control signal and the lower bridge control signal to the drive unit so that the drive unit controls the opening or closing of the upper bridge switch device and the lower bridge switch device.

[0013] In one embodiment of the present application, the short-circuit control circuit unit also includes a fault judgment circuit, a NAND gate circuit, a first AND gate circuit, a second AND gate circuit and a third AND gate circuit; the input of the fault judgment circuit is the power chip signal and the bus overvoltage signal, and when the power chip signal is at a low level or the bus overvoltage signal is at a high level, a low level is output, and when the power chip signal is at a high level and the bus overvoltage signal is at a low level, a high level is output, and the output result is output as a fault signal, and the fault signal includes a first fault signal and a second fault signal; the input of the first AND gate circuit is the first fault signal and the driver chip enable signal, and the output of the first AND gate circuit is an enable control signal, and the enable control signal is used to control the The drive unit is configured to prevent the drive unit from responding to the pulse width modulation control mode, and all upper bridge switch devices and all lower bridge switch devices in the drive unit are all turned off; the input of the NAND gate circuit is the second fault signal and the lower bridge main control signal, the output of the NAND gate circuit is the lower bridge control signal, and the lower bridge control signal is used to control the drive unit so that all lower bridge switch devices of the drive unit are turned on; the input of the second AND gate circuit is the second fault signal and the upper bridge main control signal; the input of the third AND gate circuit is the output signal of the second AND gate circuit and the lower bridge main control signal, the output of the third AND gate circuit is the upper bridge control signal, and the upper bridge control signal is used to control the drive unit so that all upper bridge switch devices of the drive unit are turned off.

[0014] In one embodiment of the present application, the short-circuit control circuit unit also includes a level conversion circuit; the level conversion circuit is used to convert the voltage of the enable control signal, the upper bridge control signal and the lower bridge control signal into a preset voltage value, and then send the converted control signal to the drive unit to control the drive unit.

[0015] The embodiment of the present application also provides an active short-circuit control device for a motor, the active short-circuit control device for a motor comprising: a signal input module, used to obtain a bus overvoltage signal, a power chip signal and a main control chip signal, the power chip signal comprising a first detection signal and a second detection signal, the first detection signal and the second detection signal having the same level type, and the second detection signal being obtained after the first detection signal; a fault detection module, used to perform fault detection based on the bus overvoltage signal and the power chip signal, and if the detection result is that a fault exists, a first fault signal is obtained based on the first detection signal and the bus overvoltage signal; an open circuit protection module, used to obtain an enable control signal based on the main control chip signal and the first fault signal, and control the drive unit of the motor to enter an open circuit protection mode based on the enable control signal; an active short circuit module, used to output a second fault signal according to the second detection signal and the bus overvoltage signal, and obtain an upper bridge control signal and a lower bridge control signal based on the main control chip signal and the second fault signal, so as to control the opening or closing of the upper bridge switch device and the lower bridge switch device in the drive unit, and the drive unit enters an active short circuit mode.

[0016] An embodiment of the present application also provides a vehicle, which is applied to the motor active short-circuit control method described in any of the above embodiments, and the vehicle includes a motor active short-circuit control device; the motor active short-circuit control device includes a signal input module, a fault detection module, an open circuit protection module and an active short-circuit module; the signal input module is used to obtain a bus overvoltage signal, a power chip signal and a main control chip signal, and the power chip signal includes a first detection signal and a second detection signal, the first detection signal and the second detection signal have the same level type, and the second detection signal is obtained after the first detection signal; the fault detection module is used to detect the bus overvoltage signal and the power chip signal based on the bus overvoltage signal and the power chip signal The first detection signal is used to detect a fault. If the detection result is that a fault exists, a first fault signal is obtained based on the first detection signal and the bus overvoltage signal; the open circuit protection module is used to obtain an enable control signal based on the main control chip signal and the first fault signal, and control the motor drive unit to enter the open circuit protection mode based on the enable control signal; the active short circuit module is used to output a second fault signal according to the second detection signal and the bus overvoltage signal, and obtain an upper bridge control signal and a lower bridge control signal based on the main control chip signal and the second fault signal to control the opening or closing of the upper bridge switch device and the lower bridge switch device in the drive unit, and the drive unit enters the active short circuit mode.

[0017] An embodiment of the present application further provides a motor, which is applied to the motor active short-circuit control method described in any one of the above embodiments.

[0018] An embodiment of the present application also provides an electronic device, comprising: one or more processors; a storage device for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the electronic device implements the motor active short-circuit control method as described in any of the above embodiments.

[0019] An embodiment of the present application further provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor of a computer, the computer is caused to execute the motor active short-circuit control method as described in any of the above embodiments.

[0020] Beneficial effects of the present application: The embodiments of the present application provide a motor active short circuit control method, device, system, vehicle and motor, the method acquires a bus overvoltage signal, a power chip signal and a main control chip signal, the power chip signal includes a first detection signal and a second detection signal, performs fault detection based on the bus overvoltage signal and the power chip signal, if the detection result is a fault, obtains a first fault signal based on the first detection signal and the bus overvoltage signal, obtains an enable control signal based on the main control chip signal and the first fault signal, controls the motor drive unit to enter an open circuit protection mode based on the enable control signal, outputs a second fault signal according to the second detection signal and the bus overvoltage signal, obtains an upper bridge control signal and a lower bridge control signal based on the main control chip signal and the second fault signal, to control the opening or closing of the upper bridge switch device and the lower bridge switch device in the drive unit, so that when a fault occurs, the drive unit first enters the open circuit protection mode based on the enable control signal, and protects the motor controller hardware from serious damage in the first time. Then, based on the upper bridge control signal and the lower bridge control signal, the switch state of the upper and lower bridge switch devices is controlled to enter the active short circuit mode to consume the electromotive force. Based on this method, the process of entering the active short-circuit mode becomes safer and more controllable. In addition, this method belongs to the controller functional safety strategy, which is highly versatile and can be applied to IGBT switching devices and various next-generation drive solutions.

[0021] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 is a schematic diagram of an active short-circuit control system for a motor shown in an exemplary embodiment of the present application;

[0023] Figure 2 is a flow chart of a motor active short-circuit control method shown in an exemplary embodiment of the present application;

[0024] Figure 3 is a schematic diagram of a short-circuit control circuit shown in an exemplary embodiment of the present application;

[0025] Figure 4 is a block diagram of a motor active short-circuit control device shown in an exemplary embodiment of the present application;

[0026] Figure 5 It is a structural schematic diagram of an electronic device shown in an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0027] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0028] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application, and thus the drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed at will, and the component layout may also be more complicated.

[0029] It should be noted that in this application, "first", "second", etc. are only used to distinguish similar objects, and are not used to limit the order or precedence of similar objects. The variations of "including", "having", etc. described above indicate that the scope covered by the subject of the word is not exclusive except for the examples shown by the word.

[0030] It is understood that the various numbers, step numbers, and other reference numerals recorded in this application are distinguished for the convenience of description and are not intended to limit the scope of this application. The size of the reference numerals in this application does not mean the order of execution. The execution order of each process should be determined by its function and internal logic.

[0031] In the following description, a large number of details are discussed to provide a more thorough explanation of the embodiments of the present application. However, it is obvious to those skilled in the art that the embodiments of the present application can be implemented without these specific details. In other embodiments, well-known structures and devices are shown in the form of block diagrams rather than in detail to avoid making the embodiments of the present application difficult to understand.

[0032] The embodiments of the present application respectively provide a motor active short-circuit control method, a motor active short-circuit control device, an electronic device, a computer-readable storage medium, and a computer program product, which will be described in detail below.

[0033] See also Figure 1 , Figure 1 It is a schematic diagram of an active short-circuit control system of a motor shown in an exemplary embodiment of the present application.

[0034] In one embodiment of the present application, the motor active short-circuit control system includes a bus voltage acquisition unit, a bus voltage overvoltage detection unit, a drive unit, a main control unit MCU, a power management unit SBC and a short-circuit control circuit unit ASC; wherein the bus voltage acquisition unit is used to collect the bus voltage of the high-voltage battery; the bus voltage sends the bus voltage AV OUT to the voltage overvoltage detection unit, and the bus voltage overvoltage detection unit is used to obtain a bus overvoltage signal VIOUT_INTB based on the bus voltage AV OUT. If the bus voltage is overvoltage, the bus overvoltage signal VIOUT_INTB is high level, and the voltage overvoltage detection unit sends the bus overvoltage signal VIOUT_INTB to the short-circuit control circuit unit ASC.

[0035] In one embodiment of the present application, the main control unit MCU sends a main control chip signal to the short-circuit control circuit unit ASC, the main control chip signal includes a driver chip enable signal MCU_FSENB, an upper bridge main control signal MCU_FSS_HS and a lower bridge main control signal MCU_FSS_LS, the power management unit SBC is used to detect the power supply and send a power chip signal to the short-circuit control circuit unit ASC, if the power supply fails, the power chip signal is low level, the power chip signal includes a first detection signal FS0B and a second detection signal FS1B, the first detection signal FS0B and the second detection signal FS1B have the same level type, the second detection signal FS1B is sent after the first detection signal FS0B, the main control unit MCU and the power management unit SBC communicate through SPI.

[0036] In one embodiment of the present application, the short-circuit control circuit unit is used to obtain the enable control signal FSENB, the upper bridge control signal FSS_HS and the lower bridge control signal FSS_LS based on the main control chip signal (the driver chip enable signal MCU_FSENB, the upper bridge main control signal MCU_FSS_HS and the lower bridge main control signal MCU_FSS_LS), the power chip signal (the first detection signal FS0B and the second detection signal FS1B) and the bus overvoltage signal VIOUT_INTB, and send the enable control signal FSENB, the upper bridge control signal FSS_HS and the lower bridge control signal FSS_LS to the driving unit so that the driving unit controls the opening or closing of the upper bridge switching device and the lower bridge switching device.

[0037] In one embodiment of the present application, the drive unit is responsible for converting the battery pack DC into a three-phase AC input to provide a motor for the vehicle to output power. The drive unit is used to drive the gate voltage of the upper bridge switch device and the lower bridge switch device to control the opening or closing of the upper bridge switch device and the lower bridge switch device. After the fault occurs, the drive unit enters the open circuit protection mode in response to the received enable control signal FSENB, turns off all the upper bridge IGBTs and all the lower bridge IGBTs, and no longer responds to the six-way PWM wave control signal MCU_PWM*6 sent by the main control unit MCU until the upper bridge control signal FSS_HS and the lower bridge control signal FSS_LS are received to turn off the upper bridge IGBT and turn on the lower bridge IGBT to control the motor to perform rotation to consume the electromotive force. When the drive unit does not fail, the PWM wave control mode is started based on the main control unit, and the IGBT gate drive signal PWM*6 is sent in response to the six-way PWM wave control signal MCU_PWM*6 sent by the MCU to control the IGBT to alternately switch and generate three-phase AC. In this embodiment, the drive unit and the main control unit MCU report faults and status to the MCU based on the INTB pin and SPI communication.

[0038] In one embodiment of the present application, the main control unit MCU generates three-phase AC power by sending six PWM waves to control the alternating switching of IGBTs, and outputs corresponding modes of FSENB, FSS_HS and FSS_LS control signals according to different request modes or faults to make the drive unit enter the active short-circuit mode.

[0039] In one embodiment of the present application, the power management unit SBC provides 5V or 3.3V power to each chip through an internal LDO. When the voltage output of the SBC fails, an alarm can be sounded by pulling down FS0B and FS1B.

[0040] In one embodiment of the present application, the bus voltage overvoltage detection unit pulls up the VIOUT_INTB signal when a fault occurs, and transmits it back to the main control unit MCU to make the main control unit MCU stop sending PWM waves.

[0041] In one embodiment of the present application, the short circuit control circuit unit ASC includes a fault judgment circuit, a NAND gate circuit, a first AND gate circuit, a second AND gate circuit, a third AND gate circuit and a level conversion circuit to control the system to safely enter the active short circuit mode, and when the fault disappears, the system exits the active short circuit mode.

[0042] See also Figure 2 , Figure 2 FIG. 1 is a flow chart of a motor active short circuit control method shown in an exemplary embodiment of the present application. Figure 2 As shown, in an exemplary embodiment, the motor active short circuit control method includes at least steps S210 to S240, which are described in detail as follows:

[0043] Step S210, obtaining a bus overvoltage signal, a power chip signal and a main control chip signal, the power chip signal includes a first detection signal and a second detection signal, the first detection signal and the second detection signal have the same level type, and the second detection signal is obtained after the first detection signal.

[0044] In one embodiment of the present application, when the overvoltage detection unit detects a bus overvoltage fault, the short-circuit control circuit unit (ASC circuit) receives a bus overvoltage signal VIOUT_INTB from the overvoltage detection module. When the bus overvoltage signal is at a high level, it indicates overvoltage. When the power management unit (SBC unit) detects that the SBC chip has a fault (such as undervoltage or self-test fault), the short-circuit control circuit unit (ASC circuit) receives a first detection signal (FS0B) and a second detection signal (FS1B) output from the power management unit. FS0B and FS1B are both When the signal status bits are all low level, it indicates a fault. In the present embodiment, there is a delay time between the two signals FS0B and FS1B. First, FS0B enters the short-circuit control circuit unit to control the drive unit to enter the open-circuit protection mode. After a short delay, FS1B enters the short-circuit control circuit unit to control the drive unit to control the opening and closing of the upper bridge switch device and the lower bridge switch device to enter the active short-circuit mode. It should be understood that the delay time described in the present embodiment can be configured by the software in the power management unit, so that the time for the system to enter the active short-circuit mode can be controlled.

[0045] Step S220, performing fault detection based on the bus overvoltage signal and the power chip signal, if the detection result is that a fault exists, obtaining a first fault signal based on the first detection signal and the bus overvoltage signal.

[0046] In one embodiment of the present application, the bus overvoltage signal and the power chip signal are used for fault detection based on the operation results in the logic gate in the short circuit control circuit unit, and the operation logic is shown in Table 1:

[0047] Table 1

[0048]

[0049] In Table 1, input A is the power chip signal (the first detection signal and the second detection signal), input B is the bus overvoltage signal, and output Y is the fault detection result, where "1" represents that the signal is at a high level, and "0" represents that the signal is at a low level. In this embodiment, when the bus is overvoltage, the bus overvoltage signal is at a high level, otherwise it is at a low level. When the power chip fails, it is at a low level, otherwise it is at a high level. When the fault detection result is that there is a fault, it is at a low level, otherwise it is at a high level. According to the logic of Table 1, when either the bus overvoltage or the power chip failure occurs, or when both occur at the same time, the output result of the logic gate is a low level.

[0050] In one embodiment of the present application, fault detection based on the bus overvoltage signal and the power chip signal includes: if the bus overvoltage signal is at a high level, the bus overvoltage signal is abnormal; if the power chip signal is at a low level, the power chip signal is abnormal; if one of the bus overvoltage signal and the power chip signal is abnormal or both the bus overvoltage signal and the power chip signal are abnormal, the detection result is that a fault exists; if the detection result is that a fault exists, a first fault signal is obtained based on the first detection signal and the bus overvoltage signal, and a second fault signal is obtained based on the second detection signal and the bus overvoltage signal.

[0051] In one embodiment of the present application, when the motor active short circuit control system is normal, when the power supply fails or the bus voltage is too high, the first fault signal and the second fault signal are both low level. However, when the power chip signal is normal and the bus voltage is not too high, the first fault signal and the second fault signal are both high level.

[0052] Step S230, obtaining an enable control signal according to the main control chip signal and the first fault signal, and controlling the drive unit of the motor to enter an open circuit protection mode based on the enable control signal.

[0053] In one embodiment of the present application, the drive unit includes three modes, namely, a pulse width modulation control mode (PWM wave control mode), an open circuit protection mode and an active short circuit mode, wherein the pulse width modulation control mode (PWM wave control mode) is a mode executed by the motor control system under normal circumstances (the power management unit does not detect an abnormality and the bus voltage is not over-voltage), and in the pulse width modulation control mode (PWM wave control mode), the drive unit responds to the PWM wave sent by the main control unit CPU to control the switch device. The open circuit protection mode is an emergency mode entered immediately based on the enable control signal sent by the short circuit control circuit unit after a fault occurs in the motor control system (the power management unit detects an abnormality and the bus voltage is over-voltage), and in the open circuit protection mode, the drive unit no longer responds to the PWM wave sent by the main control unit CPU, and all upper bridge switch devices and all lower bridge switch devices in the drive unit are completely turned off. The active short-circuit mode is a mode that consumes the excess electromotive force of the motor to ensure the safety of the motor based on the upper bridge control signal and the lower bridge control signal issued by the short-circuit control circuit unit after a short delay. In the active short-circuit mode, the drive motor controls the upper bridge switch device and the lower bridge switch device based on the upper bridge control signal and the lower bridge control signal. After the power supply or bus voltage returns to normal, the drive unit re-enters the pulse width modulation control mode (PWM wave control mode).

[0054] In one embodiment of the present application, the main control chip signal is a signal sent by the main control unit MCU, and the main control chip signal includes a driver chip enable signal MCU_FSENB, an upper bridge master control signal MCU_FSS_HS, and a lower bridge master control signal MCU_FSS_LS, wherein the first fault signal and the driver chip enable signal MCU_FSENB are operated by the logic gate in the ASC circuit to output the enable control signal FSENB, the enable control signal FSENB is low, and the enable control signal FSENB is sent to the drive unit to make the motor enter the open circuit protection mode, and the drive unit chip stops responding to the PWM wave control mode and turns off all upper bridge switch devices and lower bridge switch devices. The second fault signal and the upper bridge master control signal MCU_FSS_HS and the lower bridge master control signal MCU_FSS_LS are respectively operated by the logic gate in the ASC circuit to output the upper bridge control signal FSS_HS and the lower bridge control signal FSS_LS, and these control signals are sent to the drive unit, so that the drive unit controls all upper bridge switch devices to turn off and all lower bridge switch devices to turn on. It should be understood that because there is a delay time between the first detection signal and the second detection signal, there is also the same delay time between all the first fault signals and the second fault signals, so the drive unit will first send it to the drive unit based on the low-level enable control signal FSENB to make the motor enter the open circuit protection mode, and then after a short delay, based on the upper bridge control signal FSS_HS and the lower bridge control signal FSS_LS, open the lower bridge switch device and close the upper bridge switch device to protect the motor safety through the reverse electric power generated by the motor stator winding.

[0055] In one embodiment of the present application, the driver chip enable signal MCU_FSENB issued by the main control unit MCU is at a high level. If the power chip signal is normal and the bus voltage is not too high or when the power chip signal and the bus voltage return to normal, the first fault signal and the second fault signal are both at a high level, then the enable control signal FSENB after passing through the first AND gate circuit is at a high level. At this time, the driver unit does not respond after receiving the high-level enable control signal FSENB. At this time, the driver unit maintains or restores the normal PWM wave control mode, and controls the switching device in response to the PWM wave issued by the main control unit CPU.

[0056] In one embodiment of the present application, the switching device is an IGBT tube, the FSS_HS signal is transmitted to all the driver chips of the upper bridge and controls the corresponding IGBT gate voltage to turn it off, and the FSS_LS signal is transmitted to all the driver chips of the lower bridge and controls all the IGBTs of the lower bridge to turn on.

[0057] In one embodiment of the present application, an enable control signal is obtained based on a main control chip signal and a first fault signal, and controlling the drive unit of the motor to enter an open circuit protection mode based on the enable control signal includes: inputting the drive chip enable signal and the first fault signal into a first AND gate circuit, and using the output result of the first AND gate circuit as the enable control signal, the first fault signal is a low level, and the enable control signal is a low level; controlling the drive unit based on the enable control signal so that the drive unit does not respond to a pulse width modulation control mode (PWM wave control mode), and all upper bridge switching devices and all lower bridge switching devices in the drive unit are all turned off.

[0058] In one embodiment of the present application, when the motor controller system detects a fault (bus voltage overvoltage, SBC power supply fault, or both) during the operation of the vehicle, the bus overvoltage signal and the first detection signal will enter the logic gate of the ASC circuit for operation and output the first fault signal with a low level, and then the driver chip enable signal MCU_FSENB and the low-level first fault signal will enter the first AND gate circuit, and the output result will be used as the enable control signal FSENB, and the enable control signal FSENB is low. The enable control signal FSENB is the mode enable signal of the drive unit. When it is low, the drive unit enters the open circuit protection mode after receiving it, and then the drive chip does not respond to the PWM wave to control the switch IGBT. At this time, the motor controller system enters the FreeWheeling (all IGBTs are turned off) state.

[0059] Step S240, output a second fault signal according to the second detection signal and the bus overvoltage signal, obtain an upper bridge control signal and a lower bridge control signal based on the main control chip signal and the second fault signal to control the opening or closing of the upper bridge switch device and the lower bridge switch device of the drive unit, and the drive unit enters an active short circuit mode.

[0060] In one embodiment of the present application, a second fault signal is output according to a second detection signal and a bus overvoltage signal, and a lower bridge control signal is obtained based on the main control chip signal and the second fault signal, including: if the second detection signal is at a low level or the bus overvoltage signal is at a high level, at least one of the following is satisfied, then a second fault signal is output, and the second fault signal is at a low level; the lower bridge main control signal and the second fault signal are input into a NAND gate circuit, and a lower bridge control signal is obtained based on the output result of the NAND gate circuit, so as to control all lower bridge switch devices in the driving unit to be fully turned on based on the lower bridge control signal.

[0061] In one embodiment of the present application, a second fault signal is output according to a second detection signal and a bus overvoltage signal, and an upper bridge control signal is obtained based on the main control chip signal and the second fault signal, including: if the second detection signal is at a low level or the bus overvoltage signal is at a high level, at least one of the following is satisfied, then a second fault signal is output, and the second fault signal is at a low level; the upper bridge main control signal and the second fault signal are input into a second AND gate circuit, and an upper bridge control signal is obtained based on the output result of the second AND gate circuit, so as to control all upper bridge devices in the drive unit to be completely shut down based on the upper bridge control signal.

[0062] In one embodiment of the present application, when the main control chip signal sent by the main control unit CPU is normal, the driving chip enable signal MCU_FSENB is high, the lower bridge main control signal MCU_FSS_LS is high, and the upper bridge main control signal MCU_FSS_HS is low. However, in order to avoid the situation where the upper and lower bridge switch devices are all opened and short-circuited due to a level-type fault in the main control chip signal sent by the main control unit CPU, an interlocking circuit is also designed: after the upper bridge main control signal and the second fault signal are input into the second AND gate circuit, the output result of the second AND gate circuit and the lower bridge main control signal are input into the third AND gate circuit, and the upper bridge control signal is obtained based on the output result of the third AND gate circuit, so as to control all the upper bridge devices in the driving unit to be completely closed based on the upper bridge control signal.

[0063] In one embodiment of the present application, the operation logic of the second fault signal and the lower bridge main control signal MCU_FSS_LS and the NAND gate circuit outputs the lower bridge control signal FSS_LS. The lower bridge control signal is a high level, and then it is increased to 5V by the level conversion unit and delivered to the IGBT drive unit to execute and control all the IGBTs of the lower bridge to turn on.

[0064] In one embodiment of the present application, the second fault signal and the upper bridge master control signal MCU_FSS_HS enter the second AND gate circuit together, and its output result will control all IGBTs on the upper bridge of the drive unit to turn off. In this embodiment, a third AND gate circuit is set after the second AND gate circuit, and the lower bridge master control signal MCU_FSS_LS is pulled over and then calculated with the output result of the second AND gate circuit, and the output result of the third AND gate circuit is used as the upper bridge control signal FSS_HS to control all IGBTs on the upper bridge of the drive unit to turn off. The third AND gate circuit in this embodiment is equivalent to setting an interlocking circuit to prevent the MCU from issuing an erroneous instruction under special fault conditions, causing the ASC circuit to output FSS_LS and FSS_HS of the same high level, thereby causing the upper and lower bridge arms of the IGBT to be directly short-circuited.

[0065] In one embodiment of the present application, the power management unit has two fault output pins, namely, FS0B pin and FS1B pin. Based on the first detection signal FS0B, the driver chip enable signal MCU_FSENB is associated, and based on the second detection signal FS1B, the upper and lower bridge main control signal MCU_FSSTATE is associated. Therefore, when the SBC power chip fails, the programmable delay feature of the SBC chip fault output pin can be used to make the short-circuit control circuit first output a low-level enable control signal FSENB to stop the driver chip from responding to the PWM wave when the fault occurs, and all IGBTs are turned off to make the system enter the FreeWheeling state, which protects the motor controller hardware from serious damage in the first place. Then the second detection signal FS1B of the SBC fails and enters the ASC circuit for calculation and outputs the upper bridge control signal FSS_HS and the lower bridge control signal FSS_LS to control the IGBT switch state of the upper and lower bridges of the driver module to complete the ASC, so that the process of entering the active short-circuit mode becomes safer and more controllable. It should be understood that this embodiment belongs to the controller functional safety strategy, which is highly versatile and can be applied to IGBT and various next-generation drive solutions.

[0066] See also Figure 3 , Figure 3 is a schematic diagram of a short circuit control circuit shown in an exemplary embodiment of the present application, such as Figure 3 The short circuit control circuit shown includes a fault judgment circuit, a NAND gate circuit U1, a first AND gate circuit U4, a second AND gate circuit U2, a third AND gate circuit U3 and a level conversion circuit.

[0067] In one embodiment of the present application, the fault judgment circuit is composed of a NOT gate and an AND gate. Figure 3 The method includes two fault judgment circuits, namely a first fault judgment circuit and a second fault judgment circuit. Figure 3 As shown, the first fault judgment circuit is Figure 3 The NOT gate and AND gate in the middle, where the NOT gate input of the first fault judgment circuit is the bus overvoltage signal VIOUT_INTB, and the AND gate input of the first fault judgment circuit is the output of the NOT gate in the first fault judgment circuit and the first detection signal FS0B, and the output of the AND gate in the first fault judgment circuit is used as the first fault signal. The second fault judgment circuit is Figure 3 The NOT gate and AND gate in the lower part, wherein the NOT gate input of the second fault judgment circuit is the bus overvoltage signal VIOUT_INTB, the AND gate input of the second fault judgment circuit is the output of the NOT gate in the second fault judgment circuit and the second detection signal FS1B, and the output of the AND gate in the second fault judgment circuit is used as the second fault signal.

[0068] In one embodiment of the present application, the fault judgment circuit is connected to the input end, and the input is the first detection signal FS0B, the second detection signal FS1B, the bus overvoltage signal VIOUT_INTB, the driver chip enable signal MCU_FSENB, the upper bridge master signal MCU_FSS_HS and the lower bridge master signal MCU_FSS_LS. There are two fault judgment circuits, namely the first fault judgment circuit and the second fault judgment circuit. The first fault judgment circuit is used to judge the fault detection result of the first detection signal FS0B and the bus overvoltage signal VIOUT_INTB, and the second fault judgment circuit is used to judge the fault detection result of the second detection signal FS1B bus overvoltage signal VIOUT_INTB. The output of the first fault judgment circuit is connected to the output end of the first AND gate circuit U4, and the output of the second fault judgment circuit is connected to the input end of the NAND gate circuit and the second AND gate circuit.

[0069] In one embodiment of the present application, the input of the first AND gate circuit U4 is the first fault signal output by the first fault judgment circuit and the driver chip enable signal MCU_FSENB, the output end of the first AND gate circuit is connected to the input end A2 pin of the level conversion circuit, and the boosted output is sent to the drive unit as the enable control signal FSENB via the level conversion circuit.

[0070] In one embodiment of the present application, the input of the NAND gate circuit U1 is the second fault signal output by the second fault judgment circuit and the lower bridge main control signal MCU_FSS_LS, and the output end of the NAND gate circuit U1 is connected to the input end A1 pin of the level conversion circuit, and the boosted output is sent to the driving unit as the lower bridge control signal FSS_LS via the level conversion circuit.

[0071] In one embodiment of the present application, the input of the second AND gate circuit U2 is the second fault signal output by the second fault judgment circuit and the upper bridge master control signal MCU_FSS_HS, and the output end of the second AND gate circuit U2 is connected to the input end of the third AND gate circuit U3. The input of the third AND gate circuit U3 is the output result of the second AND gate circuit U2 and the lower bridge master control signal MCU_FSS_L, and the output end of the third AND gate circuit U3 is connected to the input end A3 pin of the level conversion circuit, and the output after boosting is sent to the driving unit as the upper bridge master control signal FSS_HS via the level conversion circuit.

[0072] See also Figure 4 , Figure 4 is a block diagram of a motor active short circuit control device shown in an exemplary embodiment of the present application, such as Figure 4 As shown, the exemplary motor active short-circuit control device includes: a signal input module 401 , a fault detection module 402 , an open circuit protection module 403 and an active short-circuit module 404 .

[0073] The signal input module 401 is used to obtain a bus overvoltage signal, a power chip signal and a main control chip signal. The power chip signal includes a first detection signal and a second detection signal. The first detection signal and the second detection signal have the same level type. The second detection signal is obtained after the first detection signal.

[0074] A fault detection module 402 is used to perform fault detection based on the bus overvoltage signal and the power chip signal, and if the detection result is that a fault exists, obtain a first fault signal based on the first detection signal and the bus overvoltage signal;

[0075] The open circuit protection module 403 is used to obtain an enable control signal based on the main control chip signal and the first fault signal, and control the drive unit of the motor to enter the open circuit protection mode based on the enable control signal;

[0076] The active short-circuit module 404 is used to output a second fault signal according to the second detection signal and the bus overvoltage signal, and obtain an upper bridge control signal and a lower bridge control signal based on the main control chip signal and the second fault signal to control the opening or closing of the upper bridge switch device and the lower bridge switch device in the drive unit, and the drive unit enters the active short-circuit mode.

[0077] An embodiment of the present application also provides a vehicle, which is applied to any one of the motor active short-circuit control methods in the above embodiments, and the vehicle includes a motor active short-circuit control device; the motor active short-circuit control device includes a signal input module, a fault detection module, an open circuit protection module and an active short-circuit module; the signal input module is used to obtain a bus overvoltage signal, a power chip signal and a main control chip signal, the power chip signal includes a first detection signal and a second detection signal, the first detection signal and the second detection signal have the same level type, and the second detection signal is obtained after the first detection signal; the fault detection module is used to detect the bus overvoltage signal and the power chip signal based on the bus overvoltage signal and the power chip signal A fault detection is performed on the signal. If the detection result is that there is a fault, a first fault signal is obtained based on the first detection signal and the bus overvoltage signal; an open circuit protection module is used to obtain an enable control signal based on the main control chip signal and the first fault signal, and control the drive unit of the motor to enter the open circuit protection mode based on the enable control signal; an active short circuit module is used to output a second fault signal according to the second detection signal and the bus overvoltage signal, and obtain an upper bridge control signal and a lower bridge control signal based on the main control chip signal and the second fault signal to control the opening or closing of the upper bridge switch device and the lower bridge switch device in the drive unit, and the drive unit enters the active short circuit mode.

[0078] An embodiment of the present application further provides a motor, which is applied to the motor active short-circuit control method described in any of the above embodiments.

[0079] Figure 5The structure diagram of the computer system suitable for implementing the electronic device of the embodiment of the present application is shown. It should be noted that: Figure 5 The computer system 500 of the electronic device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0080] like Figure 5 As shown, the computer system 500 includes a central processing unit (CPU) 501, which can perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 502 or the program loaded from the storage part 508 to the random access memory (RAM) 503, such as executing the method described in the above embodiment. Various programs and data required for system operation are also stored in the RAM 503. The CPU 501, the ROM 502 and the RAM 503 are connected to each other through the bus 504. The input / output (I / O) interface 505 is also connected to the bus 504.

[0081] The following components are connected to the I / O interface 505: an input section 506 including a keyboard, a mouse, etc.; an output section 507 including a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker; a storage section 508 including a hard disk, etc.; and a communication section 509 including a network interface card such as a LAN (Local Area Network) card, a modem, etc. The communication section 509 performs communication processing via a network such as the Internet. A drive 510 is also connected to the I / O interface 505 as needed. A removable medium 511, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 510 as needed so that a computer program read therefrom is installed into the storage section 508 as needed.

[0082] In particular, according to an embodiment of the present application, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present application includes a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a computer program for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication part 509, and / or installed from a removable medium 511. When the computer program is executed by a central processing unit (CPU) 501, various functions defined in the system of the present application are executed.

[0083] It should be noted that the computer-readable medium shown in the embodiment of the present application may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a flash memory, an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier, which carries a computer-readable computer program. This propagated data signal may take a variety of forms, including but not limited to an electromagnetic signal, an optical signal, or any suitable combination of the above. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate or transmit a program for use by or in conjunction with an instruction execution system, apparatus or device. A computer program contained on a computer-readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wired, etc., or any suitable combination of the above.

[0084] The flowchart and block diagram in the accompanying drawings illustrate the possible architecture, functions and operations of the system, method and computer program product according to various embodiments of the present application. Wherein, each box in the flowchart or block diagram can represent a module, a program segment, or a part of the code, and the above-mentioned module, program segment, or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of boxes in the block diagram or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0085] The units involved in the embodiments described in this application may be implemented by software or hardware, and the units described may also be set in a processor. The names of these units do not, in some cases, constitute limitations on the units themselves.

[0086] Another aspect of the present application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor of a computer, causes the computer to execute the motor active short-circuit control method as described above. The computer-readable storage medium may be included in the electronic device described in the above embodiment, or may exist independently without being assembled into the electronic device.

[0087] Another aspect of the present application also provides a computer program product or a computer program, which includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device executes the motor active short-circuit control method provided in each of the above embodiments.

[0088] The above embodiments are merely illustrative of the principles and effects of the present application, and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present application shall still be covered by the claims of the present application.

Claims

1. A method for active short-circuit control of a motor, characterized in that: The motor active short circuit control method comprises: Obtaining a bus overvoltage signal, a power chip signal, and a main control chip signal, wherein the power chip signal includes a first detection signal and a second detection signal, the first detection signal and the second detection signal have the same level type, and the second detection signal is obtained after the first detection signal; Performing fault detection based on the bus overvoltage signal and the power chip signal, and if the detection result is that a fault exists, obtaining a first fault signal based on the first detection signal and the bus overvoltage signal; An enable control signal is obtained based on the main control chip signal and the first fault signal, and the drive unit of the motor is controlled to enter an open circuit protection mode based on the enable control signal; the main control chip signal includes a drive chip enable signal, an upper bridge main control signal, and a lower bridge main control signal, and an enable control signal is obtained based on the main control chip signal and the first fault signal, and the drive unit of the motor is controlled to enter an open circuit protection mode based on the enable control signal, including: inputting the drive chip enable signal and the first fault signal into a first AND gate circuit, and using the output result of the first AND gate circuit as the enable control signal; A second fault signal is output according to the second detection signal and the bus overvoltage signal, and an upper bridge control signal and a lower bridge control signal are obtained based on the main control chip signal and the second fault signal to control the opening or closing of the upper bridge switch device and the lower bridge switch device in the driving unit, and the driving unit enters an active short circuit mode; obtaining the lower bridge control signal based on the main control chip signal and the second fault signal includes: inputting the lower bridge main control signal and the second fault signal into a NAND gate circuit, and obtaining the lower bridge control signal based on the output result of the NAND gate circuit; obtaining the upper bridge control signal based on the main control chip signal and the second fault signal includes: inputting the upper bridge main control signal and the second fault signal into a second AND gate circuit, and obtaining the upper bridge control signal based on the output result of the second AND gate circuit.

2. The motor active short circuit control method according to claim 1, characterized in that: Performing fault detection based on the bus overvoltage signal and the power chip signal includes: If the bus overvoltage signal is at a high level, the bus overvoltage signal is abnormal; If the power chip signal is at a low level, the power chip signal is abnormal; If one of the bus overvoltage signal and the power chip signal is abnormal or both the bus overvoltage signal and the power chip signal are abnormal, the detection result is that a fault exists; If the detection result is that a fault exists, a first fault signal is obtained based on the first detection signal and the bus overvoltage signal, and a second fault signal is obtained based on the second detection signal and the bus overvoltage signal.

3. The motor active short circuit control method according to claim 1, characterized in that: Controlling the drive unit of the motor to enter the open circuit protection mode based on the enable control signal includes: The first fault signal is at a low level, and the enable control signal is at a low level; The driving unit is controlled based on the enable control signal so that the driving unit does not respond to the pulse width modulation control mode, and all the upper bridge switching devices and all the lower bridge switching devices in the driving unit are turned off.

4. The motor active short circuit control method according to claim 1, characterized in that: Outputting a second fault signal according to the second detection signal and the bus overvoltage signal, and obtaining a lower bridge control signal based on the main control chip signal and the second fault signal comprises: If at least one of the second detection signal is at a low level or the bus overvoltage signal is at a high level, the second fault signal is output, and the second fault signal is at a low level; Based on the lower bridge control signal, all lower bridge switch devices in the driving unit are controlled to be turned on.

5. The motor active short circuit control method according to claim 1, characterized in that: Outputting a second fault signal according to the second detection signal and the bus overvoltage signal, and obtaining an upper bridge control signal based on the main control chip signal and the second fault signal comprises: If at least one of the second detection signal is at a low level or the bus overvoltage signal is at a high level, the second fault signal is output, and the second fault signal is at a low level; All upper bridge devices in the driving unit are controlled to be turned off based on the upper bridge control signal.

6. The motor active short circuit control method according to claim 5, characterized in that: After inputting the upper bridge main control signal and the second fault signal into the second AND gate circuit, the method further includes: The output result of the second AND gate circuit and the lower bridge main control signal are input into the third AND gate circuit, and the upper bridge control signal is obtained based on the output result of the third AND gate circuit, so as to control all upper bridge devices in the driving unit to be turned off based on the upper bridge control signal.

7. A motor active short-circuit control system, characterized in that: The motor active short-circuit control system includes a bus voltage acquisition unit, a bus voltage overvoltage detection unit, a drive unit, a main control unit, a power management unit and a short-circuit control circuit unit; The bus voltage collection unit is used to collect the bus voltage; The bus voltage overvoltage detection unit is used to obtain a bus overvoltage signal based on the bus voltage, and if the bus voltage is overvoltage, the bus overvoltage signal is a high level; The driving unit is used to drive the gate voltage of the upper bridge switch device and the lower bridge switch device to control the opening or closing of the upper bridge switch device and the lower bridge switch device; The main control unit is used to send a main control chip signal to the short-circuit control circuit unit, and the main control chip signal includes a drive chip enable signal, an upper bridge main control signal and a lower bridge main control signal; The power management unit is used to detect the power supply and send a power chip signal to the short-circuit control circuit unit. If the power supply fails, the power chip signal is at a low level. The power chip signal includes a first detection signal and a second detection signal. The first detection signal and the second detection signal have the same level type, and the second detection signal is sent after the first detection signal. The short-circuit control circuit unit is used to obtain an enable control signal, an upper bridge control signal and a lower bridge control signal based on the main control chip signal, the power chip signal and the bus overvoltage signal, and send the enable control signal, the upper bridge control signal and the lower bridge control signal to the drive unit so that the drive unit controls the opening or closing of the upper bridge switch device and the lower bridge switch device, including: performing fault detection based on the bus overvoltage signal and the power chip signal, and if the detection result is that there is a fault, obtaining a first fault signal based on the first detection signal and the bus overvoltage signal; obtaining an enable control signal based on the main control chip signal and the first fault signal, and controlling the drive unit of the motor to enter an open circuit protection mode based on the enable control signal; outputting a second fault signal according to the second detection signal and the bus overvoltage signal, obtaining an upper bridge control signal and a lower bridge control signal based on the main control chip signal and the second fault signal, so as to control the opening or closing of the upper bridge switch device and the lower bridge switch device in the drive unit, and the drive unit enters an active short-circuit mode Formula; the short-circuit control circuit unit includes a NAND gate circuit, a first AND gate circuit, a second AND gate circuit and a third AND gate circuit, the input of the first AND gate circuit is the first fault signal and the driver chip enable signal, the output of the first AND gate circuit is an enable control signal, the enable control signal is used to control the drive unit so that the drive unit does not respond to the pulse width modulation control mode, and all the upper bridge switch devices and all the lower bridge switch devices in the drive unit are all turned off; the input of the NAND gate circuit is the second fault signal and the lower bridge master control signal, the output of the NAND gate circuit is the lower bridge control signal, the lower bridge control signal is used to control the drive unit so that the lower bridge switch devices of the drive unit are all turned on; the input of the second AND gate circuit is the second fault signal and the upper bridge master control signal; the input of the third AND gate circuit is the output signal of the second AND gate circuit and the lower bridge master control signal, the output of the third AND gate circuit is the upper bridge control signal, the upper bridge control signal is used to control the drive unit so that the upper bridge switch devices of the drive unit are all turned off.

8. The motor active short-circuit control system according to claim 7, characterized in that: The short-circuit control circuit unit also includes a fault judgment circuit; The input of the fault judgment circuit is the power chip signal and the bus overvoltage signal, and when either the power chip signal is at a low level or the bus overvoltage signal is at a high level, a low level is output; when the power chip signal is at a high level and the bus overvoltage signal is at a low level, a high level is output, and the output result is output as a fault signal, and the fault signal includes a first fault signal and a second fault signal.

9. The motor active short-circuit control system according to claim 8, characterized in that: The short-circuit control circuit unit also includes a level conversion circuit; The level conversion circuit is used for converting the voltages of the enable control signal, the upper bridge control signal and the lower bridge control signal into preset voltage values, and then sending the converted control signals to the driving unit to control the driving unit.

10. A motor active short circuit control device, characterized in that: The motor active short circuit control device comprises: A signal input module, used to obtain a bus overvoltage signal, a power chip signal and a main control chip signal, wherein the power chip signal includes a first detection signal and a second detection signal, the first detection signal and the second detection signal have the same level type, and the second detection signal is obtained after the first detection signal; a fault detection module, configured to perform fault detection based on the bus overvoltage signal and the power chip signal, and if the detection result is that a fault exists, obtain a first fault signal based on the first detection signal and the bus overvoltage signal; An open circuit protection module, used for obtaining an enable control signal based on the main control chip signal and the first fault signal, and controlling the drive unit of the motor to enter an open circuit protection mode based on the enable control signal; the main control chip signal includes a drive chip enable signal, an upper bridge main control signal and a lower bridge main control signal, obtaining an enable control signal based on the main control chip signal and the first fault signal, and controlling the drive unit of the motor to enter an open circuit protection mode based on the enable control signal includes: inputting the drive chip enable signal and the first fault signal into a first AND gate circuit, and using the output result of the first AND gate circuit as the enable control signal; An active short-circuit module is used to output a second fault signal according to the second detection signal and the bus overvoltage signal, and obtain an upper bridge control signal and a lower bridge control signal based on the main control chip signal and the second fault signal to control the opening or closing of the upper bridge switch device and the lower bridge switch device in the drive unit, and the drive unit enters an active short-circuit mode; obtaining the lower bridge control signal based on the main control chip signal and the second fault signal includes: inputting the lower bridge main control signal and the second fault signal into a NAND gate circuit, and obtaining the lower bridge control signal based on the output result of the NAND gate circuit; obtaining the upper bridge control signal based on the main control chip signal and the second fault signal includes: inputting the upper bridge main control signal and the second fault signal into a second AND gate circuit, and obtaining the upper bridge control signal based on the output result of the second AND gate circuit.

11. A vehicle, characterized in that: The vehicle includes an active short-circuit control device for a motor; The motor active short circuit control device comprises a signal input module, a fault detection module, an open circuit protection module and an active short circuit module; The signal input module is used to obtain a bus overvoltage signal, a power chip signal and a main control chip signal, wherein the power chip signal includes a first detection signal and a second detection signal, the first detection signal and the second detection signal have the same level type, and the second detection signal is obtained after the first detection signal; The fault detection module is used to perform fault detection based on the bus overvoltage signal and the power chip signal, and if the detection result is that a fault exists, obtain a first fault signal based on the first detection signal and the bus overvoltage signal; The open circuit protection module is used to obtain an enable control signal based on the main control chip signal and the first fault signal, and control the drive unit of the motor to enter the open circuit protection mode based on the enable control signal, the main control chip signal includes a drive chip enable signal, an upper bridge main control signal and a lower bridge main control signal, and the enable control signal is obtained based on the main control chip signal and the first fault signal, and the drive unit of the motor is controlled to enter the open circuit protection mode based on the enable control signal, including: inputting the drive chip enable signal and the first fault signal into a first AND gate circuit, and using the output result of the first AND gate circuit as the enable control signal; The active short-circuit module is used to output a second fault signal according to the second detection signal and the bus overvoltage signal, and obtain an upper bridge control signal and a lower bridge control signal based on the main control chip signal and the second fault signal to control the opening or closing of the upper bridge switch device and the lower bridge switch device in the driving unit, and the driving unit enters an active short-circuit mode; obtaining the lower bridge control signal based on the main control chip signal and the second fault signal includes: inputting the lower bridge main control signal and the second fault signal into a NAND gate circuit, and obtaining the lower bridge control signal based on the output result of the NAND gate circuit; obtaining the upper bridge control signal based on the main control chip signal and the second fault signal includes: inputting the upper bridge main control signal and the second fault signal into a second AND gate circuit, and obtaining the upper bridge control signal based on the output result of the second AND gate circuit.

12. A motor, characterized in that: The motor is applied to the motor active short-circuit control method according to any one of claims 1 to 6.

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