Low dropout linear regulator

Abstract

This invention discloses a low-dropout linear regulator. The low-dropout linear regulator includes a power transistor, an error amplifier, a buffer unit, a short-circuit protection unit, and a power consumption control unit. The buffer unit is connected between the output of the error amplifier and the control terminal of the power transistor, and is used to drive the power transistor according to the output of the error amplifier, controlling the input pole of the power transistor to move in the same direction as the output pole within the load current variation range. A clamping transistor is connected between the input voltage of the low-dropout linear regulator and the input terminal of the buffer unit. The power consumption control unit is connected to the input voltage and output voltage of the low-dropout linear regulator and the input terminal of the buffer unit, and is used to pull up the input of the buffer unit when the power transistor enters the linear region, thereby reducing the output current of the buffer unit and achieving low-power pole tracking frequency compensation.

Description

Technical Field

[0001] This invention relates to the field of power supply technology, and more specifically to a low dropout linear regulator. Background Technology

[0002] As an important component of power management modules, LDOs (Low Dropout Regulators) are widely used in various systems such as data acquisition, battery power, low power consumption, and industrial control, providing them with a stable and reliable power environment. Whether their output voltage is stable and not affected by sudden changes in power supply and load directly determines the overall performance of the system.

[0003] An LDO is essentially a stable negative feedback system. Ensuring the stability of the LDO loop feedback is the most basic requirement in circuit design. As system devices continue to evolve, the output current of the LDO is required to be increasingly larger. This causes the load current to shift over a wide range during operation, and the output pole POUT will also shift over a large frequency range. This will greatly increase the difficulty of frequency compensation, and improper handling may even cause instability of the entire system. There are two low-frequency poles in an LDO that affect loop stability: the error amplifier output terminal, i.e., the power transistor input pole Pe, and the output pole POUT. On the one hand, as the load current increases, the power transistor needs to be larger, and the larger parasitic capacitance will push the power transistor input pole Pe to a low frequency, making it difficult to compensate. On the other hand, the position of the output pole will change over a large frequency range with the change of load current.

[0004] like Figure 1 As shown in the diagram, the traditional low-dropout linear regulator 100 consists of an error amplifier EA, a resistor divider network, and a power transistor Mpwr. In this circuit, at least two low-frequency poles will affect the stability of the entire feedback loop: one output pole POUT and one power transistor input pole Pe. How to handle the primary and secondary relationships and their positions is crucial to ensuring the stability of the LDO loop. Especially in high-current scenarios, such as high-voltage external capacitor LDOs, due to the external capacitor and the wide-range shifting load current, the output pole POUT will also shift over a large frequency range, making frequency compensation very difficult, or even impossible, severely limiting the LDO's output current. In previous designs, a buffer stage was inserted between the error amplifier and the power transistor to push the power transistor's input pole to a higher frequency, achieving a compensation effect. However, as the load current continues to increase, such a buffer stage is clearly no longer suitable.

[0005] Therefore, how to properly handle the primary and secondary relationship between the input and output poles of power transistors and their positions, and how to ensure loop stability over a large load current range, is a key issue in LDO design. Summary of the Invention

[0006] To address the aforementioned technical problems, this invention provides a low-dropout linear regulator capable of achieving low-power pole tracking frequency compensation.

[0007] According to one aspect of the present invention, a low-dropout linear regulator is provided, comprising: a power transistor having a current conduction path coupled between an input voltage and an output voltage and a control terminal; an error amplifier for comparing a feedback voltage of the output voltage with a reference voltage; a buffer unit connected between the output terminal of the error amplifier and the control terminal of the power transistor, for driving the power transistor according to the output of the error amplifier, and controlling the input pole of the power transistor to move in the same direction as the output pole within a load current variation range; and a power consumption control unit connected to the input voltage and output voltage of the low-dropout linear regulator and the input terminal of the buffer unit, the power consumption control unit being used to pull up the input terminal of the buffer unit when the power transistor enters the linear region, thereby reducing the output current of the buffer unit.

[0008] Optionally, the buffer unit includes: a first current source, a first transistor, and a second current source connected in series between the input voltage of the low-dropout linear regulator and ground, wherein the control terminal of the first transistor serves as the input terminal of the buffer unit and is connected to the output terminal of the error amplifier; a second transistor, wherein its first terminal is connected to the input voltage, and its control terminal and second terminal are connected to a first node between the first transistor and the first current source, wherein the control terminal and second terminal of the second transistor also serve as the output terminal of the buffer unit and are connected to the control terminal of the power transistor; and a third transistor, wherein its first terminal is connected to the second terminal and the control terminal of the second transistor, the control terminal is connected to a second node between the first transistor and the second current source, and the second terminal is connected to ground.

[0009] Optionally, the low-dropout linear regulator further includes a first compensation capacitor connected between the output voltage of the low-dropout linear regulator and the control terminal of the first transistor.

[0010] Optionally, the low-dropout linear regulator further includes a short-circuit protection unit, used to obtain a current sampling signal by sampling the load current of the power transistor, and to pull up the input of the buffer unit when the current sampling signal is greater than the reference current, so as to reduce the load current of the power transistor.

[0011] Optionally, the short-circuit protection unit includes: a clamping transistor connected between the input voltage of the low-dropout linear regulator and the input terminal of the buffer unit; a fourth transistor, a fifth transistor, and a third current source connected in series between the input voltage and ground; the control terminals of the fourth transistor and the fifth transistor are connected to the control terminal of the power transistor; and the third node between the fifth transistor and the third current source is connected to the control terminal of the clamping transistor.

[0012] Optionally, the short-circuit protection unit further includes a second compensation capacitor connected between the control terminal of the clamping transistor and the third node.

[0013] Optionally, the power consumption control unit includes: a diode, the anode of which is connected to the input voltage; a sixth transistor, the first terminal of which is connected to the cathode of the diode, and the control terminal of which is connected to the control terminal and the second terminal of the second transistor, the second terminal of which is used to connect to the control terminal of the clamping transistor; a seventh transistor, the first terminal of which is connected to the cathode of the diode, and the control terminal of which is connected to the control terminal and the second terminal of the second transistor; and a resistor, the first terminal of which is connected to the second terminal of the seventh transistor, and the second terminal of which is connected to the output voltage of the low dropout linear regulator.

[0014] Optionally, the second terminal of the sixth transistor is also connected to the first terminal of the third current source to provide a second bias current to the sixth transistor and the seventh transistor via the third current source.

[0015] In summary, the LDO disclosed in this invention, by incorporating a buffer unit, not only provides additional power transistor driving capability, helping the LDO respond quickly to load changes and reducing transient output voltage fluctuations, but also optimizes frequency compensation. Pole-pole tracking ensures that the LDO maintains appropriate loop gain and phase margin across the entire load range, thereby improving overall performance. Furthermore, the LDO disclosed in this invention reduces the static power consumption of the buffer unit by incorporating clamping transistors and a power control unit, thus reducing unnecessary energy consumption while maintaining performance.

[0016] Furthermore, the frequency compensation unit disclosed in this invention also includes a short-circuit protection unit, which can limit the current flowing through the power transistor when a short circuit occurs at the output terminal of the LDO, preventing damage to the chip or reduction of the chip's lifespan due to overcurrent, and improving the safety and stability of the circuit. Attached Figure Description

[0017] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings.

[0018] Figure 1A schematic circuit diagram of a conventional low-dropout linear regulator is shown.

[0019] Figure 2 A schematic circuit diagram of a low-dropout linear regulator according to a first embodiment of the present invention is shown.

[0020] Figure 3 The diagram shows the operating waveforms of a low-dropout linear regulator according to a first embodiment of the present invention.

[0021] Figure 4 A schematic circuit diagram of a low-dropout linear regulator according to a second embodiment of the present invention is shown.

[0022] Figure 5 The diagram shows the operating waveforms of a low-dropout linear regulator according to a second embodiment of the present invention. Detailed Implementation

[0023] Exemplary embodiments of this disclosure will now be described in detail, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings to denote the same or similar parts.

[0024] In this specification, it should be noted that similar reference numerals already used to denote similar parts in other figures are used for these elements whenever possible. In the following description, detailed descriptions of functions and configurations known to those skilled in the art that are not related to the basic configuration of this disclosure will be omitted. The terminology described in this specification should be understood as follows.

[0025] The advantages and features of this disclosure, and its implementation methods, will be set forth through the embodiments described below with reference to the accompanying drawings. However, this disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make this disclosure comprehensive and complete, so as to fully convey the scope of this disclosure to those skilled in the art. Furthermore, this disclosure is limited only by the scope of the claims.

[0026] The shapes, dimensions, ratios, angles, and quantities disclosed in the accompanying drawings used to describe embodiments of this disclosure are merely examples, and therefore this disclosure is not limited to the illustrated details. Similar reference numerals always denote similar elements. In the following description, detailed descriptions will be omitted where it would inevitably obscure the focus of this disclosure if a detailed description of a related known function or construction were to be determined.

[0027] As will be fully appreciated by those skilled in the art, the features of the various embodiments of this disclosure may be combined or integrated with each other in whole or in part, and may be interoperable and technically driven with each other in various ways. The embodiments of this disclosure may be performed independently of each other, or may be performed together in a mutually dependent relationship.

[0028] In this application, a MOS transistor (Metal-Oxide-Semiconductor Field-Effect Transistor) includes a first terminal, a second terminal, and a control terminal. When the MOS transistor is in the on state, current flows from the first terminal to the second terminal. The first terminal, second terminal, and control terminal of a PMOS transistor are the source, drain, and gate, respectively, and the first terminal, second terminal, and control terminal of an NMOS transistor are the drain, source, and gate, respectively.

[0029] The following specific examples illustrate embodiments of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0030] Figure 2 A schematic circuit diagram of a low-dropout linear regulator 200 according to a first embodiment of the present invention is shown. Figure 2 As shown, the low dropout linear regulator 200 includes a power transistor Mpwr, an error amplifier EA, a resistor divider network, a buffer unit 210, and a short-circuit protection unit 220.

[0031] In this chip, the power transistor Mpwr is the main output transistor, having a current conduction path coupled between the input voltage Vin and the output voltage Vout, as well as a control terminal. For example, the power transistor Mpwr may be a PMOS transistor, with its source coupled to the input voltage Vin and its drain coupled to an external high-voltage capacitor Cout. It provides the output voltage Vout to the downstream load based on the input voltage Vin at the power supply terminal. In other embodiments, the power transistor Mpwr may also be other types of transistors, such as NMOS transistors, NPN Darlington transistors, and NPN bipolar transistors.

[0032] A resistor divider network consisting of resistors R1 and R2 is coupled between the output terminal of the output voltage Vout and ground. This network samples and divides the output voltage Vout to obtain the feedback voltage VFB, which is provided by the node between resistors R1 and R2. The non-inverting input of the error amplifier EA receives the feedback voltage VFB, and the inverting input receives the reference voltage VREF. The error amplifier EA compares the feedback voltage VFB with the reference voltage VREF and generates a voltage V1 at its output based on the difference between the two. Although Figure 2The embodiment shown uses an error amplifier EA, but those skilled in the art will know that other suitable analog or digital circuits are equally applicable, as long as they can achieve the error amplification function.

[0033] Buffer unit 210 is connected between the output of error amplifier EA and the control terminal of power transistor Mpwr. It generates voltage V2 based on the output of error amplifier EA (i.e., voltage V1) to drive power transistor Mpwr. Buffer unit 210 can be implemented using a super source follower (SSF). Specifically, buffer unit 210 includes transistors Mp1 and Mp2, transistor Mn1, and current sources I1 and I2. Transistors Mp1 and Mp2 are PMOS transistors, and transistor Mn1 is an NMOS transistor. The first terminal of current source I1 is connected to the input voltage Vin. The second terminal of current source I1 is connected to the source of transistor Mp1 at node N1. The gate of transistor Mp1 serves as the input terminal of buffer unit 210 and is connected to the output of error amplifier EA. Transistor Mp1 is controlled by voltage V1 to be turned on or off. The drain of transistor Mp1 is connected to the first terminal of current source I2 at node N2, and the second terminal of current source I2 is connected to ground. The source of transistor Mp2 is connected to the input voltage Vin. The gate and drain of transistor Mp2 are connected to the control terminal of power transistor Mpwr as the output terminal of buffer unit 210. The gate and drain of transistor Mp2 are also connected to node N1. The drain of transistor Mn1 is connected to the gate and drain of transistor Mp2. The gate of transistor Mn1 is connected to node N2, and transistor Mn1 is turned on or off by the voltage of node N2. The source of transistor Mn1 is connected to ground.

[0034] Furthermore, the low-dropout linear regulator 200 in this embodiment also includes a compensation capacitor C1, which is connected between the output voltage Vout and the gate of the transistor Mp1, and is used to perform Miller compensation on the LDO loop when the output load current is heavy.

[0035] The short-circuit protection unit 220 obtains a current sampling signal by sampling the load current of the power transistor Mpwr, compares the current sampling signal with a reference current, and pulls the input of the buffer unit high when the current sampling signal is greater than the reference current, thereby reducing the load current of the power transistor Mpwr. Specifically, the short-circuit protection unit 220 includes a clamping transistor Mn2, transistors Mp3 and Mp4, a current source I3, and a compensation capacitor C2. The clamping transistor Mn2 is, for example, an NMOS transistor, with its drain connected to the input voltage Vin, and its source connected to the input terminal of the buffer unit 210 (i.e., the gate of transistor Mp1). Transistors Mp3 and Mp4 are, for example, PMOS transistors. The source of transistor Mp3 is connected to the input voltage Vin, the drain of transistor Mp3 is connected to the source of transistor Mp4, the drain of transistor Mp4 is connected to the first terminal of current source I3, the second terminal of current source I3 is connected to ground, and the gates of transistors Mp3 and Mp4 are connected to the control terminal of power transistor Mpwr.

[0036] In this embodiment, transistors Mp3 and Mp4 obtain the current sampling signal by mirroring the load current of power transistor Mpwr, and compare the current sampling signal with the reference current provided by current source I3. Based on the comparison result, the control signal CTRL1 is provided at node N3 between transistor Mp4 and current source I3. When the current sampling signal is greater than the reference current, the control signal CTRL1 at node N3 is pulled high, thereby turning on transistor Mn2. Transistor Mn2 pulls up the gate voltage of transistor Mp1, which in turn pulls up the gate voltages of transistors Mp2 and power transistor Mpwr, thereby reducing the load current of power transistor Mpwr. In addition, compensation capacitor C2 is also connected between the gate of clamping transistor Mn2 and node N3 to achieve frequency compensation.

[0037] When the input voltage Vin is greater than the output voltage Vout, the output pole of the buffer unit 210 will change with the output pole of the power transistor Mpwr as the load changes, keeping it outside the unity-gain bandwidth. At this time, the output current of transistor Mp2 is:

[0038]

[0039] in, This indicates the output current of transistor Mp2. This indicates the aspect ratio of transistor Mp2. This indicates the aspect ratio of the power transistor Mpwr.

[0040] When the input voltage Vin is less than the output voltage Vout, the power transistor Mpwr enters the linear region, and the output voltage Vout and the feedback voltage VFB decrease. At this time, the gate voltage of transistor Mn1 increases, leading to an enhanced pull-down capability of transistor Mn1. The gate voltage of transistor Mp2 also decreases accordingly. Since the power transistor Mpwr has almost no voltage adjustment capability at this time, the voltage loop of the LDO becomes open-loop. Therefore, the output current of transistor Mp2 increases. This will also increase, raising the chip's static power consumption at low voltage.

[0041] Figure 3 The diagram shows the operating waveforms of a low-dropout linear regulator according to a first embodiment of the present invention. Figure 3 As shown, when the input voltage Vin is greater than 4.3V, the output current Iout of the power transistor Mpwr is 106uA, and the output current of transistor Mp2 is... The current is 0.547uA; when the input voltage Vin is less than 4.3V, the circuit enters the open-loop state, and the output current of transistor Mp2 is... The voltage drops to 324µA, an increase of 592 times. Therefore, the low-dropout linear regulator 200 of the first embodiment of the present invention has the problem of high static power consumption when the input voltage Vin is low.

[0042] Figure 4 A schematic circuit diagram of a low-dropout linear regulator according to a second embodiment of the present invention is shown. Figure 4 As shown, the difference between the low-dropout linear regulator 300 in this embodiment and the low-dropout linear regulator 200 in the first embodiment is that the low-dropout linear regulator 300 also includes a power consumption control unit 330. In addition, the buffer unit 310 and the short-circuit protection unit 320 in this embodiment are exactly the same as the buffer unit 210 and the short-circuit protection unit 220 in the first embodiment, and will not be described again here.

[0043] The power consumption control unit 330 is connected to the input voltage Vin, the output voltage Vout, and the gate of the clamping transistor Mn2. It is used to turn on the clamping transistor Mn2 when the input voltage Vin is less than the output voltage Vout, thereby reducing the output current of the buffer unit 310 and reducing circuit power consumption. Specifically, the power consumption control unit 330 includes a diode Z1, transistors Mp5 and Mp6, and a resistor R3. Transistors Mp5 and Mp6 are high-voltage PMOS transistors. The gate and source of transistor Mp5 are connected to the gate and source of transistor Mp6 respectively, forming a back-to-back connection. The anode of diode Z1 is connected to the input voltage Vin, and the cathode of diode Z1 is connected to the source of transistors Mp5 and Mp6. The gates of transistors Mp5 and Mp6 are connected to the gates of transistors Mp2 and the power transistor Mpwr. The drain of transistor Mp5 is connected to the gate of the clamping transistor Mn2 to provide it with a control signal CTRL2. The drain of transistor Mp6 is connected to the output voltage Vout via resistor R3.

[0044] When the input voltage Vin is greater than the output voltage Vout, the current of transistor Mp2 is in a normal state, and at this time the gate voltage VG of transistor Mp2 is... Mp2 =Vin-VSG Mp2 VSG Mp2 The source-gate voltage difference of transistor Mp2 is given by VSG, where VSG is the source-gate voltage difference between transistors Mp5 and Mp6, and VSG is the source-gate voltage difference between Mp5 and Mp6. Z1 -( Vin-VSG Mp2 )= VSG Mp2 -V Z1 V Z1 This is the turn-on voltage of transistor Z1. When VSG Mp2 -V Z1 When the voltage is low, transistors Mp5 and Mp6 cannot be turned on. Therefore, when the input voltage Vin is greater than the output voltage Vout, the power consumption control unit 330 can be in the off state without affecting the normal operation of the circuit.

[0045] When the input voltage Vin is less than the output voltage Vout, the gate voltage VG of transistor Mp2... Mp2 The source-gate voltage difference VSG of transistor Mp2 decreases, therefore... Mp2 It will increase when the source-gate voltage difference VSG of transistor Mp2 increases. Mp2 When the voltage increases to a certain level, transistors Mp5 and Mp6 will turn on, thereby pulling up the gate voltage of clamping transistor Mn2, which in turn pulls up the gate voltages of transistors Mp1 and Mp2, ultimately reducing the branch current of transistor Mp2 and thus reducing power consumption.

[0046] Furthermore, the low-dropout linear regulator 300 in this embodiment generates two relatively close poles in the power consumption control loop, thus requiring consideration of loop stability. By using the compensation capacitor C2 in the short-circuit current limiting loop, the dominant pole of the circuit can be pushed forward, thereby ensuring phase margin. Furthermore, the drain of transistor Mp5 in the power consumption control unit 330 is also connected to the current source I3 in the short-circuit protection unit 320 to provide bias current for transistors Mp5 and Mp6 via the current source I3, which can reduce the design complexity and area of ​​the circuit. In addition, since this embodiment does not require high detection accuracy, the clamping current of the transistor Mp2 branch can be controlled by resistor R3 without increasing the area of ​​transistors Mp5 and Mp6, thereby further reducing the circuit area and cost.

[0047] Figure 5 The diagram shows the operating waveforms of a low-dropout linear regulator according to a second embodiment of the present invention. Figure 5 Using an input voltage Vin = 4V~18V, an output voltage Vout = 4.5V, and a load current Iout = 100uA as an example, a DC sweep simulation of the input voltage Vin from 4V to 12V was performed to compare the no-load power consumption performance of the low-dropout linear regulator 300 in this embodiment with that of the low-dropout linear regulator 200 in the first embodiment. Figure 5 As shown, the branch current IS of transistor Mp2 in the low-dropout linear regulator 200 of the first embodiment under no-load conditions is... Mp2 =324.8uA, while the branch current IS of transistor Mp2 in the low dropout linear regulator 300 of this embodiment is 324.8uA under no-load conditions. Mp2 =139uA, a reduction of 57%. Therefore, based on the simulation results, the power consumption control unit of this embodiment can effectively reduce the static power consumption of the normally open loop.

[0048] In summary, the LDO disclosed in this invention, by incorporating a buffer unit, not only provides additional power transistor driving capability, helping the LDO respond quickly to load changes and reducing transient output voltage fluctuations, but also optimizes frequency compensation. Pole-pole tracking ensures that the LDO maintains appropriate loop gain and phase margin across the entire load range, thereby improving overall performance. Furthermore, the LDO disclosed in this invention reduces the static power consumption of the buffer unit by incorporating clamping transistors and a power control unit, thus reducing unnecessary energy consumption while maintaining performance.

[0049] Furthermore, the frequency compensation unit disclosed in this invention also includes a short-circuit protection unit, which can limit the current flowing through the power transistor when a short circuit occurs at the output terminal of the LDO, preventing damage to the chip or reduction of the chip's lifespan due to overcurrent, and improving the safety and stability of the circuit.

[0050] Furthermore, the LDO disclosed in this invention has a simple structure, good performance, requires fewer transistors, can achieve optimal layout design, and meets the needs of most applications within a chip.

[0051] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0052] Finally, it should be noted that the above embodiments are merely examples for clearly illustrating the present invention and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A low-dropout linear regulator, comprising: A power transistor has a current conduction path coupled between the input voltage and the output voltage, as well as a control terminal; An error amplifier is used to compare the feedback voltage of the output voltage with a reference voltage; A buffer unit is connected between the output terminal of the error amplifier and the control terminal of the power transistor. It is used to drive the power transistor according to the output of the error amplifier and control the input pole of the power transistor to move in the same direction as the output pole within the range of load current variation. as well as A power consumption control unit is connected to the input voltage and output voltage of the low dropout linear regulator and the input terminal of the buffer unit. The power consumption control unit is used to pull up the input terminal of the buffer unit when the power transistor enters the linear region, so as to reduce the output current of the buffer unit.

2. The low-dropout linear regulator according to claim 1, wherein, The buffer unit includes: A first current source, a first transistor, and a second current source are connected in series between the input voltage and ground of the low dropout linear regulator. The control terminal of the first transistor is connected to the output terminal of the error amplifier as the input terminal of the buffer unit. A second transistor, having a first terminal connected to the input voltage, and a control terminal and a second terminal connected to a first node between the first transistor and the first current source, wherein the control terminal and the second terminal of the second transistor also serve as the output terminals of the buffer unit and are connected to the control terminal of the power transistor; and The third transistor has its first terminal connected to the second terminal and the control terminal of the second transistor. The control terminal is connected to the second node between the first transistor and the second current source, and the second terminal is connected to ground.

3. The low-dropout linear regulator according to claim 2, wherein, Also includes: A first compensation capacitor is connected between the output voltage of the low-dropout linear regulator and the control terminal of the first transistor.

4. The low-dropout linear regulator according to claim 2, wherein, Also includes: A short-circuit protection unit is used to obtain a current sampling signal by sampling the load current of the power transistor, and to pull the input of the buffer unit high when the current sampling signal is greater than the reference current, so as to reduce the load current of the power transistor.

5. The low-dropout linear regulator according to claim 4, wherein, The short-circuit protection unit includes: A clamping transistor is connected between the input voltage of the low-dropout linear regulator and the input terminal of the buffer unit; A fourth transistor, a fifth transistor, and a third current source are connected in series between the input voltage and ground. The control terminals of the fourth transistor and the fifth transistor are connected to the control terminal of the power transistor. The third node between the fifth transistor and the third current source is connected to the control terminal of the clamping transistor.

6. The low-dropout linear regulator according to claim 5, wherein, The short-circuit protection unit also includes: A second compensation capacitor is connected between the control terminal of the clamping transistor and the third node.

7. The low-dropout linear regulator according to claim 5, wherein, The power consumption control unit includes: A diode, the anode of which is connected to the input voltage; The sixth transistor has its first terminal connected to the cathode of the diode, and its control terminal connected to the control terminal and the second terminal of the second transistor. The second terminal of the sixth transistor is used to connect to the control terminal of the clamping transistor. A seventh transistor, the first terminal of which is connected to the cathode of the diode, and the control terminal of which is connected to the control terminal and the second terminal of the second transistor; and A resistor, the first end of which is connected to the second end of the seventh transistor, and the second end of which is connected to the output voltage of the low dropout linear regulator.

8. The low-dropout linear regulator according to claim 7, wherein, The second terminal of the sixth transistor is also connected to the first terminal of the third current source to provide a second bias current to the sixth transistor and the seventh transistor via the third current source.

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