A memory and a method for processing data thereof

Abstract

The present invention provides a memory and a data processing method thereof, wherein the memory comprises: a flash memory including a plurality of data storage areas; a main controller for controlling the power supply of each data storage area; wherein the main controller is also used to respond to a write command sent by a host to obtain host data to be written, and sequentially obtain the erasure times of blocks in a plurality of data storage areas, and is also used to start the power supply to a certain data storage area when the erasure times of some blocks in a certain data storage area are less than an erasure threshold, and write the host data into a corresponding block in a certain data storage area, and is also used to generate and save a data mapping table according to the mapping relationship between the host data and the blocks in a certain host data storage area, and is also used to turn off the power supply to the data storage area when the erasure times of all blocks in the data storage area are greater than or equal to the erasure threshold. The present invention provides a subdivided power management method, which can reduce the operating power consumption of the memory.

Description

Technical Field

[0001] The present invention relates to the field of static storage technology, and in particular to a memory and a method for processing data thereof. Background Art

[0002] The eMMC storage chip is composed of an ARM CPU as a controller and NAND Flash. The ARM CPU runs the controller software, usually called firmware. The main functions of the firmware are to manage bad blocks, GC, early warning, improve performance and life of NAND Flash, and ensure the reliable use of NAND Flash.

[0003] With the extensive application of eMMC and other storage devices in mobile phones, tablets, and wearable devices, the client's requirements for standby time are getting higher and higher, that is, the requirements for the operating power consumption of eMMC / UFS are getting higher and higher. At present, the common practice is to put the memory into a low power (Sleep) state when there is no read or write operation on the whole machine. However, there is no method or measure to reduce power consumption during the normal operation of the whole system, which leads to excessive power consumption of the whole machine. Therefore, there is room for improvement. Summary of the invention

[0004] The present invention provides a memory and a method for processing data thereof, so as to solve the technical problem of excessively high power consumption of the memory in the prior art.

[0005] The present invention provides a memory, comprising:

[0006] Flash memory including a plurality of data storage areas;

[0007] A main controller, electrically connected to the flash memory, for independently supplying power to each of the data storage areas;

[0008] The main controller is also used to respond to a write command sent by the host to obtain the host data to be written, and sequentially obtain the erasure times of the blocks in the plurality of data storage areas;

[0009] The main controller is also used to start powering on a certain data storage area and write the host data into a corresponding block in the certain data storage area when the number of erasures of some blocks in the certain data storage area is less than an erasure threshold;

[0010] The main controller is also used to generate and save a data mapping table according to the mapping relationship between the host data and the blocks in the certain host data storage area;

[0011] The main controller is also used to turn off power supply to the data storage area when the number of erasure and write times of all blocks in the data storage area is greater than or equal to an erasure threshold and / or when there is no read or write operation in the data storage area.

[0012] In one embodiment of the present invention, the main controller includes a power management module, and the power management module is electrically connected to each of the data storage areas to independently supply power to each of the data storage areas.

[0013] In one embodiment of the present invention, the main controller further comprises a mapping management module, the mapping management module is electrically connected to each of the data storage areas, and the mapping management module is used to preferentially map the logical address of the host data to the logical address range of the first of the data storage areas;

[0014] The mapping management module is used for mapping the logical address of the host data to the logical address range of other data storage areas when the first data storage area does not meet the erasing threshold.

[0015] In one embodiment of the present invention, the flash memory further includes:

[0016] A firmware storage area, used to store the firmware of the memory;

[0017] An update storage area for storing a boot program of the memory update firmware; and

[0018] The mapping table storage area is used to store the data mapping table.

[0019] In one embodiment of the present invention, the power management module is used to supply power to the firmware storage area and the mapping table storage area respectively, and the power supplies to the firmware storage area and the mapping table storage area are in a normally-on state.

[0020] In one embodiment of the present invention, when the memory is updating firmware, the power management module supplies power to the update storage area. After the memory firmware update is completed, the power management module stops supplying power to the update storage area.

[0021] In one embodiment of the present invention, the erasure threshold is divided into a plurality of successively increasing limiting thresholds, and the main controller is used to sequentially determine whether the erasure times of the blocks in the data storage area are greater than or equal to a certain limiting threshold when the erasure times of the blocks in all the data storage areas are greater than or equal to a certain limiting threshold;

[0022] The main controller is also used to start power supply to a certain data storage area when the number of erasure and write times of some blocks in the certain data storage area is less than the next limited threshold.

[0023] In one embodiment of the present invention, the total power P_NAND of the flash memory satisfies the following formula:

[0024] P_NAND=Vccc*Iccc+Vccf*Iccf+Vcct*Icct+Vccd1*Iccd1+Vccd2*Iccd2+……+Vccdn*Iccdn;

[0025] Among them, Vccc and Iccc represent the voltage and current supplied to the firmware storage area, Vccf and Iccf represent the voltage and current supplied to the update storage area, Vcct and Icct represent the voltage and current supplied to the mapping table storage area, Vccd1 and Iccd1, Vccd2 and Iccd2, ..., Vccdn and Iccdn represent the voltage and current supplied to the 1st, 2nd, ..., nth data storage areas, respectively.

[0026] The present invention also provides a data processing method of a memory, comprising:

[0027] Responding to a write command sent by the host to obtain host data to be written, and sequentially obtaining the number of erase and write times of blocks in multiple data storage areas in the flash memory;

[0028] When the number of erasure and write times of some blocks in a certain data storage area is less than an erasure and write threshold, power supply to the certain data storage area is turned on, and the host data is written into the corresponding blocks of the certain data storage area;

[0029] Generate and save a data mapping table according to the mapping relationship between the host data and the blocks in the certain host data storage area;

[0030] When the erasure times of all blocks in the data storage area are greater than or equal to an erasure threshold, and / or when there is no read or write operation in the data storage area, power supply to the data storage area is turned off.

[0031] In one embodiment of the present invention, when the number of erasure times of some blocks in a certain data storage area is less than the erasure threshold, after the step of turning on the power supply to the certain data storage area and writing the host data into the corresponding block of the certain data storage area, the method includes:

[0032] When the number of erasure times of the blocks in all the data storage areas is greater than or equal to a certain limiting threshold, sequentially determining whether the number of erasure times of the blocks in the data storage areas is greater than or equal to a next limiting threshold, wherein the erasure threshold is divided into a plurality of limiting thresholds that increase in sequence;

[0033] When the number of erasure and write times of some blocks in a certain data storage area is less than the next defined threshold, power supply to the certain data storage area is turned on.

[0034] As described above, a method for processing a memory and its data of the present invention has the following beneficial effects: the present invention can perform hierarchical management according to the usage of blocks in the memory, distinguish between normal use areas and temporarily unused areas, and perform power supply management separately, thereby effectively reducing the power consumption of the memory during the operation of the entire system and increasing the usage time of consumer-grade terminal products. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0036] Figure 1 Shown is a schematic diagram of the structure of a memory provided by an embodiment of the present invention.

[0037] Figure 2 Shown is a schematic diagram of power supply of a power management module in one embodiment of the present invention.

[0038] Figure 3 Shown is a schematic diagram of a mapping relationship in a mapping management module in an embodiment of the present invention.

[0039] Figure 4 The figure shows a flow chart of a data processing method of a memory provided by an embodiment of the present invention.

[0040] Figure 5 Shown is a schematic diagram of the process of erasure threshold management in one embodiment of the present invention. DETAILED DESCRIPTION

[0041] The following is an explanation of the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the features in the following embodiments and the embodiments can be combined with each other without conflict. It should also be understood that the terms used in the embodiments of the present invention are intended to describe specific embodiments, rather than to limit the scope of protection of the present invention. The test methods for which specific conditions are not specified in the following examples are usually carried out under conventional conditions or according to the conditions recommended by the manufacturers.

[0042] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the limiting conditions for the implementation of the present invention, so they have no substantial technical significance. Any modification of the structure, change in the proportional relationship, or adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the effects and purposes that can be achieved by the present invention. At the same time, the terms such as "upper", "lower", "left", "right", "middle" and "one" quoted in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. The change or adjustment of their relative relationship should also be regarded as the scope of the implementation of the present invention without substantially changing the technical content.

[0043] The present invention provides a memory and a data processing method thereof, which relates to the field of static storage technology and can be specifically applied to reducing the operating power consumption of the memory. The present invention provides a subdivided power management strategy, which performs hierarchical management according to the usage of blocks in the memory during the normal operation of the whole system, distinguishes the normal use area and the temporarily unused area, and performs power supply management respectively, thereby effectively reducing the power consumption of the memory during the operation of the whole system and improving the use time of consumer-grade terminal products. The following is a detailed description through specific embodiments.

[0044] See also Figure 1 In one embodiment of the present invention, the memory may include a main controller 100 and a flash memory 200. The main controller 100 is electrically connected to the flash memory 200, and the main controller 100 may be used to control and manage all read and write operations, including error checking, data encryption, wear leveling, and address mapping. The main controller 100 includes a logic control unit and a hardware circuit to coordinate the communication between the memory and an external interface (such as SATA, PCIe) and manage internal resources. The flash memory 200 may be a NAND Flash flash memory, which is the most commonly used storage medium in the memory and has the characteristics of non-volatility and high density. The flash memory 100 may be divided into multiple areas according to different functions, and each area may be independently controlled for power supply. In this embodiment, the flash memory 100 may include multiple data storage areas 240. The main controller 100 may independently control the power supply of each data storage area 240.

[0045] See also Figure 1In one embodiment of the present invention, the main controller 100 may include a processing module 110, a power management module 120 and a power supply module 130. The processing module 110 may be an MCU-RISCV, i.e., an MCU (Microcont roller Unit) based on the RISC-V architecture. The processing module 110 can efficiently execute the algorithm control and program operation in the main control task and achieve lower energy consumption. The power management module 120 can be used to finely divide the different functional modules of VCC to achieve fine control of power consumption. VCC is the working voltage input pin of the memory, which is used to provide power to the main controller 100 and flash memory 200 of the memory. In this embodiment, the power management module 120 can be electrically connected to each data storage area 240, which can be used to independently control the power supply of each data storage area 240. The power supply module 130 is electrically connected to the processing module 110 and the power management module 120. In this embodiment, the power supply module 130 can provide I / O interface power (VCCQ) input to the logic circuits such as the processing module 110. The power supply module 130 may also provide a working voltage (VCC) input to the power management module 120 .

[0046] See also Figure 1 In one embodiment of the present invention, the main controller 100 may further include a mapping management module 140. The mapping management module 140 is connected to the flash memory 200 and can be used to manage the mapping relationship between LBA (Logical Block Address) and PBA (Physical Block Address) during data reading and writing. LBA is an abstract address used by the operating system to access data on the storage device. Applications and file systems request data reading and writing through LBA, so that data access is decoupled from the specific physical storage layout. PBA is a physical address on the actual storage medium, reflecting the real location of the data on the memory.

[0047] See also Figure 1In one embodiment of the present invention, the main controller 100 may further include an interface module 150, a debugging module 160, a storage module 170, a memory module 180 and a cache module 190. The interface module 150 may be used to realize the communication connection between the memory and the external device. The interface module 150 complies with the JEDEC standard, which can simplify the system integration and improve the compatibility and interchangeability. The debugging module 160 is a universal asynchronous receiver and transmitter, which can be used for debugging information output, and is convenient for troubleshooting and system status monitoring in the development stage. The storage module 170 can store the firmware startup code and basic control library of the memory. The storage module 170 is used to ensure that the memory can be correctly initialized and run the firmware after power-on. The memory module 180 can provide temporary storage space for the programs and data running in the main controller 100, and the memory module 180 can be used to speed up the execution speed. The cache module 190 may include a read cache 191 and a write cache 192. The read cache 191 and the write cache 192 are respectively electrically connected to the flash memory 200, which can reduce the waiting time for accessing the external bus and improve the data transmission efficiency.

[0048] See also Figure 1 In one embodiment of the present invention, the flash memory 200 also includes a firmware storage area 210, an update storage area 220, and a mapping table storage area 230. Among them, the firmware storage area 210 can be used to store the underlying control software of the memory - firmware, which contains all the basic instruction sets and control logic required to drive the memory. The firmware is responsible for initializing storage particles, managing data read and write operations, error detection and correction, and power management. The firmware storage area 210 is usually read-only or protected to prevent accidental modifications from causing the device to malfunction. The update storage area 220 can be used to store a boot program for updating firmware. When the firmware of the memory needs to be updated, the boot program will be executed first. It is responsible for verifying the integrity of the new firmware, safely booting and loading the new firmware, and performing firmware installation or rollback operations when necessary. The mapping table storage area 230 can be used to store various data mapping tables. The data mapping table is a key component unique to storage media such as NAND flash memory, which records the mapping relationship between logical addresses and physical addresses.

[0049] See also Figure 1 In one embodiment of the present invention, the host data storage area of ​​the flash memory 200 can be divided into n data storage areas 240 of equal capacity according to the storage capacity of the flash memory 200. Each data storage area 240 can be powered by Vcc. For example, when the capacity of the flash memory 200 is 256GB, it can be divided into 16 data storage areas 240, and the storage capacity of each data storage area 240 is 16GB. The 16 data storage areas 240 are powered by Vccd1, Vccd2, ..., Vccd16 in sequence.

[0050] See also Figure 2 In one embodiment of the present invention, the power management module 120 can finely and hierarchically manage the power supplies of different storage spaces in the flash memory 200. It should be noted that NAND flash memory, as a non-volatile storage technology, can retain data after power failure, which provides a basis for realizing dynamic power management. The present invention improves the power supply by a single VCC in the prior art to comprehensive management by the power management module 120. The present invention can significantly reduce the overall power consumption of storage particles while ensuring normal system operation by intelligently controlling the power supply of the inactive data storage area 240 in the flash memory 200. The present invention is suitable for application scenarios with strict requirements on energy efficiency, such as mobile devices, embedded systems and SSDs in data centers.

[0051] See also Figure 2 In one embodiment of the present invention, the power management module 120 can output independent multi-channel power supply voltages. In this embodiment, the power management module 120 can supply power to the firmware storage area 210 through Vccc, and can also supply power to the update storage area 220 through Vccf, and supply power to the mapping table storage area 230 through Vcct. In addition, the power management module 120 also supplies power to n corresponding data storage areas 240 through multiple Vccdi, i=1, 2, ..., n. Figure 2 As shown, according to the usage scenarios of each storage area in the flash memory 200 and whether the blocks in the data area are inactive or active, the power management module 120 can turn on or off the corresponding Vcc. For example, the firmware storage area 210 stores firmware, so Vccc is in a normally open state. The update storage area 220 stores a boot program for updating firmware, and Vccf only needs to be in an open state when the memory is in the FFU (Flexible Firmware Update, flexible firmware update) state. The mapping table storage area 230 stores various data mapping tables, which are related to the execution of read and write instructions, so Vcct is in a normally open state. According to whether the blocks in each data storage area 240 are inactive or active, the power management module 120 can make the corresponding Vccdi in a closed or open state.

[0052] In one embodiment of the present invention, the total power of the flash memory 200 can be calculated based on the voltage and current of each area in the flash memory 200, so that the corresponding reduced power consumption can be intuitively seen. In this embodiment, the total power P_NAND of the flash memory 200 satisfies the following formula:

[0053] P_NAND=Vccc*Iccc+Vccf*Iccf+Vcct*Icct+Vccd1*Iccd1+Vccd2*Iccd2+……+Vccdn*Iccdn;

[0054] Among them, Vccc and Iccc represent the voltage and current supplied to the firmware storage area 210, Vccf and Iccf represent the voltage and current supplied to the update storage area 220, Vcct and Icct represent the voltage and current supplied to the mapping table storage area 230, Vccd1 and Iccd1, Vccd2 and Iccd2, ..., Vccdn and Iccdn represent the voltage and current supplied to the 1st, 2nd, ..., nth data storage areas 240, respectively.

[0055] See also Figure 3 In one embodiment of the present invention, the mapping management module 140 is responsible for managing the mapping relationship between LBA (logical block address) and PBA (physical block address), optimizing read and write operations, and reducing energy consumption through the power management module 120. The present invention adopts a basic strategy of dynamically allocating logical addresses to physical storage space. In this embodiment, first, a specific logical block is fixedly mapped to a specific physical block. For example, the logical address LBAc of the firmware is mapped to the PBAc of the firmware storage area 210. The logical address LBAf of the firmware update boot program is mapped to the PBAf of the update storage area 220. The logical address LBAt of the data mapping table is mapped to the PBAt of the mapping table storage area 230. The logical addresses LBA1 to LBAx of the host data are mapped to PBAd1 to PBAdx, PBA(x+1) to PBA2x, and PBA(x(n-1)+1) to PBAnx in the data storage area 240. In this embodiment, the physical address range of the first data storage area 240 is defined as PBAd1 to PBAdx, the physical address range of the second data storage area 240 is defined as PBA(x+1) to PBA2x, and so on. The physical address range of the nth data storage area 240 is defined as PBA(x(n-1)+1) to PBAnx.

[0056] See also Figure 3In one embodiment of the present invention, the mapping management module 140 preferentially maps the LBA to the physical address range of the first data storage area 240 according to the read and write instructions sent by the host CPU. When the ECT (Erase Count Threshold) value of each block on the first data storage area 240 reaches the preset erase threshold, the wear leveling operation will be triggered, and the LBA originally mapped to the data storage area 240 will be remapped to the physical address range of the data storage area 240 that has not reached the erase threshold, for example, mapped to the second data storage area 240, ..., or the nth data storage area 240. The erase count is a key indicator for measuring the degree of wear of each block in the flash memory 200. The working principle of NAND flash memory determines that the memory has a limited number of programming times and erase cycles. After each block undergoes a certain number of erase operations, its reliability will gradually decrease, which may eventually lead to data errors or block failures. Therefore, in flash memory management, by tracking the number of erases and writes to each block and adopting a wear leveling strategy, the system can effectively disperse write operations to prevent certain blocks from reaching their endurance limits prematurely, thereby extending the service life of the entire flash memory device.

[0057] In one embodiment of the present invention, the erase threshold is divided into a plurality of successively increasing limiting thresholds. When the number of erase times of blocks in all data storage areas 240 is greater than or equal to a certain limiting threshold, the main controller 100 sequentially determines whether the number of erase times of blocks in the data storage area 240 is greater than or equal to the next limiting threshold, and when the number of erase times of some blocks in a certain data storage area 240 is less than the next limiting threshold, the power supply to a certain data storage area 240 is turned on. In this embodiment, the erase threshold can be set according to the maximum ECT times of the flash memory 200. For example, the maximum ECT times of the flash memory 200 is 3000 times, and the erase threshold can be equally divided into 100 levels, so that the difference between two adjacent limiting thresholds is 30 times, and the erase threshold can also be unequally divided into multiple levels according to the needs to achieve wear balance of each block in the flash memory 200. In this embodiment, when the ECT value of each block on a certain data storage area 240 reaches a current limiting threshold, the LBA originally mapped to the data storage area 240 can be remapped to other data storage areas 240. When the ECT value of each block on all data storage areas 240 reaches a certain current limit threshold, the erase threshold can be raised to the next limit threshold, so that data reading and writing can continue according to the strategy of mapping to the first data storage area 240 first. Further, in combination with the statistics of read and write instructions by the mapping management module 140 and the monitoring of the inactive state of each data storage area 240, the processing module 110 can make intelligent decisions and turn off the power of those data storage areas 240 that have no read and write operations for a long time. For example, the inactive time threshold of the data storage area 240 is preset to 100ms. When the inactive state of a data storage area 240 reaches or exceeds 100ms, the power of the data storage area 240 will be cut off, thereby effectively reducing power consumption.

[0058] See also Figure 4 The present invention also provides a data processing method of a memory, which can be applied to the processor of any of the above embodiments. Specifically, the data processing method may include the following steps:

[0059] Step S100, in response to a write command sent by the host, to obtain host data to be written, and to sequentially obtain the erase and write times of blocks in a plurality of data storage areas in the flash memory;

[0060] Step S200, when the erasure times of some blocks in a certain data storage area are less than the erasure threshold, power supply to the certain data storage area is turned on, and host data is written into the corresponding block of the certain data storage area;

[0061] Step S300, generating and saving a data mapping table according to the mapping relationship between the host data and the blocks in a certain host data storage area;

[0062] Step S400: When the erasure times of all blocks in the data storage area are greater than or equal to the erasure threshold, and / or when there is no read or write operation in the data storage area, power supply to the data storage area is turned off.

[0063] In one embodiment of the present invention, when step S100 is executed, that is, in response to the write command sent by the host, the host data to be written is obtained, and the number of erase and write times of blocks in multiple data storage areas in the flash memory are obtained in sequence. Specifically, the flash memory 200 is divided into a firmware storage area 210, an update storage area 220, a mapping table storage area 230, and multiple data storage areas 240. Among them, the firmware storage area 210 can be used to store the underlying control software of the memory - firmware, which contains all the basic instruction sets and control logic required to drive the memory. The update storage area 220 can be used to store the boot program for updating the firmware. When the firmware of the memory needs to be updated, the boot program will be executed first. The mapping table storage area 230 can be used to store various data mapping tables. The data mapping table is a key component unique to storage media such as NAND flash memory, which records the mapping relationship between logical addresses and physical addresses. In this embodiment, the host data storage area of ​​the flash memory 200 can be divided into n data storage areas 240 of equal capacity according to the storage capacity of the flash memory 200. Each data storage area 240 can be independently powered by Vcc. For example, when the capacity of the flash memory 200 is 256GB, it can be divided into 16 data storage areas 240, and the storage capacity of each data storage area 240 is 16GB. The 16 data storage areas 240 are powered by Vccd1, Vccd2, ..., Vccd16 in sequence. In this embodiment, after the host sends a write instruction to the memory, the memory responds to the write instruction and first obtains the host data to be written and the corresponding logical addresses LBA1~LBAx. Then, the erase count of each block in the multiple data storage areas 240 is obtained in sequence. In this embodiment, the mapping management module 140 preferentially maps the LBA to the physical address range of the first data storage area 240 according to the write command sent by the host CPU. Therefore, according to the physical address order, the erase count threshold (ECT) of each block in the first data storage area 240 is first obtained, and then the erase count of each block in other data storage areas 240 is obtained.

[0064] In one embodiment of the present invention, when step S200 is executed, that is, when the number of erasures of some blocks in a certain data storage area is less than the erasure threshold, the power supply to the certain data storage area is turned on, and the host data is written into the corresponding block of the certain data storage area. Specifically, when the number of erasures of some blocks in the first data storage area 240 has not reached the preset erasure threshold, it means that the blocks in the first data storage area 240 are relatively lightly worn and have good durability, and data can be written into them. Therefore, the processing module 110 can turn on the power supply of the first data storage area 240 through the power management module 120, that is, turn on Vccd1, and then the mapping management module 140 establishes a mapping relationship between LBA1~LBAx and PBAd1~PBadx, and writes the host data into the corresponding block. When the number of erasures of all blocks in the first data storage area 240 reaches the preset erasure threshold, it means that the blocks in the first data storage area 240 are relatively heavily worn and have poor durability. At this time, it can continue to determine whether the erase count of all blocks in the second data storage area 240 reaches the preset erase threshold. The erase count is a key indicator for measuring the degree of wear of each block in the flash memory 200. The erase threshold can be set according to the maximum ECT times of the flash memory 200. For example, the maximum ECT times of the flash memory 200 is 3000 times, and the erase threshold can be divided into 100 levels, so the erase threshold of each level is 30 times. If the erase count of some blocks in the second data storage area 240 does not reach the preset erase threshold, the mapping management module 140 establishes a mapping relationship between the logical address LBA1~LBAx of the host data and the physical address PBA(x+1)~PBA2x in the second data storage area 240. If the erase count of all blocks in the second data storage area 240 reaches the preset erase threshold, the next data storage area 240 is queried. And so on, until all the host data is written into the flash memory 200.

[0065] In one embodiment of the present invention, when step S300 is executed, a data mapping table is generated and saved according to the mapping relationship between the host data and the blocks in a certain host data storage area. Specifically, while writing data, the mapping management module 140 maintains and updates a data mapping table. This table records the mapping relationship between the host logical address (LBA) and the actual physical storage location (PBA). This mapping is crucial for subsequent read operations because the physical location of the data on the flash memory particles will change with the wear leveling operation.

[0066] In one embodiment of the present invention, when step S400 is executed, that is, when the number of erase and write times of all blocks in the data storage area is greater than or equal to the erase and write threshold, and / or when there is no read and write operation in the data storage area, the power supply to the data storage area is turned off. Specifically, when the number of erase and write times of all blocks in a data storage area 240 reaches or exceeds the set erase and write threshold, it indicates that the wear degree of the data storage area 240 is higher than that of other data storage areas 240. In order to achieve wear leveling, the system will no longer allocate new write operations to the data storage area 240, so the data storage area 240 can be powered off. In addition, if a data storage area 240 has no read and write operations for a period of time, that is, it is in an inactive state, the system will also choose to turn off the power supply to the data storage area 240 to reduce unnecessary energy consumption. For example, the inactive time threshold of the data storage area 240 is preset to 100ms. When the inactive state of a data storage area 240 reaches or exceeds 100ms, the power supply of the data storage area 240 will be cut off, thereby effectively reducing power consumption.

[0067] See also Figure 5 In one embodiment of the present invention, after executing step S300, the following steps are also included:

[0068] Step S510, when the number of erasure times of the blocks in all the data storage areas is greater than or equal to a certain limiting threshold, sequentially determining whether the number of erasure times of the blocks in the data storage areas is greater than or equal to the next limiting threshold, wherein the erasure threshold is divided into a plurality of limiting thresholds that increase in sequence;

[0069] Step S520: When the number of erasure and write times of some blocks in a certain data storage area is less than the next limited threshold, power supply to the certain data storage area is turned on.

[0070] In one embodiment of the present invention, when executing step S510 to step S520, specifically, the erase threshold is divided into a plurality of successively increasing limiting thresholds. When the number of erase times of blocks in all data storage areas 240 is greater than or equal to a certain limiting threshold, the main controller 100 sequentially determines whether the number of erase times of blocks in the data storage area 240 is greater than or equal to the next limiting threshold, and when the number of erase times of some blocks in a certain data storage area 240 is less than the next limiting threshold, the power supply to a certain data storage area 240 is turned on. In this embodiment, the erase threshold can be set according to the maximum ECT number of the flash memory 200. For example, the maximum ECT number of the flash memory 200 is 3000 times, and the erase threshold can be equally divided into 100 levels, so that the difference between two adjacent limiting thresholds is 30 times, and the erase threshold can also be unequally divided into multiple levels according to needs to achieve wear balance of each block in the flash memory 200.

[0071] In this embodiment, when the erasure times of some blocks in a data storage area are less than the next limited threshold, the power supply to the data storage area can be turned on, so as to continue to read and write data according to the strategy mapped to the data storage area 240 according to the priority strategy.

[0072] To sum up, the present invention proposes a memory and a data processing method thereof, which relate to the field of static storage technology. The present invention can perform hierarchical management according to the usage of blocks in the memory, distinguish between normal use areas and temporarily unused areas, and perform power supply management separately, thereby effectively reducing the power consumption of the memory during the operation of the entire system and improving the usage time of consumer-grade terminal products.

[0073] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A memory, characterized in that: include: Flash memory including a plurality of data storage areas; A main controller, electrically connected to the flash memory, for independently supplying power to each of the data storage areas; The main controller is also used to respond to a write command sent by the host to obtain the host data to be written, and sequentially obtain the erasure times of the blocks in the plurality of data storage areas; The main controller is also used to start powering on a certain data storage area and write the host data into a corresponding block in the certain data storage area when the number of erasures of some blocks in the certain data storage area is less than an erasure threshold; The erasure threshold is divided into a plurality of limiting thresholds which increase in sequence, and the main controller is further used to sequentially determine whether the erasure times of the blocks in the data storage area are greater than or equal to a certain limiting threshold when the erasure times of the blocks in all the data storage areas are greater than or equal to a certain limiting threshold; The main controller is also used to start power supply to a certain data storage area when the number of erasure and write times of some blocks in the certain data storage area is less than the next limited threshold value; The main controller is also used to generate and save a data mapping table according to the mapping relationship between the host data and the blocks in the certain data storage area; The main controller is also used to turn off power supply to the data storage area when the number of erasure and write times of all blocks in the data storage area is greater than or equal to an erasure threshold and / or when there is no read or write operation in the data storage area.

2. The memory according to claim 1, characterized in that: The main controller includes a power management module, which is electrically connected to each of the data storage areas to independently supply power to each of the data storage areas.

3. The memory according to claim 1, characterized in that: The main controller further comprises a mapping management module, the mapping management module is electrically connected to each of the data storage areas, and the mapping management module is used to preferentially map the logical address of the host data to the logical address range of the first data storage area; The mapping management module is used for mapping the logical address of the host data to the logical address range of other data storage areas when the first data storage area does not meet the erasing threshold.

4. The memory according to claim 2, characterized in that: The flash memory also includes: A firmware storage area, used to store the firmware of the memory; An update storage area for storing a boot program of the memory update firmware; and The mapping table storage area is used to store the data mapping table.

5. The memory according to claim 4, characterized in that: The power management module is used to supply power to the firmware storage area and the mapping table storage area respectively, and the power supplies to the firmware storage area and the mapping table storage area are in a normally-on state.

6. The memory according to claim 4, characterized in that: When the memory is updating its firmware, the power management module supplies power to the update storage area. After the memory firmware is updated, the power management module stops supplying power to the update storage area.

7. The memory according to claim 4, characterized in that: The total power P_NAND of the flash memory satisfies the following formula: P_NAND=Vccc*Iccc+Vccf*Iccf+Vcct*Icct+Vccd1*Iccd1+Vccd2*Iccd2+……+Vccdn*Iccdn; Among them, Vccc and Iccc represent the voltage and current supplied to the firmware storage area, Vccf and Iccf represent the voltage and current supplied to the update storage area, Vcct and Icct represent the voltage and current supplied to the mapping table storage area, Vccd1 and Iccd1, Vccd2 and Iccd2, ..., Vccdn and Iccdn represent the voltage and current supplied to the 1st, 2nd, ..., nth data storage areas, respectively.

8. A method for processing data in a memory, characterized in that: include: Responding to a write command sent by the host to obtain host data to be written, and sequentially obtaining the number of erase and write times of blocks in multiple data storage areas in the flash memory; When the number of erasure and write times of some blocks in a certain data storage area is less than an erasure and write threshold, power supply to the certain data storage area is turned on, and the host data is written into the corresponding blocks of the certain data storage area; When the number of erasure times of the blocks in all the data storage areas is greater than or equal to a certain limiting threshold, sequentially determining whether the number of erasure times of the blocks in the data storage areas is greater than or equal to a next limiting threshold, wherein the erasure threshold is divided into a plurality of limiting thresholds that increase in sequence; When the number of erasure and write times of some blocks in a certain data storage area is less than the next limited threshold, powering on the certain data storage area; Generate and save a data mapping table according to the mapping relationship between the host data and the blocks in the certain data storage area; When the erasure times of all blocks in the data storage area are greater than or equal to an erasure threshold, and / or when there is no read or write operation in the data storage area, power supply to the data storage area is turned off.

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