A server, an acceleration device and an acceleration card

Abstract

The present application discloses a server, an acceleration device and an acceleration card, which are applied in the field of computer technology. The server comprises a bus controller, an input-output management module, a device memory, a cache proxy module and an acceleration module. The bus controller is used to communicate and connect with the host, the cache proxy module and the input-output management module based on the second mode of the fast computing interconnect bus, so as to maintain cache consistency through the fast computing interconnect bus; the acceleration module is used to receive an interrupt signal from the host through the bus controller and the input-output management module after initialization is completed, and execute the corresponding computing task. In the process of executing the computing task, the cache proxy module is used to obtain the instructions and data used to complete the computing task from the device memory and / or the host memory, and after obtaining the computing result of the computing task, the cache proxy module is used to feed back the computing result to the host. By applying the scheme of the present application, an acceleration card supporting cache consistency is effectively realized.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a server, an acceleration device and an acceleration card. Background Art

[0002] Programmable accelerator cards are devices used to assist servers in accelerating computing and are widely used in deep learning, image processing, scientific computing, and other fields. Currently, mainstream programmable accelerator cards include GPU (Graphics Processing Unit) and FPGA (Field Programmable Gate Array) accelerator cards manufactured by different companies.

[0003] Most current FPGA-based accelerators use the PCIe (Peripheral Component Interconnectexpress, a high-speed serial computer expansion bus standard) solution. PCIe does not have cache consistency and is only efficient when transmitting large amounts of computing data. It has low bandwidth utilization when frequently accessing the accelerator memory in small granularity. In addition, some FPGA accelerator cards use both PCIe and UPI (Unified Parallel Interface) to communicate with the host processor. The corresponding hardware architecture provides cache consistency support, but UPI is a dedicated bus and does not have universal features.

[0004] In summary, how to implement an accelerator card that supports cache consistency is a technical problem that technical personnel in this field urgently need to solve. Summary of the invention

[0005] The object of the present invention is to provide a server, an acceleration device and an acceleration card to effectively implement an acceleration card that supports cache consistency.

[0006] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0007] In a first aspect, the present invention provides an acceleration card, comprising: a bus controller, an input / output management module, a device memory, a cache proxy module, and an acceleration module;

[0008] The bus controller is used to communicate with the host, the cache agent module and the input and output management module based on the second mode of the fast computing interconnect bus to maintain cache consistency through the fast computing interconnect bus;

[0009] The input / output management module is in communication with the cache proxy module and the bus controller; the cache proxy module is in communication with the bus controller, the acceleration module and the device memory;

[0010] The acceleration module is communicatively connected with the input / output management module and the cache proxy module, and is used for receiving an interrupt signal from the host through the bus controller and the input / output management module after initialization is completed, and executing a corresponding computing task. In the process of executing the computing task, the cache proxy module obtains instructions and data for completing the computing task from the device memory and / or the host memory, and after obtaining the computing result of the computing task, the cache proxy module and the bus controller are used to feed back the computing result to the host.

[0011] On the other hand, the input / output management module is also used to receive and process the read transaction stream and the write transaction stream from the host through the bus controller.

[0012] On the other hand, the input-output management module includes: a memory mapping unit, a multiplexing unit, a general output unit and an interrupt input unit;

[0013] The memory mapping unit is connected to the bus controller, the multiplexing unit, the universal output unit and the acceleration module respectively, and is used for, when receiving a read transaction stream from the host through the bus controller, sending feedback data corresponding to the read transaction stream to the bus controller through the multiplexing unit, so as to be fed back to the host through the bus controller; when receiving a write transaction stream from the host through the bus controller, sending the write transaction stream to the interrupt controller of the acceleration module based on the address of the write transaction stream, so that the acceleration module receives an interrupt signal, or sending the write transaction stream to the reset unit of the acceleration module through the universal output unit to reset the acceleration module;

[0014] The interrupt input unit is connected to the bus controller, the multiplexing unit and the acceleration module respectively, and is used to send the interrupt signal received from the acceleration module to the host through the multiplexing unit and the bus controller.

[0015] On the other hand, the input-output management module is also used to monitor the status of the acceleration module and feed back the status monitoring result to the host.

[0016] On the other hand, the cache proxy module is specifically used for:

[0017] When receiving an access request for accessing the device memory from the acceleration module, reading and writing the device memory based on the access mode of the accessed memory page to complete the access request;

[0018] The access mode includes a device priority mode and a host priority mode. In the device priority mode, the acceleration module directly accesses the device memory through the cache proxy module. In the host priority mode, the acceleration module accesses the device memory through the cache proxy module under the management of the host.

[0019] When an access request for accessing the device memory from the host is received through the bus controller, the device memory is read and written to complete the access request.

[0020] On the other hand, the cache proxy module is also used for:

[0021] When an access request for accessing the host memory issued by the acceleration module is received, the host memory is read and written to complete the access request.

[0022] On the other hand, the cache proxy module is further provided with a first cache and a second cache, wherein the first cache caches part of the data in the device memory, and the second cache caches part of the data in the host memory.

[0023] On the other hand, the input-output management module is also connected to the cache proxy module in communication, so that the host accesses the designated register in the cache proxy module through the input-output management module.

[0024] On the other hand, the input and output management module is also used for:

[0025] When an access request from the host is received through the bus controller, a designated register in the cache proxy module is accessed based on the access request to query the cache size of the cache proxy module or set the bias mode of the cache proxy module.

[0026] On the other hand, the acceleration module includes an acceleration processor and a reconfiguration module, and the acceleration processor is used to:

[0027] After the initialization is completed, an interrupt signal from the host is received through the bus controller and the input / output management module, and the reconfiguration module is controlled to perform a corresponding computing task. In the process of controlling the reconfiguration module to perform the computing task, the cache proxy module obtains instructions and data for completing the computing task from the device memory and / or the host memory, so as to control the reconfiguration module accordingly;

[0028] After obtaining the calculation result of the calculation task through the reconfiguration module, the calculation result is fed back to the host through the cache agent module and the bus controller.

[0029] On the other hand, the acceleration processor is provided with an instruction bus port and a data bus port, and the instruction bus port and the data bus port are both communicatively connected to the cache proxy module through an interconnection bus, so as to obtain instructions for completing the computing task through the instruction bus port, and obtain data for completing the computing task through the data bus port.

[0030] On the other hand, the reconfiguration module is a reconfiguration module with an adjustable hardware topology structure, so that the reconfiguration module is used to complete the current customized computing function.

[0031] On the other hand, the acceleration processor is further used for:

[0032] Upon receiving an interrupt signal from the host computer indicating configuration file update and sent by the input / output management module, the configuration file of the reconfiguration module stored in the device memory or in the host computer memory is updated online through the cache proxy module.

[0033] In a second aspect, the present invention provides an acceleration device, comprising: a host and one or more acceleration cards communicatively connected to the host, and any one of the acceleration cards is the acceleration card as described above.

[0034] In a third aspect, the present invention provides a server, comprising the acceleration device as described above.

[0035] By applying the technical solution provided in the embodiment of the present invention, considering that the CXL (Compute Express Link) bus solves the problems of PCIe in cache consistency and small-granularity memory access efficiency by adding Cache sub-protocol and Memory sub-protocol while retaining the PCIe characteristics, therefore, implementing the acceleration card through the Type 2 mode of CXL can ensure that cache consistency is maintained.

[0036] Specifically, the acceleration card of the present application includes: a bus controller, an input / output management module, a device memory, a cache proxy module and an acceleration module. The bus controller can communicate with the host, the cache proxy module and the input / output management module based on the second mode of the fast computing interconnect bus (i.e., the Type 2 mode of CXL), so that the acceleration card of the present application can maintain cache consistency through the CXL bus. The input / output management module is in communication with the cache proxy module and the bus controller. The cache proxy module is in communication with the bus controller, the acceleration module and the device memory, and can read and write the device memory. The acceleration module is in communication with the input / output management module and the cache proxy module. During the specific acceleration, the acceleration module needs to perform the corresponding computing task based on the interrupt signal received from the host sent by the input / output management module after the initialization is completed. In the process of executing the computing task, the cache proxy module can obtain the instructions and data used to complete the computing task from the device memory and / or the host memory, thereby realizing the processing of the computing task. Finally, after obtaining the calculation result of the computing task, the acceleration module can feed back the calculation result to the host through the cache proxy module and the bus controller, thereby completing the processing of the computing task.

[0037] It can be seen that the accelerator card of the present application can effectively implement the acceleration function and can maintain cache consistency through the CXL bus, that is, the present application solution effectively implements an accelerator card that supports cache consistency. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0039] Figure 1 A schematic diagram of the structure of an accelerator card provided in a specific embodiment of the present invention;

[0040] Figure 2 A schematic diagram of the structure of an acceleration card provided in another specific embodiment of the present invention;

[0041] Figure 3 A schematic diagram of the structure of an input and output management module according to a specific embodiment of the present invention;

[0042] Figure 4 The figure is a schematic diagram of four interfaces of a cache proxy module in a specific implementation manner of the present invention. DETAILED DESCRIPTION

[0043] The core of the present invention is to provide a server, an acceleration device and an acceleration card, which effectively realizes an acceleration card that supports cache consistency.

[0044] In order to enable those skilled in the art to better understand the scheme of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0045] Please refer to Figure 1 , Figure 1 The schematic diagram of the structure of an acceleration card of the present invention is shown, and the acceleration card may include: a bus controller 10, an input / output management module 20, a device memory D, a cache proxy module 30, and an acceleration module 40. The acceleration card may be implemented completely based on FPGA, or may be implemented by using ASIC (Application Specific Integrated Circuit) or other methods.

[0046] The bus controller 10 is used to communicate with the host, the cache agent module 30 and the input / output management module 20 based on the second mode of the fast computing interconnect bus to maintain cache consistency through the fast computing interconnect bus;

[0047] The input / output management module 20 is in communication with the cache proxy module 30 and the bus controller 10;

[0048] The cache proxy module 30 is in communication with the bus controller 10, the acceleration module 40 and the device memory D, and is used to read and write the device memory D;

[0049] The acceleration module 40 is communicatively connected with the input / output management module 20 and the cache proxy module 30, and is used to receive an interrupt signal from the host through the bus controller 10 and the input / output management module 20 after initialization is completed, and execute the corresponding computing task. In the process of executing the computing task, the cache proxy module 30 obtains instructions and data for completing the computing task from the device memory D and / or the host memory H. After obtaining the calculation result of the computing task, the calculation result is fed back to the host through the cache proxy module 30 and the bus controller 10.

[0050] Specifically, in the solution of the present application, a CXL Type 2 accelerator card is provided, which can be implemented based on FPGA, for example, and can perform flexible software and hardware programming, and can realize the decomposition of complex computing tasks. In addition, the accelerator card adds support for cache consistency, which can prevent inconsistencies during data access and ensure the correctness of the data. In addition, maintaining cache consistency can also reduce the overhead during data transmission and improve system performance. By effectively managing the data cache, unnecessary data transmission and access delays can be reduced, thereby improving the overall performance of the system.

[0051] The accelerator card of the present application adopts a CXL bus interface that supports cache consistency, and uses three sub-protocols, namely CXL.IO, CXL.MEM, and CXL.Cache, which is the Type 2 mode of CXL. Therefore, the bus controller 10 needs to communicate with the host, the cache agent module 30, and the input and output management module 20 based on the second mode of the fast computing interconnect bus (Type 2 mode of CXL), so that cache consistency can be maintained through the CXL bus.

[0052] The bus controller 10 implements the physical layer, arbitration multiplexing layer, data link layer and transaction layer of the CXL consistency protocol. The CXL controller may include a user interface and a serial interface. The serial interface supports CXL 1.1 / CXL2.0 and is compatible with x4, x8, and x16 modes. The user interface includes an IO sub-protocol transaction flow interface and a Cache sub-protocol and Memory sub-protocol transaction flow interface. The IO sub-protocol transaction flow interface is used for the control plane, and the Cache sub-protocol and Memory sub-protocol transaction flow interface is used for the data plane.

[0053] The input-output management module 20, also known as the IO management module, is communicatively connected to the cache proxy module 30 and the bus controller 10. When acceleration is started, an interrupt signal from the host can be received through the bus controller 10. When acceleration is completed, the interrupt signal can be fed back to the host through the bus controller 10.

[0054] Furthermore, in a specific embodiment of the present invention, the input / output management module 20 is also used to receive and process the read transaction flow and the write transaction flow from the host through the bus controller 10. This embodiment takes into account that the input / output management module 20 can process the read transaction flow and the write transaction flow from the host in addition to being used to implement the bidirectional interrupt mechanism between the host and the acceleration module 40.

[0055] The specific structure of the input and output management module 20 can be set and adjusted according to actual conditions, see Figure 2 and Figure 3 , Figure 2is a schematic diagram of the structure of an acceleration card in a specific implementation manner of the present invention, Figure 3 Schematic diagram of the structure of the input-output management module 20 in a specific implementation of the present invention. In a specific implementation of the present invention, the input-output management module 20 may specifically include: a memory mapping unit, a multiplexing unit, a general output unit and an interrupt input unit;

[0056] The memory mapping unit is connected to the bus controller 10, the multiplexing unit, the general output unit and the acceleration module 40 respectively, and is used for, when receiving a read transaction stream from the host through the bus controller 10, sending feedback data corresponding to the read transaction stream to the bus controller 10 through the multiplexing unit, so as to be fed back to the host through the bus controller 10; when receiving a write transaction stream from the host through the bus controller 10, sending the write transaction stream to the interrupt controller of the acceleration module 40 based on the address of the write transaction stream, so that the acceleration module 40 receives an interrupt signal, or sending the write transaction stream to the reset unit of the acceleration module 40 through the general output unit to reset the acceleration module 40;

[0057] The interrupt input unit is connected to the bus controller 10 , the multiplexing unit and the acceleration module 40 respectively, and is used to send the interrupt signal received from the acceleration module 40 to the host through the multiplexing unit and the bus controller 10 .

[0058] Specifically, the read transaction stream and the write transaction stream input to the input / output management module 20 can be converted into a memory-mapped bus in the memory mapping unit. For the read transaction stream from the host, the memory mapping unit can send the feedback data corresponding to the read transaction stream to the bus controller 10 through the multiplexing unit. In actual applications, the feedback data corresponding to the read transaction stream can be submitted to the bus controller 10 in the form of a Complete transaction stream through the multiplexing unit, and then fed back to the host.

[0059] When a write transaction stream originating from the host is received through the bus controller 10, the memory mapping unit needs to perform corresponding processing based on the address of the write transaction stream. For example, when the address is between 0 and x1, the memory mapping unit needs to send the write transaction stream directly to the interrupt controller of the acceleration module 40. For example, when the address is between x2 and xn, the memory mapping unit will send the write transaction stream to the reset port of the acceleration module 40 through the general output unit, so that the acceleration module 40 can be reset.

[0060] It can be seen that the general output unit is a slave device of the memory mapping unit, and the memory mapping unit reserves a certain address space for it (such as addresses x2 to xn in the above example). The read and write of registers in the address space will be controlled by the signal output by the general output unit, and the acceleration module 40 can be reset. In addition, for the signal output by the general output unit, in addition to resetting the acceleration module 40, other functions can be set according to actual needs, which does not affect the implementation of the present invention. Of course, the more functions are set, the larger the address space reserved by the memory mapping unit for the general output unit will be.

[0061] When the memory mapping unit sends the write transaction stream directly to the interrupt controller of the acceleration module 40, the specific signals sent are different, and the types of interrupts generated are also different. The acceleration module 40 can also send an interrupt to the input and output management module 20, specifically, it can be sent to the interrupt input unit, and the interrupt input unit can convert the interrupt signal sent by the acceleration module 40 into a memory write transaction message corresponding to the MSI (message signal interrupt) and send it to the multiplexing unit, and then send it to the host through the bus controller 10. This type of signal does not need to complete the response, so there is no need to receive the transaction stream returned by the host.

[0062] In addition, for the write transaction flow originating from the host, the memory mapping unit is usually configured not to submit a completion message to the bus controller 10, because the write transaction flow originating from the host is a reporting type transaction.

[0063] In a specific implementation of the present invention, the input / output management module 20 is also used to monitor the status of the acceleration module 40 and feed back the status monitoring result to the host.

[0064] This implementation takes into account that, in addition to being used to implement a bidirectional interrupt mechanism between the host and the acceleration module 40, the input / output management module 20 can also perform status monitoring of the acceleration module 40 and feed back the status monitoring results to the host, thereby improving the flexibility of the present application scheme and effectively meeting the host's requirements for status monitoring of the acceleration module 40 in some cases.

[0065] The cache proxy module 30 is connected to the bus controller 10, the acceleration module 40 and the device memory D in communication, and can read and write the device memory D. In the CXL interconnection system, the host and the Type2 device can share memory, that is, the host can access the device memory D of the acceleration card, and the acceleration card can also access the host memory H, but by default, the device memory D cannot be directly accessed by the acceleration module 40, but is managed by the host. The access process of the acceleration module 40 to the host memory H and the device memory D can be completed by the cache proxy module 30. In addition, when the acceleration module 40 needs to access the host memory H or the device memory D during the execution of a computing task, a request is sent to the cache proxy through the on-chip consistency bus (AMBA, ACE or other), and the cache proxy initiates a request to the host through the external consistency bus controller 10, and different target addresses correspond to different maintenance mechanisms.

[0066] In a specific embodiment of the present invention, the cache proxy module 30 is specifically used for:

[0067] When receiving an access request for accessing the device memory D from the acceleration module 40, reading and writing the device memory D are performed based on the access mode of the accessed memory page to complete the access request;

[0068] Among them, the access mode includes device priority mode and host priority mode. In device priority mode, the acceleration module 40 directly accesses the device memory D through the cache proxy module 30. In host priority mode, the acceleration module 40 accesses the device memory D through the cache proxy module 30 under the management of the host.

[0069] When an access request for accessing the device memory D from the host is received through the bus controller 10, the device memory D is read and written to complete the access request.

[0070] This implementation takes into account that when the cache proxy module 30 receives an access request for accessing the device memory D from the acceleration module 40, the device memory D can be read and written based on the access mode of the accessed memory page to complete the access request.

[0071] Specifically, if the accessed memory page is in host priority mode, the device memory D cannot be directly accessed by the acceleration module 40, but needs to be managed by the host. Therefore, the acceleration module 40 needs to access the device memory D through the cache proxy module 30 under the management of the host. For example, the cache proxy module 30 can initiate a D2H request to the host through the Cache sub-protocol of the CXL protocol, and the host initiates a memory read forwarding request through the Memory sub-protocol. After the cache proxy module 30 reads the memory read forwarding request, it accesses the device memory D to complete the entire request, that is, accesses the device memory D to complete the access request to access the device memory D issued by the acceleration module 40. If the access mode of the accessed memory page is device priority mode, the cache proxy module 30 can directly access the device memory D to complete the access request, that is, the acceleration module 40 can directly access the device memory D through the cache proxy module 30.

[0072] In addition to the need for the acceleration module 40 to access the device memory D, the host may need to access the device memory D through the cache proxy module 30. When the cache proxy module 30 receives an access request from the host to access the device memory D through the bus controller 10, that is, when the host initiates an H2D request to the cache proxy module 30, the cache proxy module 30 can read and write the device memory D to complete the access request from the host.

[0073] In a specific embodiment of the present invention, the cache proxy module 30 may also be used for:

[0074] When an access request to access the host memory H is received from the acceleration module 40, the host memory H is read and written to complete the access request.

[0075] In the above description, the acceleration module 40 accesses the device memory D, and the host accesses the device memory D, which can be implemented through the cache proxy module 30. In this embodiment, the acceleration module 40 can also access the host memory H through the cache proxy module 30. Figure 2 In the embodiment, the host specifically includes a host processor and a host memory H.

[0076] Specifically, when receiving an access request to access the host memory H from the acceleration module 40, the cache proxy module 30 initiates a D2H request to the host through the Cache subprotocol of the CXL protocol, and the host returns H2D data and H2D response in turn according to different situations. In addition, some scenarios may also issue H2D requests. For example, when the cache proxy module 30 initiates a write invalidation operation request to a specific host, after the host issues a write back request to the cache proxy module 30, the cache proxy module 30 will successively issue two D2H data (32 bytes each) to complete the 64-byte cache line write back, and then the host will write it to the host memory H and return a completion message to the cache proxy module 30.

[0077] Furthermore, a first cache and a second cache are also provided in the cache proxy module 30, wherein the first cache caches part of the data in the device memory D, and the second cache caches part of the data in the host memory H.

[0078] See also Figure 2 , Figure 2 The cache D shown in the cache proxy module 30 is the first cache, which caches part of the data in the device memory D. Figure 2 The cache H shown in the cache proxy module 30 is the second cache, which caches part of the data in the host memory H. That is to say, the cache proxy module 30 of this embodiment saves a partial backup of the host memory H and a partial backup of the device memory D. The setting of the first cache and the second cache of this embodiment is conducive to further improving the performance of the cache proxy module 30. In addition, it can be understood that the data content of the first cache and the second cache can be set and adjusted according to actual needs, but generally speaking, the recent hot data should be cached to effectively improve the performance of the cache proxy module 30.

[0079] In a specific implementation of the present invention, the input / output management module 20 is also connected to the cache proxy module 30 for communication, so that the host accesses a designated register in the cache proxy module 30 through the input / output management module 20 .

[0080] This implementation takes into account that the input / output management module 20 can also be connected to the cache proxy module 30. The cache proxy module 30 internally includes multiple control registers and status registers. The host can access the specified registers in the cache proxy module 30 through the input / output management module 20 to complete the corresponding functions.

[0081] For example, in a specific embodiment of the present invention, the input-output management module 20 is further used for:

[0082] When an access request from the host is received through the bus controller 10 , a designated register in the cache agent module 30 is accessed based on the access request to query the cache size of the cache agent module 30 or set the bias mode of the cache agent module 30 .

[0083] In this implementation, the host can send an access request to the input / output management module 20 through the bus controller 10. When the input / output management module 20 determines that the access address is the cache proxy module 30 based on the access request, it can access the specified register in the cache proxy module 30, for example, specifically query the cache size of the cache proxy module 30, or set the bias mode of the cache proxy module 30. In this implementation, the host accesses the specified register in the cache proxy module 30 through the IO sub-protocol of CXL based on the input / output management module 20, which can be converted into a memory-mapped bus by the memory mapping unit described above, thereby achieving access to the cache proxy module 30.

[0084] See also Figure 4 , is a schematic diagram of four interfaces of the cache proxy module 30 in a specific implementation. The first is a memory mapping interface M, which is used to connect to the device memory D. Specifically, an AXI (Advanced eXtensible Interface) bus or an Avalon bus can be used to access the device memory D. Whether it is an access request to the device memory D submitted by the host or an access request to the device memory D submitted by the acceleration module 40, the cache proxy module 30 can initiate a request to the device memory D through this interface.

[0085] Then there is the memory mapping interface S, which is used to connect the acceleration module 40, and can specifically adopt the AXI bus or the Avalon bus. The acceleration module 40 can send access requests to the cache proxy module 30 through this interface, including access requests for device memory D and access requests for host memory H.

[0086] Then there is the CPI interface connected to the bus controller 10. The CPI interface is mainly used to transmit memory transactions and cache transactions in the CXL transaction layer between the bus controller 10 and the cache agent module 30. Figure 4 In the figure, six transaction types of the Cahe sub-protocol are shown: D2H request, D2H response, D2H data, H2D request, H2D response, H2D data. And four transaction types of the Memory sub-protocol are shown: M2S with data request, M2S without data request, S2M with data response, S2M without data response.

[0087] Finally Figure 4The memory mapping interface C in the cache proxy module 30, namely the memory mapping interface CSR, as described above, includes multiple control and status registers, such as cache size, bias mode, etc. The host accesses the specified registers in the cache proxy module 30 through the IO sub-protocol of CXL based on the input and output management module 20, which can be specifically converted into a memory mapping bus by the memory mapping unit described above to achieve access to the cache proxy module 30.

[0088] After the initialization is completed, the acceleration module 40 can determine that the corresponding computing task needs to be executed based on the interrupt signal from the host sent by the input / output management module 20. After the execution is completed, the computing result can be fed back to the host through the cache proxy module 30 and the bus controller 10. It should be noted that the computing result can be directly fed back to the host through the cache proxy module 30 and the bus controller 10, or it can be temporarily stored in the device memory D. When the host initiates an H2D request later, the computing result is fed back to the host through the cache proxy module 30 and the bus controller 10.

[0089] The specific structure of the acceleration module 40 can be set and adjusted according to actual needs, but should be able to achieve the functional requirements of the acceleration module 40 of this application.

[0090] See also Figure 2 In a specific embodiment of the present invention, the acceleration module 40 includes an acceleration processor and a reconfiguration module, and the acceleration processor is used to:

[0091] After the initialization is completed, the bus controller 10 and the input / output management module 20 receive an interrupt signal from the host, and control the reconfiguration module to perform the corresponding computing task. In the process of controlling the reconfiguration module to perform the computing task, the cache proxy module 30 obtains the instructions and data used to complete the computing task from the device memory D and / or the host memory H, so as to control the reconfiguration module accordingly.

[0092] After the calculation result of the calculation task is obtained through the reconfiguration module, the calculation result is fed back to the host through the cache agent module 30 and the bus controller 10.

[0093] Specifically, in this embodiment, the acceleration processor plays a controlling role and is the processor core in the acceleration module 40. The instructions and data for completing the computing task from the device memory D and / or the host memory H are all completed by the acceleration processor. Under the control of the acceleration processor, the reconfiguration module will execute the corresponding computing task, and after obtaining the computing result of the computing task, the acceleration processor will feed back the computing result to the host through the cache proxy module 30.

[0094] The reconfiguration module is connected to the acceleration processor in communication, which can also be called a partially reconfigurable area. In actual applications, it can be composed of multiple custom instruction units, all of which can be connected to the acceleration processor using the same custom instruction bus. For example, in one scenario, the signals of the custom instruction bus include: clock and reset: basic signals. Input data 1: operand 1. Input data 2: operand 2. Output data: calculation result. Enable: When this signal is set, the reconfiguration module starts to capture input data 1 and input data 2 and starts calculation. Complete: When this signal is set, the custom logic calculation of the reconfiguration module is completed, and the output data is valid.

[0095] The logic part of the reconfiguration module can be implemented by RTL. Different applications correspond to different RTL descriptions, so the reconfiguration module can be in the configuration area of ​​FPGA. Users can flexibly upgrade the functions of this part of the hardware through the tool chain provided by the FPGA manufacturer.

[0096] In a specific embodiment of the present invention, the acceleration processor is provided with an instruction bus port and a data bus port, and both the instruction bus port and the data bus port are communicatively connected to the cache proxy module 30 through an interconnection bus, so as to obtain instructions for completing computing tasks through the instruction bus port, and obtain data for completing computing tasks through the data bus port.

[0097] In the scheme of the present application, as described above, in the process of controlling the reconfiguration module to perform computing tasks, the acceleration processor needs to obtain instructions and data for completing computing tasks from the device memory D and / or the host memory H through the cache proxy module 30. In this regard, this implementation method takes into account that the acceleration processor can be provided with an instruction bus port and a data bus port to obtain instructions and data respectively. In practical applications, the acceleration processor can adopt a reduced instruction set processor, and the instruction bus port and the data bus port of the acceleration processor are connected to the cache proxy module 30 through an interconnect bus. The interconnect bus can be used to implement memory mapping bus multiplexing between multiple Masters and Slaves. Figure 2 In the example, the interconnect bus includes a slave mode interface and two master mode interfaces. The slave is connected to the cache agent module 30. The master is connected to the instruction bus port and the data bus port of the acceleration processor, so that the acceleration processor can load instructions and data through the cache agent module 30.

[0098] In a specific implementation of the present invention, the reconfiguration module is a reconfiguration module with an adjustable hardware topology structure, so that the reconfiguration module is used to complete the current customized computing function.

[0099] In this implementation manner, the reconfiguration module specifically adopts a reconfiguration module with an adjustable hardware topology structure, so that the reconfiguration module can effectively complete the current customized computing function and is flexible and adjustable.

[0100] In a specific implementation of the present invention, the acceleration processor may also be used for:

[0101] Upon receiving an interrupt signal from the host indicating configuration file update sent by the input / output management module 20 , the configuration file of the reconfiguration module stored in the device memory D or the host memory H is updated online through the cache agent module 30 .

[0102] In this implementation, the configuration file of the reconfiguration module can be updated online, further improving the flexibility of the solution of the present application. Specifically, if the acceleration processor receives an interrupt signal from the host indicating the update of the configuration file sent by the input / output management module 20, the configuration file of the reconfiguration module stored in the device memory D or the host memory H can be updated online through the cache proxy module 30. For example, the cache proxy module 30 can obtain the instruction required to update the configuration file, and after executing the instruction, a corresponding access request will be initiated to update the configuration file stored in the specified location through the access request.

[0103] The accelerator card of the present application can assist the host in calculating. In order to realize the acceleration function of the accelerator card, in a specific embodiment of the present invention, the algorithm described in a high-level language is usually decomposed into the serial code of the acceleration processor and the RTL code of the reconfiguration module through a dedicated high-level synthesis technology, and the serial code is compiled into an executable file using a compiler matching the architecture of the acceleration processor, and the RTL code of the reconfiguration module is set as the configuration file of the reconfiguration module using a dedicated tool chain. In addition, the executable file of the above-mentioned acceleration processor and the configuration file of the reconfiguration module can be stored in the device memory D or the host memory H. In the process of the acceleration processor performing the calculation task, the corresponding file content can be read based on the current calculation task, that is, the corresponding instruction can be read, and the required data read can be combined to control the reconfiguration module to complete the calculation task. Through such a setting, the executable file of the acceleration processor and the configuration file of the reconfiguration module can be modified flexibly.

[0104] By applying the technical solution provided in the embodiment of the present invention, considering that the CXL (Compute Express Link) bus solves the problems of PCIe in cache consistency and small-granularity memory access efficiency by adding Cache sub-protocol and Memory sub-protocol while retaining the PCIe characteristics, therefore, implementing the acceleration card through the Type 2 mode of CXL can ensure that cache consistency is maintained.

[0105] Specifically, the acceleration card of the present application includes: a bus controller 10, an input / output management module 20, a device memory D, a cache proxy module 30, and an acceleration module 40. The bus controller 10 can be connected to the host, the cache proxy module 30, and the input / output management module 20 in communication based on the second mode of the fast computing interconnect bus (i.e., the Type 2 mode of CXL), so that the acceleration card of the present application can maintain cache consistency through the CXL bus. The input / output management module 20 is connected to the cache proxy module 30 and the bus controller 10 in communication. The cache proxy module 30 is connected to the bus controller 10, the acceleration module 40, and the device memory D in communication, and can read and write the device memory D. The acceleration module 40 is communicatively connected with the input / output management module 20 and the cache proxy module 30. During specific acceleration, the acceleration module 40 needs to execute the corresponding computing task based on the interrupt signal received from the host and sent by the input / output management module 20 after initialization. In the process of executing the computing task, the cache proxy module 30 can obtain the instructions and data used to complete the computing task from the device memory D and / or the host memory H, thereby realizing the processing of the computing task. Finally, after obtaining the calculation result of the computing task, the acceleration module 40 can feed back the calculation result to the host through the cache proxy module 30 and the bus controller 10, thereby completing the processing of the computing task.

[0106] It can be seen that the accelerator card of the present application can effectively implement the acceleration function and can maintain cache consistency through the CXL bus, that is, the present application solution effectively implements an accelerator card that supports cache consistency.

[0107] Corresponding to the above embodiment of the acceleration card, the embodiment of the present invention further provides an acceleration device, which can be referred to in correspondence with the above. The acceleration device may include: a host and one or more acceleration cards connected to the host for communication, and any one of the acceleration cards may be an acceleration card as in any of the above embodiments.

[0108] An embodiment of the present invention further provides a server, which may include the above-mentioned acceleration device.

[0109] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0110] Professionals may further realize that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to the function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention, and the description of the above embodiments is only used to help understand the technical solution and its core idea of ​​the present invention. It should be pointed out that for ordinary technicians in the technical field, without departing from the principle of the present invention, the present invention can also be improved and modified in a number of ways, and these improvements and modifications also fall within the scope of protection of the present invention.

Claims

1. An accelerator card, characterized in that: include: Bus controller, input and output management module, device memory, cache proxy module and acceleration module; The bus controller is used to communicate with the host, the cache agent module and the input and output management module based on the second mode of the fast computing interconnect bus to maintain cache consistency through the fast computing interconnect bus; The input / output management module is in communication with the cache proxy module and the bus controller; the cache proxy module is in communication with the bus controller, the acceleration module and the device memory; The acceleration module is in communication connection with the input / output management module and the cache proxy module, and is used for receiving an interrupt signal from the host through the bus controller and the input / output management module after initialization is completed, and executing a corresponding computing task; in the process of executing the computing task, the cache proxy module obtains instructions and data for completing the computing task from the device memory and / or the host memory; after obtaining the computing result of the computing task, the cache proxy module and the bus controller are used to feed back the computing result to the host; The cache proxy module is also used for: When receiving an access request for accessing the host memory from the acceleration module, reading and writing the host memory to complete the access request; The acceleration module includes an acceleration processor and a reconfiguration module, and the acceleration processor is used for: After the initialization is completed, an interrupt signal from the host is received through the bus controller and the input / output management module, and the reconfiguration module is controlled to perform a corresponding computing task. In the process of controlling the reconfiguration module to perform the computing task, the cache proxy module obtains instructions and data for completing the computing task from the device memory and / or the host memory, so as to control the reconfiguration module accordingly; After obtaining the calculation result of the calculation task through the reconfiguration module, feeding back the calculation result to the host through the cache proxy module and the bus controller; The acceleration processor is also used for: Based on receiving an interrupt signal from the host computer indicating an update of a configuration file sent by the input / output management module, the configuration file of the reconfiguration module stored in the device memory or in the host computer memory is updated online through the cache proxy module; Among them, the executable file of the acceleration processor and the configuration file of the reconfiguration module are stored in the device memory or the host memory. The executable file of the acceleration processor is: after decomposing the algorithm described in a high-level language into the serial code of the acceleration processor and the RTL code of the reconfiguration module, the serial code is compiled using a compiler matching the architecture of the acceleration processor to obtain an executable file; the configuration file of the reconfiguration module is: after setting the RTL code of the reconfiguration module using a dedicated tool chain, the configuration file of the reconfiguration module is obtained.

2. The accelerator card according to claim 1, characterized in that: The input / output management module is also used to receive and process the read transaction stream and the write transaction stream from the host through the bus controller.

3. The accelerator card according to claim 2, characterized in that: The input and output management module includes: a memory mapping unit, a multiplexing unit, a general output unit and an interrupt input unit; The memory mapping unit is connected to the bus controller, the multiplexing unit, the universal output unit and the acceleration module respectively, and is used for, when receiving a read transaction stream from the host through the bus controller, sending feedback data corresponding to the read transaction stream to the bus controller through the multiplexing unit, so as to be fed back to the host through the bus controller; when receiving a write transaction stream from the host through the bus controller, sending the write transaction stream to the interrupt controller of the acceleration module based on the address of the write transaction stream, so that the acceleration module receives an interrupt signal, or sending the write transaction stream to the reset unit of the acceleration module through the universal output unit to reset the acceleration module; The interrupt input unit is connected to the bus controller, the multiplexing unit and the acceleration module respectively, and is used to send the interrupt signal received from the acceleration module to the host through the multiplexing unit and the bus controller.

4. The accelerator card according to claim 2, characterized in that: The input-output management module is also used to monitor the status of the acceleration module and feed back the status monitoring result to the host.

5. The accelerator card according to claim 1, characterized in that: The cache proxy module is specifically used for: When receiving an access request for accessing the device memory from the acceleration module, reading and writing the device memory based on the access mode of the accessed memory page to complete the access request; The access mode includes a device priority mode and a host priority mode. In the device priority mode, the acceleration module directly accesses the device memory through the cache proxy module. In the host priority mode, the acceleration module accesses the device memory through the cache proxy module under the management of the host. When an access request for accessing the device memory from the host is received through the bus controller, the device memory is read and written to complete the access request.

6. The accelerator card according to claim 1, characterized in that: The cache proxy module is further provided with a first cache and a second cache, wherein the first cache caches part of the data in the device memory, and the second cache caches part of the data in the host memory.

7. The accelerator card according to claim 1, characterized in that: The input-output management module is also connected to the cache proxy module in communication, so that the host accesses the designated register in the cache proxy module through the input-output management module.

8. The accelerator card according to claim 7, characterized in that: The input and output management module is also used for: When an access request from the host is received through the bus controller, a designated register in the cache proxy module is accessed based on the access request to query the cache size of the cache proxy module or set the bias mode of the cache proxy module.

9. The accelerator card according to claim 1, characterized in that: The acceleration processor is provided with an instruction bus port and a data bus port, and the instruction bus port and the data bus port are both communicatively connected to the cache proxy module through an interconnection bus, so as to obtain instructions for completing the computing task through the instruction bus port, and obtain data for completing the computing task through the data bus port.

10. The accelerator card according to claim 1, characterized in that: The reconfiguration module is a reconfiguration module with an adjustable hardware topology structure, so that the reconfiguration module is used to complete the current customized computing function.

11. An acceleration device, characterized in that: The invention comprises: a host and one or more acceleration cards communicatively connected to the host, and any one of the acceleration cards is an acceleration card according to any one of claims 1 to 10.

12. A server, characterized in that: Comprising the acceleration device as claimed in claim 11.

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