Semiconductor structures and memories

Abstract

The present disclosure relates to the field of semiconductor technology and provides a semiconductor structure and memory. The semiconductor structure includes: a memory array having a first side and a second side opposite to each other along a first direction; a row decoder located on the first side and / or the second side and configured to receive a row address signal and generate a control signal to drive a word line driver corresponding to the control signal; the memory array includes N memory sub-blocks spaced apart along the first direction and N+1 word line drivers, each memory sub-block having a word line driver on each side along the first direction, where N is a positive integer; wherein the word line driver located between two adjacent memory sub-blocks is configured to drive a portion of the word lines of one of the two adjacent memory sub-blocks or a portion of the word lines of the other of the two adjacent memory sub-blocks. The present disclosure at least helps reduce the number of word line drivers, thereby helping to reduce the overall size of the semiconductor structure.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductors, and in particular to a semiconductor structure and a memory. Background Art

[0002] As semiconductor structures evolve toward higher integration and higher storage capacity, the storage area in dynamic random access memory (DRAM) is typically divided into two regions, one for storing high-order bytes and the other for storing low-order bytes. Row decoders drive these two regions. Because each storage sub-block in each region is controlled by two wordline drivers, the resulting large number of wordline drivers occupies a larger layout space for the entire storage area. Summary of the Invention

[0003] The embodiments of the present disclosure provide a semiconductor structure and a memory, wherein the number of word line drivers needs to be reduced and the overall size of the semiconductor structure needs to be reduced.

[0004] According to some embodiments of the present disclosure, on the one hand, an embodiment of the present disclosure provides a semiconductor structure, including: a memory array, the memory array having a first side and a second side relative to each other along a first direction; a row decoder, located on the first side and / or the second side, configured to receive a row address signal and generate a control signal to drive a word line driver corresponding to the control signal; the memory array includes N memory sub-blocks arranged at intervals along the first direction and N+1 word line drivers, each memory sub-block has a word line driver on both sides along the first direction, and N is a positive integer; wherein the word line driver located between two adjacent memory sub-blocks is configured to drive part of the word lines of one of the two adjacent memory sub-blocks or part of the word lines of the other of the two adjacent memory sub-blocks.

[0005] In some embodiments, the storage sub-block located between two adjacent word line drivers is a target storage sub-block, one of the two word line drivers located on both sides of the target storage sub-block drives the odd-bit word lines in the target storage sub-block, and the other of the two word line drivers located on both sides of the target storage sub-block drives the even-bit word lines in the target storage sub-block.

[0006] In some embodiments, the semiconductor structure further includes: a plurality of the memory arrays arranged at intervals along a second direction, the first direction and the second direction intersect, and the plurality of memory arrays share the row decoder.

[0007] In some embodiments, the semiconductor structure further includes: a plurality of sense amplifiers, each of the sense amplifiers being located between two adjacent storage sub-blocks along the second direction.

[0008] In some embodiments, the two adjacent storage arrays along the second direction are a storage array group, and the storage array group includes: a first transmission line extending along the first direction, configured to receive the control signal and drive at least part of the word line drivers located in the storage array group according to the control signal; a second transmission line extending along the first direction, configured to receive the control signal and drive the remaining word line drivers located in the storage array group according to the control signal; a third transmission line extending along the second direction, configured to electrically connect the first transmission line and the word line driver through the third transmission line, or to electrically connect the second transmission line and the word line driver through the third transmission line.

[0009] In some embodiments, the memory array group includes a first memory array and a second memory array, and along the first direction, the first memory array includes a first sub-memory array and a second sub-memory array, and the second memory array includes a third sub-memory array and a fourth sub-memory array, and the first sub-memory array is opposite to the third sub-memory array in the second direction, and the second sub-memory array is opposite to the fourth sub-memory array in the second direction; the first transmission line drives at least part of the word line drivers located in the memory array group according to the control signal, including driving the word line drivers in both the first sub-memory array and the third sub-memory array according to the control signal; the second transmission line drives the remaining word line drivers located in the memory array group according to the control signal, including driving the word line drivers in both the second sub-memory array and the fourth sub-memory array according to the control signal.

[0010] In some embodiments, the row decoder is located on the first side or the second side, the first sub-memory array and the third sub-memory array are located on the side close to the row decoder, and the second sub-memory array and the fourth sub-memory array are located on the side away from the row decoder; the first transmission line and the M+1 third transmission lines corresponding to the first sub-memory array are jointly configured to realize the electrical connection between the M+1 word line drivers in the first sub-memory array and the M+1 word line drivers in the third sub-memory array and the row decoder; the second transmission line and the NM third transmission lines corresponding to the fourth sub-memory array are jointly configured to realize the electrical connection between the NM word line drivers in the second sub-memory array and the NM word line drivers in the fourth sub-memory array and the row decoder, where M is a positive integer less than N.

[0011] In some embodiments, the row decoder includes: the first sub-row decoder located on the first side and the second sub-row decoder located on the second side, the first sub-storage array and the third sub-storage array are located on a side close to the first sub-row decoder, and the second sub-storage array and the fourth sub-storage array are located on a side close to the second sub-row decoder; the first transmission line is electrically connected to the first sub-row decoder, and the first transmission line and the M+1 third transmission lines corresponding to the first sub-storage array are jointly configured to realize the electrical connection between the M+1 word line drivers in the first sub-storage array and the M+1 word line drivers in the third sub-storage array and the first sub-row decoder; the second transmission line is electrically connected to the second sub-row decoder, and the second transmission line and the NM third transmission lines corresponding to the fourth sub-storage array are jointly configured to realize the electrical connection between the NM word line drivers in the second sub-storage array and the NM word line drivers in the fourth sub-storage array and the second sub-row decoder, where M is a positive integer less than N.

[0012] In some embodiments, N is an even number, and M is

[0013] In some embodiments, the third transmission line and the first transmission line are in different layers, and the third transmission line and the second transmission line are in different layers.

[0014] In some embodiments, the first transmission line and the second transmission line are disposed on the same layer.

[0015] In some embodiments, the control signal is transmitted to one of the multiple word line drivers in the storage array group via the first transmission line and the third transmission line, or the control signal is transmitted to one of the remaining multiple word line drivers in the storage array group via the second transmission line and the third transmission line; wherein, the longest transmission path among the multiple transmission paths transmitted via the first transmission line and the third transmission line is the first transmission path, the longest transmission path among the multiple transmission paths transmitted via the second transmission line and the third transmission line is the second transmission path, and the ratio of the parasitic capacitance resistance value generated by the first transmission path to the parasitic capacitance resistance value generated by the second transmission path is 0.9 to 1.1.

[0016] In some embodiments, the storage array includes a first storage block and a second storage block arranged at intervals along the first direction, the first storage block includes A storage sub-blocks, the second storage block includes NA storage sub-blocks, and A is a positive integer less than N; wherein, the first storage block is configured to store high-order bytes, and the second storage block is configured to store low-order bytes.

[0017] In some embodiments, the first storage block and the second storage block include the same number of storage sub-blocks.

[0018] In some embodiments, the storage sub-block includes a plurality of storage cells arranged in an array, and the storage cell includes a transistor and a capacitor electrically connected to each other, the gate of the transistor is electrically connected to the word line, the word line is electrically connected to the word line driver, the drain of the transistor is electrically connected to the bit line, one end of the capacitor is electrically connected to the source of the transistor, and the other end of the capacitor is connected to a reference voltage.

[0019] According to some embodiments of the present disclosure, another aspect of the present disclosure further provides a memory, comprising the semiconductor structure as described in any one of the above items.

[0020] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0021] The row decoder is set on the side of the memory array. The word line driver located between two adjacent memory sub-blocks can drive the two memory sub-blocks. The word line driver located at the edge of the memory array can drive an adjacent memory sub-block. In this way, the driving of N memory sub-blocks in the memory array can be achieved through N+1 word line drivers, which is beneficial to reducing the number of word line drivers required to drive the memory array, thereby helping to reduce the overall size of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplifications do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the figures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0023] Figure 1 and Figure 2 Two schematic diagrams of three-dimensional structures of a semiconductor structure provided in one embodiment of the present disclosure;

[0024] Figure 3 A schematic diagram of a local circuit of a memory array in a semiconductor structure provided by an embodiment of the present disclosure;

[0025] Figure 4 and Figure 5 Two other schematic diagrams of three-dimensional structures of a semiconductor structure provided by an embodiment of the present disclosure;

[0026] Figure 6 A schematic diagram of another three-dimensional structure of a semiconductor structure provided by an embodiment of the present disclosure;

[0027] Figure 7 for Figure 6 A schematic top view of a memory array group, a sense amplifier associated with the memory array group, and a local row decoder;

[0028] Figure 8 A schematic diagram of another three-dimensional structure of a semiconductor structure provided by an embodiment of the present disclosure;

[0029] Figure 9 for Figure 8 A schematic top view of the structure of a memory array group, a sense amplifier associated with the memory array group, and a local row decoder. DETAILED DESCRIPTION

[0030] As known from the background art, the overall size of semiconductor structures needs to be reduced.

[0031] Analysis revealed that in dynamic random access memory (DRAM), the storage area is generally divided into two regions, one for storing high-order bytes and the other for storing low-order bytes. Row decoders drive these two regions. Each storage sub-block in these two regions is controlled by two wordline drivers. Therefore, to drive each storage sub-block in the storage area, at least two more wordline drivers are required than the number of storage sub-blocks. This results in a large number of wordline drivers and a larger overall storage area layout space.

[0032] The present disclosure provides a semiconductor structure and a memory. In the semiconductor structure, a row decoder is arranged on the side of a memory array. A word line driver located between two adjacent memory sub-blocks can drive the two memory sub-blocks, and a word line driver located at the edge of the memory array can drive an adjacent memory sub-block. In this way, N+1 word line drivers can be used to drive N memory sub-blocks in the memory array, which helps reduce the number of word line drivers required to drive the memory array, thereby helping to reduce the overall size of the semiconductor structure.

[0033] The following describes various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to help readers better understand the embodiments of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the embodiments of the present disclosure can be implemented.

[0034] An embodiment of the present disclosure provides a semiconductor structure, which will be described in detail below with reference to the accompanying drawings. Figure 1 and Figure 2 Two schematic diagrams of three-dimensional structures of a semiconductor structure provided in one embodiment of the present disclosure;

[0035] Figure 3 A schematic diagram of a local circuit of a memory array in a semiconductor structure provided by an embodiment of the present disclosure; Figure 4 and Figure 5 Two other schematic diagrams of three-dimensional structures of a semiconductor structure provided by an embodiment of the present disclosure; Figure 6 A schematic diagram of another three-dimensional structure of a semiconductor structure provided by an embodiment of the present disclosure; Figure 7 for Figure 6 A schematic top view of a memory array group, a sense amplifier associated with the memory array group, and a local row decoder; Figure 8 A schematic diagram of another three-dimensional structure of a semiconductor structure provided by an embodiment of the present disclosure; Figure 9 for Figure 8A schematic top view of the structure of a memory array group, a sense amplifier associated with the memory array group, and a local row decoder.

[0036] refer to Figure 1 and Figure 2 The semiconductor structure includes: a memory array 100, wherein the memory array 100 has a first side a and a second side b opposite to each other along a first direction X; a row decoder 101, located on the first side a and / or the second side b, and configured to receive a row address signal and generate a control signal to drive a word line driver 102 corresponding to the control signal; the memory array 100 includes N memory sub-blocks 110 and N+1 word line drivers 102 arranged at intervals along the first direction X, wherein each memory sub-block 110 has a word line driver 102 on both sides along the first direction X, where N is a positive integer; wherein the word line driver 102 located between two adjacent memory sub-blocks 110 is configured to drive a portion of word lines of one of the two adjacent memory sub-blocks 110 or a portion of word lines of the other of the two adjacent memory sub-blocks 110.

[0037] It should be noted that Figure 1 In the example, the row decoder 101 is only located at the second side b of the memory array 100. Figure 2 In the example, the row decoder 101 is respectively located at the first side a and the second side b of the memory array 100 . In actual applications, the row decoder 101 may also be located only at the first side a of the memory array 100 .

[0038] It can be understood that the row decoder 101 receives a row address signal, generates a control signal based on the row address signal, and then transmits the control signal to the word line driver 102 corresponding to the control signal via a data transmission line. Subsequently, the word line driver 102 controls the opening or closing of the word line in the storage sub-block 110 corresponding to the word line driver 102 based on the received control signal.

[0039] In addition, the row decoder 101 is arranged on the side of the memory array 100, and the word line driver 102 located between two adjacent memory sub-blocks 110 can drive the two memory sub-blocks 110. The word line driver 102 located at the edge of the memory array 100 can drive an adjacent memory sub-block 110. In this way, the driving of N memory sub-blocks 110 in the memory array 100 can be achieved through N+1 word line drivers 102, which is beneficial to reducing the number of word line drivers 102 required to drive the memory array 100, thereby helping to reduce the overall size of the semiconductor structure.

[0040] It should be noted that Figure 1 and Figure 2The relative position relationship between the storage sub-block 110 and the word line driver 102 in the memory array 100 is only drawn in a module-like manner, without illustrating the specific structure of the storage sub-block 110 and the word line driver 102. Figure 1 and Figure 2 In the figure, only the relative position relationship between the memory array 100 and the row decoder 101 is drawn in a modular manner, and the specific structure of the row decoder 101 is not illustrated.

[0041] An embodiment of the present disclosure will be described in more detail below with reference to the accompanying drawings.

[0042] In some embodiments, reference Figure 1 and Figure 2 , the storage sub-block 110 located between two adjacent word line drivers 102 is the target storage sub-block, one of the two word line drivers 102 located on both sides of the target storage sub-block drives the odd-bit word lines in the target storage sub-block, and the other of the two word line drivers 102 located on both sides of the target storage sub-block drives the even-bit word lines in the target storage sub-block.

[0043] It can be understood that any storage sub-block 110 can be used as a target storage sub-block.

[0044] In other words, for a word line driver 102 located between two adjacent memory sub-blocks 110, the word line driver 102 can be used to drive both odd-bit word lines in the memory sub-block 110 located on one side and odd-bit word lines in the memory sub-block 110 located on the other side. In one example, the memory sub-block 110 located on one side refers to the memory sub-block 110 located to the left of the word line driver 102 along the first direction X; the memory sub-block 110 located on the other side refers to the memory sub-block 110 located to the right of the word line driver 102 along the first direction X. Furthermore, the word line driver 102 closest to the first side a and the second side b are both used to drive either the even-bit word lines or the odd-bit word lines in the adjacent memory sub-block 110.

[0045] In this way, all word lines in the N storage sub-blocks 110 can be driven by N+1 word line drivers 102 , thereby reducing the number of word line drivers 102 required to drive the storage array 100 and reducing the overall size of the semiconductor structure.

[0046] In some embodiments, reference Figure 1 and Figure 2The memory array 100 may include a first memory block 130 and a second memory block 140 arranged at intervals along a first direction X, the first memory block 130 includes A memory sub-blocks 110, the second memory block 140 includes NA memory sub-blocks 110, and A is a positive integer less than N; wherein the first memory block 130 is configured to store high-order bytes, and the second memory block 140 is configured to store low-order bytes.

[0047] In some embodiments, the first storage block 130 and the second storage block 140 include the same number of storage sub-blocks 110, that is, N is an even number, and A is half of N. This helps ensure that the storage array 100 can effectively store high-order bytes and low-order bytes with the same number of bits, avoids redundancy in storage sub-blocks 110 storing high-order bytes or low-order bytes, and improves the utilization of storage sub-blocks 110. In other embodiments, the first storage block 130 and the second storage block 140 may also include different numbers of storage sub-blocks 110.

[0048] In some embodiments, reference Figure 3 The storage sub-block 110 may include a plurality of storage cells 150 arranged in an array. The storage cell 150 includes a transistor 160 and a capacitor 170 electrically connected to each other. The gate of the transistor 160 is electrically connected to the word line WL, the word line WL is electrically connected to the word line driver 102, the drain of the transistor 160 is electrically connected to the bit line BL, one end of the capacitor 170 is electrically connected to the source of the transistor 160, and the other end of the capacitor 170 is connected to the reference voltage.

[0049] It should be noted that Figure 3 The memory sub-block 110 is described by taking only four memory cells 150 arranged in an array as an example. An embodiment of the present disclosure does not limit the number of memory cells 150 specifically included in the memory sub-block 110.

[0050] In some embodiments, reference Figure 4 The semiconductor structure may further include: a plurality of memory arrays 100 spaced apart along a second direction Y, wherein the first direction X and the second direction Y intersect, and the plurality of memory arrays 100 share a row decoder 101. It will be appreciated that after receiving a row address signal, the row decoder 101 may generate a control signal based on the row address signal and determine which word line driver 102 in which memory array 100 the control signal should be transmitted to, and then transmit the control signal to the word line driver 102 corresponding to the address signal via a data transmission line.

[0051] In some embodiments, in conjunction with reference Figure 1 and Figure 4, multiple memory arrays 100 form a whole, denoted as a memory block, and the row decoder 101 controls any word line driver 102 in the memory block. Each memory array 100 may include a first memory block 130 and a second memory block 140 arranged at intervals along a first direction X. The first memory block 130 includes A memory sub-blocks 110, and the second memory block 140 includes NA memory sub-blocks 110, where A is a positive integer less than N. It is understood that the first memory blocks 130 in the multiple memory arrays 100 can all be configured to store high-order bytes, and the second memory blocks 140 in the multiple memory arrays 100 can all be configured to store low-order bytes.

[0052] In some embodiments, reference Figure 5 The semiconductor structure may further include: a plurality of sense amplifiers 103 , each sense amplifier 103 being located between two adjacent storage sub-blocks 110 along the second direction Y.

[0053] It is understood that the memory sub-block 110 includes a plurality of memory cells 150 arranged in an array (see Figure 3 ), and each memory cell 150 can be accessed via a memory address including a row address signal and a column address signal, wherein the row address signal is processed by the row decoder 101. When the word line WL corresponding to the row address signal is selected or activated (refer to Figure 3 ), and after selecting or activating the corresponding bit line BL via the column address signal to determine a certain memory cell 150 for a read operation, the data of the certain memory cell 150 is transferred to the sense amplifier 103, and then the data is read from the sense amplifier 103.

[0054] In some embodiments, reference Figures 6 to 9 Two memory arrays 100 adjacent to each other along the second direction Y constitute a memory array group 120. The memory array group 120 may include: a first transmission line 104 extending along the first direction X, configured to receive a control signal generated by a row decoder 101 and drive at least some of the word line drivers 102 in the memory array group 120 according to the control signal; a second transmission line 105 extending along the first direction X, configured to receive a control signal generated by the row decoder 101 and drive the remaining word line drivers 102 in the memory array group 120 according to the control signal; and a third transmission line 106 extending along the second direction Y, configured to electrically connect the first transmission line 104 and the word line driver 102 via the third transmission line 106, or to electrically connect the second transmission line 105 and the word line driver 102 via the third transmission line 106.

[0055] It is understood that the third transmission line 106 is electrically connected to the word line driver 102, and the embodiment of the present disclosure does not limit the specific manner of the electrical connection between the third transmission line 106 and the word line driver 102. In one example, the third transmission line 106 can be located on at least a portion of the top surface of two adjacent word line drivers 102 in the memory array group 120 along the second direction Y.

[0056] This facilitates transmission of control signals in the first transmission line 104 in the second direction Y via the third transmission line 106, and transmission of control signals in the second transmission line 105 in the second direction Y via the third transmission line 106. This facilitates preventing the first transmission line 104 and / or the second transmission line 105 from traversing the entire memory array 100 along the first direction X, and facilitates reducing the length of the first transmission line 104 and / or the second transmission line 105 in the first direction X, thereby facilitating reduction of the effects of parasitic capacitance and resistance on the control signals when transmitted in the first transmission line 104 and / or the effects of parasitic capacitance and resistance on the control signals when transmitted in the second transmission line 105. Furthermore, the reduced length of the first transmission line 104 and / or the second transmission line 105 in the first direction X facilitates reduction of the space occupied by the first transmission line 104 and / or the second transmission line 105 in the semiconductor structure, thereby increasing the space available for other signal transmission lines in the semiconductor structure, thereby providing more layout space for other signal transmission lines and thereby providing a wider variety of layout configurations for other signal transmission lines.

[0057] In some embodiments, reference Figure 7 or Figure 9 The storage array group 120 includes a first storage array 121 and a second storage array 122. Along the first direction X, the first storage array 121 includes a first sub-storage array 131 and a second sub-storage array 141, and the second storage array 122 includes a third sub-storage array 132 and a fourth sub-storage array 142. The first sub-storage array 131 and the third sub-storage array 132 are opposite to each other in the second direction Y, and the second sub-storage array 141 and the fourth sub-storage array 142 are opposite to each other in the second direction Y.

[0058] It should be noted that the first sub-storage array 131 and the third sub-storage array 132 are directly opposite in the second direction Y, which means that, along a projection plane perpendicular to the second direction Y, the orthographic projection of the first sub-storage array 131 on the projection plane coincides with the orthographic projection of the third sub-storage array 132 on the projection plane; the second sub-storage array 141 and the fourth sub-storage array 142 are directly opposite in the second direction Y, which means that, along a projection plane perpendicular to the second direction Y, the orthographic projection of the second sub-storage array 141 on the projection plane coincides with the orthographic projection of the fourth sub-storage array 142 on the projection plane.

[0059] Furthermore, the first transmission line 104 drives at least some of the wordline drivers 102 in the memory array group 120 based on the control signal, including driving the wordline drivers 102 in both the first sub-memory array 131 and the third sub-memory array 132 based on the control signal. That is, the control signal transmitted by the first transmission line 104 passes through at least the first sub-memory array 131 and the third sub-memory array 132. The second transmission line 105 drives the remaining wordline drivers 102 in the memory array group 120 based on the control signal, including driving the wordline drivers 102 in both the second sub-memory array 141 and the fourth sub-memory array 142 based on the control signal. That is, the control signal transmitted by the second transmission line 105 passes through at least the second sub-memory array 141 and the fourth sub-memory array 142. It will be understood that, whether the control signal is transmitted via the first transmission line 104 and the third transmission line 106 or via the second transmission line 105 and the third transmission line 106, the transmission path of the control signal can extend along either the first direction X or the second direction Y.

[0060] The positional relationship between the first transmission line 104 and the second transmission line 105 and the storage array group 120 is described in detail below through two embodiments.

[0061] In some embodiments, the row decoder 101 is located on the first side a or the second side b, the first sub-memory array 131 and the third sub-memory array 132 are located on a side close to the row decoder 101, and the second sub-memory array 141 and the fourth sub-memory array 142 are located on a side away from the row decoder 101; the first transmission line 104 and the M+1 third transmission lines 106 corresponding to the first sub-memory array 131 are jointly configured to realize the electrical connection between the M+1 word line drivers 102 in the first sub-memory array 131 and the M+1 word line drivers 102 in the third sub-memory array 132 and the row decoder 101; the second transmission line 105 and the NM third transmission lines 106 corresponding to the fourth sub-memory array 142 are jointly configured to realize the electrical connection between the NM word line drivers 102 in the second sub-memory array 141 and the NM word line drivers 102 in the fourth sub-memory array 142 and the row decoder 101, where M is a positive integer less than N.

[0062] It can be understood that the first transmission line 104 and the M+1 third transmission lines 106 corresponding to the first sub-memory array 131 constitute a transmission path for the control signal in the first sub-memory array 131 and the third sub-memory array 132, that is, the M+1 word line drivers 102 in the first sub-memory array 131 and the M+1 word line drivers 102 in the third sub-memory array 132 can be electrically connected to the row decoder 101 through the first transmission line 104 and the M+1 third transmission lines 106.

[0063] In addition, the second transmission line 105 and the NM third transmission lines 106 corresponding to the fourth sub-memory array 142 constitute a transmission path for the control signal in the second sub-memory array 141 and the fourth sub-memory array 142, that is, the NM word line drivers 102 in the second sub-memory array 141 and the NM word line drivers 102 in the fourth sub-memory array 142 can be electrically connected to the row decoder 101 through the second transmission line 105 and the NM third transmission lines 106.

[0064] In one example, continue with reference Figure 6 and Figure 7 The semiconductor structure may further include: a plurality of conductive plugs 107, part of the conductive plugs 107 contacting and connecting the first transmission line 104 and the third transmission line 106, and the remaining conductive plugs 107 contacting and connecting the second transmission line 105 and the third transmission line 106, and the conductive plugs 107 and the third transmission lines 106 correspond one to one.

[0065] It is understandable that the third transmission line 106 is mainly used to achieve electrical connection between the first transmission line 104 and the word line driver 102 through the conductive plug 107 , or to achieve electrical connection between the second transmission line 105 and the word line driver 102 through the conductive plug 107 .

[0066] It should be noted that Figure 6 and Figure 7 In the examples, the row decoder 101 is located only on the second side b. In actual applications, the row decoder 101 may also be located only on the first side a. Figure 6 and Figure 7 In the figure, the first transmission line 104 and the second transmission line 105 are both drawn in perspective. Figure 7 for Figure 6 FIG. 1 is a top view of a memory array group 120, a sense amplifier 103 associated with the memory array group 120, and a local row decoder 101. In order to clearly illustrate the memory array 100 and the memory array group 120, Figure 6 In the figure, the memory sub-blocks 110 and the word line drivers 102 included in the memory array 100 and the memory array group 120 are framed by dashed boxes of different sizes; in order to clearly illustrate the first memory array 121, the second memory array 122, the first sub-memory array 131, the second sub-memory array 141, the third sub-memory array 132 and the fourth sub-memory array 142, Figure 7 In the figure, the memory sub-blocks 110 and the word line drivers 102 included in the corresponding memory array are framed by dashed boxes of different sizes.

[0067] It is understood that the first transmission line 104 does not need to traverse the entire memory array 100 in the first direction X. This helps reduce the length of the first transmission line 104 in the first direction X, thereby reducing the effects of parasitic capacitance and resistance on control signals transmitted through the first transmission line 104. Furthermore, it helps reduce the space occupied by the first transmission line 104 in the semiconductor structure, thereby providing more layout space for other signal transmission lines and a variety of layout configurations. Furthermore, by adding the third transmission line 106, while reducing the length of the first transmission line 104 in the first direction X, each word line driver 102 in the memory array group 120 can be electrically connected to the row decoder 101.

[0068] In practical applications, the second transmission line 105 may drive M+1 word line drivers 102 in the first sub-storage array 131 and the third sub-storage array 132, and the first transmission line 104 may drive NM word line drivers 102 in the second sub-storage array 141 and the fourth sub-storage array 142, where M is a positive integer less than N.

[0069] In other embodiments, reference Figure 8 and Figure 9 The row decoder 101 may include: a first sub-row decoder 101a located at the first side a and a second sub-row decoder 101b located at the second side b, a first sub-storage array 131 and a third sub-storage array 132 located on a side close to the first sub-row decoder 101a, and a second sub-storage array 141 and a fourth sub-storage array 142 located on a side close to the second sub-row decoder 101b; a first transmission line 104 is electrically connected to the first sub-row decoder 101a, and the first transmission line 104 and the M+1 third transmission lines 106 corresponding to the first sub-storage array 131 are configured together to implement the first sub-row decoder 101a. The M+1 word line drivers 102 in the memory array 131 and the M+1 word line drivers 102 in the third sub-memory array 132 are electrically connected to the first sub-row decoder 101a; the second transmission line 105 is electrically connected to the second sub-row decoder 101b, and the second transmission line 105 and the NM third transmission lines 106 corresponding to the fourth sub-memory array 142 are configured together to realize the electrical connection between the NM word line drivers 102 in the second sub-memory array 141 and the NM word line drivers 102 in the fourth sub-memory array 142 and the second sub-row decoder 101b, where M is a positive integer less than N.

[0070] It can be understood that the first transmission line 104 and the M+1 third transmission lines 106 corresponding to the first sub-memory array 131 constitute a transmission path for the control signal in the first sub-memory array 131 and the third sub-memory array 132, that is, the M+1 word line drivers 102 in the first sub-memory array 131 and the M+1 word line drivers 102 in the third sub-memory array 132 can be electrically connected to the first sub-row decoder 101a through the first transmission line 104 and the M+1 third transmission lines 106.

[0071] In addition, the second transmission line 105 and the NM third transmission lines 106 corresponding to the fourth sub-memory array 142 constitute a transmission path for the control signal in the second sub-memory array 141 and the fourth sub-memory array 142, that is, the NM word line drivers 102 in the second sub-memory array 141 and the NM word line drivers 102 in the fourth sub-memory array 142 can be electrically connected to the second sub-row decoder 101b through the second transmission line 105 and the NM third transmission lines 106.

[0072] In one example, continue with reference Figure 8 and Figure 9 The semiconductor structure may further include: a plurality of conductive plugs 107, part of the conductive plugs 107 contacting and connecting the first transmission line 104 and the third transmission line 106, and the remaining conductive plugs 107 contacting and connecting the second transmission line 105 and the third transmission line 106, and the conductive plugs 107 and the third transmission lines 106 correspond one to one.

[0073] It can be understood that the first transmission line 104 does not need to cross the entire memory array 100 in the first direction X, which is beneficial to reducing the length of the first transmission line 104 in the first direction X, thereby reducing the influence of parasitic capacitance and resistance on the control signal when it is transmitted in the first transmission line 104, and reducing the space occupied by the first transmission line 104 in the semiconductor structure, which is beneficial to providing a larger layout space for other signal transmission lines, thereby providing more layout forms for other signal transmission lines; the second transmission line 105 does not need to cross the entire memory array 100 in the first direction X, which is beneficial to reducing the length of the second transmission line 105 in the first direction X, thereby reducing the influence of parasitic capacitance and resistance on the control signal when it is transmitted in the second transmission line 105, and reducing the space occupied by the second transmission line 105 in the semiconductor structure, thereby providing a larger layout space for other signal transmission lines, thereby providing more layout forms for other signal transmission lines. Furthermore, by adding the third transmission line 106 , each word line driver 102 in the memory array group 120 can be electrically connected to the row decoder 101 while the lengths of the first transmission line 104 and the second transmission line 105 in the first direction X are reduced.

[0074] It should be noted that, in order to illustrate the conductive plug 107, Figure 8 and Figure 9 In the figure, the first transmission line 104 and the second transmission line 105 are both drawn in perspective. Figure 9 for Figure 8 FIG. 1 is a top view of a memory array group 120, a sense amplifier 103 associated with the memory array group 120, and a local row decoder 101. In order to clearly illustrate the memory array 100 and the memory array group 120, Figure 8 In the figure, the memory sub-blocks 110 and the word line drivers 102 included in the memory array 100 and the memory array group 120 are framed by dashed boxes of different sizes; in order to clearly illustrate the first memory array 121, the second memory array 122, the first sub-memory array 131, the second sub-memory array 141, the third sub-memory array 132 and the fourth sub-memory array 142, Figure 9 In the figure, the memory sub-blocks 110 and the word line drivers 102 included in the corresponding memory array are framed by dashed boxes of different sizes.

[0075] In practical applications, the first transmission line 104 may be electrically connected to the second sub-row decoder 101b, and the first transmission line 104 drives the M+1 word line drivers 102 in the second sub-storage array 141 and the fourth sub-storage array 142; the second transmission line 105 may be electrically connected to the first sub-row decoder 101a, and the second transmission line 105 drives the NM word line drivers 102 in the first sub-storage array 131 and the third sub-storage array 132, where M is a positive integer less than N.

[0076] In some embodiments, N is an even number, and M is N / 2+1. This facilitates making the length of the first transmission line 104 in the first direction X substantially equal to the length of the second transmission line 105 in the first direction X, thereby facilitating the equalization of the effects of parasitic capacitance and resistance on the control signal when it is transmitted between the first transmission line 104 and the second transmission line 105. For example, in one example, the ratio of the length of the first transmission line 104 in the first direction X to the length of the second transmission line 105 in the first direction X can be in the range of 0.9 to 1.1, e.g., the length of the first transmission line 104 in the first direction X is equal to the length of the second transmission line 105 in the first direction X.

[0077] In the above embodiment, reference Figures 6 to 9, the third transmission line 106 and the first transmission line 104 are on different layers, and the third transmission line 106 and the second transmission line 105 are on different layers. Therefore, the conductive plug 107 enables electrical connection between a portion of the third transmission line 106 and the first transmission line 104, and also enables electrical connection between another portion of the third transmission line 106 and the second transmission line 105.

[0078] It should be noted that Figures 6 to 9 In the examples, the third transmission line 106 is closer to the memory array 100 than the first transmission line 104, and closer to the memory array 100 than the second transmission line 105. That is, the third transmission line 106 is located below the first transmission line 104 and below the second transmission line 105. In actual applications, the third transmission line 106 can be farther from the memory array 100 than the first transmission line 104 and farther from the memory array 100 than the second transmission line 105. That is, the third transmission line 106 is located above the first transmission line 104 and above the second transmission line 105. Alternatively, the third transmission line 106 is located between the first transmission line 104 and the second transmission line 105.

[0079] also, Figure 6 and Figure 8 For the sake of clarity of the diagram, the first transmission line 104 , the second transmission line 105 and the third transmission line 106 are not drawn in a stereoscopic manner.

[0080] In some embodiments, the first transmission line 104 and the second transmission line 105 are disposed on the same layer. Furthermore, the third transmission line 106 and the first transmission line 104 are disposed on a different layer. This helps reduce the height of the conductive plug 107 required for the electrical connection between the first transmission line 104 and the third transmission line 106, and for the electrical connection between the second transmission line 105 and the third transmission line 106. This helps reduce the total length of the transmission path required for the control signal to be transmitted to the word line driver 102 via the first transmission line 104, the conductive plug 107, and the third transmission line 106, and also reduces the total length of the transmission path required for the control signal to be transmitted to the word line driver 102 via the second transmission line 105, the conductive plug 107, and the third transmission line 106.

[0081] In some embodiments, a control signal is transmitted to one of the multiple wordline drivers 102 in the memory array group 120 via the first transmission line 104 and the third transmission line 106, or a control signal is transmitted to one of the remaining multiple wordline drivers 102 in the memory array group 120 via the second transmission line 105 and the third transmission line 106; wherein the longest transmission path among the multiple transmission paths transmitted via the first transmission line 104 and the third transmission line 106 is the first transmission path, and the longest transmission path among the multiple transmission paths transmitted via the second transmission line 105 and the third transmission line 106 is the second transmission path, and the ratio of the parasitic capacitance resistance value generated by the first transmission path to the parasitic capacitance resistance value generated by the second transmission path is 0.9 to 1.1. This helps to balance the effects of the parasitic capacitance resistance value on the control signal when it is transmitted in the first transmission path and the second transmission path.

[0082] In summary, by placing the row decoder 101 at the side of the memory array 100, the word line driver 102 located between two adjacent memory sub-blocks 110 can drive both memory sub-blocks 110, and the word line driver 102 located at the edge of the memory array 100 can drive an adjacent memory sub-block 110. In this way, N+1 word line drivers 102 can drive N memory sub-blocks 110 in the memory array 100, thereby reducing the number of word line drivers 102 required to drive the memory array 100 and thus reducing the overall size of the semiconductor structure. Furthermore, by reconfiguring the transmission path of the control signal in the memory array 100, the influence of parasitic capacitance and resistance on the control signal can be reduced, thereby improving the electrical performance of the semiconductor structure.

[0083] Another embodiment of the present disclosure provides a memory including the semiconductor structure provided in the embodiment of the present disclosure. This can reduce the overall size of the memory by reducing the number of word line drivers 102 and improve the electrical performance of the memory by improving the electrical performance of the semiconductor structure.

[0084] In some embodiments, the memory may be a DDR memory, such as a DDR4 memory, a DDR5 memory, a DDR6 memory, a LPDDR4 memory, a LPDDR5 memory, or a LPDDR6 memory.

[0085] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present disclosure, and in actual applications, various changes may be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the scope of protection of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that include: a storage array having a first side and a second side opposite to each other along a first direction; a row decoder, located on the first side and / or the second side, configured to receive a row address signal and generate a control signal to drive a word line driver corresponding to the control signal; The memory array includes N memory sub-blocks and N+1 word line drivers spaced apart along the first direction, each memory sub-block having one word line driver on both sides along the first direction, where N is a positive integer; The word line driver located between two adjacent storage sub-blocks is configured to drive a portion of word lines of one of the two adjacent storage sub-blocks or a portion of word lines of the other of the two adjacent storage sub-blocks; The present invention also includes: a plurality of storage arrays arranged at intervals along a second direction, wherein the first direction and the second direction intersect, and the plurality of storage arrays share the row decoder; Two adjacent storage arrays along the second direction form a storage array group, and the storage array group includes: a first transmission line extending along the first direction, configured to receive the control signal and drive at least part of the word line drivers located in the memory array group according to the control signal; a second transmission line extending along the first direction, configured to receive the control signal and drive the remaining word line drivers in the memory array group according to the control signal; A third transmission line extending along the second direction is configured to electrically connect the first transmission line and the word line driver through the third transmission line, or to electrically connect the second transmission line and the word line driver through the third transmission line, and neither the first transmission line nor the second transmission line passes through the corresponding storage array in the first direction.

2. The semiconductor structure according to claim 1, wherein The storage sub-block located between two adjacent word line drivers is the target storage sub-block, one of the two word line drivers located on both sides of the target storage sub-block drives the odd-bit word lines in the target storage sub-block, and the other of the two word line drivers located on both sides of the target storage sub-block drives the even-bit word lines in the target storage sub-block.

3. The semiconductor structure according to claim 1, wherein: Also includes: A plurality of sense amplifiers are provided, each of the sense amplifiers being located between two adjacent memory sub-blocks along the second direction.

4. The semiconductor structure according to claim 1, wherein: The storage array group includes a first storage array and a second storage array. Along the first direction, the first storage array includes a first sub-storage array and a second sub-storage array, and the second storage array includes a third sub-storage array and a fourth sub-storage array. The first sub-storage array is directly opposite to the third sub-storage array in the second direction, and the second sub-storage array is directly opposite to the fourth sub-storage array in the second direction. The first transmission line drives at least part of the word line drivers in the memory array group according to the control signal, including driving the word line drivers in the first sub-memory array and the third sub-memory array according to the control signal; The second transmission line drives the remaining word line drivers in the memory array group according to the control signal, including driving the word line drivers in the second sub-memory array and the fourth sub-memory array according to the control signal.

5. The semiconductor structure according to claim 4, wherein: The row decoder is located on the first side or the second side, the first sub-memory array and the third sub-memory array are located on a side close to the row decoder, and the second sub-memory array and the fourth sub-memory array are located on a side far from the row decoder; The first transmission line and the M+1 third transmission lines corresponding to the first sub-memory array are configured to realize electrical connection between the M+1 word line drivers in the first sub-memory array and the M+1 word line drivers in the third sub-memory array and the row decoder; The second transmission line and the NM third transmission lines corresponding to the fourth sub-storage array are configured together to realize the electrical connection between the NM word line drivers in the second sub-storage array and the NM word line drivers in the fourth sub-storage array and the row decoder, where M is a positive integer less than N.

6. The semiconductor structure according to claim 4, wherein: The row decoder includes: a first sub-row decoder located on the first side and a second sub-row decoder located on the second side, the first sub-memory array and the third sub-memory array are located on a side close to the first sub-row decoder, and the second sub-memory array and the fourth sub-memory array are located on a side close to the second sub-row decoder; The first transmission line is electrically connected to the first sub-row decoder, and the first transmission line and the M+1 third transmission lines corresponding to the first sub-memory array are configured together to realize electrical connection between the M+1 word line drivers in the first sub-memory array and the M+1 word line drivers in the third sub-memory array and the first sub-row decoder; The second transmission line is electrically connected to the second sub-row decoder, and the second transmission line and the NM third transmission lines corresponding to the fourth sub-storage array are configured together to realize the electrical connection between the NM word line drivers in the second sub-storage array and the NM word line drivers in the fourth sub-storage array and the second sub-row decoder, where M is a positive integer less than N.

7. The semiconductor structure according to claim 5 or 6, wherein: N is an even number, and M is 8. The semiconductor structure according to claim 4, wherein: The third transmission line and the first transmission line are on different layers, and the third transmission line and the second transmission line are on different layers.

9. The semiconductor structure according to claim 4 or 8, wherein: The first transmission line and the second transmission line are arranged on the same layer.

10. The semiconductor structure according to claim 4, wherein: The control signal is transmitted to one of the plurality of word line drivers in the memory array group via the first transmission line and the third transmission line, or the control signal is transmitted to one of the remaining plurality of word line drivers in the memory array group via the second transmission line and the third transmission line; Among them, the longest transmission path among the multiple transmission paths transmitted via the first transmission line and the third transmission line is the first transmission path, the longest transmission path among the multiple transmission paths transmitted via the second transmission line and the third transmission line is the second transmission path, and the ratio of the parasitic capacitance resistance value generated by the first transmission path to the parasitic capacitance resistance value generated by the second transmission path is 0.9 to 1.

1.

11. The semiconductor structure according to claim 1, wherein: The storage array includes a first storage block and a second storage block arranged at intervals along the first direction, the first storage block includes A storage sub-blocks, and the second storage block includes NA storage sub-blocks, where A is a positive integer less than N; The first storage block is configured to store high-order bytes, and the second storage block is configured to store low-order bytes.

12. The semiconductor structure according to claim 11, wherein The first storage block and the second storage block include the same number of storage sub-blocks.

13. The semiconductor structure according to claim 1, wherein: The storage sub-block includes a plurality of storage cells arranged in an array, and the storage cell includes a transistor and a capacitor electrically connected to each other, the gate of the transistor is electrically connected to the word line, the word line is electrically connected to the word line driver, the drain of the transistor is electrically connected to the bit line, one end of the capacitor is electrically connected to the source of the transistor, and the other end of the capacitor is connected to a reference voltage.

14. A memory, characterized in that: include: The semiconductor structure according to any one of claims 1 to 13.

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