Signal generation circuit, test circuit and memory

Abstract

The present disclosure provides a signal generating circuit, a test circuit and a memory, and relates to the field of semiconductor technology. The signal generating circuit includes a counting circuit and a selection circuit; the counting circuit includes n counting signal output terminals; the selection circuit includes a selection signal input terminal, n first receiving terminals corresponding to binary bits, and n second receiving terminals; each first receiving terminal is connected to the counting signal output terminal located at the same binary bit; in order from low to high bits, the first m second receiving terminals are connected to the last m counting signal output terminals, and each remaining second receiving terminal is connected to the counting signal output terminal m bits lower than itself, m<n; the selection circuit is configured to: based on the selection signal received by the selection signal input terminal, select and output a target signal, and the target signal can be used for multiple addressing modes such as address ascending addressing, address descending addressing, address jumping ascending addressing, address jumping descending addressing, etc., which can better meet the testing requirements of the memory.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a signal generating circuit, a test circuit, and a memory. Background Art

[0002] MBIST (Memory Build In Self Test) is a test circuit built into the memory that can generate commands, addresses, data and other information to test the memory.

[0003] In MBIST, according to the controller's requirements, the address generation circuit generally counts in ascending order from 0. However, as testing requirements increase, the types of test vectors required are increasing, and existing test circuits can no longer meet current testing requirements. Summary of the Invention

[0004] The present disclosure provides a signal generating circuit, a test circuit, and a memory, which can solve the technical problem that the signal generating circuit in the existing test circuit cannot meet the test requirements.

[0005] In a first aspect, an embodiment of the present disclosure provides a signal generating circuit, comprising a counting circuit and a selecting circuit;

[0006] The counting circuit includes n counting signal output terminals for outputting n-bit binary counting signals, where n is a positive integer;

[0007] The selection circuit includes a selection signal input terminal, n first receiving terminals corresponding to binary bits, and n second receiving terminals corresponding to binary bits;

[0008] Each of the first receiving ends is connected to the counting signal output end at the same binary position; in order from the lowest position to the highest position, the first m second receiving ends are connected to the next m counting signal output ends, and each of the remaining second receiving ends is connected to the counting signal output end at a position m lower than the first receiving end, where m is a positive integer and m<n;

[0009] The selection circuit is configured to: based on the selection signal received by the selection signal input end, select and output any one of the following target signals: the signal received by the n first receiving ends, the signal received by the n second receiving ends, the reverse signal of the signal received by the n first receiving ends, and the reverse signal of the signal received by the n second receiving ends.

[0010] In some embodiments, in order from low to high, when i is less than or equal to m, the i-th second receiving end is connected to the m-i+1-th counting signal output end from the end, and when i is greater than m, the i-th second receiving end is connected to the im-th counting signal output end; where i∈{1, 2, 3, ..., n}.

[0011] In some embodiments, m=1, and in order from low to high, the lowest-order second receiving end is connected to the highest-order signal output end, and each of the remaining second receiving ends is connected to the signal output end that is 1 bit lower than itself.

[0012] In some embodiments, m=2, and in order from low to high, the first second receiving end is connected to the n-1th counting signal output end, the second second receiving end is connected to the nth counting signal output end, and each of the remaining second receiving ends is connected to the counting signal output end 2 bits lower than itself.

[0013] In some embodiments, the selection circuit includes n signal selection circuits corresponding to binary bits; each of the signal selection circuits includes a first selector, a second selector, and a first inverter; the selection signal input terminal includes a first selection signal input terminal and a second selection signal input terminal;

[0014] Each of the first selectors includes the first receiving end, the second receiving end, the first selection signal input end, and a first output end;

[0015] Each of the second selectors includes a third receiving terminal, a fourth receiving terminal, a second selection signal input terminal, and a second output terminal;

[0016] The first output end is connected to the third receiving end and the input end of the first inverter respectively, and the output end of the first inverter is connected to the fourth receiving end.

[0017] In some embodiments, when the first selection signal input terminal receives a non-skip selection signal, the first output terminal outputs the signal received by the first receiving terminal, and when the first selection signal input terminal receives a skip selection signal, the first output terminal outputs the signal received by the second receiving terminal;

[0018] When the second selection signal input terminal receives an ascending selection signal, the second output terminal outputs the signal received by the third receiving terminal; when the second selection signal input terminal receives a descending selection signal, the second output terminal outputs the signal received by the fourth receiving terminal.

[0019] In some embodiments, the signal generating circuit is applied to a memory;

[0020] The selection circuit is configured to: based on the selection signal received by the selection signal input terminal, select and output any one of the target signals as a row address addressing signal or a column address addressing signal of the memory.

[0021] In some embodiments, the counting circuit includes n cascaded counting units, and the output end of each counting unit is connected to the counting signal output end located at the same binary bit;

[0022] The n cascaded counting units are configured to output the n-bit binary counting signal based on a clock signal.

[0023] In a second aspect, an embodiment of the present disclosure provides a test circuit for use in a memory built-in self-test, the test circuit comprising a counting circuit and a selection circuit;

[0024] The counting circuit includes n counting signal output terminals for outputting n-bit binary counting signals, where n is a positive integer;

[0025] The selection circuit includes a selection signal input terminal and n receiving terminals corresponding to binary bits;

[0026] In order from low to high, the first m receiving ends are connected to the last m counting signal output ends, and each of the remaining receiving ends is connected to the counting signal output end m lower than itself, where m is a positive integer and m<n;

[0027] The selection circuit is configured to: based on the selection signal received by the selection signal input terminal, select and output any one of the following target signals as the address signal of the memory built-in self-test: the signal received by the n receiving terminals, and the inverse signal of the signal received by the n receiving terminals.

[0028] In some embodiments, in order from low to high, when i is less than or equal to m, the i-th receiving end is connected to the m-i+1th counting signal output end from the end before, and when i is greater than m, the i-th receiving end is connected to the im-th counting signal output end; where i∈{1, 2, 3, ..., n}.

[0029] In some embodiments, m=1, and in order from low to high, the lowest-order receiving end is connected to the highest-order signal output end, and each of the remaining receiving ends is connected to the signal output end that is 1 bit lower than itself.

[0030] In a third aspect, an embodiment of the present disclosure provides a memory, comprising the signal generating circuit provided in the first aspect or the test circuit provided in the second aspect.

[0031] The signal generating circuit, test circuit and memory provided by the embodiments of the present disclosure can realize a variety of counting timing control methods, such as address ascending addressing, address descending addressing, address jumping ascending addressing, address jumping descending addressing and other addressing methods, thereby supporting more test vectors. The scheme is simple and easy to implement, and has little impact on circuit area, power consumption and timing, and can better meet the current memory testing requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A schematic structural diagram of a signal generating circuit provided in an embodiment of the present disclosure;

[0033] Figure 2 A schematic structural diagram of a signal selection circuit provided in an embodiment of the present disclosure;

[0034] Figure 3 A schematic structural diagram of a counting circuit provided in an embodiment of the present disclosure;

[0035] Figure 4 A timing diagram of a signal generating circuit and a testing circuit provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure. In addition, although the disclosure in the present disclosure is introduced according to one or several exemplary examples, it should be understood that each aspect of these disclosures can also constitute a complete implementation method separately.

[0037] It should be noted that the brief descriptions of terms in this disclosure are only for the purpose of facilitating the understanding of the embodiments described below, and are not intended to limit the embodiments of this disclosure. Unless otherwise specified, these terms should be understood according to their ordinary and usual meanings.

[0038] In the specification and claims of this disclosure, as well as in the accompanying drawings, the terms "first," "second," and the like are used to distinguish between similar or similar objects or entities and are not necessarily intended to limit a particular order or precedence, unless otherwise noted. It should be understood that the terms used in this manner are interchangeable where appropriate, e.g., embodiments of the disclosure can be implemented in an order other than that shown or described in the drawings.

[0039] In addition, the terms "comprises" and "comprising" and any variations thereof are intended to cover but not exclude inclusion, for example, a product or device comprising a list of components is not necessarily limited to those components expressly listed but may include other components not expressly listed or inherent to such product or device.

[0040] The term "module" used in the embodiments of the present disclosure refers to any known or later developed hardware, software, firmware, artificial intelligence, fuzzy logic, or combination of hardware and / or software code that can perform the functions associated with the element.

[0041] The embodiments of the present disclosure can be applied to the field of semiconductor technology, for example, can be applied to the test circuit design of memory in integrated circuit design, including the design of an address generator in memory testing to generate the address information required for memory testing, but it is not limited to this scope. Other command planning and generation circuits and counting timing control circuits can adopt the technical solutions provided by the embodiments of the present disclosure.

[0042] With the rapid development of integrated circuits (ICs), their scale is increasing, and the requirements for circuit quality and reliability are further increasing. Testing ICs is becoming increasingly difficult. To achieve rapid testing and screening of ICs, automated test equipment (ATE) provides strong support. ATE uses IC design simulation files as IC input stimulus, provides an IC test environment through the ATE test platform, and compares the IC output with the test results to determine the quality of the IC.

[0043] In the integrated circuit testing industry, test vectors represent the timing characteristics of the integrated circuit being tested. Simply put, during IC testing, ATE sends a series of timing signals to the input pins of the IC being tested. The output timing signals are then compared at the IC's output pins to verify that the IC meets its functional requirements. In a narrow sense, test vectors are the truth table of the IC.

[0044] MBIST is a test circuit built into the memory, capable of automatically generating commands, addresses, data, and other information for memory testing. "Built-in" refers to the fact that test vectors for the memory are not generated by an external ATE, but rather automatically generated by the built-in memory test logic, with results compared. During MBIST testing, the machine simply issues test commands via the standard JTAG interface, and the test results are retrieved via the TDO interface.

[0045] It is understood that a memory typically includes multiple bit lines (BLs), multiple word lines (WLs), and multiple memory cells, where each memory cell is connected to a corresponding WL and a corresponding BL. In practical applications, a memory cell can be activated using a row address and a column address to access it.

[0046] Address generation (AG) is an addressing technique that facilitates the addressing of large-capacity memories and the implementation of dynamic program floating. In MBIST, address generation circuits typically count in ascending order from 0, as required by the controller. However, as testing demands increase, the demand for more and more test vectors increases, and address generation circuits with only ascending addressing capabilities are no longer able to meet current testing needs.

[0047] In view of the above technical problems, a signal generating circuit is provided in the embodiment of the present disclosure, which can generate ascending counts, descending counts, jumping ascending counts, and jumping descending counts to realize multiple counting timing controls. And it can be applied to test circuits. The test circuit has a simple structure and has little impact on circuit area, power consumption, and timing. It can realize multiple addressing modes such as address ascending addressing, address descending addressing, address jumping ascending addressing, and address jumping descending addressing, so as to support more test vectors and better meet the test requirements of the memory. It should be noted that the function of the above test circuit is not limited to this range test circuit and MBIST. Other command planning and generation circuits and counting timing control circuits can adopt this design. The detailed process can be referred to the following embodiments.

[0048] Reference Figure 1 , Figure 1 FIG. 3 is a schematic diagram of a signal generating circuit provided in an embodiment of the present disclosure. In some embodiments of the present disclosure, the signal generating circuit 300 includes a counting circuit 310 and a selecting circuit 320 .

[0049] The counting circuit 310 includes n counting signal output terminals, namely RA <n-1>,……,RA <3> , RA <2> , RA <1> , RA <0> , used to output n-bit binary counting signal RA <n-1:0>Wherein, n is a positive integer, and illustratively, n can be 4, 8, 10, 14, 15, 16, 32, etc., and can be specifically determined according to the number of address lines of the memory.

[0050] The selection circuit 320 includes a selection signal input terminal S, n first receiving terminals corresponding to binary bits, n second receiving terminals corresponding to binary bits, and n output terminals corresponding to binary bits.

[0051] Among them, the above n first receiving ends are CA <0> , CA <1> , CA <2> 、……、CA <n-1>, this embodiment Figure 1 CA <n-1>-CA <0> The above n second receiving ends are CB <0> , CB <1> , CB <2> 、……、CB <n-1>, this embodiment Figure 1 CB for Chinese use <n-1>-CB <0> The above n output terminals are RB <0> , RB <1> , RB <2> ,……,RB <n-1>, this embodiment Figure 1 RB <n-1>-RB <0> express.

[0052] In some embodiments, each first receiving terminal is connected to a counting signal output terminal located at the same binary bit. Taking n=16 as an example, CA <0> with RA <0> Connection, CA <1> with RA <1> Connection, CA <2> with RA <2> Connect, ..., CA <15> with RA <15> connect.

[0053] Each second receiving end is connected to the counting signal output end according to a preset method, wherein the first m second receiving ends are connected to the next m counting signal output ends in ascending order, and each remaining second receiving end is connected to the counting signal output end m lower than itself. Where m is a positive integer and m<n.

[0054] Taking n=16, m=1 as an example, CB <0> with RA <15> Connection, CB <1> with RA <0> Connection, CB <2> with RA <1> Connect, ..., CB <15> with RA <14> connect.

[0055] In which, the selection circuit 320 is configured to: based on the selection signal received by the selection signal input terminal S, select and output any one of the following target signals: the signal received by the above-mentioned n first receiving terminals, the signal received by the above-mentioned n second receiving terminals, the reverse signal of the signal received by the above-mentioned n first receiving terminals, and the reverse signal of the signal received by the above-mentioned n second receiving terminals.

[0056] It can be understood that since each first receiving end is connected to the counting signal output end at the same binary bit, the signals received by the n first receiving ends output by the selection circuit 320 and the n-bit binary counting signal RA output by the n counting signal output ends are connected. <n-1:0>consistent.

[0057] Since each second receiving end is connected to the counting signal output end according to the above preset method, the signals received by the n second receiving ends output by the selection circuit 320 and the n-bit binary counting signal RA output by the n counting signal output ends are equal. <n-1:0>There will be differences, specifically the above n-bit binary counting signal RA <n-1:0>The corresponding counting result is continuously increasing, while the counting results corresponding to the signals received by the n second receiving ends are jumping increasing.

[0058] For example, taking n=4 and m=1 as an example, when the above-mentioned n-bit binary counting signal RA<3:0> is 0001, the signal received by the above-mentioned n second receiving ends is 0010; when the above-mentioned n-bit binary counting signal RA<3:0> is 0010, the signal received by the above-mentioned n second receiving ends is 0100; when the above-mentioned n-bit binary counting signal RA<3:0> is 0011, the signal received by the above-mentioned n second receiving ends is 0110; ...

[0059] In some embodiments, the selection circuit 320 can select and output any one of the following target signals based on the selection signal received by the selection signal input terminal S: the signal received by the above-mentioned n first receiving terminals, the signal received by the above-mentioned n second receiving terminals, the reverse signal of the signal received by the above-mentioned n first receiving terminals, and the reverse signal of the signal received by the above-mentioned n second receiving terminals.

[0060] It is understood that since the signals received by the first receiving end and the second receiving end are either 0 or 1, by reversing the signals received by the n first receiving ends, a descending signal with a count value gradually changing from large to small can be obtained. Similarly, by reversing the signals received by the n second receiving ends, a jumping descending signal with a count value gradually changing from large to small can be obtained.

[0061] In some embodiments, the signals received by the above-mentioned n first receiving ends can be used as ascending addresses for ascending addressing, the signals received by the above-mentioned n second receiving ends can be used as jumping ascending addresses for ascending addressing, the reverse signals of the signals received by the above-mentioned n first receiving ends can be used as descending addresses for descending addressing, and the reverse signals of the signals received by the above-mentioned n second receiving ends can be used as jumping descending addresses for descending addressing.

[0062] It is understandable that as the density of memory continues to increase, the data lines in its storage cells are physically closer, resulting in a gradual increase in capacitive coupling between adjacent data lines. In the process of testing the memory, when reading and writing a certain data line, it will have an impact on the adjacent data lines, including but not limited to leakage, causing faults between data lines. By jump addressing, different data can be written to each data line, making it easier to stimulate faults and facilitate troubleshooting. For example, by writing data to the 1st, 3rd, and 5th row data lines, the leakage of the 2nd and 4th row data lines can be tested.

[0063] In addition, faults between storage cells can also be detected through jump addressing. For example, by writing different data to different data lines, the leakage effect of surrounding storage cells on the target storage cell is stimulated to detect the problem.

[0064] The disclosed embodiments provide a signal generating circuit that can implement a variety of counting timing control methods, such as address ascending addressing, address descending addressing, address jumping ascending addressing, address jumping descending addressing, and other addressing methods, thereby supporting more test vectors. The solution is simple and easy to implement, and has little impact on circuit area, power consumption, and timing, and can better meet the current memory testing requirements.

[0065] Based on the contents described in the above embodiments, in some embodiments, in order from low to high, when i is less than or equal to m, the i-th second receiving end is connected to the penultimate (m-i+1) counting signal output end, and when i is greater than m, the i-th second receiving end is connected to the im-th signal output end; wherein, i∈{1, 2, 3, ..., n}.

[0066] Exemplarily, in some embodiments, taking m=1 as an example, in order from low to high, the first (lowest bit) second receiving end is connected to the penultimate (highest bit) counting signal output end, and each of the remaining second receiving ends is connected to a counting signal output end that is 1 bit lower than itself, thereby enabling the count value of the signal received by the above n second receiving ends to be increased by 2 each time a trigger edge of the clock signal arrives.

[0067] In other embodiments, taking m=2 as an example, in order from low to high, the first second receiving end is connected to the second-to-last counting signal output end, the second second receiving end is connected to the first-to-last counting signal output end, and each of the remaining second receiving ends is connected to the counting signal output end 2 bits lower than itself. Taking n=16 and m=2 as an example, CB <0> with RA <14> Connection, CB <1> with RA <15> Connection, CB <2> with RA <0> Connection, CB <3> with RA <1> Connect, ..., CB <15> with RA <13> Thus, each time a trigger edge of the clock signal arrives, the count value of the signals received by the n second receiving ends is increased by 4.

[0068] It is understandable that the value of m can also be 3, 4, 5, ...; it will not be repeated in the embodiments of the present disclosure.

[0069] Reference Figure 2 , Figure 2 This is a schematic diagram of the structure of a signal selection circuit provided in an embodiment of the present disclosure. In some embodiments, the selection circuit includes n signal selection circuits 410 corresponding to binary bits; each signal selection circuit 410 includes a first selector 411, a second selector 412, and a first inverter 413; the selection signal input terminal S includes a first selection signal input terminal S1 and a second selection signal input terminal S2.

[0070] Each first selector 411 includes a first receiving terminal CA, a second receiving terminal CB, a first selection signal input terminal S1, and a first output terminal Z. Each second selector 412 includes a third receiving terminal EA, a fourth receiving terminal EB, a second selection signal input terminal S2, and a second output terminal RB. The first output terminal Z is connected to the third receiving terminal EA and the input terminal of the first inverter 413, respectively. The output terminal of the first inverter 413 is connected to the fourth receiving terminal EB.

[0071] In some embodiments, when the first selection signal input terminal S1 receives a non-jump selection signal, the first output terminal Z outputs the signal received by the first receiving terminal CA; when the first selection signal input terminal S1 receives a jump selection signal, the first output terminal Z outputs the signal received by the second receiving terminal CB.

[0072] When the second selection signal input terminal S2 receives an ascending selection signal, the second output terminal RB outputs the signal received by the third receiving terminal EA. When the second selection signal input terminal S2 receives a descending selection signal, the second output terminal RB outputs the signal received by the fourth receiving terminal EB.

[0073] Optionally, the non-jump selection signal and the ascending selection signal can be low level signals 0, and the jump selection signal and the descending selection signal can be high level signals 1. Alternatively, the non-jump selection signal and the ascending selection signal can be high level signals 1, and the jump selection signal and the descending selection signal can be low level signals 0.

[0074] In some embodiments, the selection circuit may be further configured to: based on the selection signal received by the selection signal input terminal, select and output any target signal as an addressing signal of the memory.

[0075] For example, in some embodiments, the memory includes n row address lines and n column address lines; the second output terminal of each second selector is connected to one of the row address lines or the column address lines. The target signals can be used as row address addressing signals of the memory for row addressing.

[0076] Alternatively, the aforementioned target signals may be used as column address signals of a memory for column addressing.

[0077] Based on the contents described in the above embodiments, in some embodiments, the present disclosure further provides a test circuit for use in a memory built-in self-test, the test circuit including a counting circuit and a selection circuit;

[0078] The counting circuit includes n counting signal output terminals for outputting n-bit binary counting signals, where n is a positive integer.

[0079] The selection circuit includes a selection signal input terminal and n receiving terminals corresponding to binary bits; in order from low to high bits, the first m receiving terminals are connected to the next m counting signal output terminals, and each of the remaining receiving terminals is connected to a counting signal output terminal m bits lower than itself, where m is a positive integer and m<n;

[0080] The selection circuit is configured to: based on the selection signal received by the selection signal input terminal, select and output any one of the following target signals as the addressing signal of the memory: the signal received by the n receiving terminals, and the inverse signal of the signal received by the n receiving terminals.

[0081] In some embodiments, in order from low to high, when i is less than or equal to m, the i-th receiving end is connected to the (m-i+1)th counting signal output end from the end, and when i is greater than m, the i-th receiving end is connected to the (im)th counting signal output end; where i∈{1, 2, 3, ..., n}.

[0082] Exemplarily, in some embodiments, taking m=1 as an example, in order from low to high, the first (lowest bit) receiving end is connected to the penultimate (highest bit) counting signal output end, and each of the remaining receiving ends is connected to a counting signal output end that is 1 bit lower than itself, thereby enabling the count value of the signal received by the above n receiving ends to be increased by 2 each time a trigger edge of the clock signal arrives.

[0083] Optionally, the value of m can be 1, 2, 3, 4, 5, ... etc. For details, please refer to the description of the above embodiment and will not be repeated here.

[0084] It is understandable that, since the signal received by the above receiving end is either 0 or 1, after reversing the signals received by the above n receiving ends, a jumping descending signal with a count value gradually changing from large to small can be obtained.

[0085] In some embodiments, the signals received by the n receiving ends may be used as jumping ascending addresses for ascending addressing, and the reverse signals of the signals received by the n receiving ends may be used as jumping descending addresses for descending addressing.

[0086] The test circuit provided in the embodiment of the present disclosure can be applied to the built-in self-test of the memory. It can detect faults between data lines or between storage cells through address jumping ascending addressing or address jumping descending addressing. The solution is simple and easy to implement, and has little impact on circuit area, power consumption, and timing, better meeting the testing requirements of current memories.

[0087] In some embodiments, the counting circuit 310 includes n cascaded counting units, each of which has an output connected to a counting signal output terminal located at the same binary bit. The n cascaded counting units are configured to output an n-bit binary counting signal based on a clock signal, wherein the difference between the counting results of two consecutive n-bit binary counting signals is 1.

[0088] Optionally, the counting unit may be an asynchronous counter composed of a D-type flip-flop (Data Flip-Flop or Delay Flip-Flop, DFF). A D-type flip-flop is an information storage device with a memory function and two stable states. It is the most basic logic unit in various sequential circuits and an important unit circuit in digital logic circuits. A D-type flip-flop has two stable states, "0" and "1," and can flip from one stable state to the other under the influence of a signal received at the clock terminal of the flip-flop.

[0089] In the disclosed embodiment, the flip-flop may include an input terminal D, a clock terminal Clk, an output terminal Q, and a reset terminal RST. The output terminal Q of each stage of the flip-flop is used to output the corresponding bit in the counting signal, while the reset terminal RST of each stage of the flip-flop is used to receive a reset signal, thereby resetting the counting circuit and restarting counting.

[0090] In some embodiments of the present disclosure, the first counting unit may include a first trigger, an inverter is connected between the input terminal D and the output terminal Q of the first trigger, the clock terminal of the first trigger is used to receive the first clock signal, and the output terminal Q of the first trigger is used to output the first counting signal, and the first counting signal is the 0th bit in the counting signal; the second counting unit may include a second trigger and a second XOR gate, the first input terminal of the second XOR gate is connected to the output terminal Q of the first trigger, the second input terminal of the second XOR gate is connected to the output terminal Q of the second trigger, the output terminal of the second XOR gate is connected to the input terminal D of the second trigger, the clock terminal of the second trigger is used to receive the first clock signal, and the output terminal Q of the second trigger is used to output the second counting signal, and the second counting signal is the 1st bit in the counting signal.

[0091] By analogy, the i-th counting submodule may include an i-th trigger, an i-th NAND gate, an i-th NOT gate and an i-th XOR gate, the first input terminal of the i-th NAND gate is connected to the output terminal Q of the i-1-th trigger, the second input terminal of the i-th NAND gate is connected to the first input terminal of the i-1-th XOR gate, the output terminal of the i-NAND gate is connected to the input terminal of the i-NAND gate, the output terminal of the i-NAND gate is connected to the first input terminal of the i-XOR gate, the second input terminal of the i-XOR gate is connected to the output terminal Q of the i-th trigger, the output terminal of the i-XOR gate is connected to the input terminal D of the i-th trigger, the clock terminal of the i-th trigger is used to receive the first clock signal, and the output terminal Q of the i-th trigger is used to output the i-th counting signal, and the i-th counting signal is the i-1-th bit in the counting signal; wherein, i is an integer greater than or equal to 3 and less than or equal to n.

[0092] In some embodiments, the D input terminal of the D flip-flop in the counting unit may also directly use the signal of the Q inverted output terminal of the D flip-flop as the input signal, without introducing a NOT gate structure through the Q output terminal.

[0093] Reference Figure 3 , Figure 3 Schematic diagram of a counting circuit provided in an embodiment of the present disclosure. In some embodiments of the present disclosure, taking n=8 as an example, the counting circuit 310 includes a clock source CLK, 8 cascaded counting units, and each counting unit includes a trigger.

[0094] For example, the triggers in the eight cascaded counting units are respectively denoted as D0, D1, D2, ..., D7; the counting signal output terminals connected to the output terminals Q of the triggers in the eight cascaded counting units are respectively denoted as RA <0> , RA <1> , RA <2> ,……,RA <7> .

[0095] The clock source CLK is respectively coupled to the clock input terminals of the eight flip-flops for providing a clock signal Clk.

[0096] The first counting unit includes D0 and an inverter, the output terminal Q of D0 is connected to the input terminal of the inverter, and the input terminal D of D0 is connected to the output terminal of the inverter.

[0097] The second counting unit includes D1 and an XOR gate, the output terminal Q of D1 is connected to the first input terminal of the XOR gate, the output terminal Q of D0 is connected to the second input terminal of the XOR gate, and the input terminal D of D1 is connected to the output terminal of the XOR gate.

[0098] The third counting unit includes D2, an AND gate, and an XOR gate. The output terminal Q of D2 is connected to the first input terminal of the XOR gate, the output terminal of the AND gate is connected to the second input terminal of the XOR gate, the input terminal D of D2 is connected to the output terminal of the XOR gate, and the two input terminals of the AND gate are respectively connected to the output terminal Q of D0 and the output terminal Q of D1.

[0099] The structures of the fourth to seventh counting units are similar to those of the third counting unit and will not be described in detail in the embodiment of the present disclosure.

[0100] For example, taking D0, D1, D2, ..., D7 as rising edge triggers, the working principle of the above counting circuit 310 is as follows:

[0101] In the initial state, the reset signal RST is used to reset D0, D1, D2, ..., D7, so that the output terminals Q of D0, D1, D2, ..., D7 all output a low level 0, and the initial binary counting signal RA<7:0> output by the counting circuit 310 is 00000000.

[0102] Before the first rising edge of the clock signal received by the counting circuit 310 appears, except for the input terminal D of D0 which is at the high level 1 (because an inverter is connected between the output terminal Q of D0 and the input terminal D), the input terminals D of the remaining D1, D2, ..., D7 are all at the low level 0. Therefore, when the first rising edge of the clock signal appears, the output terminal Q of D0 flips from the low level 0 to the high level 1, and the output terminals Q of the remaining D1, D2, ..., D7 remain at the low level 0. The binary counting signal RA<7:0> output by the counting circuit 310 is 00000001.

[0103] Before the second rising edge of the clock signal received by the counting circuit 310 occurs, the input terminal D of D0 is at a low level 0 (because an inverter is connected between the output terminal Q of D0 and the input terminal D), the input terminal D of D1 is at a high level 1 (because the input terminal D of D1 is connected to the output terminal of an exclusive-OR gate. Since the first input terminal of the exclusive-OR gate, which is connected to the output terminal Q of D0, is at a high level 1, and the second input terminal connected to the output terminal Q of D1 is at a low level 0, the output terminal of the exclusive-OR gate is at a high level 1). The remaining input terminals D of D2, ..., D7 are all at a low level 0. Therefore, when the second rising edge of the clock signal occurs, the output terminal Q of D1 flips from a low level 0 to a high level 1. The output terminals Q of the remaining terminals D0, D2, D3, ..., D7 remain at a low level 0, and the binary count signal RA<7:0> output by the counting circuit 310 is 00000010.

[0104] Before the third rising edge of the clock signal received by the counting circuit 310 occurs, the input terminal D of D0 is at a high level 1 (because an inverter is connected between the output terminal Q of D0 and the input terminal D), the input terminal D of D1 is at a high level 1 (because the input terminal D of D1 is connected to the output terminal of an exclusive-OR gate. Since the first input terminal of the exclusive-OR gate, which is connected to the output terminal Q of D0, is at a low level 0, and the second input terminal connected to the output terminal Q of D1 is at a high level 1, the output terminal of the exclusive-OR gate is at a high level 1). The remaining input terminals D of D2, ..., D7 are all at a low level 0. Therefore, when the third rising edge of the clock signal occurs, the output terminal Q of D0 flips from a low level 0 to a high level 1, the output terminal Q of D1 remains at a high level 1, and the output terminals Q of the remaining D2, D3, ..., D7 remain at a low level 0. The binary count signal RA<7:0> output by the counting circuit 310 is 00000011.

[0105] Similarly, when the clock signal has the 4th rising edge, the binary counting signal RA<7:0> output by the counting circuit 310 is 00000100, ..., and when the clock signal has the 255th rising edge, the binary counting signal RA<7:0> output by the counting circuit 310 is 11111111.

[0106] In some embodiments, the above-mentioned counting circuit may also be implemented by other structures, that is, any counting circuit capable of outputting an n-bit binary counting signal may be used as the counting circuit described in the above-mentioned embodiments.

[0107] For a better understanding of the embodiments of the present disclosure, in some embodiments of the present disclosure, if n=16, the counting circuit may include 16 cascaded counting units. When the initial output value of each counting unit is 0, each counting unit undergoes a transition at each rising edge of the clock signal Clk output by the clock source, and the signal generation circuit and test circuit output a 16-bit binary counting signal RB<15:0>.

[0108] Reference Figure 4 , Figure 4 A timing diagram of a signal generating circuit and a testing circuit provided in an embodiment of the present disclosure.

[0109] It should be noted that for ease of reading, Figure 4 The 16-bit binary count signal RB<15:0> is converted into hexadecimal and displayed.

[0110] Among them, the selection circuit can use the signal received by the first selection signal input terminal S1 to select and output n signals received by the first receiving terminal or n signals received by the second receiving terminal, and use the signal of the second selection signal input terminal S2 to select and output the reverse signals of the signals received by the n first receiving terminals or the reverse signals of the signals received by the n second receiving terminals.

[0111] For example, Figure 4 As shown in , when the first selection signal input terminal S1 and the second selection signal input terminal S2 are both low level 0, the count value of RB<15:0> increases by 1 with the rising edge of the clock signal. At this time, RB<15:0> can be used as an ascending addressing signal; when the first selection signal input terminal S1 is low level 0 and the second selection signal input terminal S2 is high level 1, the count value of RB<15:0> decreases by 1 with the rising edge of the clock signal. At this time, RB<15:0> can be used as a descending addressing signal; when the first selection signal input terminal S1 is high level 1 and the second selection signal input terminal S2 is low level 0, the count value of RB<15:0> increases by 2 with the rising edge of the clock signal. At this time, RB<15:0> can be used as a skip ascending addressing signal; when the first selection signal input terminal S1 and the second selection signal input terminal S2 are both high level 1, the count value of RB<15:0> decreases by 2 with the rising edge of the clock signal. At this time, RB<15:0> can be used as a skip descending addressing signal.

[0112] The signal generating circuit and the test circuit provided in the embodiments of the present disclosure, based on the counting circuit, can realize a variety of addressing modes such as address ascending addressing, address descending addressing, address jumping ascending addressing, address jumping descending addressing, etc. by designing the above-mentioned selection circuit, thereby being able to support more test vectors. The scheme is simple and easy to implement, and has little impact on circuit area, power consumption, and timing, and can better meet the current memory testing requirements.

[0113] Based on the contents described in the above embodiments, a memory is further provided in the embodiments of the present disclosure, which includes the signal generating circuit or the test circuit described in the above embodiments, which will not be described in detail here.

[0114] The above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A signal generating circuit, characterized in that: including a counting circuit and a selection circuit; The counting circuit includes n counting signal output terminals for outputting n-bit binary counting signals, where n is a positive integer; The selection circuit includes a selection signal input terminal, n first receiving terminals corresponding to binary bits, and n second receiving terminals corresponding to binary bits; Each of the first receiving ends is connected to the counting signal output end at the same binary position; in order from the lowest position to the highest position, the first m second receiving ends are connected to the next m counting signal output ends, and each of the remaining second receiving ends is connected to the counting signal output end at a position m lower than the first receiving end, where m is a positive integer and m<n; The selection circuit is configured to: based on the selection signal received by the selection signal input terminal, select and output any one of the following target signals: the signals received by the n first receiving terminals, the signals received by the n second receiving terminals, the inverse signals of the signals received by the n first receiving terminals, and the inverse signals of the signals received by the n second receiving terminals; The selection circuit includes n signal selection circuits corresponding to binary bits; each of the signal selection circuits includes a first selector, a second selector, and a first inverter; the selection signal input terminal includes a first selection signal input terminal and a second selection signal input terminal; Each of the first selectors includes the first receiving end, the second receiving end, the first selection signal input end, and a first output end; Each of the second selectors includes a third receiving terminal, a fourth receiving terminal, a second selection signal input terminal, and a second output terminal; The first output end is connected to the third receiving end and the input end of the first inverter respectively, and the output end of the first inverter is connected to the fourth receiving end.

2. The signal generating circuit according to claim 1, wherein: In order from low to high, when i is less than or equal to m, the i-th second receiving end is connected to the m-i+1-th counting signal output end from the end before, and when i is greater than m, the i-th second receiving end is connected to the im-th counting signal output end; where i∈{1, 2, 3, ..., n}.

3. The signal generating circuit according to claim 1 or 2, characterized in that: The m=1, in order from low to high, the second receiving end at the lowest bit is connected to the signal output end at the highest bit, and each of the remaining second receiving ends is connected to the signal output end that is 1 bit lower than itself.

4. The signal generating circuit according to claim 1 or 2, characterized in that: Where m=2, in order from low to high, the first second receiving end is connected to the n-1th counting signal output end, the second second receiving end is connected to the nth counting signal output end, and each of the remaining second receiving ends is connected to the counting signal output end 2 bits lower than itself.

5. The signal generating circuit according to claim 1, wherein: When the first selection signal input terminal receives a non-jump selection signal, the first output terminal outputs the signal received by the first receiving terminal; when the first selection signal input terminal receives a skip selection signal, the first output terminal outputs the signal received by the second receiving terminal; When the second selection signal input terminal receives an ascending selection signal, the second output terminal outputs the signal received by the third receiving terminal; when the second selection signal input terminal receives a descending selection signal, the second output terminal outputs the signal received by the fourth receiving terminal.

6. The signal generating circuit according to claim 5, wherein: The signal generating circuit is applied to a memory; The selection circuit is configured to: based on the selection signal received by the selection signal input terminal, select and output any one of the target signals as a row address addressing signal or a column address addressing signal of the memory.

7. The signal generating circuit according to claim 1, wherein: The counting circuit comprises n cascaded counting units, and the output end of each counting unit is connected to the counting signal output end located at the same binary bit; The n cascaded counting units are configured to output the n-bit binary counting signal based on a clock signal.

8. A test circuit, characterized in that: Applied to memory built-in self-test, the test circuit includes a counting circuit and a selection circuit; The counting circuit includes n counting signal output terminals for outputting n-bit binary counting signals, where n is a positive integer; The selection circuit includes a selection signal input terminal and n receiving terminals corresponding to binary bits; In order from low to high, the first m receiving ends are connected to the last m counting signal output ends, and each of the remaining receiving ends is connected to the counting signal output end m lower than itself, where m is a positive integer and m<n; The selection circuit is configured to: based on the selection signal received by the selection signal input terminal, select and output any one of the following target signals as the address signal of the memory built-in self-test: the signal received by the n receiving terminals, and the inverse signal of the signal received by the n receiving terminals; The selection circuit includes n signal selection circuits corresponding to binary bits; each of the signal selection circuits includes a first selector, a second selector, and a first inverter; the selection signal input terminal includes a first selection signal input terminal and a second selection signal input terminal; Each of the first selectors includes a first receiving end, a second receiving end, a first selection signal input end, and a first output end; Each of the second selectors includes a third receiving terminal, a fourth receiving terminal, a second selection signal input terminal, and a second output terminal; The first output end is connected to the third receiving end and the input end of the first inverter respectively, and the output end of the first inverter is connected to the fourth receiving end.

9. The test circuit according to claim 8, characterized in that: In order from low to high, when i is less than or equal to m, the i-th receiving end is connected to the m-i+1th counting signal output end from the end before, and when i is greater than m, the i-th receiving end is connected to the im-th counting signal output end; where i∈{1, 2, 3, ..., n}.

10. The test circuit according to claim 8 or 9, characterized in that: The m=1, in order from low to high, the receiving end at the lowest bit is connected to the signal output end at the highest bit, and each of the remaining receiving ends is connected to the signal output end that is 1 bit lower than itself.

11. A memory, characterized in that: The method comprises the signal generating circuit according to any one of claims 1 to 7, or comprises the test circuit according to any one of claims 8 to 10.

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