Epitaxial wafer and preparation method thereof

Abstract

The present application discloses an epitaxial wafer and a method for preparing the same, relating to the field of semiconductor manufacturing technology. The method for preparing the epitaxial wafer comprises: forming an epitaxial structure on a substrate located in a reaction chamber, the epitaxial structure including a channel layer; during the growth of the channel layer, introducing a gallium source and a nitrogen source into the reaction chamber, the temperature of the reaction chamber being 1025-1070°C; the pressure of the reaction chamber being 200-400 mbar; the gallium source having a first flow rate Q1, and the nitrogen source having a second flow rate Q2, satisfying: 500≤Q2 / Q1≤5000. The present application achieves improved crystal quality and lower deep-level defect density in the channel layer of the epitaxial wafer prepared by controlling the temperature and pressure of the reaction chamber and the flow ratio of the gallium source to the nitrogen source, thereby improving the performance of the epitaxial wafer.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to an epitaxial wafer and a method for preparing the same. Background Art

[0002] Gallium nitride (GaN) power devices primarily use silicon-based GaN epitaxial wafers as raw material. That is, GaN epitaxial material is grown on a silicon substrate. The channel layer and barrier layer jointly determine the electrical performance of the epitaxial wafer. Various defects in the channel layer not only reduce the conductivity of the epitaxial wafer, but also cause the current collapse effect of the device, reducing the device stability. Therefore, the crystal quality of the channel layer is very important to the various performance of the manufactured device. How to improve the crystal quality of the channel layer in GaN epitaxial wafers is a technical problem that needs to be solved urgently. Summary of the Invention

[0003] The purpose of this application is to provide an epitaxial wafer and a preparation method thereof, which can improve the crystal quality of the channel layer in the GaN epitaxial wafer, thereby improving the performance of the epitaxial wafer.

[0004] A first aspect of the present application provides a method for preparing an epitaxial wafer, comprising:

[0005] forming an epitaxial structure on a substrate located in a reaction chamber, wherein the epitaxial structure includes a channel layer;

[0006] In the process of forming the channel layer, a gallium source and a nitrogen source are introduced into the reaction chamber, the temperature of the reaction chamber is 1025~1070℃; the pressure of the reaction chamber is 200~400mbar; the gallium source has a first flow rate Q1, and the nitrogen source has a second flow rate Q2, satisfying: 500≤Q2 / Q1≤5000.

[0007] In some embodiments, the gallium source is selected from triethylgallium.

[0008] In some embodiments, the nitrogen source is selected from ammonia.

[0009] In some embodiments, the first flow rate Q1 is 500-3000 sccm.

[0010] In some embodiments, the second flow rate Q2 is 250 to 15,000 slm.

[0011] In some embodiments, the storage temperature of the gallium source is 15-30° C., and the storage pressure of the gallium source is 600-1200 mbar.

[0012] In some embodiments, before forming the channel layer, the method further includes:

[0013] forming a nucleation layer on one side of the substrate;

[0014] forming a first buffer layer on a side of the nucleation layer away from the substrate;

[0015] forming a second buffer layer on a side of the first buffer layer away from the nucleation layer;

[0016] forming a back barrier layer on a side of the second buffer layer away from the nucleation layer;

[0017] The channel layer is located on a side of the back barrier layer away from the second buffer layer.

[0018] In some embodiments, after forming the channel layer, the method further includes:

[0019] forming an insertion layer on a side of the channel layer away from the back barrier layer;

[0020] forming a barrier layer on a side of the insertion layer away from the channel layer;

[0021] A surface layer is formed on a side of the barrier layer away from the insertion layer.

[0022] In some embodiments, the substrate is made of silicon, silicon carbide, or sapphire.

[0023] In some embodiments, the material of the nucleation layer is selected from AlN.

[0024] In some embodiments, the material of the back barrier layer is selected from AlGaN.

[0025] In some embodiments, the material of the channel layer is selected from GaN.

[0026] In some embodiments, the material of the insertion layer is selected from AlN, AlGaN or SiN x Any one of .

[0027] In some embodiments, the material of the surface layer is selected from GaN, P-GaN or SiN x Any one of .

[0028] In some embodiments, the thickness of the nucleation layer is 200-300 nm.

[0029] In some embodiments, the thickness of the first buffer layer is 1500-2000 nm.

[0030] In some embodiments, the second buffer layer has a thickness of 1200-1800 nm.

[0031] In some embodiments, the back barrier layer has a thickness of 600 to 1200 nm.

[0032] In some embodiments, the thickness of the channel layer is 150-200 nm.

[0033] In some embodiments, the thickness of the insertion layer is 0.5 to 2 nm.

[0034] In some embodiments, the barrier layer has a thickness of 15 to 25 nm.

[0035] In some embodiments, the thickness of the surface layer is 1 to 3 nm.

[0036] In some embodiments, the material of the barrier layer is selected from AlGaN, the chemical formula of AlGaN is Al y Ga 1-y N, where 0.15≤y≤0.25.

[0037] In some embodiments, the first buffer layer includes an AlGaN layer stacked with K layers, satisfying: 3≤K≤5.

[0038] In some embodiments, the material of the first buffer layer is selected from AlGaN, the chemical formula of AlGaN is Al x Ga 1- x N, wherein 0.05≤x≤0.95, and the molar content of Al in the first buffer layer gradually decreases in a direction away from the nucleation layer.

[0039] In some embodiments, the second buffer layer includes L stacked AlN / GaN layers, with 40≤L≤60.

[0040] In some embodiments, in the AlN / GaN stack, the thickness of the AlN layer is 1 to 10 nm, and the thickness of the GaN layer is 10 to 50 nm.

[0041] A second aspect of the present application provides an epitaxial wafer, which is prepared using the epitaxial wafer preparation method as described above.

[0042] In some embodiments, the epitaxial wafer includes a substrate and an epitaxial structure, wherein the epitaxial structure is located on one side of the substrate, and the epitaxial structure includes a channel layer, wherein the channel layer is doped with carbon atoms, and the carbon atom concentration is 1E15 to 5E15 atom / cm -3 .

[0043] The beneficial effects of this application are:

[0044] The present application improves the crystal quality of the channel layer in the GaN epitaxial wafer while reducing the deep energy level defect density by controlling the temperature and pressure of the reaction chamber and the flow ratio of the gallium source to the nitrogen source, that is, by controlling the epitaxial growth temperature, epitaxial growth pressure and the flow ratio of the gallium source to the nitrogen source of the channel layer.

[0045] The present application uses triethylgallium as a metal source and ammonia as a nitrogen source to epitaxially grow a gallium nitride channel layer, and controls the epitaxial growth temperature, epitaxial growth pressure, and the flow ratio of the gallium source to the nitrogen source. Ethyl groups are cracked out of triethylgallium, and gaseous ethylene is obtained through the elimination reaction of hydrogen of the ethyl groups. This effectively reduces the carbon doping concentration in the channel layer, improves the crystal quality of the channel layer, and reduces the deep energy level defect density. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 This is a schematic diagram of the structure of the epitaxial wafer provided in this application.

[0047] In the accompanying drawings, the components represented by the reference numerals are as follows:

[0048] 1. Substrate; 2. Channel layer; 3. Nucleation layer; 4. First buffer layer; 5. Second buffer layer; 6. Back barrier layer; 7. Insertion layer; 8. Barrier layer; 9. Surface layer. DETAILED DESCRIPTION

[0049] The technical solutions of the present application will be described clearly and completely below in conjunction with the embodiments and drawings of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. The various embodiments of the present application may be presented in the form of a range; it should be understood that the description in the form of a range is only for convenience and brevity and should not be understood as a rigid limitation on the scope of the present application; therefore, it should be considered that the range description has specifically disclosed all possible sub-ranges and single numerical values ​​within the range. For example, it should be considered that the range description from 1 to 6 has specifically disclosed sub-ranges, such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6, etc., as well as single numbers within the numbered range, such as 1, 2, 3, 4, 5 and 6, which applies regardless of the range. In addition, whenever a numerical range is indicated herein, it is meant to include any quoted number (fractional or integer) within the indicated range.

[0050] See Figure 1 , a method for preparing an epitaxial wafer, comprising:

[0051] forming an epitaxial structure on a substrate 1 located in a reaction chamber, wherein the epitaxial structure includes a channel layer 2;

[0052] During the formation of the channel layer 2 , the temperature of the reaction chamber is 1025-1070° C.; the pressure of the reaction chamber is 200-400 mbar; the gallium source has a first flow rate Q1, and the nitrogen source has a second flow rate Q2, satisfying: 500≤Q2 / Q1≤5000.

[0053] Specifically, the temperature of the reaction chamber may be any one of 1025° C., 1030° C., 1035° C., 1040° C., 1045° C., 1050° C., 1055° C., 1060° C., 1065° C., and 1070° C., or a range consisting of any two values; the pressure of the reaction chamber may be any one of 200 mbar, 250 mbar, 300 mbar, 350 mbar, and 400 mbar, or a range consisting of any two values; and the ratio (V / III) of the second flow rate Q2 to the first flow rate Q1 may be any one of 500, 1000, 1500, 2000, 2500, 3000, 3500, 4000, 4500, and 5000, or a range consisting of any two values.

[0054] It can be understood that the present application improves the crystal quality of the channel layer 2 while reducing the deep energy level defect density by controlling the temperature and pressure of the reaction chamber and the flow ratio of the gallium source to the nitrogen source, that is, by controlling the epitaxial growth temperature, epitaxial growth pressure and the flow ratio (V / III) of the channel layer 2.

[0055] In some embodiments, the formation time of the channel layer 2 is 10 to 50 minutes. Specifically, the formation time of the channel layer 2 (unit: min) can be any one of 10, 20, 30, 40, and 50 minutes, or a range consisting of any two of these values.

[0056] It can be understood that by controlling the formation time of the channel layer 2 , that is, controlling the growth time of the channel layer 2 , the thickness of the channel layer 2 can be controlled.

[0057] In some embodiments, a Metal-Organic Chemical Vapour Deposition (MOCVD) system is used as the epitaxial growth system. The MOCVD system herein comprises an epitaxial growth system primarily comprising a source supply system, a gas transport and flow control system, a reaction chamber and temperature control system, an exhaust gas treatment and safety alarm system, a wafer transport system, and an electrical control system. Epitaxial wafers grown using the MOCVD system exhibit excellent crystal quality.

[0058] In some embodiments, the gallium source is selected from triethylgallium (TEGa).

[0059] In some embodiments, the nitrogen source is selected from ammonia (NH 3 ).

[0060] It is understandable that in the preparation process of gallium nitride (GaN) epitaxial wafers, trimethylgallium (TMGa) is usually used as the gallium source for growing the gallium nitride (GaN) channel layer. TMGa easily decomposes into gallium atoms and carbon atoms at high temperatures, resulting in unintentional carbon doping of the GaN channel layer, reducing the crystal quality of the channel layer, and introducing deep energy level defects. The present application uses triethylgallium as a metal source and ammonia as a nitrogen source to epitaxially grow the gallium nitride (GaN) channel layer 2, and controls the temperature of epitaxial growth, the pressure of epitaxial growth, and the flow ratio of the gallium source to the nitrogen source. Ethyl groups are decomposed by TEGa, and gaseous ethylene is obtained through the elimination reaction of hydrogen of the ethyl group. Ethylene can be released from the channel layer 2 in a timely manner, thereby effectively reducing the carbon doping concentration in the channel layer 2, improving the crystal quality of the channel layer 2, and reducing the deep energy level defect density.

[0061] In some embodiments, the first flow rate Q1 is 500-3000 sccm. Specifically, the first flow rate Q1 can be any one of 500 sccm, 1000 sccm, 1500 sccm, 2000 sccm, 2500 sccm, and 3000 sccm, or a range consisting of any two of the values.

[0062] In some embodiments, the second flow rate Q2 is 250 to 15,000 slm. Specifically, the second flow rate Q2 can be any one of 250 slm, 500 slm, 1,000 slm, 2,000 slm, 3,000 slm, 4,000 slm, 5,000 slm, 6,000 slm, 7,000 slm, 8,000 slm, 9,000 slm, 10,000 slm, 11,000 slm, 12,000 slm, 13,000 slm, 14,000 slm, and 15,000 slm, or a range consisting of any two of the values.

[0063] It is understood that by using triethylgallium as the gallium source, the gaseous ethylene generated during the growth process can be promptly released from the channel layer 2, thereby effectively reducing the carbon doping concentration in the channel layer 2, improving the crystal quality of the channel layer 2, and reducing the deep energy level defect density. By controlling the value range of the first flow rate Q1 and the second flow rate Q2, that is, controlling the flow rates of the gallium source and the nitrogen source, the growth rate of the gallium nitride (GaN) channel layer 2 can be controlled, thereby more effectively reducing the carbon doping concentration in the channel layer 2, further improving the crystal quality of the channel layer 2, and reducing the deep energy level defect density.

[0064] In some embodiments, the gallium source is stored at a temperature of 15°C to 30°C, and a pressure of 600 to 1200 mbar. Specifically, the gallium source can be stored at a temperature of 15°C, 20°C, 25°C, or 30°C, or a range consisting of any two of these values; and the gallium source can be stored at a pressure of 600 mbar, 700 mbar, 800 mbar, 900 mbar, 1000 mbar, 1100 mbar, or 1200 mbar, or a range consisting of any two of these values.

[0065] It is understood that when the gallium source is stored in a storage tank, controlling the temperature and pressure of the storage tank, that is, controlling the storage temperature and pressure of the gallium source, can adjust the saturated vapor pressure of triethylgallium. This application ensures the safety of epitaxial growth by controlling the storage temperature and pressure of the gallium source. At the same time, by adjusting the saturated vapor pressure of triethylgallium, different proportions of triethylgallium in the total gas flow rate are achieved, facilitating adjustment of process parameters during the growth of the GaN channel layer 2.

[0066] In some embodiments, the gallium source is stored in a steel cylinder placed in a water bath having a temperature of 15-30° C. Specifically, the temperature of the water bath can be any one of 15° C., 20° C., 25° C., and 30° C., or a range consisting of any two of these values.

[0067] It is understandable that the temperature of the steel cylinder is controlled by the water bath, thereby controlling the storage temperature and saturated vapor pressure of the gallium source in the steel cylinder.

[0068] In some embodiments, the carrier gas of the gallium source is hydrogen, and the flow rate of the carrier gas is 100-170 slm. Specifically, the flow rate of the carrier gas can be any one of 100 slm, 110 slm, 120 slm, 130 slm, 140 slm, 150 slm, 160 slm, and 170 slm, or a range consisting of any two values.

[0069] It can be understood that by controlling the flow rate of the gallium source carrier gas to 100-170 slm, the growth rate of the gallium nitride (GaN) channel layer 2 can be controlled, so that the gaseous ethylene generated during the growth process can be released from the channel layer 2 in a timely manner, thereby effectively reducing the carbon doping concentration in the channel layer 2, improving the crystal quality of the channel layer 2, and reducing the deep energy level defect density.

[0070] In some embodiments, before forming the channel layer 2, the method further includes:

[0071] forming a nucleation layer 3 on one side of the substrate 1;

[0072] forming a first buffer layer 4 on a side of the nucleation layer 3 away from the substrate 1;

[0073] forming a second buffer layer 5 on a side of the first buffer layer 4 away from the nucleation layer 3;

[0074] A back barrier layer 6 is formed on a side of the second buffer layer 5 away from the nucleation layer 3;

[0075] The channel layer 2 is located on a side of the back barrier layer 6 away from the second buffer layer 5 .

[0076] In some embodiments, after forming the channel layer 2 on the substrate 1, the method further includes:

[0077] An insertion layer 7 is formed on a side of the channel layer 2 away from the back barrier layer 6;

[0078] A barrier layer 8 is formed on a side of the insertion layer 7 away from the channel layer 2;

[0079] A surface layer 9 is formed on the side of the barrier layer 8 that is away from the insertion layer 7 .

[0080] It can be understood that the formation of a nucleation layer 3 on one side of the substrate 1 can introduce compressive stress to compensate for the tensile stress of the epitaxial wafer, thereby improving the stress and warping during the epitaxial growth process, avoiding the occurrence of surface microcracks, and improving the quality and uniformity of the epitaxial wafer; the formation of a first buffer layer 4 on the side of the nucleation layer 3 away from the substrate 1 can filter the penetrating dislocations formed by the growth of the nucleation layer 3 and reduce the crystal defect density; the formation of a second buffer layer 5 on the side of the first buffer layer 4 away from the nucleation layer 3, the second buffer layer 5 is a superlattice stacking structure, which can increase the impedance of the epitaxial wafer in the vertical direction, thereby improving the vertical breakdown voltage of the epitaxial wafer and the device; the formation of a back barrier layer 6 on the side of the second buffer layer 5 away from the first buffer layer 4 can prevent the electrons in the channel layer 2 from diffusing to the side of the substrate 1, thereby And enhance the conductivity of the channel layer 2; the channel layer 2 is formed on the side of the back barrier layer 6 away from the second buffer layer 5, and the spontaneous polarization of GaN in the channel layer 2 generates a large number of conductive electrons in the channel layer 2, and the electron density is higher on the side close to the insertion layer 7, making the channel layer 2 conductive; the insertion layer 7 and the barrier layer 8 are formed in sequence on the side of the channel layer 2 away from the back barrier layer 6. On the one hand, the piezoelectric polarization between the channel layer 2 and the barrier layer 8 will increase the electron density in the channel layer 2 and improve the conductivity of the channel layer 2. On the other hand, the insertion layer 7 will reduce the carrier scattering between the channel layer 2 and the barrier layer 8 and improve the conductivity of the channel layer 2; a surface layer 9, that is, a cap layer, is formed on the side of the barrier layer 8 away from the insertion layer 7, which can protect the barrier layer 8 and prevent the barrier layer 8 from being oxidized, thereby improving the performance of the epitaxial wafer.

[0081] In some embodiments, the material of the substrate 1 is selected from any one of silicon (Si), silicon carbide (SiC), or sapphire.

[0082] In some embodiments, the material of the nucleation layer 3 is selected from AlN.

[0083] In some embodiments, the material of the back barrier layer 6 is selected from AlGaN.

[0084] In some embodiments, the material of the channel layer 2 is selected from GaN.

[0085] In some embodiments, the material of the insertion layer 7 is selected from any one of AlN, AlGaN, or SiNx.

[0086] In some embodiments, the material of the surface layer 9 is selected from GaN, P-GaN or SiN x Any one of .

[0087] It can be understood that by using Si substrate, the cost can be greatly reduced; by using AlN to prepare the nucleation layer 3, the formation of silicon-gallium alloy can be avoided, thereby avoiding melt-back etching, and the lattice constant of AlN is more matched with GaN, which can improve the crystal quality of GaN; by using AlGaN back barrier layer 6, the conductivity of channel layer 2 can be improved; by using AlN, AlGaN or SiNx insertion layer 7, carrier scattering can be reduced and the mobility of carriers in channel layer 2 can be improved; by using GaN, P-GaN or SiN x The surface layer 9 can prevent the barrier layer 8 from being oxidized, thereby improving the quality of the epitaxial wafer.

[0088] In some embodiments, during the formation of the first buffer layer 4 , the second buffer layer 5 , the back barrier layer 6 , the channel layer 2 , the insertion layer 7 , the barrier layer 8 , and the surface layer 9 , the gallium source is selected from trimethyl gallium or triethyl gallium.

[0089] In some embodiments, the thickness of the nucleation layer 3 is 200-300 nm. Specifically, the thickness of the nucleation layer 3 can be any one of 200 nm, 210 nm, 220 nm, 230 nm, 240 nm, 250 nm, 260 nm, 270 nm, 280 nm, 290 nm, and 300 nm, or a range consisting of any two of these values.

[0090] In some embodiments, the thickness of the first buffer layer 4 is 1500-2000 nm. Specifically, the thickness of the first buffer layer 4 can be any one of 1500 nm, 1600 nm, 1700 nm, 1800 nm, 1900 nm, and 2000 nm, or a range consisting of any two of these values.

[0091] In some embodiments, the thickness of the second buffer layer 5 is 1200-1800 nm. Specifically, the thickness of the second buffer layer 5 can be any one of 1200 nm, 1300 nm, 1400 nm, 1500 nm, 1600 nm, 1700 nm, and 1800 nm, or a range consisting of any two of these values.

[0092] In some embodiments, the back barrier layer 6 has a thickness of 600-1200 nm. Specifically, the thickness of the back barrier layer can be any one of 600 nm, 700 nm, 800 nm, 900 nm, 1000 nm, 1100 nm, and 1200 nm, or a range consisting of any two of these values.

[0093] In some embodiments, the thickness of the channel layer 2 is 150-200 nm. Specifically, the thickness of the channel layer 2 can be any one of 150 nm, 160 nm, 170 nm, 180 nm, 190 nm, and 200 nm, or a range consisting of any two of these values.

[0094] In some embodiments, the thickness of the insertion layer 7 is 0.5-2 nm. Specifically, the thickness of the insertion layer 7 can be any one of 0.5 nm, 1 nm, 1.5 nm, and 2 nm, or a range consisting of any two of these values.

[0095] In some embodiments, the barrier layer 8 has a thickness of 15 to 25 nm. Specifically, the thickness of the barrier layer 8 can be any one of 15 nm, 18 nm, 20 nm, 13 nm, and 25 nm, or a range consisting of any two of these values.

[0096] In some embodiments, the thickness of the surface layer 9 is 1-3 nm. Specifically, the thickness of the surface layer 9 can be any one of 1 nm, 1.5 nm, 2 nm, 2.5 nm, and 3 nm, or a range consisting of any two of these values.

[0097] It can be understood that due to the lattice mismatch and thermal mismatch between the substrate 1 and the nucleation layer 3, cracks are prone to occur on the surface of the epitaxial layer, and the thicker the epitaxial layer, the more difficult it is to avoid surface cracks. Therefore, the nucleation layer 3, the first buffer layer 4, the second buffer layer 5, the back barrier layer 6, the channel layer 2, the insertion layer 7, the barrier layer 8 and the surface layer 9 must have a certain thickness to realize their functions, and at the same time, an upper limit needs to be set for their thickness to avoid the epitaxial layer being too thick and causing cracks on the surface of the epitaxial wafer; by controlling the thickness of the nucleation layer 3 to be 200-300nm, the pinholes on the surface of the nucleation layer 3 can be reduced and surface cracks can be avoided, while providing appropriate tensile stress to balance the compressive stress and improve the crystal quality of the epitaxial layer; by controlling the thickness of the first buffer layer 4 to be 1500-2000nm, the penetrating dislocations can be filtered and the lattice mismatch between the AlN nucleation layer 3 and the AlGaN back barrier layer 6 can be gradually improved; by controlling the thickness of the second buffer layer 5 The thickness is 1200-1800nm, which can increase the impedance of the epitaxial wafer in the vertical direction; by controlling the thickness of the back barrier layer 6 to 600-1200nm, the carrier mobility can be improved, thereby enhancing the conductivity of the channel layer 2 and improving the electrical performance of the epitaxial wafer; by controlling the thickness of the channel layer 2 to 150-200nm, the channel layer 2 has a certain thickness to improve the horizontal withstand voltage. At the same time, an overly thick channel layer 2 causes its surface crystal quality to decrease and the defect density to increase, which will reduce the conductivity of the channel layer 2 and deteriorate the core performance of the epitaxial wafer; by controlling the thickness of the insertion layer 7 to 0.5-2nm, it can be ensured that the insertion layer 7 completely covers the surface of the channel layer 2, inhibiting carrier scattering in the channel layer 2, and avoiding the weakening of the piezoelectric polarization due to the excessive thickness of the insertion layer 7, which causes the conductivity of the channel layer 2 to decrease; by controlling the thickness of the barrier layer 8 to 15-25nm, combined with the control chemical formula of Al y Ga 1-y In the barrier layer 8 of N, 0.15≤y≤0.25 is achieved, so that the square resistance range of the epitaxial wafer is 350~650Ω / sq, which meets the requirements of device preparation; by controlling the thickness of the surface layer 9 to 1~3nm, it can be ensured that the surface layer 9 covers the surface of the barrier layer 8, protecting the barrier layer 8 and preventing it from oxidation.

[0098] In some embodiments, the material of the barrier layer 8 is selected from AlGaN, and the chemical formula of AlGaN is Al y Ga 1-y N, wherein 0.15≤y≤0.25. Specifically, the value of y can be any one of 0.15, 0.18, 0.20, 0.23, and 0.25, or a range consisting of any two values.

[0099] It can be understood that when the value of y, that is, the molar content of Al in the barrier layer 8 satisfies the above-mentioned value range, the Al component can generate sufficient two-dimensional electron gas without increasing scattering and affecting mobility, thereby achieving an epitaxial wafer square resistance range of 350 to 650Ω / sq, which meets the requirements of device preparation.

[0100] In some embodiments, the first buffer layer 4 includes an AlGaN layer stacked with a K layer, satisfying: 3≤K≤5. Specifically, the value of K can be any one of 3, 4, and 5, or a range consisting of any two values.

[0101] It can be understood that by controlling the first buffer layer 4 to include an AlGaN layer stacked with K layers, satisfying: 3≤K≤5, the first buffer layer 4 can gradually filter the penetrating dislocations formed by the growth of the nucleation layer 3, and can achieve layer-by-layer filtering, thereby greatly reducing crystal defects.

[0102] In some embodiments, the material of the first buffer layer 4 is selected from AlGaN, and the chemical formula of AlGaN is Al x Ga 1-x N, wherein 0.05≤x≤0.95, and the molar content of Al in the first buffer layer 4 gradually decreases in a direction away from the nucleation layer 3. Specifically, the value of x can be any one of 0.05, 0.1, 0.15, 0.2, 0.25, 0.3, 0.35, 0.4, 0.45, 0.5, 0.55, 0.6, 0.65, 0.7, 0.75, 0.8, 0.85, 0.9, and 0.95, or a range consisting of any two of these values.

[0103] It can be understood that when the value of x, that is, the molar content of Al in the first buffer layer 4 satisfies the above value range, the defect density can be rapidly reduced while reducing the lattice mismatch of epitaxial growth.

[0104] In some embodiments, the second buffer layer 5 includes L stacked AlN / GaN layers, and 40≤L≤60. Specifically, the value of L can be any one of 40, 45, 50, 55, and 60, or a range consisting of any two values.

[0105] It can be understood that the second buffer layer 5 is a superlattice stacking structure. In the AlN / GaN stacking layer, the AlN layer is a wide bandgap layer and the GaN layer is a narrow bandgap layer. The present application sets a superlattice stacking structure on the side of the first buffer layer 4 away from the nucleation layer 3, wherein the AlN / GaN stacking layer in the superlattice stacking layer can block dislocations, improve stress and warping during epitaxial growth, inhibit the occurrence of microcracks, and improve the quality and uniformity of epitaxial wafers.

[0106] In some embodiments, in the AlN / GaN stack, the thickness of the AlN layer is 1 to 10 nm, and the thickness of the GaN layer is 10 to 50 nm. Specifically, in the AlN / GaN stack, the thickness of the AlN layer can be any one of 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, and 10 nm, or a range consisting of any two values; in the AlN / GaN stack, the thickness of the GaN layer can be any one of 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, and 50 nm, or a range consisting of any two values.

[0107] In some embodiments, the material of the back barrier layer 6 is selected from AlGaN, and the chemical formula of AlGaN is Al z Ga 1-z N, wherein 0.01≤z≤0.1. Specifically, the value of z can be any one of 0.01, 0.02, 0.03, 0.04, 0.05, 0.06, 0.07, 0.08, 0.09, and 0.1, or a range consisting of any two values.

[0108] It can be understood that when the value of z, that is, the molar content of Al in the back barrier layer 6 satisfies the above value range, the channel layer 2 can have a smaller lattice mismatch during growth, while raising the energy band of the channel layer 2 and increasing the mobility of the two-dimensional electron gas.

[0109] See Figure 1 In a second aspect, the present application provides an epitaxial wafer prepared using the aforementioned epitaxial wafer preparation method. Specifically, the epitaxial wafer includes a substrate 1 and an epitaxial structure disposed on one side of the substrate 1. The epitaxial structure includes, but is not limited to, a nucleation layer 3, a first buffer layer 4, a second buffer layer 5, a back barrier layer 6, a channel layer 2, an insertion layer 7, a barrier layer 8, and a surface layer 9.

[0110] It can be understood that the present application uses triethylgallium as a metal source and ammonia as a nitrogen source to epitaxially grow a gallium nitride (GaN) channel layer 2, and controls the temperature of epitaxial growth, the pressure of epitaxial growth, and the flow ratio of the gallium source to the nitrogen source. Ethyl groups are cracked out by TEGa, and gaseous ethylene is obtained by the elimination reaction of hydrogen of the ethyl group, which can be released from the channel layer 2 in a timely manner, effectively reducing the carbon doping concentration in the channel layer 2, improving the crystal quality of the channel layer 2, and reducing the deep energy level defect density.

[0111] In some embodiments, the epitaxial wafer includes a substrate 1 and an epitaxial structure, the epitaxial structure is located on one side of the substrate 1, and the epitaxial structure includes a channel layer 2, the channel layer 2 is doped with carbon atoms, and the carbon atom concentration is 1E15 to 5E15 atoms / cm -3Specifically, the carbon atoms doped in the channel layer 2 are unintentionally doped, and the carbon atom concentration is 1E15atom / cm -3 、2E15atom / cm -3 、3E15atom / cm -3 、4E15atom / cm -3 、5E15atom / cm -3 Any value or any two values ​​in the range.

[0112] It can be understood that the carbon atom concentration in the channel layer of the epitaxial wafer prepared by using triethylgallium as the metal source is reduced by about one order of magnitude compared to the epitaxial wafer prepared by using trimethylgallium as the metal source.

[0113] The present application will be described below with reference to specific embodiments.

[0114] Example 1

[0115] Step S1: providing an 8-inch silicon substrate and placing the silicon substrate in a reaction chamber for epitaxial growth, wherein the crystal orientation of silicon in the silicon substrate is (111) and the thickness of the silicon substrate is 1150 μm;

[0116] Step S2: in-situ growing an AlN nucleation layer on a silicon substrate with a thickness of 250 nm;

[0117] Step S3: in-situ growing a first buffer layer on the AlN nucleation layer, the first buffer layer comprising four AlGaN layers stacked sequentially, wherein the molar content of Al in each AlGaN layer is 78%, 50%, 30%, and 20%, respectively, and the thicknesses are 250 nm, 500 nm, 500 nm, and 500 nm, respectively;

[0118] Step S4: growing a second buffer layer on the first buffer layer. The second buffer layer is an SLS superlattice layer, comprising 50 stacked AlN / GaN layers. In the AlN / GaN stack, the thickness of the AlN layer is 3 nm, and the thickness of the GaN layer is 27 nm. The total thickness of the SLS superlattice layer is 1500 nm.

[0119] Step S5: growing an AlGaN back barrier layer on the second buffer layer, wherein the molar content of Al in the back barrier layer is 5% and the thickness is 900 nm;

[0120] Step S6: introducing a gallium source and a nitrogen source into the reaction chamber to grow a GaN channel layer on the AlGaN back barrier layer, wherein the gallium source is TEGa, the nitrogen source is NH3, the temperature of TEGa in the TEGa cylinder is 30°C, the pressure of TEGa in the TEGa cylinder is 800 mbar, the temperature of the reaction chamber is 1050°C, the pressure of the reaction chamber is 200 mbar, the flow rate of TEGa is 1000 sccm, the flow rate of ammonia is 2100 slm, the V / III ratio is 2100, the carrier gas is hydrogen, the flow rate of the carrier gas is 150 slm, the growth time is 25 min, and the thickness of the GaN channel layer is 200 nm;

[0121] Step S7: growing an AlN insertion layer on the GaN channel layer with a thickness of 1 nm;

[0122] Step S8: growing an AlGaN barrier layer on the AlN insertion layer, wherein the molar concentration of Al in the AlGaN barrier layer is 23% and the thickness is 22 nm;

[0123] Step S9: growing a GaN surface layer on the AlGaN barrier layer with a thickness of 2 nm;

[0124] Step S10: Cooling in situ to room temperature to complete the growth of the GaN epitaxial wafer.

[0125] Example 2

[0126] The preparation method of Example 2 is the same as that of Example 1, except that the process parameters for growing the GaN channel layer are adjusted. Specifically, the temperature of TEGa in the TEGa cylinder is 30°C, the pressure of TEGa in the TEGa cylinder is 800 mbar, the temperature of the reaction chamber is 1040°C, the pressure of the reaction chamber is 200 mbar, the flow rate of TEGa is 3000 sccm, the flow rate of NH3 is 1500 slm, the V / III ratio is 500, the carrier gas is hydrogen, the flow rate of the carrier gas is 150 slm, the growth time is 10 min, and the thickness of the GaN channel layer is 200 nm.

[0127] Example 3

[0128] The preparation method of Example 3 is the same as that of Example 1, except that the process parameters for growing the GaN channel layer are adjusted. Specifically, the temperature of TEGa in the TEGa cylinder is 30°C, the pressure of TEGa in the TEGa cylinder is 800 mbar, the temperature of the reaction chamber is 1040°C, the pressure of the reaction chamber is 200 mbar, the flow rate of TEGa is 3000 sccm, the flow rate of NH3 is 15000 slm, the V / III ratio is 5000, the carrier gas is hydrogen, the flow rate of the carrier gas is 150 slm, the growth time is 10 min, and the thickness of the GaN channel layer is 200 nm.

[0129] Comparative Example 1

[0130] The preparation direction of Comparative Example 1 is the same as that of Example 1, except that the process parameters for growing the GaN channel layer are adjusted. Specifically, the gallium source is trimethylgallium (TMGa), the nitrogen source is NH3, the temperature of TMGa in the TMGa cylinder is 5°C, the TMGa pressure in the TMGa cylinder is 1000 mbar, the temperature of the reaction chamber is 1050°C, the pressure of the reaction chamber is 200 mbar, the flow rate of TMGa is 250 sccm, the flow rate of ammonia is 200 slm, the V / III ratio is 800, the carrier gas is hydrogen, the flow rate of the carrier gas is 150 slm, the growth time is 330 s, and the thickness of the GaN channel layer is 200 nm.

[0131] Performance testing methods

[0132] (1) Secondary-ion mass spectrometry (SIMS) was used to measure the concentration of carbon atoms in the GaN channel layer. The test results are shown in Table 1.

[0133] (2) X-ray diffraction (XRD) was used to evaluate the crystal quality of the GaN channel layer from the crystal plane index (002) and (102), and the full width at half maximum (FWHM) was used to characterize the quality. The test results are shown in Table 1.

[0134] (3) Photoluminescence (PL) spectroscopy was used to measure the ratio of the yellow light intensity to the intrinsic band intensity of GaN in the epitaxial wafer (YL / BE). The smaller the value, the smaller the deep level defect density. The test results are shown in Table 1.

[0135] Table 1 shows the test results of the epitaxial wafers prepared in Examples 1 to 3 and Comparative Example 1.

[0136]

[0137]

[0138] Result analysis:

[0139] From the test results of Example 1, Comparative Example 1 and Table 1, it can be seen that the carbon atom concentration in the GaN channel layer decreases from 2E16 to 3E15, the half-peak width of GaN (002) decreases from 638.7 arcsec to 570.4 arcsec, the half-peak width of GaN (102) decreases from 1153.9 arcsec to 1030.2 arcsec, and YL / BE decreases from 1.05% to 0.18%. The carbon atom concentration in the GaN channel layer decreases significantly, and the crystal quality is significantly improved.

[0140] It can be seen from the test results of Example 1 and Example 2 and Table 1 that low growth temperature, high growth rate and low V / III ratio are all conducive to self-doping of carbon atoms, and low V / III ratio will reduce the quality of GaN crystal. Compared with Example 1, the carbon atom concentration of Example 2 increases from 3E15 to 5E15, the half-peak width of GaN (002) increases from 570.4 arcsec to 598.8 arcsec, the half-peak width of GaN (102) increases from 1030.2 arcsec to 1098.8 arcsec, and YL / BE increases from 0.18% to 0.23%. The carbon atom concentration in the GaN channel layer increases significantly, and the crystal quality decreases significantly.

[0141] It can be seen from the test results of Example 3 and Example 2 and Table 1 that since a high V / III ratio is beneficial to reducing the self-doping of carbon atoms, and a high V / III ratio will improve the quality of GaN crystals, compared with Example 2, the carbon atom concentration of Example 3 is reduced from 5E15 to 4E15, the half-peak width of GaN (002) is increased from 598.8 arcsec to 576.8 arcsec, the half-peak width of GaN (102) is reduced from 1098.8 arcsec to 1038.6 arcsec, and YL / BE is reduced from 0.23% to 0.20%. The carbon atom concentration in the GaN channel layer is significantly reduced, and the crystal quality is significantly improved.

[0142] From the test results of Example 2, Comparative Example 1 and Table 1, it can be seen that when Example 2 uses triethylgallium as the gallium source, even if low growth temperature, high growth rate, low V / III ratio, which are process conditions that are conducive to carbon atom self-doping, are adopted, compared with Comparative Example 1, the carbon atom concentration of Example 2 decreases from 2E16 to 5E15, the half-peak width of GaN (002) decreases from 638.7 arcsec to 598.8 arcsec, the half-peak width of GaN (102) decreases from 1153.9 arcsec to 1098.8 arcsec, and YL / BE decreases from 1.05% to 0.23%. The carbon atom concentration in the GaN channel layer is significantly reduced and the crystal quality is significantly improved, indicating that when triethylgallium is used as the gallium source, even under process conditions such as low growth temperature, high growth rate, and low V / III ratio, which are process conditions that are conducive to carbon atom self-doping, the carbon atom concentration in the GaN crystal can still be greatly reduced, thereby reducing carbon atom self-doping.

[0143] The above is a detailed introduction to the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. At the same time, for those skilled in the art, based on the idea of ​​the present application, there may be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A method for preparing an epitaxial wafer, characterized in that: include: forming a nucleation layer (3) on one side of the substrate (1); A first buffer layer (4) is formed on a side of the nucleation layer (3) away from the substrate (1); the first buffer layer (4) comprises an AlGaN layer stacked with a K layer, satisfying: 3≤K≤5; the material of the first buffer layer (4) is selected from AlGaN, and the chemical formula of AlGaN is Al x Ga 1-x N, wherein 0.05≤x≤0.95, and the molar content of Al in the first buffer layer (4) gradually decreases in a direction away from the nucleation layer (3); forming a second buffer layer (5) on a side of the first buffer layer (4) away from the nucleation layer (3); forming a back barrier layer (6) on a side of the second buffer layer (5) away from the nucleation layer (3); An epitaxial structure is formed on a substrate (1) located in a reaction chamber, wherein the epitaxial structure comprises a channel layer (2), wherein the channel layer (2) is doped with carbon atoms, and the carbon atom concentration is 1E15 to 5E15 atom / cm -3 The channel layer (2) is located on a side of the back barrier layer (6) away from the second buffer layer (5); the thickness of the channel layer (2) is 150 to 200 nm; the material of the channel layer (2) is selected from GaN; the formation time of the channel layer (2) is 10 to 50 minutes; In the process of forming the channel layer (2), a gallium source and a nitrogen source are introduced into the reaction chamber, the gallium source is selected from triethyl gallium, the nitrogen source is selected from ammonia, the storage temperature of the gallium source is 15-30°C, the storage pressure of the gallium source is 600-1200 mbar, the temperature of the reaction chamber is 1025-1070°C; the pressure of the reaction chamber is 200-400 mbar; the gallium source has a first flow rate Q1, and the nitrogen source has a second flow rate Q2, satisfying: 500≤Q2 / Q1≤5000; the first flow rate Q1 is 500-3000 sccm; the second flow rate Q2 is 250-15000 slm.

2. The method for preparing an epitaxial wafer according to claim 1, wherein: After forming the channel layer (2), the method further comprises: forming an insertion layer (7) on a side of the channel layer (2) away from the back barrier layer (6); forming a barrier layer (8) on a side of the insertion layer (7) away from the channel layer (2); A surface layer (9) is formed on a side of the barrier layer (8) away from the insertion layer (7).

3. The method for preparing an epitaxial wafer according to claim 2, wherein: The material of the substrate (1) is selected from any one of silicon, silicon carbide or sapphire; and / or, The material of the nucleation layer (3) is selected from AlN; and / or, The material of the back barrier layer (6) is selected from AlGaN; and / or, The material of the insertion layer (7) is selected from AlN, AlGaN or SiN x Any of; and / or, The material of the surface layer (9) is selected from GaN, P-GaN or SiN x Any one of .

4. The method for preparing an epitaxial wafer according to claim 3, wherein: The thickness of the nucleation layer (3) is 200 to 300 nm; and / or, The thickness of the first buffer layer (4) is 1500-2000 nm; and / or, The thickness of the second buffer layer (5) is 1200-1800 nm; and / or, The thickness of the back barrier layer is 600 to 1200 nm; and / or, The thickness of the insertion layer (7) is 0.5 to 2 nm; and / or, The barrier layer (8) has a thickness of 15 to 25 nm; and / or, The thickness of the surface layer (9) is 1 to 3 nm.

5. The method for preparing an epitaxial wafer according to claim 3, wherein: The material of the barrier layer (8) is selected from AlGaN, and the chemical formula of AlGaN is Al y Ga 1-y N, where 0.15≤y≤0.

25.

6. The method for preparing an epitaxial wafer according to claim 1, wherein: The second buffer layer (5) comprises L stacked AlN / GaN layers, 40≤L≤60.

7. The method for preparing an epitaxial wafer according to claim 6, wherein: In the AlN / GaN stack, the thickness of the AlN layer is 1 to 10 nm, and the thickness of the GaN layer is 10 to 50 nm.

8. An epitaxial wafer, characterized in that: The epitaxial wafer is prepared by the method for preparing the epitaxial wafer according to any one of claims 1 to 7.

9. The epitaxial wafer according to claim 8, characterized in that: The epitaxial wafer comprises a substrate (1) and an epitaxial structure, wherein the epitaxial structure is located on one side of the substrate (1), and the epitaxial structure comprises the channel layer (2).

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