Photovoltaic cell with selective polycrystalline silicon layer and preparation method thereof, and photovoltaic module

Abstract

The present application discloses a photovoltaic cell with a selective polysilicon layer and a preparation method thereof, and a photovoltaic module, and relates to the technical field of photovoltaic cells; wherein the method comprises the following steps: performing a texturing treatment on a silicon wafer; sequentially depositing a tunneling oxide layer, a first amorphous silicon layer, and a second amorphous silicon layer on the surface of the silicon wafer; performing high-temperature diffusion so that the first amorphous silicon layer and the second amorphous silicon layer form a first doped polysilicon layer and a second doped polysilicon layer; subsequently, placing the silicon wafer in a nitric acid solution so that a first oxide layer is formed on the surface of the silicon wafer; then placing the silicon wafer in an ozone atmosphere, and using a first laser to scan a gate line region, so that a second oxide layer is formed on the gate line region; removing the silicon wafer from the ozone atmosphere, and using a second laser to scan a non-gate line region; using a wet alkali treatment to remove the second doped polysilicon layer and the first oxide layer in the non-gate line region of the silicon wafer; and using an acid to remove the first oxide layer and the second oxide layer in the gate line region.

Description

Technical Field

[0001] The present application relates to the field of photovoltaic cell technology, and in particular to a photovoltaic cell with a selective polysilicon layer, a preparation method thereof, and a photovoltaic module. Background Art

[0002] How to form a passivation structure with better performance in TOPCon (Tunnel Oxide Passivated Contact) batteries and TBC (Tunnel Back Contact) batteries is the current research focus.

[0003] The existing passivation structure is mainly composed of a tunneling oxide layer and a polysilicon layer. Since the polysilicon layer has optical parasitic phenomena, which affects the passivation effect, how to reduce the optical parasitic absorption of polysilicon in the passivation structure has always been a research difficulty in the passivation structure. Summary of the invention

[0004] The purpose of the present application is to provide a photovoltaic cell with a selective polysilicon layer, a preparation method thereof, and a cell assembly. The present application adopts hot nitric acid solution and ozone environment laser scanning to first prepare an oxide layer. The thickness of the oxide layer can effectively resist the wet etching of the doped polysilicon layer to form a selective polysilicon layer. By forming a selective polysilicon layer, the optical absorption caused by the excessive thickness of the doped polysilicon layer in the non-gate line area can be effectively reduced, thereby significantly improving the passivation effect and the electrical performance of the photovoltaic cell.

[0005] A first aspect of the present application provides a method for preparing a photovoltaic cell having a selective polycrystalline silicon layer, the method comprising the following steps:

[0006] Step 101: Select a silicon wafer and perform a texturing process on the silicon wafer;

[0007] Step 102: depositing a tunneling oxide layer, a first amorphous silicon layer, and a second amorphous silicon layer in sequence on the surface of the silicon wafer;

[0008] Step 103: performing high temperature diffusion so that the first amorphous silicon layer and the second amorphous silicon layer form a first doped polysilicon layer and a second doped polysilicon layer;

[0009] Step 104: Subsequently, placing the silicon wafer in a nitric acid solution so that a first oxide layer is formed on the surface of the silicon wafer;

[0010] Step 105: placing the silicon wafer in an ozone atmosphere, and scanning the gate line region with a first laser, so that a second oxide layer is formed on the gate line region;

[0011] Step 106: moving the silicon wafer out of the ozone atmosphere, and scanning the non-gate line area with a second laser; wherein the spot diameter of the first laser is larger than the spot diameter of the second laser;

[0012] Step 107: removing the second doped polysilicon layer and the first oxide layer in the non-gate line region of the silicon wafer by wet alkali treatment; and removing the first oxide layer and the second oxide layer in the gate line region by acid.

[0013] In an optional manner, the thickness of the second oxide layer is greater than the thickness of the first oxide layer.

[0014] In an optional manner, in step 104, the mass fraction of the nitric acid solution is 50%-90%, and the temperature is 50-100°C; and / or, in step 104, the time for which the first silicon wafer is placed in the nitric acid solution is 100-2000 seconds.

[0015] In an optional manner, in step 105, the first laser is picosecond or nanosecond, with a spot diameter of 50-100 µm, a wavelength of 193-1064 nm, a repetition frequency of 100-1000 KHz, an output power of 1-10 W, and a laser energy density of 0.1 J / cm 2 -1J / cm 2 ; and / or, in step 106, the spot diameter of the second laser is larger than the spot diameter of the first laser; the second laser is picosecond or nanosecond, with a spot diameter of 80-120µm, a wavelength of 193-1064nm, a repetition frequency of 100-1000KHz, an output power of 1-20W, and a laser energy density of 0.5JJ / cm 2 -4J / cm 2 .

[0016] In an optional manner, in step 105, in the ozone atmosphere, the ozone flow rate is 10000-40000 sccm.

[0017] In an optional manner, in step 107, the solution of the wet alkali treatment is at least one of KOH, NaOH, and NH4OH.

[0018] In an optional manner, in step 107, the acid is at least one of hydrochloric acid or hydrofluoric acid.

[0019] In an optional manner, in step 107, the mass fraction of the solution is 1%-20%; and / or, an additive is provided in the solution, and the additive is at least one of a detergent, an oxidant, a diffusant, a surfactant, a buffer, a defoaming agent or a promoter, and the mass fraction of the additive is 1%-3%.

[0020] The second aspect of the present application provides a photovoltaic cell having a selective polycrystalline silicon layer, which is prepared by the preparation method of the first aspect of the present application.

[0021] In an optional embodiment, a photovoltaic cell includes a silicon wafer and a passivation layer, wherein the passivation layer is arranged on the surface of the silicon wafer, and the passivation layer is sequentially provided with a tunneling oxide layer, a first doped polysilicon layer and a second doped polysilicon layer on the surface of the silicon wafer, wherein the tunneling oxide layer and the first doped polysilicon layer are arranged in an area on the entire surface of the silicon wafer; and the second doped polysilicon layer is arranged in a gate line area.

[0022] In an optional manner, in the gate line region, the thickness of the second doped polysilicon layer is greater than the thickness of the first doped polysilicon layer.

[0023] The third aspect of the present application provides a photovoltaic assembly, comprising any photovoltaic cell described in the second aspect of the present application.

[0024] Compared with the prior art, this application:

[0025] (1) The present application obtains a selective polysilicon layer by preparation, and the second doped polysilicon layer is only arranged in the gate line area, thereby greatly reducing the optical absorption caused by the excessive thickness of the doped polysilicon layer in the non-gate line area, significantly improving the passivation effect, and improving the electrical performance of the photovoltaic cell.

[0026] (2) The present application adopts hot nitric acid solution and ozone environment laser scanning to first prepare an oxide layer, the thickness of which can effectively resist wet etching of the doped polysilicon layer, and then uses acid to remove the oxide layer to prepare a selective polysilicon layer. The method is simple, low-cost, and the prepared battery has good efficiency and is suitable for large-scale promotion.

[0027] (3) The present application adopts ozone environment laser scanning to grow the second oxide layer, which can further increase the oxygen content in the first doped polysilicon layer and further improve the passivation effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0029] Figure 1 A schematic flow chart of the method for preparing a photovoltaic cell of the present application is shown.

[0030] Figure 2 A schematic diagram showing an embodiment of a passivation layer structure of a photovoltaic cell of the present application.

[0031] Figure 3A schematic diagram of an embodiment of the passivation layer structure preparation process of the present application is shown.

[0032] Figure 4 A schematic diagram of another embodiment of the passivation layer structure preparation process of the present application is shown.

[0033] Reference numerals:

[0034] 1-silicon wafer; 2-tunneling oxide layer; 3-first doped polysilicon layer; 4-second doped polysilicon layer; 5-first oxide layer; 6-second oxide layer. DETAILED DESCRIPTION

[0035] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0036] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "multiple" means two or more, unless otherwise clearly and specifically defined. "Several" means one or more, unless otherwise clearly and specifically defined.

[0037] Studies have shown that recombination on the back side of TOPcon cells accounts for 9.2% of the total recombination losses of the cells. Optical parasitic absorption of the back polysilicon layer is an important cause of cell efficiency loss and is also a research difficulty in the passivation structure.

[0038] The first aspect of the present application provides a method for preparing a photovoltaic cell with a selective polycrystalline silicon layer. The back polycrystalline silicon layer prepared by the method of the present application is selectively arranged in the gate line area and the non-gate line area, effectively reducing the optical absorption caused by the excessive thickness of the doped polycrystalline silicon layer in the non-gate line area, significantly improving the passivation effect, and improving the electrical performance of the photovoltaic cell.

[0039] The preparation method of the present application, such as Figure 1 As shown, the following steps are included:

[0040] Step 101: Select a silicon wafer and perform a texturing process on the silicon wafer;

[0041] In this step, the silicon wafer is a silicon wafer that has been squared, chamfered, sliced, cleaned and sorted from a crystal rod. The silicon wafer can be an N-type single crystal silicon wafer or a P-type single crystal silicon wafer. After the silicon wafer is prepared into a battery cell, it is generally divided into a front side and a back side relative to each other. The front side is generally the main side that absorbs sunlight. In a general photovoltaic module, the front side of the silicon wafer or battery refers to the side that is in contact with the glass in the photovoltaic module; the back side is the side away from the glass in the photovoltaic module.

[0042] The silicon wafer is subjected to texturing treatment to obtain a velvet structure on the surface of the silicon wafer; generally refers to the silicon wafer being subjected to alkali texturing treatment to form a pyramid structure on the silicon wafer.

[0043] In an optional manner, the surface of the silicon wafer forming the passivation layer needs to be alkaline polished so that a tower base structure is formed on the surface of the silicon wafer, so that the passivation layer can be deposited. The passivation layer in this application can be set on the front side of the silicon wafer or on the back side of the silicon wafer, which is not limited in this application. Texturing treatment and alkaline polishing treatment are conventional technologies for preparing battery cells and will not be described in detail here.

[0044] Step 102: depositing a tunneling oxide layer, a first amorphous silicon layer, and a second amorphous silicon layer in sequence on the surface of the silicon wafer;

[0045] In this step, a tunneling oxide layer, a first amorphous silicon layer, and a second amorphous silicon layer are deposited on the surface of the silicon wafer; for example, LPCVD (Low Pressure Chemical Vapor Deposition) or PECVD (Plasma-Enhanced Chemical Vapour Deposition) can be used to sequentially deposit a tunneling oxide layer, a first amorphous silicon layer, and a second amorphous silicon layer on the surface of the silicon wafer. The tunneling oxide layer, the first amorphous silicon layer, and the second amorphous silicon layer are arranged on the entire surface of the silicon wafer.

[0046] Step 103: performing high temperature diffusion so that the first amorphous silicon layer and the second amorphous silicon layer form a first doped polysilicon layer and a second doped polysilicon layer;

[0047] In this step, after high temperature diffusion, the first amorphous silicon layer and the second amorphous silicon layer are formed into a first doped polysilicon layer and a second doped polysilicon layer, and the first silicon wafer is a silicon wafer including a tunneling oxide layer, a first doped polysilicon layer and a second doped polysilicon layer. At this time, the tunneling oxide layer, the first doped polysilicon layer and the second doped polysilicon layer are arranged on the entire surface of the silicon wafer.

[0048] BCL can be used for high temperature diffusion 3 or POCL 3 The gas is diffused for processing. The high temperature diffusion process is a conventional technology for preparing battery cells and will not be described in detail here.

[0049] In an optional manner, in the gate line region, the thickness of the second doped polysilicon layer is greater than the thickness of the first doped polysilicon layer.

[0050] Preferably, in the gate line area, 0mm<the thickness of the first doped polysilicon layer ≤80; that is, the thickness of the first doped polysilicon layer is greater than 0mm and less than or equal to 80nm; for example, it can be 1nm, 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm, 10nm, 11nm, 12nm, 13nm, 14nm, 15nm, 16nm, 17nm, 18nm, 19nm, 20nm, 22nm, 24nm, 25nm, 26nm, 28nm, 29nm, 30nm, 32nm, 35nm, 40nm, 45nm, 50nm, 53nm, 55nm, 57nm, 60nm, 62nm, 64nm, 65nm, 66nm, 68nm, 69nm, 70nm, 72nm, 75nm, 78nm or 80nm. 80mm<the thickness of the second doped polysilicon layer ≤150nm; that is, the thickness of the second doped polysilicon layer is greater than 80 and less than or equal to 150nm; for example, it can be 81nm, 85nm, 90nm, 95nm, 100nm, 105nm, 110nm, 115nm, 120nm, 125nm, 130nm, 135nm, 140nm, 145nm or 150nm.

[0051] If the second polysilicon layer is too thick, it will cause serious parasitic absorption. If the second polysilicon layer is too thin, the metal gate line will burn through the passivation layer during the subsequent screen printing sintering and directly contact the silicon substrate, affecting the passivation effect.

[0052] Step 104: Subsequently, placing the silicon wafer in a nitric acid solution so that a first oxide layer is formed on the surface of the silicon wafer;

[0053] In this step, a nitric acid solution is used to form a first oxide layer on a silicon wafer on which a tunneling oxide layer, a first doped polysilicon layer and a second doped polysilicon layer have been formed, thereby obtaining a silicon wafer comprising a tunneling oxide layer, a first doped polysilicon layer, a second doped polysilicon layer and a first oxide layer, wherein the tunneling oxide layer, the first doped polysilicon layer, the second doped polysilicon layer and the first oxide layer are all arranged on the entire surface of the silicon wafer.

[0054] Specifically, the silicon wafer is placed in a nitric acid solution to allow the silicon wafer to form a first oxide layer in the nitric acid solution.

[0055] In an optional manner, the mass fraction of the nitric acid solution is 50%-90%, for example, it can be 50%, 55%, 60%, 65%, 70%, 75%, 80%, 85% or 90%; the temperature of the nitric acid solution is 50-100°C; for example, it can be 50°C, 55°C, 60°C, 65°C, 70°C, 75°C, 80°C, 85°C, 90°C, 95°C or 100°C.

[0056] Preferably, the silicon wafer is placed in the nitric acid solution for 100-2000 seconds; for example, it can be 100 seconds, 150 seconds, 200 seconds, 250 seconds, 300 seconds, 400 seconds, 500 seconds, 600 seconds, 700 seconds, 800 seconds, 900 seconds, 1000 seconds, 1100 seconds, 1200 seconds, 1300 seconds, 1400 seconds, 1500 seconds, 1600 seconds, 1700 seconds, 1800 seconds, 1900 seconds or 2000 seconds.

[0057] Step 105: placing the silicon wafer in an ozone atmosphere, and scanning the gate line region with the first laser, so that a second oxide layer is formed on the gate line region;

[0058] In this step, the gate line region on the surface of the silicon wafer is scanned by using the first laser in an ozone atmosphere to form a second oxide layer in the gate line region. Figure 3 As shown, the tunneling oxide layer 2, the first doped polysilicon layer 3, the second doped polysilicon layer 4 and the first oxide layer 5 are all arranged on the entire surface of the silicon wafer 1; and the second oxide layer 6 is arranged in the gate line region.

[0059] It is worth noting that the gate line area refers to the area where the gate line (i.e., the electrode) is placed after the cell is prepared. Since the gate line position is fixed, in step 105, although the gate line is not printed, the gate line area is preset in advance, so the second oxide layer can be set according to the preset gate line area. The non-gate line area refers to the area of ​​the cell that is prepared as the non-gate line.

[0060] In an optional manner, the thickness of the second oxide layer is greater than that of the first oxide layer. The second oxide layer is only disposed in the gate line region, and the thickness of the second oxide layer affects the thickness of the first oxide layer and the second doped layer in the gate line region.

[0061] In a specific embodiment, the thickness of the first oxide layer is 1-5nm; for example, it can be 1nm, 2nm, 3nm, 4nm or 5nm; the thickness of the second oxide layer is 1-10nm; for example, it can be 1nm, 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm or 10nm. The second oxide layer is only arranged in the gate line area, and the thickness of the second oxide layer will affect the thickness of the first oxide layer and the second doping layer in the gate line area. The thicker and denser the oxide layer is, the more hydrophilic and denser it is; the second oxide layer only exists in the gate line area in order to increase the difference in oxide layer between the gate line area and the non-gate line area. The denser the oxide layer in the gate line area is, the better the effect of blocking subsequent wet etching is.

[0062] In an optional embodiment, the first laser is picosecond or nanosecond, the spot diameter is 50-100µm, for example, it can be 50µm, 55µm, 60µm, 65µm, 70µm, 75µm, 80µm, 85µm, 90µm, 95µm or 100µm; the wavelength is 193-1064nm, for example, it can be 193nm, 532nm, 785nm, 850nm, 980nm or 1064nm; repeated The frequency is 100-1000KHz, for example, it can be 100KHz, 200KHz, 300KHz, 400KHz, 500KHz, 600KHz, 700KHz, 800KHz, 900KHz, or 1000KHz; the output power is 1-10W, for example, it can be 1W, 2W, 3W, 4W, 5W, 6W, 7W, 8W, 9W or 10W; the laser energy density is 0.1-1J / cm 2 , for example, it can be 0.1 J / cm 2 , 0.2J / cm 2 , 0.3J / cm 2 , 0,4J / cm 2 , 0.5J / cm 2 , 0.6J / cm 2 , 0.7J / cm 2 , 0.8J / cm 2 , 0.9J / cm 2 or 1J / cm 2 The size of the spot affects the growth area of ​​the oxide layer. If the spot is too large, the area of ​​selective polysilicon removal will be reduced. If the spot is too small, the area of ​​selective polysilicon removal will be too large, and not enough polysilicon area will be left in the subsequent wet cleaning. The repetition frequency, output power and energy density affect the laser energy. Too much energy can easily damage the silicon wafer, and too little energy cannot form a sufficiently dense and thick oxide layer.

[0063] Preferably, in the ozone atmosphere, the ozone flow rate is 10000-40000 sccm; for example, it can be 10000 sccm, 15000 sccm, 20000 sccm, 25000 sccm, 30000 sccm, 35000 sccm or 40000 sccm.

[0064] Step 106: moving the silicon wafer out of the ozone atmosphere, and scanning the non-gate line area with a second laser;

[0065] In this step, the silicon wafer is removed from the ozone atmosphere, for example, nitrogen may be purged so that the environment in the furnace is no longer an ozone atmosphere; or the silicon wafer is placed in an air environment; and then a second laser is used to perform laser scanning on the non-gate line area on the surface of the silicon wafer. The second laser scans the non-gate line area so that the oxygen in the non-gate line area diffuses into the second doped polysilicon layer below, thereby distinguishing the oxide layer of the gate line area and the second doped polysilicon layer of the non-gate line area, so as to facilitate the subsequent selective removal of the first oxide layer and the doped polysilicon layer.

[0066] Among them, the spot diameter of the second laser is larger than that of the first laser; because the second laser is mainly used for scanning the non-gridline area, the non-gridline area is larger, so the spot diameter of the second laser can be increased, so that the first oxide layer and doped polysilicon can be removed efficiently and quickly. However, the spot and pulse energy will damage the silicon wafer. If the spot is larger, the energy density is smaller, and the silicon wafer surface cannot be effectively treated. If the spot is too small, the energy is more concentrated, which will cause damage to the silicon wafer surface.

[0067] In an optional manner, the second laser is picosecond or nanosecond, the spot diameter is 80-120µm, for example, 80µm, 85µm, 90µm, 95µm or 100µm; the wavelength is 193-1064nm, for example, 193nm, 532nm, 785nm, 850nm, 980nm or 1064nm; the repetition frequency is 100-1000KHz, for example, 100KHz, 200KHz, 3 00KHz, 400KHz, 500KHz, 600KHz, 700KHz, 800KHz, 900KHz, or 1000KHz; the output power is 1-20W, for example, it can be 1W, 2W, 3W, 4W, 5W, 6W, 7W, 8W, 9W, 10W, 11W, 12W, 13W, 14W, 15W, 16W, 17W, 18W, 19W or 20W; the laser energy density is 0.5-4J / cm 2 , for example, it can be 0.5 J / cm 2 , 0.6J / cm 2 , 0.7J / cm 2 , 0.8J / cm2 , 0.9J / cm 2 , 1J / cm 2 , 1.5J / cm 2 , 1.8J / cm 2 , 2J / cm 2 , 2.5J / cm 2 , 2.7J / cm 2 , 3J / cm 2 , 3.3J / cm 2 、3.5J / cm 2 、3.7J / cm 2 .

[0068] Step 107: using wet alkali treatment to remove the second doped polysilicon layer and the first oxide layer in the non-gate line region of the silicon wafer; and using acid to remove the first oxide layer and the second oxide layer in the gate line region.

[0069] In this step, first, the second doped polysilicon layer and the first oxide layer in the non-gate line area of ​​the silicon wafer are removed by wet alkali treatment to obtain a selectively doped polysilicon layer, and the second polysilicon layer and the first oxide layer and the second oxide layer are only arranged in the gate line area.

[0070] like Figure 4 As shown, after the second doped polysilicon layer and the first oxide layer in the non-gate line area of ​​the silicon wafer are removed by wet alkali treatment, the structure of the battery at this time includes: a silicon wafer 1, a passivation layer, and a passivation layer is arranged on the silicon wafer 1, wherein the passivation layer is composed of a tunneling oxide layer 2, a first doped polysilicon layer 3, a second doped polysilicon layer 4, a first oxide layer 5 and a second oxide layer 6 arranged on the surface of the silicon wafer; wherein the tunneling oxide layer 2 and the first doped polysilicon layer 3 are arranged on the entire surface of the silicon wafer, and the second doped polysilicon layer 4, the first oxide layer 5 and the second oxide layer 6 are selectively arranged in the area in contact with the gate line.

[0071] In an optional embodiment, the solution of the wet alkali treatment is KOH, NaOH, NH 4 At least one of OH; for example, KOH, NaOH or NH 4 OH; or KOH, NaOH or NH 4A mixed solution of two or three kinds of OH. The mass fraction of the solution is 1%-20%; for example, it can be 1%, 2%, 3%, 4%, 5%, 6%, 7%, 8%, 9%, 10%, 11%, 12%, 13%, 14%, 15%, 16%, 17%, 18%, 19% or 20%; an additive is provided in the solution, and the additive is at least one of a detergent, an oxidant, a diffuser, a surfactant, a buffer, a defoamer or a promoter, for example, the detergent can be potassium sorbate; the oxidant can be polyethylene glycol; the diffuser can be sodium acetate; the surfactant can be diquaternary ammonium carboxymethyl sodium salt; the buffer can be ethylenediaminetetramethylenephosphonic acid; the defoamer can be silicone polyether; the promoter can be polyether modified silicone oil.

[0072] The mass fraction of the additive is 1%-3%; for example, it can be 1%, 2% or 3%;

[0073] The temperature of the solution is 40-80°C; for example, it can be 40°C, 50°C, 55°C, 60°C, 65°C, 70°C, 75°C or 80°C.

[0074] Preferably, the wet alkali treatment time is 200-400 seconds; for example, it can be 200 seconds, 250 seconds, 300 seconds, 350 seconds or 400 seconds.

[0075] Next, acid is used to remove the first oxide layer and the second oxide layer in the gate line region.

[0076] The acid may be at least one of hydrofluoric acid and hydrochloric acid. For example, a mixture of hydrofluoric acid and hydrochloric acid may be used.

[0077] The second aspect of the present application provides a photovoltaic cell having a selective polycrystalline silicon layer, which is prepared by the preparation method of the first aspect of the present application.

[0078] In an alternative approach, such as Figure 2 As shown, the photovoltaic cell includes: a silicon wafer 1 and a passivation layer, wherein the passivation layer is composed of a tunneling oxide layer 2, a first doped polysilicon layer 3 and a second doped polysilicon layer 4 arranged on the surface of the silicon wafer; the tunneling oxide layer 2 and the first doped polysilicon layer 3 are arranged on the entire surface of the silicon wafer, and the second doped polysilicon layer 4 is selectively arranged in the gate line area.

[0079] Among them, the silicon wafer can be an N-type single crystal silicon wafer or a P-type single crystal silicon wafer; the first doped polysilicon layer or the second doped polysilicon layer can be an N-type or a P-type. This application does not limit this. After the silicon wafer is prepared into a battery cell, it is generally divided into a relative front and back side, and the passivation layer can be set on the front side of the silicon wafer or on the back side of the silicon wafer. This application does not limit this.

[0080] Therefore, the present application selectively sets a second doped polysilicon layer, thereby greatly reducing the optical absorption caused by the excessive thickness of the doped polysilicon layer in the non-gate line area, significantly improving the passivation effect, and improving the electrical performance of the photovoltaic cell.

[0081] In an optional manner, in the gate line region, the thickness of the second doped polysilicon layer is greater than the thickness of the first doped polysilicon layer.

[0082] Preferably, in the gate line area, 0mm<the thickness of the first doped polysilicon layer ≤80; that is, the thickness of the first doped polysilicon layer is greater than 0mm and less than or equal to 80nm; for example, it can be 1nm, 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm, 10nm, 11nm, 12nm, 13nm, 14nm, 15nm, 16nm, 17nm, 18nm, 19nm, 20nm, 22nm, 24nm, 25nm, 26nm, 28nm, 29nm, 30nm, 32nm, 35nm, 40nm, 45nm, 50nm, 53nm, 55nm, 57nm, 60nm, 62nm, 64nm, 65nm, 66nm, 68nm, 69nm, 70nm, 72nm, 75nm, 78nm or 80nm. 80mm<thickness of the second doped polysilicon layer≤150nm; that is, the thickness of the second doped polysilicon layer is greater than 80 and less than or equal to 150nm; for example, it can be 81nm, 85nm, 90nm, 95nm, 100nm, 105nm, 110nm, 115nm, 120nm, 125nm, 130nm, 135nm, 140nm, 145nm or 150nm. If the second doped polysilicon layer is too thick, it will cause serious parasitic absorption. If the second doped polysilicon layer is too thin, it will cause the metal gate line to burn through the passivation layer during the subsequent screen printing sintering, and directly contact with the silicon substrate, affecting the passivation effect.

[0083] The third aspect of the present application provides a photovoltaic assembly, comprising any photovoltaic cell described in the second aspect of the present application.

[0084] The following describes in detail the method for preparing the photovoltaic cell disclosed in the first aspect of the present application and the photovoltaic cell disclosed in the second aspect of the present application with several specific embodiments. It is worth noting that the following description is only for illustrative purposes and is not a specific limitation of the invention.

[0085] Example 1

[0086] Step 101: Select an N-type single crystal silicon wafer with a resistivity of 0.5-2Ω·cm, a size of 182×182mm, and a thickness of 130µm, and perform an alkali texturing treatment on the silicon wafer.

[0087] Step 102: Depositing a tunnel oxide layer, a first amorphous silicon layer, and a second amorphous silicon layer on the surface of the silicon wafer in sequence by LPCVD; wherein the tunnel oxide layer is deposited first at a deposition temperature of 590°C, an oxygen flow rate of 40,000 sccm, and a time of 900 seconds, and then depositing the first amorphous silicon layer and the second amorphous silicon layer at a deposition temperature of 610°C and SiH 4 The flow rate is 1200 sccm, the time is 1960 seconds, and the thicknesses of the three film layers are 1.5 nm, 60 nm and 100 nm respectively.

[0088] Step 103: Then, the silicon wafer on which the tunnel oxide layer, the first amorphous silicon layer and the second amorphous silicon layer have been prepared is subjected to high temperature diffusion, and POCL is selected. 3 As the doping source, the doping source flow rate in the source step is 1350 sccm, the pressure is 150 bar, the temperature is 810°C, and the time is 1200 seconds. The pressure in the annealing step is 300 bar, the temperature is 890°C, and the process time is 900 seconds.

[0089] First test: using a four-probe square resistance tester to test the square resistance of the silicon wafer after step 103, using an ECV (diffusion doping concentration tester) to test the doping concentration on the surface of the silicon wafer after step 103; using a full-spectrum gyrograph to test the thickness of the entire polysilicon layer (including the first doped polysilicon layer and the second doped polysilicon layer) of the silicon wafer after step 103;

[0090] Step 104: placing the tested silicon wafer in a nitric acid solution, wherein the mass fraction of the solution is 65% nitric acid, the temperature is 85° C., the process time is 1200 s, and a first oxide layer is formed on the surface with a thickness of 1 nm;

[0091] Step 105: Place the silicon wafer with the first oxide layer in ozone, with an ozone flow rate of 40,000 sccm, select nanosecond laser, set the pulse width to 10ns, the spot diameter to 50µm, the wavelength to 355nm, the repetition frequency to 500kHz, the output power to 7W, and the laser energy density to 0.5J / cm 2 , scanning the metal gate line area of ​​the silicon wafer to grow a second oxide layer on the surface with a thickness of 5nm;

[0092] Step 106: Then stop the ozone flow, use nitrogen to purge the silicon wafer surface, adjust the laser energy, the spot diameter is 90μm, the wavelength is 355nm, the repetition frequency is 150kHz, the output power is 10W, and the laser energy density is 2.5J / cm 2 , laser scanning is performed on the non-metallic gate line area on the back side to destroy the first oxide layer on the surface, so that the surface oxygen diffuses into the underlying doped polysilicon layer;

[0093] Step 107: Then, the silicon wafer is placed in a tank machine, wherein the tank includes a 3.5% by mass NaOH solution and 1.5% by mass additives; the additives include: 3wt% polyether-modified silicone oil, 5wt% diquaternary ammonium carboxymethyl sodium salt new amphoteric gemini surfactant, 2wt% PEG-400, 1wt% sodium acetate, 8wt% ethylenediaminetetramethylenephosphonic acid, 1wt% potassium sorbate, the temperature is 50° C., and the process time is 70 s;

[0094] The silicon wafer is passed through an acid tank containing a mixed solution of 37% HF solution by mass, 49% HCl solution by mass, and water at a temperature of 25°C and a process time of 280s.

[0095] The second test: using a four-probe square resistance tester to test the square resistance of the non-gate line area of ​​the silicon wafer after step 107, using ECV to test the doping concentration on the surface of the non-gate line area of ​​the silicon wafer after step 107; using a full-spectrum gyrograph to test the thickness of the entire polysilicon layer (including the first doped polysilicon layer and the second doped polysilicon layer) in the non-gate line area of ​​the silicon wafer after step 107.

[0096] Example 2

[0097] Step 101: Select an N-type single crystal silicon wafer with a resistivity of 0.5-2Ω·cm, a size of 182×182mm, and a thickness of 130µm, and perform an alkali texturing treatment on the silicon wafer.

[0098] Step 102: Depositing a tunnel oxide layer, a first amorphous silicon layer, and a second amorphous silicon layer on the surface of the silicon wafer in sequence by LPCVD; wherein the tunnel oxide layer is deposited first at a deposition temperature of 600°C, an oxygen flow rate of 40,000 sccm, and a time of 900 seconds, and then depositing the first amorphous silicon layer and the second amorphous silicon layer at a deposition temperature of 610°C and SiH 4 The flow rate is 1200 sccm, the time is 2560 seconds, and the thicknesses of the three film layers are 1.5 nm, 80 nm and 120 nm respectively.

[0099] Step 103: Then, the silicon wafer on which the tunnel oxide layer, the first amorphous silicon layer and the second amorphous silicon layer have been prepared is subjected to high temperature diffusion, and BCL is selected. 3 As the doping source, the doping source flow rate in the source step is 200 sccm, the pressure is 160 bar, the temperature is 850°C, and the time is 470 seconds. The pressure in the annealing step is 300 bar, the temperature is 900°C, and the process time is 1500 seconds.

[0100] The first test: using a four-probe square resistance tester to test the square resistance of the silicon wafer after step 103, using ECV to test the doping concentration on the surface of the silicon wafer after step 103; using a full-spectrum gyrograph to test the thickness of the entire polysilicon layer (including the first doped polysilicon layer and the second doped polysilicon layer) of the silicon wafer after step 103.

[0101] Step 104: placing the tested silicon wafer in a nitric acid solution, wherein the mass fraction of the solution is 65% nitric acid, the temperature is 85° C., the process time is 1200 s, and a first oxide layer is formed on the surface with a thickness of 1 nm;

[0102] Step 105: Place the silicon wafer with the first oxide layer in ozone, with an ozone flow rate of 40,000 sccm, select nanosecond laser, set the pulse width to 10ns, the spot diameter to 50µm, the wavelength to 355nm, the repetition frequency to 500kHz, the output power to 10W, and the laser energy density to 0.6J / cm 2 , scanning the metal gate line area of ​​the silicon wafer to grow a second oxide layer on the surface with a thickness of 7nm;

[0103] Step 106: Then stop the ozone flow, use nitrogen to purge the silicon wafer surface, adjust the laser energy, the spot diameter is 90µm, the wavelength is 355nm, the repetition frequency is 150kHz, the output power is 15W, and the laser energy density is 3J / cm 2 , laser scanning is performed on the non-metallic gate line area on the back side to destroy the first oxide layer on the surface, so that the surface oxygen diffuses into the underlying doped polysilicon layer;

[0104] Step 107: Then, the silicon wafer is placed in a tank machine, wherein the tank includes a 4.5% by mass NaOH aqueous solution and 1.5% additives; the additives include: 3wt% polyether modified silicone oil, 5wt% diquaternary ammonium carboxymethyl sodium salt new amphoteric gemini surfactant, 2wt% PEG-400, 1wt% sodium acetate, 8wt% ethylenediaminetetramethylenephosphonic acid, 1wt% potassium sorbate, the temperature is 50°C, and the process time is 90s.

[0105] The silicon wafer is passed through an acid tank containing a mixed solution of 37% HF solution by mass, 49% HCl solution by mass, and water at a temperature of 25°C and a process time of 280s.

[0106] The second test: using a four-probe square resistance tester to test the square resistance of the non-gate line area of ​​the silicon wafer after step 107, using ECV to test the doping concentration on the surface of the non-gate line area of ​​the silicon wafer after step 107; using a full-spectrum gyrograph to test the thickness of the entire polysilicon layer (including the first doped polysilicon layer and the second doped polysilicon layer) in the non-gate line area of ​​the silicon wafer after step 107.

[0107] Example 3

[0108] The difference between Example 3 and Example 1 is that:

[0109] Step 104: Place the tested silicon wafer in a nitric acid solution with a mass fraction of 30% nitric acid, a temperature of 85° C., and a process time of 1200 seconds to form a first oxide layer on the surface with a thickness of 0.5 nm.

[0110] Example 4

[0111] The difference between Example 4 and Example 1 is that,

[0112] Step 104: placing the tested silicon wafer in a nitric acid solution, wherein the mass fraction of the solution is 100% nitric acid, the temperature is 85° C., the process time is 1200 seconds, and a first oxide layer is formed on the surface with a thickness of 1 nm;

[0113] Example 5

[0114] The difference between Example 5 and Example 2 is that:

[0115] In step 105, in the ozone atmosphere, the ozone flow rate is 8000 sccm.

[0116] Comparative Example 1

[0117] The difference between Comparative Example 1 and Example 1 is that

[0118] Step 105 is not performed in an ozone environment but in an air environment.

[0119] Comparative Example 2

[0120] The difference between Comparative Example 2 and Example 2 is that,

[0121] Step 105 is not performed in an ozone environment but in an air environment.

[0122] Table 1 below shows the relevant parameters in the preparation process of Examples 1-5 and Comparative Examples 1-2. It can be seen from the table:

[0123] (1) Using the preparation method of the present application, Examples 1-5 all achieve a selective polysilicon layer, so that the polysilicon layer in the non-gate line area is removed.

[0124] (2) By adopting the preparation method of the present application, the square resistance of Examples 1-2 is not much different before and after the two tests. For example, before Example 1, the thickness of the first amorphous silicon layer is 60nm, and the thickness of the second amorphous silicon layer is 100nm. Then the thickness of the first doped polycrystalline silicon layer prepared subsequently is 60nm, and the thickness of the second doped polycrystalline silicon layer is also 100nm. By adopting the preparation method of the present application, after selective removal, the thickness of the entire polycrystalline silicon layer is 61.3nm, and the thickness of the second doped polycrystalline silicon layer is retained by 1.3nm; that is, the second doped polycrystalline silicon layer in the non-gate line area is completely removed; for example, before Example 2, the thickness of the first amorphous silicon layer is 80nm, and the thickness of the second amorphous silicon layer is 120nm. Then the thickness of the first doped polycrystalline silicon layer prepared subsequently is 80nm, and the thickness of the second doped polycrystalline silicon layer is also 120nm. By adopting the preparation method of the present application, after selective removal, the thickness of the entire polycrystalline silicon layer is 83nm, and the thickness of the second doped polycrystalline silicon layer is retained by 3nm; that is, the second doped polycrystalline silicon layer in the non-gate line area is completely removed; the effect is relatively good.

[0125] (3) Compared with Example 1, in Example 3, due to the low proportion of nitric acid solution, the proportion of the oxide layer removed is too high. After selective removal, the thickness of the entire polysilicon layer is 44.3nm, the second doped polysilicon layer in the non-gate line area is completely removed, and the first doped polysilicon layer is also partially removed, resulting in excessive removal of the non-gate line area. The effect is relatively poor compared with Example 1.

[0126] (4) Compared with Example 1, in Example 4, due to the excessively large proportion of nitric acid solution, the oxidation reaction is too fast, resulting in uneven growth of the oxide layer and less removal. After selective removal, the thickness of the entire polysilicon layer is 81.2 nm. The second doped polysilicon layer in the non-gate line area is not completely removed, resulting in a relatively poor film thickness effect of the entire polysilicon layer compared with Example 1.

[0127] (5) Compared with Example 2, since the ozone flow rate in Example 5 is too low, the thickness of the prepared second oxide layer is relatively small, and the second oxide layer cannot effectively protect the removal of the second doped polysilicon layer. After selective removal, the thickness of the entire polysilicon layer is 67.5nm. Not only is the second doped polysilicon layer in the non-gate line area completely removed, but the first doped polysilicon layer is also partially removed, making the effect relatively poor compared with Example 2.

[0128] Table 1 Related parameters during the preparation of Examples 1-5 and Comparative Examples 1-2

[0129]

[0130] Example 6

[0131] The difference between Example 6 and Example 1 is that

[0132] Step 105: Place the silicon wafer with the first oxide layer in ozone with an ozone flow rate of 40,000 sccm. Select nanosecond laser with a pulse width of 10 ns, a spot diameter of 30 µm, a wavelength of 355 nm, a repetition frequency of 500 kHz, an output power of 7 W, and a laser energy density of 0.6 J / cm 2 , the metal gate line area of ​​the silicon wafer is scanned to grow a second oxide layer on the surface with a thickness of 8nm.

[0133] Step 106: Then stop the ozone flow, use nitrogen to purge the silicon wafer surface, adjust the laser energy, the spot diameter is 50µm, the wavelength is 355nm, the repetition frequency is 150kHz, the output power is 10W, and the laser energy density is 3.5J / cm 2 , laser scanning is performed on the non-metallic gate line area on the back side to destroy the first oxide layer on the surface, so that the surface oxygen diffuses into the underlying doped polysilicon layer;

[0134] Example 7

[0135] The difference between Example 7 and Example 1 is that

[0136] Step 105: Set the pulse width to 10ns, the spot diameter to 200µm, the wavelength to 355nm, the repetition rate to 2000kHz, the output power to 20W, and the laser energy density to 3J / cm 2 .

[0137] Example 8

[0138] The difference between Example 8 and Example 1 is that,

[0139] Step 106: Then stop the ozone flow, use nitrogen to purge the silicon wafer surface, adjust the laser energy, the spot diameter is 30µm, the wavelength is 355nm, the repetition frequency is 150kHz, the output power is 10W, and the laser energy density is 5J / cm 2 .

[0140] Comparative Example 3

[0141] The difference between Comparative Example 3 and Example 1 is that

[0142] The preparation of steps 104-107 was not performed.

[0143] The solar cells of Example 1 and Examples 6-8 were prepared. The prepared solar cells include a front side and a back side opposite to each other. The front side is provided with a P+ emitter layer, an aluminum oxide passivation layer, a front side anti-reflection film layer and a front side gate line, and the back side is provided with a tunneling oxide layer, a first doped polysilicon layer, a second doped polysilicon layer, a back side anti-reflection film layer and a back side gate line. The tunneling oxide layer and the first doped polysilicon layer are provided in the entire back side region of the silicon wafer; and the second doped polysilicon layer is provided in the gate line region.

[0144] A cell was prepared for Comparative Example 3, and the prepared cell included a relative front and back side, the front side was provided with a P+ emitter layer, an aluminum oxide passivation layer, a front anti-reflection film layer and a front gate line, the back side was provided with a tunneling oxide layer, a first doped polysilicon layer, a second doped polysilicon layer, a back anti-reflection film layer and a back gate line, and the tunneling oxide layer, the first doped polysilicon layer and the second doped polysilicon layer were all provided in the entire back area of ​​the silicon wafer.

[0145] The electrical performance data of Example 1, Examples 6-8 and Comparative Example 3 were tested using a battery efficiency tester, as shown in Table 2 below. It can be seen from the table that:

[0146] (1) Compared with Comparative Example 3, the only difference in structure between the cell prepared in Example 1 and the cell prepared in Comparative Example 3 is that Example 1 adopts a selective polysilicon setting method, by removing the second polysilicon layer in the non-gate line area and retaining only the second polysilicon layer in the gate line area; the efficiency value Eta of the cell of Example 1 is significantly improved, by nearly 0.1%.

[0147] (2) Compared with Example 1, in the preparation of the second oxide layer in Example 6, the first laser spot diameter is too small and the energy is too concentrated, resulting in the second oxide layer becoming narrower and insufficient to protect the second doped polysilicon layer. When the second laser scans the non-gate line area, the spot diameter is too small, causing damage to the polysilicon layer in the gate line area, resulting in the second doped polysilicon layer in the gate line area becoming thinner, resulting in a decrease in the efficiency Eta of the battery.

[0148] (3) Compared with Example 1, in Example 7, in the preparation of the second oxide layer, the spot diameter of the first laser used was too large and the energy was weak, resulting in poor surface treatment effect of the silicon wafer, which led to a decrease in the efficiency Eta of the subsequent battery;

[0149] (4) Compared with Example 1, in Example 8, when the second laser scans the non-gate line area, the spot diameter is too small and the energy is too concentrated, causing damage to the polysilicon layer in the gate line area. The second doped polysilicon layer is too thin and is burned through, resulting in a significant reduction in the efficiency Eta of the subsequent battery.

[0150] Table 2 Test data of electrical properties of Example 1, Examples 6-8 and Comparative Example 3

[0151]

[0152] Although the present application is described herein in conjunction with various embodiments, in the process of implementing the claimed application, those skilled in the art may understand and implement other changes to the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude multiple situations. A single processor or other unit may implement several functions listed in a claim. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0153] Although the present application has been described in conjunction with specific features and embodiments thereof, it is obvious that various modifications and combinations may be made thereto without departing from the spirit and scope of the present application. Accordingly, this specification and the drawings are merely exemplary illustrations of the present application as defined by the appended claims, and are deemed to have covered any and all modifications, variations, combinations or equivalents within the scope of the present application. Obviously, those skilled in the art may make various modifications and variations to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A method for preparing a photovoltaic cell having a selective polycrystalline silicon layer, characterized in that: The method comprises the following steps: Step 101: Select a silicon wafer and perform a texturing process on the silicon wafer; Step 102: depositing a tunneling oxide layer, a first amorphous silicon layer, and a second amorphous silicon layer in sequence on the surface of the silicon wafer; Step 103: performing high temperature diffusion so that the first amorphous silicon layer and the second amorphous silicon layer form a first doped polysilicon layer and a second doped polysilicon layer; Step 104: Subsequently, placing the silicon wafer in a nitric acid solution, so that a first oxide layer is formed on the surface of the silicon wafer; the mass fraction of the nitric acid solution is 50%-90%, and the temperature is 50-100° C.; the silicon wafer is placed in the nitric acid solution for 100-2000 seconds; Step 105: placing the silicon wafer in an ozone atmosphere, and scanning the gate line region with a first laser, so that a second oxide layer is formed on the gate line region; the thickness of the second oxide layer is greater than the thickness of the first oxide layer; The first laser is picosecond or nanosecond, with a spot diameter of 50-100µm, a wavelength of 193-1064nm, a repetition frequency of 100-1000KHz, an output power of 1-10W, and a laser energy density of 0.1J / cm 2 -1J / cm 2 ; Step 106: Move the silicon wafer out of the ozone atmosphere, and use a second laser to scan the non-gate line area; so that the oxygen in the non-gate line area diffuses into the lower second doped polysilicon layer, and the oxide layer and the second doped polysilicon layer in the gate line area and the non-gate line area are distinguished; wherein the spot diameter of the second laser is larger than the spot diameter of the first laser; the second laser is picosecond or nanosecond, the spot diameter is 80-120µm, the wavelength is 193-1064nm, the repetition frequency is 100-1000KHz, the output power is 1-20W, and the laser energy density is 0.5J / cm 2 -4J / cm 2 ; Step 107: removing the second doped polysilicon layer and the first oxide layer in the non-gate line region of the silicon wafer by wet alkali treatment; and removing the first oxide layer and the second oxide layer in the gate line region by acid.

2. The method for preparing a photovoltaic cell according to claim 1, characterized in that: In step 105, in the ozone atmosphere, the ozone flow rate is 10000-40000 sccm.

3. The method for preparing a photovoltaic cell according to claim 1, characterized in that: In step 107, the solution of the wet alkali treatment is at least one of KOH, NaOH, and NH4OH; and / or, in step 107, the acid is at least one of hydrochloric acid or hydrofluoric acid.

4. The method for preparing a photovoltaic cell according to claim 3, characterized in that: In step 107, the mass fraction of the solution is 1%-20%; and / or, an additive is provided in the solution, and the additive is at least one of a detergent, an oxidant, a diffusant, a surfactant, a buffer, a defoaming agent or a promoter, and the mass fraction of the additive is 1%-3%.

5. A photovoltaic cell having a selective polysilicon layer, characterized in that: The method is described in any one of claims 1 to 4.

6. The photovoltaic cell according to claim 5, characterized in that: The photovoltaic cell includes a silicon wafer and a passivation layer, wherein the passivation layer is arranged on the surface of the silicon wafer, and the passivation layer is sequentially provided with a tunneling oxide layer, a first doped polysilicon layer and a second doped polysilicon layer on the surface of the silicon wafer, wherein the tunneling oxide layer and the first doped polysilicon layer are arranged in an area on the entire surface of the silicon wafer; and the second doped polysilicon layer is arranged in a gate line area.

7. The photovoltaic cell according to claim 6, characterized in that: In the gate line region, the thickness of the second doped polysilicon layer is greater than the thickness of the first doped polysilicon layer.

8. A photovoltaic module, characterized in that: The photovoltaic cell comprises any one of claims 5-7.

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