Switching network chip, shared cache management method, electronic device and medium

Abstract

The application discloses a switching network chip, a shared cache management method, electronic equipment and a medium, and relates to the technical field of chips.The switching network chip comprises a plurality of input ports and a plurality of output ports, a shared cache and a shared cache management module connected with the plurality of input ports and the plurality of output ports, the shared cache management module is configured to write cells received through the plurality of input ports to the shared cache, and read stored cells from the shared cache to be sent through the plurality of output ports, the shared cache management module is configured to detect a cache occupation depth of each input port and a total cache usage depth of the shared cache, determine a load balancing signal based on a preset balancing threshold and the cache occupation depth, and perform load balancing adjustment according to the load balancing signal; determine a congestion adjustment signal based on a preset congestion threshold, the cache occupation depth and the total cache usage depth, and perform congestion adjustment according to the congestion adjustment signal. The application can improve the cache utilization rate of the switching network chip.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a switching network chip, a shared cache management method, an electronic device, and a medium. Background Technology

[0002] A storage-and-forward switching chip first receives and stores all cells to be forwarded at the input port. Then, according to the forwarding requirements, it reads cells from the buffer and sends them through different subsystem switching units (i.e., subsystems), finally sending them out from the corresponding output port. The buffer capacity of each input port and each subsystem in the switching chip is limited. When congestion occurs due to sudden traffic surges, it can backpressure and block incoming traffic, or cause random packet loss at the input port, affecting normal data exchange. This deficiency is addressed by increasing the buffer size, but this leads to low buffer utilization. Summary of the Invention

[0003] The main objective of this invention is to provide a switching network chip, a shared cache management method, an electronic device, and a medium, aiming to solve the technical problem of how to improve the cache utilization rate of a switching network chip.

[0004] To achieve the above objectives, this application provides a switching network chip, comprising:

[0005] The system includes multiple input ports and multiple output ports, a shared buffer and a shared buffer management module connected to the input ports and the output ports, wherein the shared buffer management module is configured to write cells received through the input ports into the shared buffer and read stored cells from the shared buffer for transmission through the output ports.

[0006] The shared cache management module is configured to detect the cache occupancy depth of each input port and the total cache usage depth of the shared cache, determine a load balancing signal based on a preset balancing threshold and the cache occupancy depth, and perform load balancing adjustments according to the load balancing signal; and determine a congestion adjustment signal based on a preset congestion threshold, the cache occupancy depth, and the total cache usage depth, and perform congestion adjustments according to the congestion adjustment signal.

[0007] In addition, to achieve the above objectives, this application also provides a shared cache management method, including:

[0008] Detect the buffer occupancy depth of each input port of the switching chip and the total buffer usage depth of the shared buffer;

[0009] The load balancing signal is determined based on the preset balancing threshold and the cache occupancy depth, and the load balancing is adjusted according to the load balancing signal.

[0010] A congestion adjustment signal is determined based on a preset congestion threshold, the cache occupancy depth, and the total cache usage depth, and congestion adjustment is performed according to the congestion adjustment signal.

[0011] In addition, to achieve the above objectives, this application also provides an electronic device, which includes: a memory, a processor, and a shared cache management program stored on the memory and executable on the processor. When the shared cache management program is executed by the processor, it implements the steps of the shared cache management method described above.

[0012] In addition, to achieve the above objectives, this application also provides a medium, including a computer-readable storage medium, on which a shared cache management program is stored, which, when executed by a processor, implements the steps of the shared cache management method as described above.

[0013] This application embodiment sets up multiple input ports and multiple output ports in the switching network chip, along with a shared buffer and a shared buffer management module connected to these input and output ports. The shared buffer management module is configured to write cells received through the multiple input ports into the shared buffer and read stored cells from the shared buffer to send them through the multiple output ports, thereby enabling multiple ports to share a single shared buffer for cell storage. Furthermore, the shared buffer management module is configured to detect the buffer occupancy depth of each input port and the total buffer usage depth of the shared buffer, and determine a load balancing signal based on a preset balancing threshold and buffer occupancy depth. Load balancing adjustments are then made based on the load balancing signal, allowing for the determination of load balancing for each input port based on buffer occupancy depth. This allows for observation of any imbalances in port depths and balancing of traffic at the input ports according to the load balancing signal. In other words, load balancing is used as a pre-emptive measure for congestion management, balancing traffic across ports in advance to simplify congestion management. It will determine the congestion adjustment signal based on the preset congestion threshold, cache occupancy depth and total cache usage depth to perform congestion adjustment, thereby avoiding the phenomenon of back pressure at each level, reducing congestion recovery time, and improving the cache utilization rate of the switching network chip. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the framework of the first embodiment of the switching network chip in this application;

[0015] Figure 2 This is a schematic diagram of the framework of the second embodiment of the switching network chip in this application;

[0016] Figure 3 This is a schematic diagram of the shared cache management module in the switching network chip of this application embodiment;

[0017] Figure 4 This is a schematic diagram of the address reclamation module in the switching network chip of this application embodiment;

[0018] Figure 5 This is a schematic diagram of the overall framework of the switching network chip in an embodiment of this application;

[0019] Figure 6 This is a flowchart illustrating the third embodiment of the shared cache management method of this application;

[0020] Figure 7 This is a schematic diagram of the overall process of the shared cache management method in this application for one scenario;

[0021] Figure 8 This is a schematic diagram of the device structure of the hardware operating environment involved in the shared cache management method of this application.

[0022] Explanation of icon numbers:

[0023] 1000 Switching chip 2000 upstream switching network chip 3000 Back-end switching network chip 110 Input port 120 Output port 200 Shared cache 300 Shared cache management module 400 Address allocation module 500 Address recycling module 510 Port Selector Module 520 Read enable module

[0024] The objectives, features, and advantages of this invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0025] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0026] When a sudden surge in traffic causes congestion, the switching chip may backpressure and block incoming traffic or cause random packet loss at the input ports, affecting normal data exchange. To avoid this, methods such as increasing the buffer size and setting buffer thresholds can be used. However, while increasing the buffer size allows more packets to enter the buffer queue and absorb sudden traffic, it also increases the waiting time for packet forwarding and results in low buffer utilization and high costs under normal circumstances. Setting buffer thresholds, while allowing for early detection of congestion and reduction of incoming traffic, cannot accurately identify and report congestion on a single link or port. Therefore, in this embodiment, to accurately report load imbalance and congestion in the switching system and improve buffer utilization, all ports of the switching chip share a buffer, and the buffer occupancy depth is monitored periodically to observe the degree of imbalance in the depth of each port. The load balancing monitoring result is used as the first-level congestion warning, and the total buffer occupancy depth is used as the second-level congestion warning. Simultaneously, measures are taken on both the output and input sides to avoid congestion. Load balancing is used as a pre-emptive measure for congestion management to average the inbound traffic of each port in advance, simplifying congestion management. The total cache occupancy depth is used as a second-level congestion warning to avoid backpressure at each level, reduce path latency, reduce congestion recovery time, and improve cache utilization.

[0027] This application primarily applies to the input / output ports of switching network chips. By using a shared cache, it provides precise early warnings of load imbalances and congestion, allowing for timely intervention and reducing the probability of packet loss during sudden traffic surges, thus improving cache utilization. All cells received by all ports / links of the switching network or switching network chip are stored in the same cache. The shared cache usage is monitored, and the load balancing degree of each port is periodically calculated. Traffic distribution between upstream and downstream stages is adjusted to achieve load balancing. Simultaneously, the load balancing calculation result serves as the first-level congestion warning, and two congestion thresholds are set for the shared cache usage depth to intervene in congestion in advance and reduce the probability of congestion. Furthermore, this application can be used in scenarios such as switches, routers, and switching networks.

[0028] The embodiments of this application will be further described below with reference to the accompanying drawings.

[0029] Reference Figure 1 This application provides a switching network chip. In a first embodiment of the switching network chip 1000, the switching network chip 1000 includes a plurality of input ports 110 and a plurality of output ports 120, as well as a shared buffer 200 and a shared buffer management module 300 connected to the plurality of input ports 110 and the plurality of output ports 120. The shared buffer management module 300 is configured to write cells received through the plurality of input ports 110 into the shared buffer 200, and to read stored cells from the shared buffer 200 for transmission through the plurality of output ports 120.

[0030] The shared cache management module 300 is configured to detect the cache occupancy depth of each input port 110 and the total cache usage depth of the shared cache 200, determine a load balancing signal based on a preset balancing threshold and the cache occupancy depth, and perform load balancing adjustments according to the load balancing signal; and determine a congestion adjustment signal based on a preset congestion threshold, the cache occupancy depth and the total cache usage depth, and perform congestion adjustments according to the congestion adjustment signal.

[0031] In this embodiment of the application, the switching network chip 1000 can be connected to the previous-level switching network chip 2000 and the next-level switching network chip 3000 respectively. The switching network chip where the previous-level switching network chip 2000 is located and the switching network chip where the next-level switching network chip 3000 is located can have the same architecture as the switching network chip 1000, all of which include multiple input ports 110, multiple output ports 120, a shared buffer 200 and a shared buffer management module 300.

[0032] Optionally, refer to Figure 2The preceding-stage switching chip 2000 is connected to multiple input ports 110 of the switching chip 1000. Each input port 110 is connected to a shared buffer 200, allowing the preceding-stage switching chip 200 to send cells to the shared buffer 200 for storage via the input ports 110. The shared buffer 200 is also connected to multiple output ports 120. The following-stage switching chip 3000 is connected to the multiple output ports 120 of the switching chip 1000. Cells stored in the shared buffer 200 can be sent to the following-stage switching chip 300 via the output ports 120. Furthermore, a shared buffer management module 300 within the switching chip 1000 manages the switching chip 1000; that is, the shared buffer management module 300 is connected to the multiple input ports 110, the shared buffer 200, and the multiple output ports 120.

[0033] Optionally, multiple input ports 110 can be configured, and each input port 110 is connected to the shared buffer 200. Similarly, multiple output ports 120 can also be configured, and each output port 120 is connected to the shared buffer 200. Load balancing and congestion management are performed through the shared buffer 200. Cells received by each input port 110 are shared and buffered in the shared buffer 200. Input ports 110 and output ports 120 can be USB interfaces or other interfaces capable of transmitting traffic data; there are no restrictions on this.

[0034] Optionally, the preceding-stage switching chip 2000 sends cells to input port 110 of the switching chip 1000, where the switching chip 1000 is located. The switching chip 1000 constructs a cell identifier corresponding to the received cell. The cell identifier includes cell validity information and the address where the cell is stored in the shared buffer 200. Then, the cell body (i.e., the cell received at input port 110) is stored in the shared buffer 200. The address where the cell body is stored can be one or multiple. The cell identifier to be sent to the following-stage switching chip 3000 is obtained from output port 120, and the cell body stored in the shared buffer 200 is extracted based on the cell identifier. The cell body is then output to the following-stage switching chip 3000.

[0035] Optionally, the shared cache management module 300 manages the overall status of the switching chip 1000, including detecting the cache occupancy depth of each input port 110 and the total cache usage depth of the shared cache 200. This allows for the management of load balancing and congestion in the switching chip. By combining shared cache with congestion management, idle cache is provided promptly during sudden traffic surges, preventing packet loss. Optionally, the shared cache management module 300 can also detect the cache occupancy depth of the output port 120. The shared cache management module 300 determines the cache occupancy depth of each input port 110 and / or the total cache usage depth of the shared cache 200 to generate different feedback signals, and then performs different processing operations based on these signals. Optionally, a load balancing signal can be determined based on a preset balancing threshold and the cache occupancy depth of each input port 110, allowing for load balancing adjustments to the input ports 110. Optionally, the preset balancing threshold can be a user-defined load balancing value. For example, based on the load balancing signal, the traffic data (including transmitted packets) of input port 110 is adjusted, such as balancing the inbound traffic of input port 110. Furthermore, congestion detection is performed based on a preset congestion threshold, buffer occupancy depth, and total buffer usage depth, generating corresponding congestion adjustment signals, and congestion adjustment of input port 110 is performed according to these signals. The preset congestion threshold can be a user-defined threshold for congestion control. Optionally, the preset congestion threshold may include a first port congestion threshold B1, a second port congestion threshold B2, a first buffer congestion threshold A1, and a second buffer congestion threshold A2, wherein the first port congestion threshold B1 is less than the second port congestion threshold B2, the second port congestion threshold B2 is less than the first buffer congestion threshold A1, and the first buffer congestion threshold A1 is less than the second buffer congestion threshold A2. The feedback signals may include a CA signal (i.e., congestion warning signal), a LB signal (i.e., load balancing signal), a CN signal (i.e., congestion alarm signal), an inbound weight signal, and a log signal (congestion warning signal). Optionally, a congestion warning signal is sent to the address reclamation module 500 to change the read enable of the cell identifier RAM for the forwarding path terminal. A load balancing signal is sent to the address reclamation module of the upstream switching chip 2000 to change which output port of the upstream switching chip 2000 the cell body is output from. A congestion alarm signal is sent to the address reclamation module of the upstream switching chip 2000 to reduce bandwidth. An ingress weight signal is applied to the address allocation module 400 to prevent low-priority cells from being written to the shared buffer 200. A congestion warning signal is sent to the shared buffer 200 to release the low-priority cell address.

[0036] In this embodiment, by setting multiple input ports and multiple output ports in the switching network chip, as well as a shared cache and a shared cache management module connected to the multiple input ports and multiple output ports, and by configuring the shared cache management module to write cells received through the multiple input ports into the shared cache and read stored cells from the shared cache and send them through the multiple output ports, multiple ports can share a single shared cache for cell storage. Furthermore, the shared cache management module is configured to detect the cache occupancy depth of each input port and the total cache usage depth of the shared cache, and determine a load balancing signal based on a preset balancing threshold and cache occupancy depth. Load balancing adjustments are then made based on the load balancing signal to determine the load balancing status of each input port based on the cache occupancy depth, observe any imbalances in port depth, and adjust the traffic of the input ports accordingly. In other words, load balancing is used as a pre-emptive measure for congestion management, balancing the traffic of each port in advance to simplify congestion management. It will determine the congestion adjustment signal based on the preset congestion threshold, cache occupancy depth and total cache usage depth to perform congestion adjustment, thereby avoiding the phenomenon of back pressure at each level, reducing congestion recovery time, and improving the cache utilization rate of the switching network chip.

[0037] Furthermore, based on the first embodiment of the switching network chip described above, a second embodiment of the switching network chip is proposed, with reference to... Figure 2 Multiple input ports 110 are respectively connected to multiple output ports (not shown in the figure) of the previous stage switching network chip 2000.

[0038] The shared cache management module 300 is further configured to match each cache occupancy depth with the preset balancing threshold, and, if it is determined that there is a cache occupancy depth that does not match the preset balancing threshold, trigger the generation of a load balancing signal and send the load balancing signal to the previous-level switching chip, so that the shared cache management module (not shown in the figure) of the previous-level switching chip 2000 adjusts the weight of the output port of the previous-level switching chip 2000 according to the load balancing signal, generates a previous-level port sequence, and determines the previous-level cell transmission port according to the previous-level port sequence.

[0039] In this embodiment, the switching network chip 1000 also establishes a connection with the preceding switching network chip 2000 to perform data transmission, such as cell transmission, between the preceding switching network chip 2000 and the switching network chip 1000. Optionally, multiple output ports in the preceding switching network chip 2000 are respectively connected to multiple input ports in the switching network chip 1000. Optionally, the preceding switching network chip 2000 has the same architecture as the switching network chip 1000.

[0040] Optionally, the preceding switching network chip 2000 sends cells to multiple input ports 110 in the switching network chip 1000 through multiple output ports in the preceding switching network chip 2000. Then, the shared buffer management module 300 writes the cells received by the multiple input ports into the shared buffer 200 and reads the stored cells from the shared buffer 200 to send them through multiple output ports 120, such as to the subsequent switching network chip.

[0041] Optionally, when performing load balancing detection and adjustment on each input port of the switching network chip 1000, the preceding switching network chip 2000 can be used for auxiliary adjustment. Furthermore, when the shared cache management module 300 performs load balancing detection on each input port 110, it can periodically perform load balancing detection on each input port 110 of the switching network chip 110, such as according to a preset monitoring period. During load balancing detection, the cache occupancy depth of each input port 110 can be matched with a pre-set preset balancing threshold to determine the load balancing detection result based on the matching result.

[0042] If a buffer occupancy depth that does not match the preset balancing threshold is detected, a load balancing signal will be generated. Optionally, the load balancing signal is obtained by mapping the balancing description value and port number of each input port 110, and the load balancing signal is sent to the previous-level switching chip 2000 through the shared buffer management module. The shared buffer management module in the previous-level switching chip 2000 adjusts the traffic input to each port only when it receives the load balancing signal. Optionally, the shared buffer management module in the previous-level switching chip 2000 adjusts the weight of the output ports of the previous-level switching chip according to the load balancing signal, such as incrementing the weight of a certain output port of the previous-level switching chip by 1 to generate a port sequence, which is used as the previous-level port sequence. Then, the previous-level port sequence is polled to determine the previous-level cell transmission port, and the cells in the previous-level switching chip 2000 are sent to each input port 110 in the switching chip 1000 through the previous-level cell transmission port. Optionally, when the shared buffer management module in the upstream switching network chip 2000 receives both the load balancing signal and the congestion alarm signal simultaneously, it shall prioritize processing based on the congestion alarm signal.

[0043] Optionally, four levels of port load severity can be set in the load balancing signal based on the load balancing description value: severely overloaded, moderately overloaded, moderately idle, and severely idle. When the upstream switching chip 2000 adjusts port traffic based on the load balancing signal, it can make different adjustments according to different levels, such as a significant decrease, a slight decrease, a slight increase, and a significant increase in traffic.

[0044] In this embodiment, by connecting the previous switching network chip 2000 to the switching network chip 1000, and setting the shared cache management module 300 to match the occupancy depth of each cache with a preset load balancing threshold, and by calculating the load balancing value, and generating a load balancing signal when the load balancing value is greater than the preset load balancing threshold, and sending it to the previous switching network chip 2000, the traffic input to each port is adjusted, thereby ensuring the load balancing of each port.

[0045] Furthermore, the shared cache management module 300 is also configured to calculate the load balancing value corresponding to each cache occupancy depth according to a preset monitoring period, compare each load balancing value with the preset balancing threshold, and if it is determined that there is a load balancing value greater than the preset balancing threshold, determine that the cache occupancy depth corresponding to the load balancing value greater than the preset balancing threshold does not match the preset balancing threshold.

[0046] In this embodiment, the shared cache management module 300 can also periodically calculate the load balancing description value corresponding to the cache occupancy depth of each input port 110. For example, the load balancing value corresponding to the cache occupancy depth can be calculated based on a pre-set monitoring period. The load balancing description value can be calculated based on the deviation value, such as calculating the variance of the cache occupancy depth of the entire port (including all input ports 110) using the deviation value and using it as the load balancing description value. The deviation value can be calculated based on the cache occupancy depth of each input port 110. Furthermore, when the load balancing description value is greater than a preset load balancing threshold (which can be any load balancing threshold set by the user in advance), it indicates that the ingress traffic of each input port 110 differs significantly. At this point, it can be determined that the cache occupancy depth corresponding to the load balancing value greater than the preset load balancing threshold does not match the preset load balancing threshold, meaning that the ingress traffic of a certain input port 110 is too high, and load balancing adjustment is required.

[0047] In this embodiment, the shared cache management module 300 calculates the load balancing value corresponding to each cache occupancy depth, and triggers the generation of a load balancing signal when the load balancing value is greater than a preset balancing threshold. The load balancing signal is then sent to the previous-level switching network chip 2000, which adjusts the load balancing of the input ports, thereby ensuring the load balancing of the input ports 110 in the switching network chip 1000.

[0048] Furthermore, referring to Figure 2 and Figure 3 The shared cache management module 300 further includes an address reclamation module 500, which is connected to multiple output ports 110 and the shared cache 200.

[0049] The address reclamation module 500 is configured to, when a congestion warning signal is detected, adjust the weights corresponding to the cell identifiers of the output port 120 whose cache occupancy depth is greater than the first port congestion threshold according to the congestion warning signal, and read the cell bodies in the shared cache 200 according to the cell identifiers after the weight adjustment. In the case where the cache occupancy depth is greater than the preset first port congestion threshold, a congestion warning signal is triggered to be generated.

[0050] In this embodiment, the address recycling module 500 can obtain the cell body address based on the read cell identifier, then read the cell from the shared buffer 200 based on the cell body address, and output it through the output port 120. Optionally, a forwarding path (not shown in the figure) can also be set in the switching network chip 1000. The forwarding path terminal on the forwarding path stores the cell body identifier ram, and the cell body identifier ram stores the cell body addresses corresponding to multiple cell bodies. Optionally, the cell body address can be the address where the cell body is stored in the shared buffer 200.

[0051] Optionally, if the cache occupancy depth of a certain port exceeds a preset first port congestion threshold, a congestion warning signal is triggered in the shared cache management module 300. When the address reclamation module 500 detects the congestion warning signal, it increases the processing line speed, increases the output weight of the cell identifier in the output port 120, and prioritizes reading and sending the cell corresponding to the cell identifier with the adjusted weight until the cache occupancy depth is less than or equal to the first preset threshold.

[0052] In this embodiment, the address reclamation module 500 adjusts the weight of the cell identifier of the output port 120 when a congestion warning signal is detected, so as to prioritize reading the cell body corresponding to the cell identifier after the weight adjustment, thereby realizing congestion warning adjustment on the output port side and reducing the probability of congestion.

[0053] Furthermore, referring to Figure 4 Address recycling module 500, including read enable module 520.

[0054] The read enable module 520 is configured to adjust the weights corresponding to the cell identifiers of the output port 120 whose cache occupancy depth is greater than the first port congestion threshold according to the congestion warning signal, and to read out the cell identifiers after weight adjustment first, and to read out the cell bodies in the shared cache 200 according to the address information in the cell identifiers read out first.

[0055] Optionally, the congestion warning signal applies to the module generating the read enable of the cell identifier RAM (i.e., read enable module 520). Cell identifiers from different ports occupy different positions in the cell identifier RAM, and by default, each position has equal weight. Optionally, when the output port 120 corresponding to the first buffer occupancy depth is determined, the weight of the cell identifier in the cell identifier RAM position segment of the output port 120 is adjusted according to the congestion warning signal. The cell identifier with the adjusted weight is read first, and the cell storage address (i.e., cell body address) recorded in the cell identifier is sent to the shared buffer 200 to read the cell body stored in the shared buffer 200 and release the address. Furthermore, the processing method for the congestion warning signal can be specifically determined based on conditions such as the number of shared buffer read ports. The cell identifier includes cell validity information and the cell storage address (i.e., cell body address).

[0056] In this embodiment, by setting a read enable module 520 in the address recycling module 500, and by reading the cell identifier through the read enable module 520 to perform weight adjustment operations and read out the cell body corresponding to the cell identifier, it is possible to realize congestion warning adjustment on the output port side according to the read enable module 520, thereby reducing the probability of congestion.

[0057] Furthermore, referring to Figure 2 and Figure 4 Multiple output ports 120 are respectively connected to multiple input ports (not shown in the figure) of the subsequent switching network chip 3000. The address recycling module 500 also includes a port selector module 510.

[0058] The port selector module 510 is configured to receive the load balancing signal sent by the downstream switching network chip 3000, adjust the weight of the output port 120 according to the load balancing signal, generate the local port sequence, and determine the local cell transmission port according to the local port sequence.

[0059] In this embodiment, the switching network chip 1000 is connected to the next-stage switching network chip 3000, and the switching network chip 1000 can send the cell data stored in the shared buffer 200 to the next-stage switching network chip 3000 through the output port 110. Optionally, the next-stage switching network chip 3000 has the same architecture as the switching network chip 1000.

[0060] Furthermore, the address recycling module 500 includes a port selector module 510, and the shared buffer 200, the port selector module 510, and multiple output ports 120 are connected sequentially. The port selector module 510 can select at least one output port 120 as the cell body transmission port for cell body transmission. For example, when the shared buffer 200 is of type 1w1r, at most one cell body can be read out at any given time, enter the port selector module 510, and then be transmitted out from one output port 120.

[0061] Optionally, in the port terminal module 510, the weights of each output port 120 are equal by default. The cell body output port is polled by each output port 120 in a round-robin fashion, such as port 1, port 2, ..., port n. Based on the load balancing signal (i.e., the load balancing signal of the next-level switching network chip 3000) received, the weights of at least one output port 120 among the ports are adjusted to obtain a port sequence, which is used as the port sequence of this level. For example, if the weight of port 1 is increased, the cell body output port becomes port 1, port 1, port 2, ..., port n in a round-robin fashion. The port sequence can be port 1, port 1, port 2, ..., port n. After determining the cell body output port, the cell body corresponding to the cell identifier can be output through the cell body output port.

[0062] Optionally, the congestion warning signal and the load balancing signal can be applied simultaneously to the address reclamation module 500 to balance the buffer pressure of each port from two aspects. For example, the load balancing signal (i.e., the downstream load balancing signal) sent by the downstream switching network chip 3000 is received to adjust the weight of the output port 120. The weight corresponding to the cell identifier of the output port 120 is adjusted according to the congestion warning signal generated, and the cell body in the shared buffer 200 is read out according to the cell identifier after the weight adjustment.

[0063] In this embodiment, a port selector module 510 is set in the address recycling module 500, and the port selector module 510 adjusts the weight of the output port according to the load balancing signal sent by the downstream switching network chip 3000, so as to achieve load balancing of the input ports of the downstream switching network chip 3000.

[0064] Furthermore, the shared cache management module 300 is also configured to compare the total cache usage depth with the cache congestion threshold when the cache occupancy depth is detected to be greater than the second port congestion threshold, obtain a comparison result, determine a congestion adjustment signal based on the comparison result, and perform congestion adjustment based on the congestion adjustment signal, wherein the second port congestion threshold is greater than the first port congestion threshold.

[0065] In this embodiment of the application, when the shared cache management module 300 performs congestion detection and adjustment on each input port 110, it can detect the cache occupancy depth of each input port 110 and the total cache usage depth of the shared cache 200.

[0066] Optionally, if the shared cache management module 300 detects that the cache occupancy depth of at least one input port 110 is greater than the first port congestion threshold, it also needs to detect the shared cache 200. This involves comparing the total cache usage depth in the shared cache 200 with a pre-set cache congestion threshold to obtain a comparison result. Based on the comparison result, different congestion adjustment signals are generated, and different congestion adjustments are performed according to these signals. The first port congestion threshold can be a user-preset threshold for input ports. The cache congestion threshold can be a user-preset threshold for the shared cache.

[0067] In this embodiment, the shared cache management module 300 performs congestion detection and adjustment based on the cache occupancy depth of the input port 110 and the total cache usage depth of the shared cache 200, thereby achieving congestion detection and adjustment from both the input port 110 and the shared cache 200 levels, ensuring the effectiveness of congestion detection and adjustment.

[0068] Furthermore, the shared cache management module 300 is also configured to generate a congestion alarm signal when the comparison result indicates that the total cache usage depth is greater than the first cache congestion threshold, and send the congestion alarm signal to the upstream switching network chip 2000 connected to the switching network chip 1000, wherein the upstream switching network chip 2000 reduces the ingress traffic to each of the input ports based on the congestion alarm signal;

[0069] The shared cache management module 300 is also configured to reduce the preset monitoring period when the comparison result is that the total cache usage depth is less than or equal to the first cache congestion threshold, and execute the load balancing signal determined based on the preset balancing threshold and the cache occupancy depth according to the reduced monitoring period.

[0070] The cache congestion threshold includes a first cache congestion threshold, which is greater than the second port congestion threshold.

[0071] In this embodiment, when the shared cache management module 300 detects that the cache occupancy depth of at least one input port 110 is less than or equal to the first port congestion threshold, and also detects that the total cache usage depth is less than or equal to the first cache congestion threshold, it can be determined that some input ports 110 have high ingress traffic while other input ports 110 have low ingress traffic. Therefore, the monitoring period corresponding to the load balancing situation can be shortened, that is, the monitoring period for calculating the load balancing value can be shortened, and the cache depth of each input port 110 can be balanced through the load balancing signal. In other words, the ingress traffic of the input ports 110 in the switching network chip 1000 is balanced and adjusted by the upstream switching network chip 2000.

[0072] Optionally, if the shared cache management module 300 detects that the cache occupancy depth of at least one input port 110 is less than or equal to the first port congestion threshold, and the total cache occupancy depth is greater than the first cache congestion threshold, it will generate a congestion alarm signal and send the congestion alarm signal to the upstream switching chip 2000, requesting a reduction in the inbound traffic of all input ports 110. The upstream switching chip 2000 reduces the inbound traffic to each input port 110 based on the congestion alarm signal. Furthermore, after sending the congestion alarm signal to the upstream switching chip 2000, it will monitor the cache occupancy depth of each input port 110 in real time. When the cache occupancy depth of all input ports 110 is less than the second cache congestion threshold, it will restore the load balancing monitoring cycle to the default value.

[0073] In this embodiment, the shared cache management module 300 compares the total cache usage depth with a first cache congestion threshold and performs different actions based on different comparison results to adjust congestion and speed up congestion recovery time.

[0074] Furthermore, referring to Figure 2 and Figure 3 The shared cache management module 300 includes an address allocation module 400, which is connected to multiple input ports 110 and the shared cache 200.

[0075] The address allocation module 400 is configured to discard cells with a priority lower than a preset priority in the shared cache 200 when a congestion warning signal is detected, and to stop writing cells to be enqueued into the shared cache 200 when the priority of cells to be enqueued is lower than the preset priority. The congestion warning signal is generated when the total cache usage depth is greater than a second cache congestion threshold, and the second cache congestion threshold is greater than a first cache congestion threshold.

[0076] In this embodiment, when the shared cache management module 300 detects that the total cache usage depth is greater than the second cache congestion threshold, it generates a congestion warning signal. The address allocation module 400 then determines whether a cell can be enqueued based on the cache occupancy depth of the input port and the cells to be enqueued (i.e., cells to be enqueued). This can be determined using a preset priority (a priority set by the user in advance). Optionally, the more congested the input port and the lower the cell priority, the less likely it is to be enqueued. Simultaneously, low-priority cells in the shared cache are discarded, the address pointer is released, and the cache usage depth counter decreases accordingly. After generating the congestion warning signal response, the total cache usage depth of the shared cache 200 is monitored until the total usage depth of the shared cache 200 (i.e., the total cache usage depth) falls below the second cache congestion threshold, meaning the latest detected total cache usage depth is less than the second cache congestion threshold, thus releasing the congestion warning signal. Optionally, the preset congestion threshold may include a first port congestion threshold and a cache congestion threshold, and may also include a second port congestion threshold. The cache congestion threshold may include both a first cache congestion threshold and a second cache congestion threshold. For example, a first port congestion threshold B1, a second port congestion threshold B2, a first cache congestion threshold A1, and a second cache congestion threshold A2, wherein the first port congestion threshold B1 is less than the second port congestion threshold B2, the second port congestion threshold B2 is less than the first cache congestion threshold A1, and the first cache congestion threshold A1 is less than the second cache congestion threshold A2.

[0077] Optionally, after receiving a cell from the preceding switching network chip 2000, the input port 110 can generate a cell identifier through the address allocation module 400 and store the received cell as a cell body in the shared buffer 200. Optionally, the address allocation module 400 can also detect the cell received by the input port 110, determining whether the cell can be written to the shared buffer 200 and whether an address can be allocated to the shared buffer. It then combines the cell validity information and the allocated address (i.e., the cell body address) to form a cell identifier, writes it to the cell identifier RAM, and enters the forwarding path. Simultaneously, the cell body is written to the shared buffer 200 for storage.

[0078] In this embodiment of the application, by performing a shared cache cell discarding operation and stopping the writing of low-priority cells to the shared cache when a congestion warning signal is detected, the congestion recovery time can be accelerated.

[0079] Furthermore, the shared cache management module 300 is also configured to count the number of incoming cells in each input port 110 of the switching network chip 1000, and determine the cache occupancy depth of the input port 110 based on the number of incoming cells;

[0080] The shared cache management module 300 is further configured to read the number of allocated shared cache addresses from a pre-stored linked list and determine the total cache usage depth of the shared cache 200 based on the number of addresses. In this embodiment, the addresses of cells in the shared cache are managed using a linked list in the shared cache management module 300. In the address allocation module 400, each time an address is allocated, a cell is entered into the corresponding port (e.g., input port 110), and the count is incremented by 1. In the address reclamation module 500, each time an address is released, a cell is output from the corresponding port (e.g., output port 120), and the count is decremented by 1. The shared cache management module 300 determines the cache occupancy depth based on the count corresponding to the input port.

[0081] Optionally, the shared cache management module 300 assigns an address (such as an address to be allocated in the shared cache) to each cell flowing into input port 110 according to the linked list, increments the count by 1, and counts the number of incoming cells at each input port 110 in the switching network chip in this way, and then determines the cache occupancy depth of each input port 110 based on this. For example, within a certain time range, the number of cells (i.e., the number of incoming cells) flowing into input port 110 with allocated shared cache addresses is used as the cache occupancy depth of that input port 110. Optionally, a linked list can be set in the shared cache management module 300. The addresses of cell bodies in the shared cache 200 are managed through a linked list. The allocated shared cache address can be the cell body address in the shared cache 200. Therefore, the total cache occupancy depth of the shared cache can be directly counted by the number of addresses recorded in the linked list.

[0082] In this embodiment, the shared cache management module 300 determines the cache occupancy depth of the input port 110 by counting the number of incoming cells of each input port 110, and determines the total cache usage depth of the shared cache 200 based on the linked list, thereby ensuring the validity of the obtained cache occupancy depth and total cache usage depth.

[0083] In addition, to aid in understanding the architecture of the switching network chip in this embodiment, examples are provided below.

[0084] For example, such as Figure 5As shown, the system includes a preceding-stage switching chip 2000, a switching chip 1000, and a subsequent-stage switching chip 3000 connected in sequence. The switching chip 1000 includes an address allocation module 400, a shared buffer 200, an address recycling module 500, a shared buffer management module 300, and a forwarding path. The address recycling module 500 includes a selector (i.e., a port selector module 510). The preceding-stage switching chip 2000 inputs cells to the various input ports of the switching chip 1000 via inputs 1, 2, and m. The address allocation module 400 stores the received cells in the shared buffer 200, generates a cell identifier based on the cell's valid information and the address stored in the shared buffer, stores it in the cell identifier RAM, and uploads it to the forwarding path. The shared buffer management module 300 counts the ports of each input port. When the read enable is high, the address reclamation module obtains the cell identifier from the forwarding path and sends the address to the shared cache 200. The shared cache 200 sends the stored cell body to the address reclamation module 400 based on the address. The port selector module 510 selects the output port to determine the cell sending port, and then sends it to the next-level switching chip 3000 through the cell sending port (e.g., output 1, output 2, output n). The shared cache management module 300 counts the output counts of each output port 120. Based on the counts obtained from the input port 110 and output port 120, the shared cache management module 300 determines the cache occupancy depth of each port and obtains the total cache depth of the shared cache 200. If load balancing detection is performed based on the cache occupancy depth, a load balancing signal (LB signal) is generated and sent to the previous-level switching chip 2000 to adjust the ingress traffic of input port 110. If a congestion alarm signal (CA signal) is generated based on the cache occupancy depth and sent to the address reclamation module 400, the corresponding interface is prioritized for processing. If a congestion alarm signal (CN) is generated based on the cache occupancy depth and total cache depth, and sent to the upstream switching chip 2000, the input traffic at the input port will be reduced. If a congestion log is generated based on the total cache depth, it will be sent to the shared cache 200, and low-priority cells in the shared cache 200 will be discarded.

[0085] Furthermore, this application also provides a shared cache management method, referring to... Figure 6 In the third embodiment of the shared cache management method of this application, the shared cache management method is applied to a shared cache management module, and the shared cache management module is configured in the switching network chip, including:

[0086] Step S10: Detect the cache occupancy depth of each input port of the switching network chip and the total cache usage depth of the shared cache;

[0087] In this application embodiment, the switching network chip management method can be applied to the shared cache management module in the switching network chip as described in the first or second embodiment above, and can also be applied to the switching network chip 1000 in the switching network chip.

[0088] Optionally, load balancing and congestion management can be achieved through a shared buffer, where all cells received from all ports are entered into the shared buffer. The valid cell information and the address information in the shared buffer are extracted to form a cell identifier. The cell body (i.e., the received cell) is stored in the shared buffer, the cell identifier enters the forwarding path, and finally, at the output port, the cell is read based on the cell identifier for transmission.

[0089] Optionally, the addresses of the shared buffer can be managed using a linked list. At the input port, it is determined whether a cell can be written to the buffer, and an address is assigned to the cell that can be stored; at the output port, the cell is read from the shared buffer according to the address information, the cell is forwarded, and the address is released.

[0090] Therefore, when performing load balancing and congestion management through shared buffers, the buffer occupancy depth of each input port in the switching chip and the total buffer usage depth of the shared buffer can be monitored and calculated in real time. The buffer occupancy depth of the input ports can be determined based on the number of cells in the flow port (the number of cells can be determined based on the address assigned to each cell). The total buffer usage depth can be determined based on the status of each preset address in the shared buffer, and the status of all addresses in the shared buffer can be written to the linked list in the shared buffer management module.

[0091] Step S20: Determine the load balancing signal based on the preset balancing threshold and the cache occupancy depth, and adjust the load balancing according to the load balancing signal;

[0092] Optionally, the load balancing status of each input port can be calculated periodically based on the buffer occupancy depth of each input port. For example, the load balancing status of each input port can be calculated based on a pre-set monitoring period and buffer occupancy depth. Then, all load balancing statuses are checked against a pre-set preset balancing threshold. If at least one load balancing status is detected that does not match the preset balancing threshold, a load balancing signal is triggered, and the traffic to the input ports is adjusted according to the load balancing signal. Optionally, the ingress traffic to the input ports can be balanced and adjusted in the upstream switching network chip 2000 to make the ingress traffic to each input port as consistent as possible. Optionally, the preset balancing threshold can be a load balancing value set by the user in advance. Optionally, if the load balancing value corresponding to a load balancing status is greater than the preset balancing threshold, it can be determined that the load balancing status is abnormal and does not match the preset balancing threshold.

[0093] Step S30: Determine a congestion adjustment signal based on a preset congestion threshold, the cache occupancy depth, and the total cache usage depth, and perform congestion adjustment according to the congestion adjustment signal.

[0094] Optionally, after load balancing judgment and adjustment of the switching network chip, congestion detection, congestion warning, and congestion adjustment also need to be performed on the switching network chip. At this time, congestion detection can be performed by preset congestion thresholds, cache occupancy depth, and total cache usage depth. When an anomaly is detected, a corresponding congestion adjustment signal is generated, and then congestion adjustment is performed based on the congestion adjustment signal to reduce congestion recovery time. The load balancing signal and the congestion adjustment signal can be feedback signals. Feedback signals can include CA signals (i.e., congestion warning signals), LB signals (i.e., load balancing signals), CN signals (i.e., congestion alarm signals), ingress weight signals, and log signals (congestion alert signals), etc.

[0095] Furthermore, to aid understanding of shared cache management methods, examples are provided below. For instance, as... Figure 7 As shown, the system continuously monitors the port cache occupancy depth and total cache usage depth for each port. It can periodically calculate the load balancing description value for each port's cache depth and check if this value is greater than C (the preset load balancing threshold). If not, no action is taken. If so, an lb signal (load balancing signal) is generated and sent to the upstream switching chip 2000 to average the traffic across ports. Furthermore, it can also check the port depth based on port occupancy depth to determine if it is greater than B1 (the first port congestion threshold). If not, no action is taken. If so, a ca signal (congestion warning signal) is generated and sent to the data dequeue module to adjust the output weights. The data dequeue module can be an address reclamation module. Then, it continues to check the port depth to determine if it is greater than B2 (the second port congestion threshold). If not, the process of calculating the load balancing description value is restored. If so, it checks if the total depth is greater than A1 (the first cache congestion threshold). The total depth can be the total cache usage depth. If not, the process of calculating the load balancing description value is accelerated. If so, a cn signal (i.e., a congestion alarm signal) is generated and sent to the upstream switching chip 2000 to reduce the inbound traffic on all ports. Then, it checks if the total depth is greater than A2 (i.e., the second buffer congestion threshold). If not, it checks if the total depth is greater than A1. If so, a log signal (i.e., a congestion warning signal) is generated and sent to the enqueue module to adjust the input weights, send them to the shared buffer, and discard low-priority packets. The enqueue module can be an enqueue determination and address allocation module. Low-priority packets can include low-priority cells.

[0096] In this embodiment, by detecting the cache occupancy depth of each input port and the total cache usage depth of the shared cache, and determining a load balancing signal based on a preset balancing threshold and cache occupancy depth, load balancing adjustments are made according to the load balancing signal. This achieves the determination of the load balancing status of each input port based on the cache occupancy depth, allowing observation of any imbalance in port depths, and adjusting the traffic of the input ports according to the load balancing signal. In other words, load balancing is used as a pre-emptive measure for congestion management, balancing the traffic of each port in advance to simplify congestion management. Furthermore, a congestion adjustment signal is determined based on a preset congestion threshold, cache occupancy depth, and total cache usage depth to perform congestion adjustment, thereby avoiding backpressure at each level, reducing congestion recovery time, and improving the cache utilization rate of the switching network chip.

[0097] In addition, this application also provides an electronic device, which includes a memory, a processor, and a shared cache management program stored on the memory and executable on the processor. When the shared cache management program is executed by the processor, it implements the steps of the shared cache management method described above.

[0098] Furthermore, in one embodiment, Figure 8 This is a schematic diagram of the structure of an electronic device according to an embodiment of the present invention, as shown below. Figure 8 As shown, at the hardware level, this electronic device includes a processor, and optionally also includes an internal bus, a network interface, and memory. The memory may include main memory, such as high-speed random-access memory (RAM), or non-volatile memory, such as at least one disk storage device. Of course, this electronic device may also include other hardware required for its functions. The processor, network interface, and memory can be interconnected via an internal bus, which can be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus, or an EISA (Extended Industry Standard Architecture) bus, etc. This bus can be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, Figure 6The term "bus" is represented by a single double-headed arrow, but this does not imply a single bus or a single type of bus. Memory is used to store programs. Specifically, the program may include program code, which includes computer operation instructions. The processor reads the corresponding computer program from non-volatile memory into memory and then executes it, forming a shared resource access control device at the logical level. The processor executes the program stored in memory and specifically performs the steps of the aforementioned shared cache management method.

[0099] The specific implementation of the electronic device in this application is basically the same as the embodiments of the shared cache management method described above, and will not be repeated here.

[0100] Furthermore, to achieve the above objectives, this application also provides a computer-readable storage medium, which can be a non-volatile readable storage medium. The computer-readable storage medium stores computer-readable instructions, including a shared cache management program. When executed by a processor, the shared cache management program implements the steps of the shared cache management method described above.

[0101] The specific implementation of the computer-readable storage medium in this application is basically the same as the embodiments of the shared cache management method described above, and will not be repeated here.

[0102] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0103] The above are merely preferred embodiments of the present invention and do not limit the scope of the patent. Any equivalent structural or procedural transformations made based on the description and drawings of the present invention, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of the present invention.

Claims

1. A switching network chip, characterized in that, include: The system includes multiple input ports and multiple output ports, a shared buffer and a shared buffer management module connected to the input ports and the output ports, wherein the shared buffer management module is configured to write cells received through the input ports into the shared buffer and read stored cells from the shared buffer for transmission through the output ports. The shared cache management module is configured to detect the cache occupancy depth of each input port and the total cache usage depth of the shared cache, determine a load balancing signal based on a preset balancing threshold and the cache occupancy depth, and perform load balancing adjustments according to the load balancing signal; and determine a congestion adjustment signal based on a preset congestion threshold, the cache occupancy depth, and the total cache usage depth, and perform congestion adjustments according to the congestion adjustment signal.

2. The switching network chip as described in claim 1, characterized in that, The multiple input ports are respectively connected to the multiple output ports of the preceding stage switching network chip. The shared cache management module is further configured to match each cache occupancy depth with the preset balancing threshold, and if it is determined that there is a cache occupancy depth that does not match the preset balancing threshold, trigger the generation of a load balancing signal and send the load balancing signal to the previous-level switching chip, so that the shared cache management module of the previous-level switching chip adjusts the weight of the output port of the previous-level switching chip according to the load balancing signal, generates a previous-level port sequence, and determines the previous-level cell transmission port according to the previous-level port sequence.

3. The switching network chip as described in claim 2, characterized in that, The shared cache management module is further configured to calculate the load balancing value corresponding to each cache occupancy depth based on a preset monitoring period, compare each load balancing value with the preset balancing threshold, and determine that the cache occupancy depth corresponding to the load balancing value greater than the preset balancing threshold does not match the preset balancing threshold if a load balancing value greater than the preset balancing threshold is found to exist.

4. The switching network chip as described in claim 1, characterized in that, The shared cache management module also includes an address reclamation module, which is connected to multiple output ports and the shared cache. The address reclamation module is configured to, upon detecting a congestion warning signal, adjust the weights corresponding to the cell identifiers of output ports whose cache occupancy depth is greater than a first port congestion threshold based on the congestion warning signal, and read the cell bodies in the shared cache based on the cell identifiers with adjusted weights. Specifically, when the cache occupancy depth is greater than a preset first port congestion threshold, a congestion warning signal is triggered.

5. The switching network chip as described in claim 4, characterized in that, The address reclamation module includes a read enable module. The read enable module is configured to adjust the weights corresponding to the cell identifiers of output ports whose cache occupancy depth is greater than the first port congestion threshold based on the congestion warning signal, and to read out the cell identifiers after weight adjustment first, and to read out the cell bodies in the shared cache based on the address information in the cell identifiers read out first.

6. The switching network chip as described in claim 4, characterized in that, The multiple output ports are respectively connected to the multiple input ports of the subsequent switching network chip, and the address recycling module also includes a port selector module. The port selector module is configured to receive the load balancing signal sent by the downstream switching network chip, adjust the weight of the output port according to the load balancing signal, generate the local port sequence, and determine the local cell output port according to the local port sequence.

7. The switching network chip as described in claim 1, characterized in that, The shared cache management module is further configured to, when it detects that the cache occupancy depth is greater than the second port congestion threshold, compare the total cache usage depth with the cache congestion threshold, obtain a comparison result, determine a congestion adjustment signal based on the comparison result, and perform congestion adjustment based on the congestion adjustment signal, wherein the second port congestion threshold is greater than the first port congestion threshold.

8. The switching network chip as described in claim 7, characterized in that, The shared cache management module is further configured to generate a congestion alarm signal when the comparison result indicates that the total cache usage depth is greater than the first cache congestion threshold, and send the congestion alarm signal to the upstream switching network chip connected to the switching network chip, wherein the upstream switching network chip reduces the ingress traffic to each of the input ports based on the congestion alarm signal. The shared cache management module is also configured to reduce the preset monitoring period when the comparison result is that the total cache usage depth is less than or equal to the first cache congestion threshold, and execute the load balancing signal determined based on the preset balancing threshold and the cache occupancy depth according to the reduced monitoring period. The cache congestion threshold includes a first cache congestion threshold, which is greater than the second port congestion threshold.

9. The switching network chip as described in claim 7, characterized in that, The shared cache management module includes an address allocation module, which is connected to multiple input ports and the shared cache. The address allocation module is configured to discard cells with a priority lower than a preset priority in the shared cache when a congestion warning signal is detected, and to stop writing cells to be enqueued into the shared cache when the priority of cells to be enqueued is lower than the preset priority. The congestion warning signal is generated when the total cache usage depth is greater than a second cache congestion threshold, and the second cache congestion threshold is greater than a first cache congestion threshold.

10. The switching network chip as described in claim 1, characterized in that, The shared cache management module is also configured to count the number of incoming cells at each input port in the switching network chip, and determine the cache occupancy depth of the input port based on the number of incoming cells; The shared cache management module is also configured to read the number of allocated shared cache addresses in a pre-stored linked list and determine the total cache usage depth of the shared cache based on the number of addresses.

11. A shared cache management method, characterized in that, Applied to a shared cache management module, the shared cache management module is located in the switching network chip and includes: Detect the buffer occupancy depth of each input port of the switching chip and the total buffer usage depth of the shared buffer; The load balancing signal is determined based on the preset balancing threshold and the cache occupancy depth, and the load balancing is adjusted according to the load balancing signal. A congestion adjustment signal is determined based on a preset congestion threshold, the cache occupancy depth, and the total cache usage depth, and congestion adjustment is performed according to the congestion adjustment signal.

12. An electronic device, characterized in that, The electronic device includes: a memory, a processor, and a shared cache management program stored in the memory and executable on the processor, wherein the shared cache management program, when executed by the processor, implements the steps of the shared cache management method as described in claim 11.

13. A medium, characterized in that, The medium includes a computer-readable storage medium storing a shared cache management program, which, when executed by a processor, implements the steps of the shared cache management method as described in claim 11.

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