A high-consistency biasing circuit for an image sensor

Abstract

The application discloses a high-consistency bias circuit for an image sensor, comprising a reference current generating module, a global current bias module and a current output module; the reference current generating module is used for providing a reference current proportional to absolute temperature; the global current bias module is used for shunting the reference current into at least one input current proportional to absolute temperature; and the current output module is used for shunting the input current into at least one output bias current proportional to absolute temperature. According to the application, the reference current is set to be proportional to absolute temperature, so that the output bias current output finally is also proportional to absolute temperature, the problem that the performance of the biased circuit is reduced with the increase of temperature is solved, and the output bias current output can keep high consistency through the cooperation of the reference current generating module, the global current bias module and the current output module.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of image sensors, and particularly relates to a high-consistency bias circuit for an image sensor. BACKGROUND

[0002] An image sensor is a device for converting optical signals into electrical signals and performing operations such as amplification, sampling and analog-to-digital conversion, and is composed of a light-sensing element and a readout circuit. According to different detection wavebands, it is currently mainly divided into visible light and infrared image sensors, and has been widely applied in the fields of network cameras, automatic driving and industrial detection.

[0003] As shown in Figure 1 , it is a bias circuit structure schematic diagram in the prior art. The NMOS tube MN0 adopts a diode connection method to convert a reference current I REF into a voltage for MN 1-N to provide voltage bias; the source of MN 1-N is connected to ground, and the drain is connected to the output and the biased circuit. Since the scale of the image sensor is large, the parasitic resistance R 1-N between the source wire of MN Par and the left ground potential cannot be ignored, resulting in inconsistent gate-source voltages of different columns MN 1-N , so that the output bias current IO 1-N exists deviation.

[0004] Figure 2 is an improvement on Figure 1 , which adjusts the current size of MP1 and MN1 by adjusting the transistor size. Under the premise of ensuring the output current IO 1-N , reducing the current flowing through MP1 can reduce the influence of the parasitic resistance R Par , but as the circuit scale increases, the current flowing through the parasitic resistance becomes larger and larger, resulting in larger and larger deviation of the output current IO 1-N . The above two biasing methods are difficult to ensure the consistency of the output current IO 1-N , and increase the fixed pattern noise of the image sensor. SUMMARY

[0005] The technical problem to be solved by the present application is that in order to enable the existing bias circuit to maintain consistency as the circuit scale increases, the present application provides a high-consistency bias circuit for an image sensor.

[0006] In order to solve the above technical problem, the embodiment of the present application provides a high-consistency bias circuit for an image sensor, comprising: a reference current generating module, a global current biasing module and a current output module.

[0007] The reference current generating module is configured to provide a reference current proportional to absolute temperature;

[0008] The global current biasing module is configured to split the reference current into at least one input current proportional to absolute temperature;

[0009] The current output module is configured to split the input current into at least one output biasing current proportional to absolute temperature;

[0010] The output end of the reference current generating module is connected to the input end of the global current biasing module; the output end of the global current biasing module is connected to the input end of the current output module; the reference current generating module, the global current biasing module and the current output module transmit current signals therebetween, and MOS transistors inside the global current biasing module and the current output module abut; the output end of the current output module is configured to output the output biasing current, and the deviation between the output biasing currents is less than 1%.

[0011] Preferably, the reference current generating module comprises an operational amplifier, a first NMOS transistor and a first resistor.

[0012] The non-inverting input end of the operational amplifier is connected to a first reference voltage, the inverting input end is connected to the source of the first NMOS transistor, and the output end is connected to the gate of the first NMOS transistor; the drain of the first NMOS transistor is connected to the output end of the reference current generating module and the input end of the global current biasing module; one end of the first resistor is connected to the source of the first NMOS transistor, and the other end is grounded.

[0013] Preferably, the first resistor is a resistor with a negative temperature coefficient.

[0014] Preferably, the global current biasing module comprises a first PMOS transistor and a second PMOS transistor group; the second PMOS transistor group comprises at least one second PMOS transistor; the gate and the drain of the first PMOS transistor are connected to the output end of the reference current generating module and the input end of the global current biasing module; the source of the first PMOS transistor and the source of the second PMOS transistor are connected to a second reference voltage; the gate of the first PMOS transistor is connected to the gate of the second PMOS transistor to form a current mirror structure; the drain of the second PMOS transistor is connected to the output end of the global current biasing module and the input end of the current output module.

[0015] Preferably, the current output module comprises at least one current output unit; the second PMOS transistor corresponds to the current output unit one by one, and the drain of each second PMOS transistor is connected to the input end of a current output unit.

[0016] Preferably, the first PMOS tube and the second PMOS tube abut.

[0017] Preferably, the plurality of second PMOS tubes are respectively located at the left and right ends of the first PMOS tube and abut each other with the first PMOS tube.

[0018] Preferably, the current output module comprises at least one current output unit; the current output unit comprises a second NMOS tube and a third NMOS tube group; the third NMOS tube group comprises at least one third NMOS tube; the gate and the drain of the second NMOS tube are connected with the output end of the global current biasing module as the input end of the current output module; the source of the second NMOS tube and the source of the third NMOS tube are grounded; the gate of the second NMOS tube is connected with the gate of the third NMOS tube to form a current mirror structure; and the drain of the third NMOS tube outputs the output biasing current as the output end of the current output module.

[0019] Preferably, when there are at least two current output units, the current output units are arranged at equal intervals; and the second NMOS tube and the third NMOS tube in the current output unit abut.

[0020] Preferably, the plurality of third NMOS tubes in the current output unit are respectively located at the left and right ends of the second NMOS tube and abut each other with the second NMOS tube.

[0021] The embodiment of the present application has the following beneficial effects:

[0022] The embodiment of the present application uses a reference current proportional to the absolute temperature to make the output biasing current proportional to the absolute temperature, thereby relieving the problem of performance decline of the biased circuit caused by temperature rise. The global current biasing module and the current output module are used for twice current division, so that the deviation between the output biasing currents is less than 1%, thereby obtaining the output biasing current with high consistency.

[0023] The embodiment of the present application divides the current output module into a plurality of current output units, the input current of different current output units is provided by the global current biasing module, and the transistors in the current output module and the global current biasing module abut. The parasitic resistance in each module can be ignored, and the resistance between the modules does not affect the uniformity of the output biasing current, thereby reducing the fixed pattern noise of the image sensor. BRIEF DESCRIPTION OF DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description only constitute some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0025] Figure 1 A bias circuit structure schematic diagram of the prior art;

[0026] Figure 2 A bias circuit structure schematic diagram of the prior art improved for Figure 1

[0027] Figure 3 A high-consistency bias circuit structure schematic diagram for an image sensor provided by the embodiments of the present application;

[0028] Figure 4 A high-consistency bias circuit output bias current transient simulation result diagram for an image sensor provided by the embodiments of the present application. DETAILED DESCRIPTION

[0029] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments only constitute some embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of the present application.

[0030] As shown in Figure 3 , the high-consistency bias circuit for an image sensor disclosed by the embodiments comprises a reference current generation module 40, a global current bias module 50 and a current output module 60. The output end of the reference current generation module 40 is connected with the input end of the global current bias module. The output end of the global current bias module 50 is connected with the input end of the current output module 60. The output end of the current output module 60 is used to output the output bias current (IO1 ~ IO K ).

[0031] The reference current generation module 40 is used to provide a reference current I PTAT proportional to absolute temperature. The global current bias module 50 is used to generate a global bias current I PTAT ​An input current proportional to the absolute temperature is generated and output to the current output module 60. The current output module 60 is used to output an output bias current proportional to the absolute temperature based on the input current. This alleviates the problem of performance degradation of the biased circuit due to increasing temperature. Furthermore, by using a global current bias module and a current output module for two current splits, the deviation between the final output bias currents is less than 1%, thus achieving a highly consistent output bias current.

[0032] The reference current generation module 40 includes: an operational amplifier 401 (AMP), a first NMOS transistor 402 (MNB), and a first resistor 403 (R). Bias The non-inverting input of the operational amplifier 401 is connected to the first reference voltage V. BG The inverting input terminal is connected to the source of the first NMOS transistor 402, and the output terminal is connected to the gate of the first NMOS transistor 402. The first reference voltage V... BG The reference voltage is the bandgap voltage. The drain of the first NMOS transistor 402 is connected to the output of the reference current generation module 40 and the input of the global current bias module 50. The two ends of the first resistor 403 are connected to the source of the first NMOS transistor 402 and ground (GND), respectively. The operational amplifier 401, the first NMOS transistor 402, and the first resistor 403 form a negative feedback structure to maintain the reference current I. PTAT The stability is ensured. The first resistor 403 is selected as a high-precision, large-block resistance resistor with a negative temperature coefficient.

[0033] In some embodiments, the bandgap reference voltage V BG It is the low-voltage bandgap reference voltage of 500-600mV after voltage division, and the resistance R Bias Select a polycrystalline silicon resistor with a resistance of 500-600kΩ; at the bandgap reference voltage V BG With polycrystalline silicon resistor R Bias Under its influence, a reference current I proportional to the absolute temperature can be generated. PTAT And at room temperature I PTAT Its size is approximately 1 μA.

[0034] The global current bias module 50 includes a first PMOS transistor 501 (MP0) and a second PMOS transistor group 510 (MP1~MP2). J). The second PMOS tube group 510 includes at least one second PMOS tube 502. The first PMOS tube 501 adopts a diode connection method. The gate and the drain of the first PMOS tube 501 are connected to the output end of the reference current generation module 40, i.e., the gate and the drain of the first PMOS tube 501 are connected to the drain of the first NMOS tube 402. The source of the first PMOS tube 501 and the source of the second PMOS tube 502 are connected to the second reference voltage VCC. The second reference voltage VCC is a power supply voltage. The gate of the first PMOS tube 501 is connected to the gate of the second PMOS tube 502 to form a current mirror structure. The drain of the second PMOS tube 502 is connected to the input end of the current output module 60 as the output end of the global current bias module 50.

[0035] In some embodiments, there is also a resistor R Par0 between the reference current generation module 40 and the global current bias module 50. J The current size is also proportional to the absolute temperature, the width-length ratio of the first PMOS tube 501 and the second PMOS tube 502, and the reference current I PTAT . All the PMOS tubes in the global current bias module 50 abut in the high-consistency bias circuit for image sensors, and the resistance R Par0 can be ignored. Among them, the first PMOS tube 501 is located in the middle, and the plurality of second PMOS tubes 502 are respectively located on the left and right of the first PMOS tube 501. The first PMOS tube 501 abuts with the plurality of second PMOS tubes 502. The reference current generation module and the global current bias module transfer current signals, and the resistance R Par0 does not affect the current replication accuracy of the global current bias module 50, so as not to affect the accuracy of the input current.

[0036] The current output module 60 includes at least one current output unit 610. The current output unit 610 includes a second NMOS tube 601 and a third NMOS tube group 620. The third NMOS tube group 620 includes at least one third NMOS tube 602. The second PMOS tube 502 corresponds to the current output unit 610 one by one, and the drain of each second PMOS tube 502 is connected to the input end of one current output unit 610. The second NMOS tube 601 adopts a diode connection method, and the gate and the drain are connected to the output end of the global current bias module 50 as the input end of the current output module 60, that is, the gate and the drain of the second NMOS tube 601 are connected to the drain of the second PMOS tube 502. The source of the second NMOS tube 601 and the source of the third NMOS tube 602 are connected to the ground. The gate of the second NMOS tube 601 is connected to the gate of the third NMOS tube 602 to form a current mirror structure. The drain of the third NMOS tube 602 is connected to the biased circuit as the output end of the current output module 60, and outputs the output bias current to the biased circuit.

[0037] When the current output module 60 includes at least two current output units 610, the current output module 60 further includes at least one second resistor 603 (R Par1 ). The second resistor 603 is located between the adjacent two current output units 610, and the two ends are respectively connected to the source of the second NMOS tube 601 and the source of the third NMOS tube 602 in the adjacent two current output units 610.

[0038] In some embodiments, the current output module 60 provides the output bias current (IO1 ~ IO KThe current size is proportional to the absolute temperature, and is related to the width-length ratio of the second NMOS tube 601 and the third NMOS tube 602 and the input current. All NMOS tubes of the current output unit 610 abut in the high consistency bias circuit for the image sensor. The second NMOS tube 601 is located in the middle, and the plurality of third NMOS tubes 602 are respectively located at the left and right ends of the second NMOS tube 601. The second NMOS tube 601 and the plurality of third NMOS tubes 602 abut each other. All current output units 610 in the current output module 60 are placed at equal intervals. By dividing the current output module 60 into J current output units 610, the number of second NMOS tubes 601 and third NMOS tubes 602 in each current output unit 610 is reduced, and the second NMOS tube 601 and the plurality of third NMOS tubes 602 abut each other, thereby reducing the resistance in each current output unit 610, so that the internal resistance of the current output module 610 can be ignored. The consistency of the final output bias current output by the current output unit 610 is determined by the consistency of the input current and the accuracy of the current output unit replication. The second resistance 603 between the current output units 610 does not affect the current replication accuracy of the current output module. The resistance in each module can be ignored, and the resistance between the modules does not affect the uniformity of the output bias current, thereby reducing the fixed pattern noise of the image sensor.

[0039] In some embodiments, the second PMOS tube is J, and the current output unit 610 is also J. The third NMOS tube 602 in the current output unit 610 is K. The total number of third NMOS tubes 602 in the current output module 60 is N=J×K. The number of output output bias currents is also N=J×K. Considering power consumption and consistency of the output bias current output, the values of J and K are usually not much different, and the product of J and K is consistent with the size of the biased circuit array. The width-length ratio of the first PMOS tube 501 and the second PMOS tube 502 is 3:2~3:1. The width-length ratio of the second NMOS tube 601 and the third NMOS tube 602 is 4:1~6:1.

[0040] In some embodiments, J and K are respectively 64 and 32, i.e. there are 64 current output modules 60 in total, each of which provides high-consistency output bias current for 32 columns of circuits. A total of 2048 output bias currents are formed. The 2048 output bias currents are connected to a 2048-array-size biased circuit array. The high-consistency bias circuit for image sensors can be optimized by adjusting the width-length ratios of the first PMOS tube 501 and the second PMOS tube in the global current bias module 50 and the second NMOS tube 601 and the third NMOS tube 602 in the current output module 60. The width-length ratio of the first PMOS tube 501 and the second PMOS tube 502 is 2:1. The width-length ratio of the second NMOS tube 601 and the third NMOS tube 602 is 5:1. Therefore, the total output bias current is about 10 μA. Referring to Figure 4 As shown in Figure 4 the transient simulation results of the output bias currents IO 1-4 , IO 1023-1026 and IO 2045-2048 are all distributed around 11.58 μA, and the maximum output deviation is less than 9.5 nA, i.e. less than 1‰. The output bias currents have the effect of high consistency.

[0041] In summary, the embodiment of the present application sets the reference current output by the reference current generation module 40 to be proportional to absolute temperature, and then duplicates the reference current through the global current bias module 50 and the current output module 60, so that the output bias current is also proportional to absolute temperature, thereby alleviating the problem of performance degradation of the biased circuit caused by temperature rise, and keeping the reference current stable. The global current bias module and the current output module are used for twice current division, so that the deviation between the finally output output bias currents is less than 1%, thereby obtaining high-consistency output bias currents. The arrangement of the PMOS tubes and the NMOS tubes in the embodiment is adjusted, so that the PMOS tubes and the NMOS tubes are all in the abutting state, thereby making the parasitic resistance in the embodiment negligible and the resistance between the modules not affecting the uniformity of the output bias current, thereby reducing the fixed pattern noise of the image sensor.

[0042] The above only discloses one preferred embodiment of the present application, and of course cannot limit the scope of the rights of the present application. Those skilled in the art can understand that the whole or part of the above-mentioned embodiment can be implemented, and equivalent changes made according to the claims of the present application still belong to the scope covered by the present application.

Claims

1. A high-consistency biasing circuit for an image sensor, characterized by, The application relates to a current output module, which comprises a reference current generating module, a global current biasing module and a current output module. The reference current generating module is used for providing a reference current proportional to absolute temperature. The global current biasing module is used for shunting the reference current into at least one input current proportional to absolute temperature. The current output module is used for shunting the input current into at least one output biasing current proportional to absolute temperature. The output end of the reference current generating module is connected with the input end of the global current biasing module. The output end of the global current biasing module is connected with the input end of the current output module. The reference current generating module, the global current biasing module and the current output module transmit current signals, and MOS tubes in the global current biasing module and the current output module abut. The output end of the current output module is used for outputting the output biasing current, and the deviation between the output biasing currents is less than 1%. The global current biasing module comprises a first PMOS tube and a second PMOS tube group; the second PMOS tube group comprises a plurality of second PMOS tubes; the gate and the drain of the first PMOS tube are connected with the output end of the reference current generating module and the input end of the global current biasing module; the source of the first PMOS tube and the source of the second PMOS tube are connected with a second reference voltage; the gate of the first PMOS tube is connected with the gate of the second PMOS tube to form a current mirror structure; and the drain of the second PMOS tube is connected with the input end of the current output module and the output end of the global current biasing module. The reference current generating module comprises an operational amplifier, a first NMOS tube and a first resistor.

2. The high-consistency biasing circuit for an image sensor of claim 1, wherein, The non-inverting input end of the operational amplifier is connected with a first reference voltage, the inverting input end is connected with the source of the first NMOS tube, and the output end is connected with the gate of the first NMOS tube; the drain of the first NMOS tube is connected with the input end of the global current biasing module and the output end of the reference current generating module; and one end of the first resistor is connected with the source of the first NMOS tube, and the other end is grounded. The first resistor is a resistor with a negative temperature coefficient.

3. The high-consistency biasing circuit for an image sensor of claim 2, wherein, The current output module comprises at least one current output unit; the second PMOS tube is in one-to-one correspondence with the current output unit, and the drain of each second PMOS tube is connected with the input end of a current output unit.

4. The high-consistency biasing circuit for an image sensor of claim 1, wherein, The first PMOS tube abuts against the second PMOS tube.

5. The high-consistency biasing circuit for an image sensor of claim 1, wherein, The plurality of second PMOS tubes are respectively arranged at the left and right ends of the first PMOS tube and abut against the first PMOS tube.

6. The high-consistency biasing circuit for an image sensor of claim 5, wherein, ​ 7. The high-consistency biasing circuit for an image sensor of claim 1, wherein, The current output module comprises at least one current output unit; the current output unit comprises a second NMOS tube and a third NMOS tube group; the third NMOS tube group comprises at least one third NMOS tube; the gate and the drain of the second NMOS tube are connected with the output end of the global current bias module as the input end of the current output module; the source of the second NMOS tube and the source of the third NMOS tube are grounded; the gate of the second NMOS tube is connected with the gate of the third NMOS tube to form a current mirror structure; the drain of the third NMOS tube outputs the output bias current as the output end of the current output module.

8. The high-consistency biasing circuit for an image sensor of claim 7, wherein, When there are at least two current output units, the current output units are placed at equal intervals; the second NMOS tube and the third NMOS tube in the current output unit abut each other.

9. The high-consistency biasing circuit for an image sensor of claim 8, wherein, The plurality of third NMOS tubes in the current output unit are respectively located at the left and right ends of the second NMOS tube and abut each other with the second NMOS tube.

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