Semiconductor structure and preparation method thereof, and buried word line

Abstract

The present disclosure relates to a semiconductor structure, a method for fabricating the same, and a buried wordline structure. The semiconductor structure includes a substrate, a trench, a first dielectric layer, a first conductive layer, a second conductive layer, a target sidewall spacer, and a third conductive layer. The substrate includes spaced doped regions; the trench is located between the doped regions, with its bottom surface no higher than the bottom surface of the doped regions; the first dielectric layer covers the sidewalls and bottom surface of the trench; the first conductive layer is located on the surface of the first dielectric layer at the bottom of the trench, with its top surface no higher than the bottom surface of the doped regions; the second conductive layer is located on the top surface of the first conductive layer, with its top surface lower than the top surface of the doped regions; the target sidewall spacer is located on the top surface of the second conductive layer and covers a portion of the side surface of the first dielectric layer; and the third conductive layer is located on the top surface of the second conductive layer, with its top surface higher than the bottom surface of the doped regions and lower than the top surface of the target sidewall spacer. This semiconductor structure can increase drive current and reduce gate leakage current, thereby improving the read and write speed and reliability of the semiconductor structure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a preparation method thereof, and a buried word line. Background Art

[0002] The embedded fin field-effect transistor (FINFET) is an innovative design derived from the traditional standard field-effect transistor (FET). In the FINFET architecture, the gate is a forked 3D structure similar to a fish fin, which can control the connection and disconnection of the circuit on both sides, significantly improving circuit control.

[0003] The FINFET process requires a thicker oxide layer, but a thicker gate oxide layer and longer channel lead to lower drive current and slower read and write speeds. Traditionally, increasing drive current is achieved by increasing the overlap area between the source / drain and the gate. However, this increased overlap increases leakage current, impacting device operation. Summary of the Invention

[0004] Based on this, the present disclosure provides a semiconductor structure and a manufacturing method thereof, and a buried word line, which can increase the driving current while reducing the gate leakage current.

[0005] A semiconductor structure includes a substrate, a trench, a first dielectric layer, a first conductive layer, a second conductive layer, a target sidewall, and a third conductive layer. The substrate includes spaced doped regions. The trench is located between the doped regions and has a bottom surface no higher than the bottom surface of the doped region. The first dielectric layer covers the sidewalls and bottom surface of the trench. The first conductive layer is located on the surface of the first dielectric layer at the bottom of the trench and has a top surface no higher than the bottom surface of the doped region. The second conductive layer is located on the top surface of the first conductive layer and has a top surface lower than the top surface of the doped region. The target sidewall is located on the top surface of the second conductive layer and covers part of the side surface of the first dielectric layer. The third conductive layer is located on the top surface of the second conductive layer and has a top surface higher than the bottom surface of the doped region and lower than the top surface of the target sidewall.

[0006] In the semiconductor structure of the above embodiment, by providing a target sidewall having a corner within the second conductive layer and the third conductive layer and providing a multi-layer conductive layer, the contact area between the target sidewall and the third conductive layer is increased without increasing the channel length, and the overlap capacitance between the target sidewall and the doped region is increased, thereby improving the drive current and thereby improving the read and write speed of the semiconductor structure. In this embodiment, the dielectric layer is further provided with a multi-layer structure consisting of the first dielectric layer and the target sidewall, thereby increasing the thickness of the dielectric layer, reducing the leakage current and maintaining the gate-induced drain leakage (GIDL) current unchanged. Therefore, the reliability of the semiconductor structure is improved while improving the read and write speed of the semiconductor structure.

[0007] In some embodiments, the target sidewall spacer includes a second dielectric layer and a third dielectric layer, wherein the second dielectric layer is located on the top surface of the second conductive layer and covers at least a portion of the side surface of the first dielectric layer; the third dielectric layer is located on the top surface of the second conductive layer and between the second dielectric layer and the third conductive layer. The dielectric layer includes a three-layer structure consisting of the first dielectric layer, the second dielectric layer, and the third dielectric layer, thereby increasing the thickness of the dielectric layer, reducing leakage current, and improving the reliability of the semiconductor structure.

[0008] In some embodiments, the second dielectric layer includes a first portion and a second portion. The first portion is located on the top surface of the second conductive layer and covers a portion of the side surface of the first dielectric layer, thereby increasing the contact area between the target sidewall and the third conductive layer. The second portion is located on the top surface of the second conductive layer and between the first portion and the third conductive layer, thereby adding a corner to the second dielectric layer while ensuring that the channel length is not increased.

[0009] In some embodiments, a material of the third dielectric layer is the same as a material of the first dielectric layer and different from a material of the second dielectric layer.

[0010] In some embodiments, the top surface of the third dielectric layer has a rounded surface to avoid tip discharge.

[0011] In some embodiments, the second conductive layer has a thickness of a first predetermined thickness, which is less than the thickness of the first conductive layer, such that a top surface of the second conductive layer is lower than a top surface of the doped region, thereby increasing the overlap area between the target sidewall spacer and the doped region, increasing the overlap capacitance between the target sidewall spacer and the doped region, improving the drive current, and increasing the read / write speed of the semiconductor structure. In some embodiments, the third conductive layer has a thickness greater than the first predetermined thickness, thereby increasing the contact area between the target sidewall spacer and the third conductive layer, increasing the overlap capacitance between the target sidewall spacer and the doped region, increasing the drive current, and improving the read / write speed of the semiconductor structure.

[0012] In some embodiments, the material of the first conductive layer is different from the material of the second conductive layer and the material of the third conductive layer.

[0013] In some embodiments, the semiconductor structure further includes a capping layer, which fills the gap on the third conductive layer in the trench and covers the exposed top surface of the substrate to protect the entire semiconductor structure.

[0014] Another aspect of the present disclosure provides a buried wordline structure, comprising a substrate, a trench, a first dielectric layer, a first conductive layer, a second conductive layer, a target sidewall spacer, and a third conductive layer. The substrate is provided with spaced doped regions; the trench is formed between the doped regions and has a bottom surface no higher than the bottom surface of the doped region; the first dielectric layer covers the sidewalls and bottom surface of the trench; the first conductive layer is located at the bottom of the trench and has a top surface no higher than the bottom surface of the doped region; the second conductive layer is located on the top surface of the first conductive layer and has a top surface lower than the top surface of the doped region; the target sidewall spacer is located on the top surface of the second conductive layer and covers a portion of the side surface of the first dielectric layer; the third conductive layer is located on the top surface of the second conductive layer, and has a top surface higher than the bottom surface of the doped region and lower than the top surface of the target sidewall spacer. The first dielectric layer, the first conductive layer, the second conductive layer, the target sidewall spacer, and the third conductive layer constitute the wordline structure.

[0015] The buried word line structure in the above-mentioned embodiment increases the contact area between the target sidewall and the third conductive layer without increasing the channel length by providing a target sidewall having a corner and providing a conductive layer with a multi-layer structure within the second conductive layer and the third conductive layer, thereby increasing the overlap capacitance between the target sidewall and the doped region, and improving the drive current, thereby improving the read and write speed of the buried word line structure. This embodiment further increases the thickness of the dielectric layer by providing a multi-layer structure composed of the first dielectric layer and the target sidewall, thereby reducing the leakage current and maintaining the GIDL, thereby improving the read and write speed of the buried word line structure while improving the reliability of the buried word line structure.

[0016] In some embodiments, the target sidewall spacer includes a second dielectric layer and a third dielectric layer. The second dielectric layer is located on top of the second conductive layer and covers at least a portion of the side surface of the first dielectric layer. The third dielectric layer is located on top of the second conductive layer and between the second and third dielectric layers. The dielectric layer comprises a three-layer structure consisting of the first, second, and third dielectric layers. Increasing the thickness of the dielectric layer reduces leakage current and improves the reliability of the buried wordline structure. In some embodiments, the thickness of the second conductive layer is a first predetermined thickness that is less than the thickness of the first conductive layer. This allows the top surface of the second conductive layer to be lower than the top surface of the doped region, thereby increasing the overlap area between the target sidewall spacer and the doped region, increasing the overlap capacitance between the target sidewall spacer and the doped region, and increasing the drive current, thereby improving the read and write speed of the buried wordline structure.

[0017] In some embodiments, the thickness of the third conductive layer is greater than the first preset thickness, which increases the contact area between the target sidewall and the third conductive layer, increases the overlap capacitance between the target sidewall and the doped region, increases the drive current, and thus improves the read and write speed of the buried word line structure.

[0018] In some embodiments, a material of the second conductive layer is the same as a material of the third conductive layer, and different from a material of the first conductive layer.

[0019] Another aspect of the present disclosure provides a method for fabricating a semiconductor structure, comprising: providing a substrate having spaced doped regions formed therein; forming a trench in the substrate between adjacent doped regions, wherein the bottom surface of the trench is no higher than the bottom surface of the doped region; forming a first dielectric layer on the sidewalls and bottom surface of the trench; forming a first conductive layer on the surface of the first dielectric layer at the bottom of the trench, wherein the top surface of the first conductive layer is no higher than the bottom surface of the doped region; forming a second conductive layer on the top surface of the first conductive layer, wherein the top surface is lower than the top surface of the doped region; forming a target sidewall on the top surface of the second conductive layer, covering a portion of the side surface of the first dielectric layer; and forming a third conductive layer on the top surface of the second conductive layer, wherein the top surface is higher than the bottom surface of the doped region and lower than the top surface of the target sidewall.

[0020] The method for preparing the semiconductor structure in the above-mentioned embodiment increases the contact area between the target sidewall and the third conductive layer without increasing the channel length by providing a target sidewall having a corner and providing a conductive layer with a multi-layer structure. This increases the overlap capacitance between the target sidewall and the doped region, thereby improving the drive current and thereby improving the read and write speed of the semiconductor structure. This embodiment also increases the thickness of the dielectric layer by providing a multi-layer structure consisting of the first dielectric layer and the target sidewall, thereby reducing the leakage current and maintaining the GIDL unchanged. Therefore, the reliability of the semiconductor structure is improved while improving the read and write speed of the semiconductor structure.

[0021] In some embodiments, forming a target sidewall spacer on the top surface of the second conductive layer that covers a portion of the side surface of the first dielectric layer includes: after forming the second conductive layer, forming a second dielectric material layer, the second dielectric material layer covering the top surface of the second conductive layer, a portion of the side surface of the first dielectric layer, and the exposed top surface of the substrate; forming a third dielectric material layer, the third dielectric material layer covering the exposed surface of the second dielectric material layer; and etching back the third dielectric material layer and the second dielectric material layer that cover the top surface of the substrate and the top surface of the second conductive layer, the remaining third dielectric material layer and the remaining second dielectric material layer forming the target sidewall spacer, the dielectric layer including a three-layer structure consisting of the first dielectric layer, the second dielectric layer, and the third dielectric layer, thereby increasing the thickness of the dielectric layer, reducing leakage current, and improving the reliability of the semiconductor structure.

[0022] In some embodiments, the material of the third dielectric material layer is the same as that of the first dielectric material layer, and different from that of the second dielectric material layer.

[0023] In some embodiments, forming a first dielectric layer on the sidewalls and bottom of the trench includes: forming the first dielectric layer on the sidewalls and bottom of the trench using an atomic layer deposition process and an in-situ water vapor generation process to improve electrical properties of the first dielectric layer.

[0024] In some embodiments, after forming a third conductive layer on the top surface of the second conductive layer, whose top surface is higher than the bottom surface of the doped region and lower than the top surface of the target sidewall, it also includes: forming a cap layer that fills the gap on the third conductive layer in the trench and covers the exposed top surface of the substrate to protect the overall semiconductor structure.

[0025] In some embodiments, the thickness of the second conductive layer is a first preset thickness, which is less than the thickness of the first conductive layer; and / or the thickness of the third conductive layer is greater than the first preset thickness, so that the top surface of the second conductive layer is lower than the top surface of the doped region, increasing the overlapping area between the target side wall and the doped region and the contact area with the third conductive layer, increasing the overlapping capacitance between the target side wall and the doped region, increasing the driving current, and improving the read and write speed of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0027] Figure 1 A schematic structural diagram of a semiconductor structure provided in one embodiment of the present disclosure;

[0028] Figure 2 This is a schematic structural diagram of a semiconductor structure provided in yet another embodiment of the present disclosure;

[0029] Figure 3 This is a schematic structural diagram of a semiconductor structure provided in yet another embodiment of the present disclosure;

[0030] Figure 4 A schematic flow chart of a method for preparing a semiconductor structure provided in one embodiment of the present disclosure;

[0031] Figure 5 A schematic diagram of a cross-sectional structure of a substrate provided in some embodiments of the present disclosure;

[0032] Figure 6 In some embodiments of the present disclosure, Figure 5A schematic cross-sectional structure diagram of a trench formed on a substrate shown;

[0033] Figure 7 In some embodiments of the present disclosure, Figure 6 A schematic cross-sectional structural diagram of a first dielectric layer formed on the structure shown;

[0034] Figure 8 In some embodiments of the present disclosure, Figure 7 A schematic cross-sectional structural diagram of a first conductive material layer formed on the structure shown;

[0035] Figure 9 In some embodiments of the present disclosure, Figure 8 A schematic cross-sectional structural diagram of a first conductive layer formed on the structure shown;

[0036] Figure 10 In some embodiments of the present disclosure, Figure 9 A schematic cross-sectional view of a second conductive material layer formed on the structure shown;

[0037] Figure 11 In some embodiments of the present disclosure, Figure 10 A schematic cross-sectional view of a second conductive layer formed on the structure shown;

[0038] Figure 12 In some embodiments of the present disclosure, Figure 11 A schematic cross-sectional structural diagram of a second dielectric material layer formed on the structure shown;

[0039] Figure 13 In some embodiments of the present disclosure, Figure 12 A schematic cross-sectional structural diagram of a third dielectric material layer formed on the structure shown;

[0040] Figure 14 In some embodiments of the present disclosure, Figure 13 A schematic diagram of a cross-sectional structure of a target side wall formed on the structure shown;

[0041] Figure 15 In some embodiments of the present disclosure, Figure 14 A schematic cross-sectional structural diagram of a third conductive material layer formed on the structure shown;

[0042] Figure 16 Schematic diagram of the technical effect of the buried word line structure provided in one embodiment of the present disclosure.

[0043] Description of reference numerals:

[0044] 10. Substrate; 11. Doped region; 20. Trench; 30. First dielectric layer; 41. First conductive material layer; 40. First conductive layer; 51. Second conductive material layer; 50. Second conductive layer; 60. Target sidewall spacer; 161. Second dielectric material layer; 61. Second dielectric layer; 611. First portion; 612. Second portion; 162. Third dielectric material layer; 62. Third dielectric layer; 71. Third conductive material layer; 70. Third conductive layer; 80. Cap layer. DETAILED DESCRIPTION

[0045] To facilitate understanding of the present disclosure, a more comprehensive description of the present disclosure will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present disclosure. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0047] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0048] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0049] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0050] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present disclosure. Although the illustrations only show components related to the present disclosure and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation can be changed arbitrarily, and the component layout type may also be more complex.

[0051] In Dynamic Random Access Memory (DRAM) products, the front-end Metal-Oxide-Semiconductor (MOS) requires a FINFET structure due to its manufacturing process. The FINFET process steps have very high requirements for the working performance of the FINFET. First, the channel length needs to cover the short channel effect, so a long channel MOS needs to be produced. Secondly, due to the limitations of its Time Dependent Dielectric Breakdown RE test (TDDB RE test), a thicker oxide layer is required. Since the array MOS is responsible for reading and writing information, the drive current needs to be increased to improve the reading and writing speed. However, according to the driving current calculation formula, the thicker gate oxide layer and longer channel required by the process issues will result in a smaller driving current and slower reading and writing speeds.

[0052] I dsat ≈1 / 2μC ox (W / L)(V GS -V T ) 2

[0053] I dsat is the driving current, C ox is the parasitic capacitance, μ is a constant, W is the effective channel width, L is the effective channel length, V GS is the gate-source voltage difference, V T is the threshold voltage. MOS tube drive current I dsat It is inversely proportional to the effective channel length L and directly proportional to the effective channel width W. Other factors that affect the drive current include: abnormal well ion implantation; abnormal N+ or P+ ion implantation; abnormal dimensions of the active area or polysilicon gate after etching; and abnormal gate oxide thickness.

[0054] The method of increasing the driving current in the prior art is to increase the capacitance of the overlapping area between the source / drain and the gate oxide layer by increasing the overlapping area between the source / drain and the gate oxide layer to increase the driving current. However, since the overlapping area between the source / drain and the gate oxide layer increases, the leakage current increases, affecting the operation of the device.

[0055] Based on this, the present invention discloses a semiconductor structure that increases the driving current by increasing the overlapping area between the source / drain and the gate oxide layer, reduces the gate leakage, and maintains the GIDL unchanged.

[0056] Please refer to Figure 1 The present disclosure provides a semiconductor structure including a substrate 10, a trench 20, a first dielectric layer 30, a first conductive layer 40, a second conductive layer 50, a target spacer 60, and a third conductive layer 70. The substrate 10 includes spaced doped regions 11. The trench 20 is located between the doped regions 11 and has a bottom surface no higher than the bottom surface of the doped region 11. The first dielectric layer 30 covers the sidewalls and bottom surface of the trench 20. The first conductive layer 40 is located on the surface of the first dielectric layer 30 at the bottom of the trench 20 and has a top surface no higher than the bottom surface of the doped region 11. The second conductive layer 50 is located on the top surface of the first conductive layer 40 and has a top surface lower than the top surface of the doped region 11. The target spacer 60 is located on the top surface of the second conductive layer 50 and covers a portion of the side surface of the first dielectric layer 30. The third conductive layer 70 is located on the top surface of the second conductive layer 50, and the top surface of the third conductive layer 70 is higher than the bottom surface of the doped region 11 and lower than the top surface of the target spacer 60.

[0057] As an example, please refer to Figure 1In this embodiment, the first conductive layer 40, the second conductive layer 50, and the third conductive layer 70 may be gate conductive layers, the first dielectric layer 30 and the target sidewall spacer 60 may be gate dielectric layers, and the doped region 11 may be a source and a drain. By providing a target sidewall spacer 60 with a corner within the second conductive layer 50 and the third conductive layer 70 and providing a multi-layer gate conductive layer, the contact area between the gate dielectric layers is increased without increasing the channel length, and the overlap capacitance between the gate dielectric layer and the source / drain is increased, thereby increasing the drive current and improving the read / write speed of the semiconductor structure. In this embodiment, the gate dielectric layer is provided with a multi-layer structure composed of the first dielectric layer 30 and the target sidewall spacer 60, thereby increasing the thickness of the gate dielectric layer, reducing the leakage current and maintaining the GIDL unchanged. Therefore, the reliability of the semiconductor structure is improved while improving the read / write speed.

[0058] In some embodiments, please refer to Figure 2 The target sidewall spacer 60 includes a second dielectric layer 61 and a third dielectric layer 62. The second dielectric layer 61 is located on the top surface of the second conductive layer 50 and covers at least a portion of the side surface of the first dielectric layer 30. The third dielectric layer 62 is located on the top surface of the second conductive layer 50 and between the second dielectric layer 61 and the third conductive layer 70. The gate dielectric layer includes a three-layer structure consisting of the first dielectric layer 30, the second dielectric layer 61, and the third dielectric layer 62. This increases the thickness of the gate dielectric layer, reduces leakage current, and improves the reliability of the semiconductor structure.

[0059] In some embodiments, please refer to Figure 2 The second dielectric layer 61 includes a first portion 611 and a second portion 612. The first portion 611 is located on the top surface of the second conductive layer 50 and covers a portion of the side surface of the first dielectric layer 30, thereby increasing the contact area between the target sidewall 60 and the third conductive layer 70. The second portion 612 is located on the top surface of the second conductive layer 50 and between the first portion 611 and the third conductive layer 70. This adds a corner to the second dielectric layer 61 while ensuring that the channel length is not increased.

[0060] In some embodiments, please refer to Figure 2 The material of the third dielectric layer 62 is the same as that of the first dielectric layer 30 , and different from that of the second dielectric layer 61 .

[0061] As an example, please refer to Figure 2The material of the first dielectric layer 30 includes silicon oxide, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, hafnium zirconium oxide, zirconium oxide, yttrium oxide, and combinations thereof; the material of the second dielectric layer 61 includes silicon nitride, hafnium nitride, hafnium silicon nitride, hafnium aluminum nitride, hafnium zirconium nitride, zirconium nitride, yttrium nitride, and combinations thereof. The first dielectric layer 30, the second dielectric layer 61, and the third dielectric layer 62 may be gate oxide layers. The second dielectric layer 61 may be a nitride layer with tensile stress. The stress accelerates carrier movement, improves carrier mobility, reduces power consumption, increases the current carrying capacity of the semiconductor structure, and increases the switching speed of the semiconductor structure. The first dielectric layer 30, the second dielectric layer 61, and the third dielectric layer 62 together form an oxide-nitride-oxide (ONO) gate oxide layer, which has lower leakage current than a traditional single-layer oxide gate oxide layer.

[0062] In some embodiments, please refer to Figure 2 The top surface of the third dielectric layer 62 has an arc surface to avoid tip discharge.

[0063] In some embodiments, please refer to Figure 2 , the thickness of the second conductive layer 50 is a first preset thickness, which is less than the thickness of the first conductive layer 40 .

[0064] As an example, please refer to Figure 2 The first conductive layer 40 can be a composite gate metal layer, and the second conductive layer 50 can be a composite gate polysilicon layer. The first preset thickness is approximately half of the thickness of the composite gate polysilicon layer in the prior art, so that the top surface of the second conductive layer 50 is lower than the top surface of the doped region 11, increasing the overlapping area between the target sidewall 60 and the doped region 11, increasing the overlapping capacitance between the gate oxide layer and the source / drain, increasing the driving current, and improving the read and write speed of the semiconductor structure.

[0065] In some embodiments, please refer to Figure 2 , the thickness of the third conductive layer 70 is greater than the first preset thickness.

[0066] As an example, please refer to Figure 2The third conductive layer 70 can be a composite gate polysilicon layer. The thickness of the third conductive layer 70 plus the thickness of the second conductive layer 50 is a second preset thickness. The second preset thickness is greater than the thickness of the composite gate polysilicon layer in the prior art. Therefore, the contact area between the gate oxide layer and the third conductive layer 70 is increased, the overlapping area between the source / drain and the gate oxide layer is increased, the overlapping capacitance between the source / drain and the gate oxide layer is increased, the driving current is increased, and the read and write speed of the semiconductor structure is increased. Moreover, since this embodiment adopts an ONO structured gate oxide layer, while increasing the overlapping area between the source / drain and the gate oxide layer, the gate leakage current increased due to the increased overlapping area between the source / drain and the gate oxide layer is reduced, and the GIDL is kept unchanged, thereby improving the read and write speed of the semiconductor structure while improving the reliability of the semiconductor structure.

[0067] In some embodiments, please refer to Figure 2 The material of the first conductive layer 40 is different from the material of the second conductive layer 50 and the material of the third conductive layer 70 .

[0068] As an example, please refer to Figure 2 The material of the first conductive layer 40 includes copper, tungsten, aluminum, copper alloy, titanium, titanium nitride, palladium nitride and combinations thereof; the material of the second conductive layer 50 includes polysilicon; and the material of the third conductive layer 70 can be the same as that of the second conductive layer 50.

[0069] In some embodiments, please refer to Figure 3 The semiconductor structure further includes a capping layer 80 , which fills the gap on the third conductive layer 70 in the trench 20 and covers the exposed top surface of the substrate 10 .

[0070] As an example, please refer to Figure 3 The material of the cap layer 80 includes silicon nitride, hafnium nitride, hafnium silicon nitride, hafnium aluminum nitride, hafnium zirconium nitride, zirconium nitride, yttrium nitride, and combinations thereof. The material of the cap layer 80 can be the same as that of the second dielectric layer 61 .

[0071] Please refer to Figure 1Another aspect of the present disclosure provides a buried wordline structure, comprising a substrate 10, a trench 20, a first dielectric layer 30, a first conductive layer 40, a second conductive layer 50, a target sidewall spacer 60, and a third conductive layer 70. The substrate 10 is provided with spaced doped regions 11; the trench 20 is formed between the doped regions 11 and has a bottom surface no higher than the bottom surface of the doped region 11; the first dielectric layer 30 covers the sidewalls and bottom surface of the trench 20; and the first conductive layer 40 is located at the bottom of the trench 20 and has a top surface no higher than the bottom surface of the doped region 11. The second conductive layer 50 is located on the top surface of the first conductive layer 40 and is lower than the top surface of the doped region 11. The target sidewall 60 is located on the top surface of the second conductive layer 50 and covers part of the side surface of the first dielectric layer 30. The third conductive layer 70 is located on the top surface of the second conductive layer 50, and the top surface of the third conductive layer 70 is higher than the bottom surface of the doped region 11 and lower than the top surface of the target sidewall 60. The first dielectric layer 30, the first conductive layer 40, the second conductive layer 50, the target sidewall 60, and the third conductive layer 70 constitute a word line structure.

[0072] As an example, please refer to Figure 1 In this embodiment, the first conductive layer 40, the second conductive layer 50, and the third conductive layer 70 may be gate conductive layers, the first dielectric layer 30 and the target sidewall spacer 60 may be gate dielectric layers, and the doped region 11 may be a source and a drain. By providing a target sidewall spacer 60 with a corner within the second conductive layer 50 and the third conductive layer 70 and providing a multi-layer gate conductive layer, the contact area between the gate dielectric layer and the gate conductive layer is increased without increasing the channel length, and the overlap capacitance between the gate dielectric layer and the source / drain is increased, thereby increasing the drive current and improving the read and write speed of the buried word line structure. In this embodiment, the gate dielectric layer is provided with a multi-layer structure composed of the first dielectric layer 30 and the target sidewall spacer 60, thereby increasing the thickness of the gate dielectric layer, reducing the leakage current and maintaining the GIDL unchanged. Therefore, the read and write speed of the buried word line structure is improved while improving the reliability of the buried word line structure.

[0073] In some embodiments, please refer to Figure 2 The target spacer 60 includes a second dielectric layer 61 and a third dielectric layer 62. The second dielectric layer 61 is located on the top surface of the second conductive layer 50 and covers at least a portion of the side surface of the first dielectric layer 30. The third dielectric layer 62 is located on the top surface of the second conductive layer 50 and between the second dielectric layer 61 and the third conductive layer 70. The gate dielectric layer includes a three-layer structure consisting of the first dielectric layer 30, the second dielectric layer 61, and the third dielectric layer 62. This increases the thickness of the gate dielectric layer, reduces leakage current, and improves the reliability of the semiconductor structure. The multi-layer gate dielectric layer has lower leakage current than the single-layer gate dielectric layer of the traditional buried wordline structure.

[0074] As an example, please refer to Figure 2The material of the third dielectric layer 62 is the same as that of the first dielectric layer 30, and different from that of the second dielectric layer 61. The materials of the first dielectric layer 30 include silicon oxide, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, hafnium zirconium oxide, zirconium oxide, yttrium oxide, and combinations thereof; the materials of the second dielectric layer 61 include silicon nitride, hafnium nitride, hafnium silicon nitride, hafnium aluminum nitride, hafnium zirconium nitride, zirconium nitride, yttrium nitride, and combinations thereof. The first dielectric layer 30, the second dielectric layer 61, and the third dielectric layer 62 may be gate oxide layers. The second dielectric layer 61 may be a nitride layer with tensile stress. The stress accelerates carrier movement, improves carrier mobility, reduces power consumption, increases the current carrying capacity of the semiconductor structure, and increases the switching speed of the semiconductor structure. The first dielectric layer 30 , the second dielectric layer 61 and the third dielectric layer 62 together form an oxide-nitride-oxide (ONO) gate oxide layer, which has a smaller leakage current than a conventional single-layer oxide gate oxide layer.

[0075] As an example, please refer to Figure 2 The top surface of the third dielectric layer 62 has an arc surface to avoid tip discharge.

[0076] In some embodiments, please refer to Figure 2 , the thickness of the second conductive layer 50 is a first preset thickness, which is less than the thickness of the first conductive layer 40 .

[0077] As an example, please refer to Figure 2 The first conductive layer 40 can be a composite gate metal layer, and the second conductive layer 50 can be a composite gate polysilicon layer. The first preset thickness is approximately half the thickness of the composite gate polysilicon layer in the prior art, so that the top surface of the second conductive layer 50 is lower than the top surface of the doped region 11, increasing the overlapping area between the target sidewall 60 and the doped region 11, increasing the overlapping capacitance between the gate oxide layer and the source / drain, and increasing the driving current, thereby improving the read and write speed of the buried word line structure.

[0078] In some embodiments, please refer to Figure 2 , the thickness of the third conductive layer 70 is greater than the first preset thickness.

[0079] As an example, please refer to Figure 2The third conductive layer 70 can be a composite gate polysilicon layer. The thickness of the third conductive layer 70 plus the thickness of the second conductive layer 50 is a second preset thickness. The second preset thickness is greater than the thickness of the gate conductive layer in the prior art. Therefore, the contact area between the gate oxide layer and the third conductive layer 70 is increased, the overlapping area between the source / drain and the gate oxide layer is increased, the overlapping capacitance between the source / drain and the gate oxide layer is increased, the driving current is increased, and the read and write speed of the semiconductor structure is increased. Moreover, since this embodiment adopts an ONO structured gate oxide layer, while increasing the overlapping area between the source / drain and the gate oxide layer, the gate leakage current increased due to the increase in the overlapping area between the source / drain and the gate oxide layer is reduced, and the GIDL is kept unchanged, thereby improving the read and write speed of the buried word line structure while improving the reliability of the buried word line structure.

[0080] In some embodiments, please refer to Figure 2 The material of the second conductive layer 50 is the same as that of the third conductive layer 70 , and different from that of the first conductive layer 40 .

[0081] As an example, please refer to Figure 2 The material of the first conductive layer 40 includes copper, tungsten, aluminum, copper alloy, titanium, titanium nitride, palladium nitride and combinations thereof; the material of the second conductive layer 50 includes polysilicon; and the material of the third conductive layer 70 can be the same as that of the second conductive layer 50.

[0082] Based on the same invention concept, please refer to Figure 4 The present disclosure also provides a method for fabricating the semiconductor structure described above. The solution to the problem provided by this method is similar to the solution described in the above structure. Therefore, the specific limitations of the following embodiments of the method for fabricating one or more semiconductor structures can be found in the above definitions of the antifuse structure and will not be repeated here. The method comprises:

[0083] Step S102: providing a substrate, wherein spaced doping regions are formed in the substrate;

[0084] Step S104: forming a trench in the substrate between adjacent doped regions, wherein the bottom surface of the trench is not higher than the bottom surface of the doped region;

[0085] Step S106: forming a first dielectric layer on the sidewalls and bottom surface of the trench;

[0086] Step S108: forming a first conductive layer on the surface of the first dielectric layer at the bottom of the trench, wherein the top surface of the first conductive layer is not higher than the bottom surface of the doped region;

[0087] Step S110: forming a second conductive layer on a top surface of the first conductive layer, the top surface of the second conductive layer being lower than a top surface of the doped region;

[0088] Step S112: forming a target sidewall spacer on the top surface of the second conductive layer to cover a portion of the side surface of the first dielectric layer;

[0089] Step S114 : forming a third conductive layer on the top surface of the second conductive layer, wherein the third conductive layer has a top surface higher than the bottom surface of the doped region and lower than the top surface of the target spacer.

[0090] As an example, please refer to Figure 4 In this embodiment, the first conductive layer 40, the second conductive layer 50, and the third conductive layer 70 may be gate conductive layers, the first dielectric layer 30 and the target sidewall spacer 60 may be gate dielectric layers, and the doped region 11 may be a source and a drain. By providing a target sidewall spacer 60 with a corner within the second conductive layer 50 and the third conductive layer 70 and providing a multi-layer gate conductive layer, the contact area between the gate dielectric layers is increased without increasing the channel length, and the overlap capacitance between the gate dielectric layer and the source / drain is increased, thereby increasing the drive current and improving the read / write speed of the semiconductor structure. In this embodiment, the gate dielectric layer is provided with a multi-layer structure composed of the first dielectric layer 30 and the target sidewall spacer 60, thereby increasing the thickness of the gate dielectric layer, reducing the leakage current and maintaining the GIDL unchanged. Therefore, the reliability of the semiconductor structure is improved while improving the read / write speed.

[0091] As an example, see Figure 5 In step 102, the substrate 10 can be made of a semiconductor material, an insulating material, a conductive material, or any combination thereof. The substrate 10 can be a single-layer structure or a multi-layer structure. For example, the substrate 10 can be a silicon (Si) substrate 10, a silicon germanium (SiGe) substrate 10, a silicon germanium carbon (SiGeC) substrate 10, a silicon carbide (SiC) substrate 10, a gallium arsenide (GaAs) substrate 10, an indium arsenide (InAs) substrate 10, an indium phosphide (InP) substrate 10, or other III / V semiconductor substrates 10 or II / VI semiconductor substrates 10. Alternatively, for example, the substrate 10 can be a layered substrate 10 including Si / SiGe, Si / SiC, silicon on insulator (SOI), or silicon germanium on insulator. Therefore, the type of substrate 10 should not limit the scope of protection of the present disclosure. An ion implantation process can be used to form spaced doped regions 11 in the substrate 10, and the doped regions 11 constitute the source and the drain. For example, P-type ions are implanted into the substrate 10 to form a first type doped well region. The P-type ions may include but are not limited to any one or more of boron (B) ions, gallium (Ga) ions, boron fluoride (BF2) ions, and indium (In) ions.

[0092] As an example, see Figure 6In step S104, an etching process may be used to form trenches 20 in the substrate 10 between adjacent doped regions 11. The etching process may include, but is not limited to, a dry etching process and / or a wet etching process. The etching process may include, but is not limited to, a dry etching process and / or a wet etching process. The dry etching process may include, but is not limited to, one or more of reactive ion etching (RIE), inductively coupled plasma etching (ICP), and high concentration plasma etching (HDP).

[0093] As an example, please refer to Figure 6 In step S104, a deposition process may be used to coat a photoresist material layer (not shown) on the top surface of the substrate 10. After a series of steps such as exposure and development, a patterned photoresist layer is formed. The patterned photoresist layer has an opening pattern for defining the groove 20. The photoresist may be a positive photoresist or a negative photoresist, and the development method may be a positive development or a negative development. The deposition process may include, but is not limited to, one or more of a chemical vapor deposition process (CVD), an atomic layer deposition process (ALD), a high density plasma deposition (HDP), a plasma enhanced deposition process, and a spin-on dielectric layer (SOD). An etching process is then used to etch the substrate 10 using the patterned photoresist layer as a mask to obtain a groove 20 whose bottom surface is no higher than the bottom surface of the doped region 11. For example, the groove 20 can be etched using a laser etching process, which uses a high-energy laser beam to irradiate the surface of the substrate 10, causing the substrate 10 to melt or vaporize, forming a groove of a certain depth, thereby achieving the purpose of etching the substrate 10. The use of the laser etching process can improve the yield and stability of the semiconductor structure, and achieve one-time molding of different graphics and angles, without consumables, pollution, and low cost.

[0094] In some embodiments, please refer to Figure 7 Step S106 forms a first dielectric layer 30 on the sidewalls and bottom of the trench 20, including:

[0095] Step S1061 : forming a first dielectric layer 30 on the sidewalls and bottom surface of the trench 20 by using an atomic layer deposition process and an in-situ water vapor generation process.

[0096] As an example, please refer to Figure 7In step 1061, an atomic deposition process is first used to introduce two independent volatile precursors into the sidewalls and bottom of the trench 20 in the form of gas pulses at different time intervals. These precursors undergo chemical adsorption and chemical reaction with the sidewalls and bottom of the trench 20, forming a deposited silicon film. This improves the uniformity and density of the formed silicon film and optimizes the performance of the semiconductor structure. An in-situ water vapor generation process is then used to introduce an initial reaction gas, such as oxygen doped with a small amount of hydrogen. The silicon is heated to 800°C-1100°C using a radiative rapid heating technique. The oxidizing gas required for the reaction is generated by the direct reaction of hydrogen and oxygen on the silicon surface. In this high-temperature atmosphere, a chemical reaction similar to detonation occurs on the silicon surface, generating a large number of oxidizing gas-phase active free radicals. These free radicals include active oxygen atoms, water molecules, and OH groups. These free radicals then participate in the oxidation process of the silicon. Due to the extremely strong oxidizing effect of oxygen atoms, the resulting first dielectric layer 30 has fewer defects and the silicon interface is fully oxidized, effectively improving the electrical properties of the first dielectric layer 30.

[0097] As an example, see Figure 8-Figure 9 In step S108, a first conductive material layer 41 is first deposited at the bottom of the trench 20 using a deposition process. The first conductive material layer 41 fills the interior of the trench 20 and covers the top of the substrate 10. The deposition process may include but is not limited to CVD, ALD, HDP, SOD or a combination thereof. Then, an etch-back process is used to etch the first conductive material layer 41 until the top surface of the first conductive material layer 41 is no higher than the bottom surface of the doped region 11, thereby forming a first conductive layer 40.

[0098] As an example, see Figure 10-11 In step S110, a second conductive material layer 51 is first deposited on the top surface of the first conductive layer 40 using a deposition process. The second conductive material layer 51 fills the inside of the trench 20 and covers the top of the substrate 10. The deposition process may include but is not limited to CVD, ALD, HDP, SOD or a combination thereof. Then, an etch-back process is used to etch the second conductive material layer 51 until the top surface of the second conductive material layer 51 is lower than the top surface of the doped region 11, thereby forming a second conductive layer 50.

[0099] In some embodiments, please refer to Figure 12-14 In step S112, a target sidewall spacer 60 covering a portion of the side surface of the first dielectric layer 30 is formed on the top surface of the second conductive layer 50, including:

[0100] Step S1121: After forming the second conductive layer 50 , forming a second dielectric material layer 161 , the second dielectric material layer 161 covering the top surface of the second conductive layer 50 , part of the side surface of the first dielectric layer 30 , and the exposed top surface of the substrate 10 ;

[0101] Step S1122 : forming a third dielectric material layer 162 , where the third dielectric material layer 162 covers the exposed surface of the second dielectric material layer 161 ;

[0102] Step S1123 : etching back the third dielectric material layer 162 and the second dielectric material layer 161 covering the top surface of the substrate 10 and the top surface of the second conductive layer 50 . The remaining third dielectric material layer 162 and the remaining second dielectric material layer 161 constitute the target spacer 60 .

[0103] As an example, please refer to Figure 12-14 In step S112, a deposition process may be used to form the second dielectric material layer 161 and the third dielectric material layer 162. The deposition process may include, but is not limited to, CVD, ALD, HDP, SOD, or a combination thereof. An etching process is then used to remove the third dielectric material layer 162 and the second dielectric material layer 161 covering the top surface of the substrate 10 and the top surface of the second conductive layer 50, thereby forming the second dielectric layer 61 and the third dielectric layer 62. In step S1123, a polishing process may also be used to round the top surface of the third dielectric layer 62 to prevent tip discharge.

[0104] As an example, please refer to Figure 12-14 The second dielectric layer 61 includes a first portion 611 and a second portion 612. The first portion 611 is located on the top surface of the second conductive layer 50 and covers a portion of the side surface of the first dielectric layer 30, thereby increasing the contact area between the target sidewall 60 and the third conductive layer 70. The second portion 612 is located on the top surface of the second conductive layer 50 and between the first portion 611 and the third conductive layer 70. This adds a corner to the second dielectric layer 61 while ensuring that the channel length is not increased.

[0105] In some embodiments, please refer to Figure 12-14 The material of the third dielectric material layer 162 is the same as that of the first dielectric layer 30 , and different from that of the second dielectric material layer 161 .

[0106] As an example, please refer to Figure 12-14The material of the first dielectric layer 30 includes silicon oxide, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, hafnium zirconium oxide, zirconium oxide, yttrium oxide, and combinations thereof; the material of the second dielectric layer 61 includes silicon nitride, hafnium nitride, hafnium silicon nitride, hafnium aluminum nitride, hafnium zirconium nitride, zirconium nitride, yttrium nitride, and combinations thereof. The first dielectric layer 30, the second dielectric layer 61, and the third dielectric layer 62 may be gate oxide layers. The second dielectric layer 61 may be a nitride layer with tensile stress. The stress accelerates carrier movement, improves carrier mobility, reduces power consumption, increases the current carrying capacity of the semiconductor structure, and increases the switching speed of the semiconductor structure. The first dielectric layer 30, the second dielectric layer 61, and the third dielectric layer 62 together form an oxide-nitride-oxide (ONO) gate oxide layer, which has lower leakage current than a traditional single-layer oxide gate oxide layer.

[0107] As an example, see Figure 15 and Figure 2 In step S114, a deposition process is first used to deposit a third conductive material layer 71 on the top surface of the second conductive layer 50. The third conductive material layer 71 fills the inside of the trench 20 and covers the top of the substrate 10. The deposition process may include but is not limited to CVD, ALD, HDP, SOD or a combination thereof. Then, an etch-back process is used to etch the third conductive material layer 71 to the top surface of the second conductive layer 50, forming a third conductive layer 70 whose top surface is higher than the bottom surface of the doped region 11 and lower than the top surface of the target sidewall 60.

[0108] As an example, see Figure 2 The material of the second conductive layer 50 is the same as that of the third conductive layer 70, and different from that of the first conductive layer 40. The material of the first conductive layer 40 includes copper, tungsten, aluminum, copper alloy, titanium, titanium nitride, palladium nitride, and combinations thereof; the material of the second conductive layer 50 includes polysilicon; and the material of the third conductive layer 70 can be the same as that of the second conductive layer 50.

[0109] In some embodiments, please refer to Figure 2 , the thickness of the second conductive layer 50 is a first preset thickness, which is less than the thickness of the first conductive layer 40 ; and / or the thickness of the third conductive layer 70 is greater than the first preset thickness.

[0110] As an example, please refer to Figure 2The first conductive layer 40 may be a composite gate metal layer, and the second conductive layer 50 may be a composite gate polysilicon layer. The first preset thickness is approximately half the thickness of the composite gate polysilicon layer in the prior art. The third conductive layer 70 may be a composite gate polysilicon layer. The thickness of the third conductive layer 70 plus the thickness of the second conductive layer 50 is a second preset thickness. The second preset thickness is greater than the thickness of the gate conductive layer in the prior art. Therefore, the contact area between the gate oxide layer and the third conductive layer 70 is increased, the overlapping area between the source / drain and the gate oxide layer is increased, the overlapping capacitance between the source / drain and the gate oxide layer is increased, the drive current is increased, and the read / write speed of the semiconductor structure is improved. Moreover, since this embodiment uses an ONO structured gate oxide layer, while increasing the overlapping area between the source / drain and the gate oxide layer, the gate leakage current increased due to the increased overlapping area between the source / drain and the gate oxide layer is reduced, and the GIDL is kept unchanged, thereby improving the read / write speed of the semiconductor structure while improving the reliability of the semiconductor structure.

[0111] In some embodiments, please refer to Figure 3 After forming a third conductive layer 70 on the top surface of the second conductive layer 50 in step S114, the top surface of the third conductive layer 70 is higher than the bottom surface of the doped region 11 and lower than the top surface of the target sidewall spacer 60 , the method further includes:

[0112] Step S115 : forming a capping layer 80 to fill the gap on the third conductive layer 70 in the trench 20 and cover the exposed top surface of the substrate 10 .

[0113] As an example, please refer to Figure 3 In step 115, a deposition process may be used to form a cap layer 80 that fills the gap above the third conductive layer 70 in the trench 20 and covers the exposed top surface of the substrate 10. The deposition process may include, but is not limited to, CVD, ALD, HDP, SOD, or a combination thereof. The material of the cap layer 80 includes silicon nitride, hafnium nitride, hafnium silicon nitride, hafnium aluminum nitride, hafnium zirconium nitride, zirconium nitride, yttrium nitride, and a combination thereof. The material of the cap layer 80 may be the same as the material of the second dielectric layer 61.

[0114] It should be understood that although Figure 4 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, although Figure 4At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The order of execution of these steps or stages is not necessarily one by one, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0115] As an example, Figure 16 : This is a comparison diagram of the technical effects of the buried word line structure of this embodiment and the traditional buried word line structure. The thickness of the composite gate polysilicon layer of the buried word line structure of this embodiment is increased by a preset thickness compared to the thickness of the composite gate polysilicon layer of the traditional buried word line structure. The preset thickness can be 4nm-6nm. For example, the preset thickness is 4nm, 4.5nm, 5nm, 5.5nm or 6nm, etc. PH corresponds to the technical effect of the thickness of the traditional composite gate polysilicon layer, H corresponds to the technical effect of the thickness of the composite gate polysilicon layer in this embodiment, and PHM corresponds to the average of the technical effects of the thickness of the traditional composite gate polysilicon layer. Figure 16 (a) and Figure 16 (b) It can be seen that the overlap capacitance of the bit line and the overlap capacitance of the metal contact layer of this embodiment are both increased compared with the prior art. Figure 16 (c) It can be seen that the GIDL of this embodiment is basically unchanged compared to the GIDL in the prior art. Figure 16 (d) and Figure 16 (e) It can be seen that the leakage current from the bit line to the word line and the leakage current from the metal contact layer to the word line in this embodiment are both lower than those in the prior art. From the above experimental data, it can be seen that this embodiment achieves the purpose of increasing the overlap capacitance between the gate dielectric layer and the source / drain and reducing the leakage current while maintaining GIDL unchanged by increasing the thickness of the composite gate polysilicon layer and the gate oxide layer of the ONO structure. Therefore, this embodiment improves the read and write speed of the semiconductor structure while improving the reliability of the semiconductor structure.

[0116] Please note that the above embodiments are for illustrative purposes only and are not intended to limit the present disclosure.

[0117] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0118] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0119] The above embodiments merely illustrate several implementations of the present disclosure, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the disclosed patent. It should be noted that a person of ordinary skill in the art would be able to make numerous variations and improvements without departing from the scope of the present disclosure, all of which fall within the scope of protection of the present disclosure. Therefore, the scope of protection of the disclosed patent shall be determined by the appended claims.

Claims

1. A semiconductor structure, characterized in that include: A substrate, wherein the substrate includes doped regions distributed at intervals; a trench, located between the doped regions and having a bottom surface no higher than a bottom surface of the doped regions; a first dielectric layer covering the sidewalls and bottom surface of the trench; a first conductive layer, located on the surface of the first dielectric layer at the bottom of the trench and with a top surface no higher than a bottom surface of the doped region; a second conductive layer, located on a top surface of the first conductive layer and having a top surface lower than a top surface of the doped region; a target sidewall spacer, located on a top surface of the second conductive layer and covering a portion of a side surface of the first dielectric layer; a third conductive layer, located on a top surface of the second conductive layer, wherein the top surface of the third conductive layer is higher than the bottom surface of the doped region and lower than the top surface of the target sidewall spacer; The thickness of the second conductive layer is a first preset thickness, and the first preset thickness is smaller than the thickness of the first conductive layer.

2. The semiconductor structure according to claim 1, wherein: The target side wall comprises: a second dielectric layer, located on a top surface of the second conductive layer and covering at least a portion of a side surface of the first dielectric layer; and The third dielectric layer is located on the top surface of the second conductive layer and between the second dielectric layer and the third conductive layer.

3. The semiconductor structure according to claim 2, wherein: The second dielectric layer includes: a first portion, located on a top surface of the second conductive layer and covering a portion of a side surface of the first dielectric layer; The second portion is located on the top surface of the second conductive layer and between the first portion and the third conductive layer.

4. The semiconductor structure according to claim 1, wherein: The thickness of the third conductive layer is greater than the first preset thickness.

5. A buried word line structure, characterized in that: include: a substrate having spaced doping regions formed therein; a trench formed between the doped regions and having a bottom surface no higher than a bottom surface of the doped region; a first dielectric layer covering the sidewalls and bottom surface of the trench; a first conductive layer, located at the bottom of the trench and with a top surface no higher than a bottom surface of the doped region; a second conductive layer, located on a top surface of the first conductive layer and having a top surface lower than a top surface of the doped region; a target sidewall spacer, located on a top surface of the second conductive layer and covering a portion of a side surface of the first dielectric layer; a third conductive layer, located on a top surface of the second conductive layer, wherein the top surface of the third conductive layer is higher than the bottom surface of the doped region and lower than the top surface of the target sidewall spacer; Wherein, the first dielectric layer, the first conductive layer, the second conductive layer, the target spacer, and the third conductive layer constitute the word line structure; The thickness of the second conductive layer is a first preset thickness, and the first preset thickness is smaller than the thickness of the first conductive layer.

6. The buried word line structure according to claim 5, wherein: The target side wall comprises: a second dielectric layer, located on a top surface of the second conductive layer and covering at least a portion of a side surface of the first dielectric layer; and The third dielectric layer is located on the top surface of the second conductive layer and between the second dielectric layer and the third conductive layer.

7. The buried word line structure according to claim 5, wherein: The thickness of the third conductive layer is greater than the first preset thickness.

8. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, wherein spaced doping regions are formed in the substrate; forming a trench in the substrate between adjacent doped regions, wherein the bottom surface of the trench is no higher than the bottom surface of the doped region; forming a first dielectric layer on the sidewalls and bottom surface of the trench; forming a first conductive layer on the surface of the first dielectric layer at the bottom of the trench, wherein the top surface of the first conductive layer is not higher than the bottom surface of the doped region; forming a second conductive layer on the top surface of the first conductive layer, the top surface of which is not higher than the bottom surface of the doped region; forming a second conductive layer on a top surface of the first conductive layer, the top surface of which is lower than the top surface of the doped region; forming a target sidewall spacer on the top surface of the second conductive layer and covering a portion of the side surface of the first dielectric layer; forming a third conductive layer on the top surface of the second conductive layer, the top surface of which is higher than the bottom surface of the doped region and lower than the top surface of the target sidewall spacer; The thickness of the second conductive layer is a first predetermined thickness, and the first predetermined thickness is less than the thickness of the first conductive layer; and / or The thickness of the third conductive layer is greater than the first preset thickness.

9. The preparation method according to claim 8, characterized in that The step of forming a target sidewall on the top surface of the second conductive layer and covering a portion of the side surface of the first dielectric layer includes: After forming the second conductive layer, forming a second dielectric material layer, wherein the second dielectric material layer covers the top surface of the second conductive layer, part of the side surface of the first dielectric layer and the exposed top surface of the substrate; forming a third dielectric material layer, wherein the third dielectric material layer covers the exposed surface of the second dielectric material layer; The third dielectric material layer and the second dielectric material layer covering the top surface of the substrate and the top surface of the second conductive layer are etched back, and the remaining third dielectric material layer and the remaining second dielectric material layer constitute the target sidewall spacer.

10. The preparation method according to claim 8 or 9, characterized in that: After forming a third conductive layer on the top surface of the second conductive layer, the third conductive layer having a top surface higher than the bottom surface of the doped region and lower than the top surface of the target sidewall spacer, the method further includes: A capping layer is formed to fill the gap on the third conductive layer in the trench and cover the exposed top surface of the substrate.

Images