Semiconductor structure preparation method and semiconductor structure

Abstract

The present disclosure relates to a method for preparing a semiconductor structure and a semiconductor structure. The method for preparing a semiconductor structure includes: providing a substrate; forming a plurality of bit line structures on the upper surface of the substrate, the bit line structure including a bit line stack structure and an isolation sidewall located on the sidewall of the bit line stack structure, the isolation sidewall having a first air gap; forming a storage node contact structure material layer between adjacent bit line structures; etching the storage node contact structure material layer to obtain a storage node contact structure and a first gap groove, the first gap groove being located between the bit line structure and the storage node contact structure; forming a first isolation layer in the first gap groove, the first isolation layer having a second air gap. Due to the presence of the first air gap and the second air gap, the capacitance between the storage node contact structure and the bit line structure can be reduced, thereby reducing the capacitance of the bit line structure as a whole, thereby improving the sensing margin of the chip.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure and a semiconductor structure. Background Art

[0002] With the development of dynamic random access memory (DRAM), the size of its bit lines (BL) and word lines (WL) has been designed to be smaller and smaller, resulting in an increasing bit line capacitance (C_BL). For example, the reduction in bit line size may cause the capacitance between the BL and the node contact (NC) (C_BL / NC) to increase. Typically, C_BL / NC contributes approximately 40% to the capacitance of C_BL. Therefore, as C_BL / NC increases, the overall C_BL capacitance also increases. Excessive bit line capacitance can reduce the chip's sensing margin. Summary of the Invention

[0003] Based on this, it is necessary to provide a method for manufacturing a semiconductor structure and a semiconductor structure to address the problem of reduced sensing margin of the above-mentioned chip.

[0004] To achieve the above objectives, the present disclosure provides, in one aspect, a method for preparing a semiconductor structure, comprising:

[0005] providing a substrate;

[0006] forming a plurality of bit line structures on the upper surface of the substrate, wherein the bit line structures include a bit line stack structure and an isolation spacer located on a sidewall of the bit line stack structure, wherein a first air gap is formed in the isolation spacer;

[0007] forming a storage node contact structure material layer between adjacent bit line structures;

[0008] Etching the storage node contact structure material layer to obtain a storage node contact structure and a first gap trench, wherein the first gap trench is located between the bit line structure and the storage node contact structure;

[0009] A first isolation layer is formed in the first gap groove, wherein the first isolation layer has a second air gap.

[0010] The method for fabricating the semiconductor structure comprises forming a plurality of bitline structures on the upper surface of the substrate, the bitline structures comprising a bitline stack structure and isolation sidewalls located on the sidewalls of the bitline stack structure, the isolation sidewalls having a first air gap therein, forming a storage node contact structure material layer between adjacent bitline structures, etching the storage node contact structure material layer to obtain a storage node contact structure and a first gap trench located between the bitline structure and the storage node contact structure, and forming a first isolation layer within the first gap trench, the first isolation layer having a second air gap therein. The presence of the first and second air gaps reduces the capacitance between the storage node contact structure and the bitline structure, thereby reducing the overall capacitance of the bitline structure and improving the sensing margin of the chip.

[0011] In one embodiment, providing a substrate comprises:

[0012] providing a substrate;

[0013] forming a shallow trench isolation structure in the substrate, wherein the shallow trench isolation structure isolates a plurality of active areas arranged in an array at intervals in the substrate;

[0014] forming a first dielectric layer on the upper surface of the substrate;

[0015] A plurality of bit line contact holes are formed in the base and the first dielectric layer to form the substrate.

[0016] In one embodiment, a plurality of bit line structures are formed on the upper surface of the substrate, including:

[0017] filling the bit line contact hole with a bit line contact structure material layer, and forming an initial bit line stack on the bit line contact structure material layer;

[0018] Patterning the initial bit line stack, the bit line contact structure material layer, and the first dielectric layer to form a bit line stack structure, a bit line contact structure, and second gap grooves located on both sides of the bit line contact structure, wherein the top of the bit line contact structure contacts the bottom of the bit line stack structure, and the bit line contact structure contacts the active area below the bit line contact hole;

[0019] A second isolation structure is formed in the second gap groove, a second dielectric layer is formed on the surface of the second isolation structure and the surface of the substrate, and isolation sidewalls are formed on the sidewalls of the bit line stack structure.

[0020] In one embodiment, after forming a plurality of bit line structures on the upper surface of the substrate and before forming a storage node contact structure material layer between adjacent bit line structures, the method further includes:

[0021] The second dielectric layer and the substrate are etched to form a contact hole, wherein the contact hole exposes a portion of the active area; the storage node contact structure material layer also fills the contact hole.

[0022] In one embodiment, the bit line stack structure includes a conductive layer and a passivation layer; and forming an initial bit line stack on the bit line contact structure material layer includes:

[0023] forming a conductive material layer on the upper surface of the bit line contact structure material layer;

[0024] forming a passivation material layer on the upper surface of the conductive material layer;

[0025] The patterning of the initial bit line stack comprises:

[0026] The passivation material layer and the conductive material layer are etched to obtain a plurality of the bit line stack structures arranged at intervals, the remaining passivation material layer serves as a passivation layer, and the remaining conductive material layer serves as a conductive layer.

[0027] In one embodiment, forming an isolation spacer on a sidewall of the bit line stack structure includes:

[0028] forming a first spacer on a sidewall of the bit line stack structure;

[0029] forming a first sacrificial layer on a surface of the first sidewall;

[0030] forming a second sidewall spacer on a surface of the first sidewall spacer and a surface of the first sacrificial layer;

[0031] The first sacrificial layer is removed to form the first air gap, and the first sidewall spacer, the first air gap, and the second sidewall spacer constitute the isolation sidewall spacer.

[0032] In one embodiment, forming a first isolation layer in the first gap groove, wherein the first isolation layer has a second air gap, includes:

[0033] The first isolation layer is formed in the first gap groove by using a deposition process, and the second air gap is formed in the first isolation layer.

[0034] In one embodiment, forming a first isolation layer in the first gap groove, wherein the first isolation layer has a second air gap, includes:

[0035] forming a first sub-isolation layer on the sidewalls and bottom of the first gap groove;

[0036] forming a second sacrificial layer on a surface of the first sub-isolating layer;

[0037] forming a second sub-isolation layer on a surface of the second sacrificial layer, wherein the first sub-isolation layer, the second sacrificial layer, and the second sub-isolation layer together fill the first gap groove;

[0038] removing the second sacrificial layer to form a sacrificial gap;

[0039] A third sub-isolating layer is formed, wherein the third sub-isolating layer fills a portion of the sacrificial gap to form the second air gap.

[0040] In another aspect, the present disclosure further provides a semiconductor structure, comprising:

[0041] substrate;

[0042] A plurality of bit line structures are located on the upper surface of the substrate, wherein the bit line structures include a bit line stack structure and an isolation spacer located on a sidewall of the bit line stack structure, wherein a first air gap is formed in the isolation spacer;

[0043] a storage node contact structure located between the bit line structures;

[0044] The first isolation layer is located between the bit line structure and the storage node contact structure, and a second air gap is defined in the first isolation layer.

[0045] The semiconductor structure comprises a substrate, a plurality of bitline structures, a storage node contact structure, and a first isolation layer. The plurality of bitline structures are located on the upper surface of the substrate, the bitline structure comprising a bitline stack structure and an isolation sidewall located on the sidewalls of the bitline stack structure, the isolation sidewall comprising a first air gap. A storage node contact structure is located between the bitline structures. A first isolation layer is located between the bitline structure and the storage node contact structure, the first isolation layer comprising a second air gap. The presence of the first and second air gaps reduces the capacitance between the storage node contact structure and the bitline structure, thereby reducing the overall capacitance of the bitline structure and improving the chip's sensing margin.

[0046] In one embodiment, the substrate comprises:

[0047] A substrate having a shallow trench isolation structure therein, wherein the shallow trench isolation structure isolates a plurality of active areas arranged at intervals within the substrate;

[0048] a plurality of spaced-apart bit line contact holes located in the substrate;

[0049] a second isolation trench located in the bit line contact hole;

[0050] a dielectric layer, located on the upper surface of the substrate;

[0051] The semiconductor structure also includes a plurality of bit line contact structures located in the bit line contact holes, which are arranged in a one-to-one correspondence with the bit line contact holes. The bit line contact structures penetrate the dielectric layer and the second isolation layer along the thickness direction. The top of the bit line contact structure contacts the bottom of the bit line stack structure, and the bit line contact structure contacts the active area below the bit line contact hole.

[0052] In one embodiment, the storage node contact structure further penetrates the dielectric layer along the thickness direction and extends into the substrate to contact the active area.

[0053] In one embodiment, the bit line stack structure includes a conductive layer and a passivation layer, and the storage node contact structure includes:

[0054] a contact structure located between conductive layers of adjacent bit line structures;

[0055] The contact pad is located between the upper surface of the contact structure and the passivation layer of the bit line structure and partially covers the top of the passivation layer.

[0056] In one embodiment, the first isolation layer is located between the contact pad and the bit line structure.

[0057] In one embodiment, a plurality of the bit line structures are arranged at intervals along a first direction and extend along a second direction, and a plurality of the storage node contact structures are arranged in an array along the first direction and the second direction; in two rows of the storage node contact structures arranged adjacent to each other along the second direction, a second air gap exists between one row of the storage node contact structures and the bit line structure adjacent to the first side of the first direction, and a second air gap exists between the other row of the storage node contact structures and the bit line structure adjacent to the second side of the first direction.

[0058] In one embodiment, in each of the first isolation layers, the number of the second air gaps is one or more. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the following briefly introduces the drawings required for use in the embodiments or the description of the traditional technology. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0060] Figure 1 A schematic flow chart of a method for preparing a semiconductor structure provided in one embodiment of the present disclosure;

[0061] Figure 2 A schematic flow chart of the step of providing a substrate in a method for preparing a semiconductor structure provided in one embodiment of the present disclosure;

[0062] Figure 3 A schematic diagram of a cross-sectional structure of a substrate provided in some embodiments of the present disclosure;

[0063] Figure 4 In some embodiments of the present disclosure, Figure 3 A schematic cross-sectional view of a shallow trench isolation structure formed in a substrate is shown;

[0064] Figure 5 In some embodiments of the present disclosure, Figure 4 A schematic cross-sectional structural diagram of a first dielectric layer formed on the structure shown;

[0065] Figure 6 In some embodiments of the present disclosure, Figure 5 A schematic cross-sectional view of a structure in which a plurality of bit line contact holes are formed;

[0066] Figure 7 A schematic flow chart of the steps of forming a plurality of bit line structures in a method for preparing a semiconductor structure provided in one embodiment of the present disclosure;

[0067] Figure 8 In some embodiments of the present disclosure, Figure 6 A schematic cross-sectional structure diagram of a bit line contact structure material layer formed in a bit line contact hole is shown;

[0068] Figure 9 A schematic flow chart of a step of forming an initial bit line stack in a method for preparing a semiconductor structure provided in one embodiment of the present disclosure;

[0069] Figure 10 In some embodiments of the present disclosure, Figure 8 A schematic cross-sectional view of a conductive material layer formed on the structure shown;

[0070] Figure 11 In some embodiments of the present disclosure, Figure 10 A schematic cross-sectional view of a passivation material layer formed on the structure shown;

[0071] Figure 12 The etching process provided in some embodiments of the present disclosure Figure 11 The structure shown is a schematic cross-sectional view of a bit line stack structure and a second gap groove;

[0072] Figure 13 Schematic diagram of a top view of a structure in which a second isolation structure, a second dielectric layer, and an isolation sidewall are formed in some embodiments of the present disclosure;

[0073] Figure 14 for Figure 13 Schematic diagram of the cross-sectional structure of the structure along the A-A' direction;

[0074] Figure 15 A schematic flow chart of a step of forming an isolation spacer in a method for preparing a semiconductor structure provided in one embodiment of the present disclosure;

[0075] Figure 16 In some embodiments of the present disclosure, Figure 12 A schematic cross-sectional structural diagram of a structure in which the sidewalls of the bit line stack structure in the structure shown form first spacers;

[0076] Figure 17 In some embodiments of the present disclosure, Figure 16 A schematic cross-sectional view of the structure in which the first sacrificial layer is formed;

[0077] Figure 18 In some embodiments of the present disclosure, Figure 17 A schematic cross-sectional view of the structure in which the second sidewall is formed;

[0078] Figure 19 In some embodiments of the present disclosure, Figure 18 A schematic diagram of the cross-sectional structure of the structure shown after the first sacrificial layer is removed;

[0079] Figure 20 In some embodiments of the present disclosure, Figure 19 A schematic cross-sectional view of a contact hole formed in the structure shown;

[0080] Figure 21 In some embodiments of the present disclosure, Figure 20 A schematic diagram of a cross-sectional structure of a material layer forming a storage node contact structure in the structure shown;

[0081] Figure 22 In some embodiments of the present disclosure, Figure 21 A schematic cross-sectional view of the structure in which the first gap groove is formed is shown;

[0082] Figure 23 Schematic diagram of a top view of a structure in which a first isolation layer and a second air gap are formed in some embodiments of the present disclosure;

[0083] Figure 24 for Figure 23 Schematic diagram of the cross-sectional structure of the structure along the A-A' direction;

[0084] Figure 25A schematic top view of a structure in which a first isolation layer and a second air gap are formed by a deposition process in some other embodiments of the present disclosure;

[0085] Figure 26 for Figure 25 Schematic diagram of the cross-sectional structure of the structure along the A-A' direction;

[0086] Figure 27 A schematic flow chart of steps of forming a first isolation layer and a second air gap in a method for preparing a semiconductor structure provided in one embodiment of the present disclosure;

[0087] Figure 28 In some embodiments of the present disclosure, Figure 20 A schematic cross-sectional view of the structure in which the first sub-isolating layer is formed is shown;

[0088] Figure 29 In some embodiments of the present disclosure, Figure 26 A schematic cross-sectional view of the structure in which a second sacrificial layer is formed;

[0089] Figure 30 In some embodiments of the present disclosure, Figure 27 A schematic cross-sectional view of the structure in which the second sub-isolating layer is formed;

[0090] Figure 31 In some embodiments of the present disclosure, Figure 28 A schematic cross-sectional view of the structure in which the second sacrificial layer is removed to form a sacrificial gap;

[0091] Figure 32 In some embodiments of the present disclosure, Figure 29 The cross-sectional structural diagram of the structure shown is a schematic diagram of a third sub-isolation layer formed in the structure to fill part of the sacrificial gap to form a second air gap.

[0092] Description of the accompanying drawings: 10-substrate, 101-active area, 102-shallow trench isolation structure, 103-second gap groove, 104-second isolation structure, 20-dielectric layer, 201-first dielectric layer, 2011-bit line contact hole, 202-second dielectric layer, 203-contact hole, 30-bit line structure, 301-bit line contact structure, 301a-bit line contact structure material layer, 302-bit line stack structure, 302a-initial bit line stack, 3021-conductive layer, 3021a-conductive material layer, 302 2-passivation layer, 3022a-passivation material layer, 303-isolation sidewall, 3031-first sidewall, 3032-first sacrificial layer, 3033-second sidewall, 3034-first air gap, 50-storage node contact structure, 501-storage node contact structure material layer, 60-first isolation layer, 601-first gap groove, 602-second air gap, 602a-sacrificial gap, 603-first sub-isolation layer, 604-second sacrificial layer, 605-second sub-isolation layer, 606-third sub-isolation layer. DETAILED DESCRIPTION

[0093] To facilitate understanding of the present disclosure, a more comprehensive description of the present disclosure will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present disclosure. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0094] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0095] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0096] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0097] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0098] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Accordingly, embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Accordingly, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the present disclosure.

[0099] like Figure 1 As shown, the present disclosure provides a method for preparing a semiconductor structure, which may include the following steps:

[0100] S101: providing a substrate;

[0101] S102: forming a plurality of bit line structures on the upper surface of the substrate, the bit line structures comprising a bit line stack structure and an isolation spacer located on a sidewall of the bit line stack structure, wherein a first air gap is formed in the isolation spacer;

[0102] S103: forming a storage node contact structure material layer between adjacent bit line structures 30;

[0103] S104: etching the storage node contact structure material layer to obtain a storage node contact structure and a first gap trench, wherein the first gap trench is located between the bit line structure and the storage node contact structure;

[0104] S105: forming a first isolation layer in the first gap groove, wherein the first isolation layer has a second air gap.

[0105] The method for fabricating the semiconductor structure comprises forming a plurality of bitline structures on the upper surface of a substrate. The bitline structures include a bitline stack structure and isolation sidewalls located on the sidewalls of the bitline stack structure, with a first air gap defined within the isolation sidewalls. A storage node contact structure material layer is formed between adjacent bitline structures. The storage node contact structure material layer is etched to obtain a storage node contact structure and a first gap trench, the first gap trench being located between the bitline structure and the storage node contact structure. A first isolation layer is formed within the first gap trench, with a second air gap defined within the first isolation layer. The presence of the first and second air gaps reduces the capacitance between the storage node contact structure and the bitline structure, as well as the capacitance between adjacent storage node contact structures 50. This reduces the overall capacitance of the bitline structure, thereby improving the sensing margin of the chip and enhancing data transmission efficiency.

[0106] In step S101, refer to Figure 1 Step S101 in Figure 2-Figure 6 , providing a substrate.

[0107] In one embodiment, Figure 2 As shown, the above step S101 includes:

[0108] S1011: providing a substrate;

[0109] S1012: forming a shallow trench isolation structure in the substrate, wherein the shallow trench isolation structure isolates a plurality of active areas arranged in an array at intervals in the substrate;

[0110] S1013: forming a first dielectric layer on the upper surface of the substrate;

[0111] S1014: forming a plurality of bit line contact holes in the base and the first dielectric layer to form a substrate.

[0112] In step S1011, Figure 3 As shown, a substrate 10 is provided.

[0113] The material of the substrate 10 may be any suitable substrate material known in the art, for example, at least one of the following materials: silicon (Si), germanium (Ge), red phosphorus, silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI), or double-side polished silicon wafers (DSP), or ceramic substrates such as alumina, quartz or glass substrates, etc., which are not limited in this embodiment.

[0114] In step S1011, Figure 4 As shown, a shallow trench isolation structure 102 can be formed in the substrate 10 by combining processes such as photolithography, etching, and deposition. The shallow trench isolation structure 102 isolates a plurality of active areas 101 arranged in an array of intervals within the substrate 10. The processes for forming the shallow trench isolation structure 102 and the active area 101 are relatively common and will not be described in detail here.

[0115] Among them, the dielectric material filled in the shallow trench isolation (STI) structure can be any suitable dielectric material known in the art, for example, it can be a combination of one or more of silicon dioxide, fluorosilicate glass, undoped silicate glass (USG) or tetraethyl orthosilicate, and this embodiment is not limited here.

[0116] In step S1011, Figure 5 As shown, a first dielectric layer 201 can be formed on the upper surface of the substrate 10 by a deposition process, such as an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, etc., which is not limited in this embodiment.

[0117] The material of the first dielectric layer 201 may include at least one of silicon oxide, silicon oxynitride, silicon oxycarbide and silicon oxynitride and carbon oxynitride.

[0118] In step S1011, Figure 6 As shown, a plurality of bit line contact holes 2011 may be formed in the substrate 10 and the first dielectric layer 201 by combining processes such as photolithography and etching to form a substrate.

[0119] In step S102, refer to Figure 1 Step S101 in Figure 7-Figure 19 A plurality of bit line structures 30 are formed on the upper surface of the substrate. The bit line structure 30 includes a bit line stack structure 302 and an isolation spacer 303 located on the sidewall of the bit line stack structure 302 . The isolation spacer 303 has a first air gap 3034 therein.

[0120] In one embodiment, Figure 7 As shown, the above step S102 includes:

[0121] S1021: filling the bit line contact hole with a bit line contact structure material layer, and forming an initial bit line stack on the bit line contact structure material layer;

[0122] S1022: Patterning the initial bit line stack, the bit line contact structure material layer, and the first dielectric layer to form a bit line stack structure, a bit line contact structure, and second gaps located on both sides of the bit line contact structure, wherein the top of the bit line contact structure contacts the bottom of the bit line stack structure, and the bit line contact structure contacts the active area below the bit line contact hole;

[0123] S1023: forming a second isolation structure in the second gap trench, forming a second dielectric layer on a surface of the second isolation structure and a surface of the substrate, and forming isolation sidewalls on sidewalls of the bit line stack structure.

[0124] In step S1021, if Figure 8 As shown, a deposition process can be used to fill the bit line contact hole 2011 with a bit line contact structure material layer 301a. During the deposition process, part of the bit line contact structure material layer 301a will also cover the surface of the first dielectric layer 201. The material of the bit line contact structure material layer 301a can include polysilicon.

[0125] In one embodiment, the bit line stack structure includes a conductive layer and a passivation layer, such as Figure 9 As shown, the step of forming an initial bit line stack on the bit line contact structure material layer in the above step S1021 includes:

[0126] S1021a: forming a conductive material layer on an upper surface of the bit line contact structure material layer;

[0127] S1021b: forming a passivation material layer on the upper surface of the conductive material layer.

[0128] In step S1021a, if Figure 10 As shown, a deposition process can be used to form a conductive material layer 3021a on the upper surface of the bit line contact structure material layer 301a. The material of the conductive material layer 3021a may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or other metals.

[0129] In step S1021a, if Figure 11 As shown, a passivation material layer 3022a is formed on the upper surface of the conductive material layer 3021a. The material of the passivation material layer 3022a may include nitride, for example, silicon nitride (SiN).

[0130] In step S1022, if Figure 12 As shown, the initial bit line stack 302a, the bit line contact structure material layer 301a and the first dielectric layer 201 are patterned to form a bit line stack structure 302, a bit line contact structure 301 and second gap grooves 103 located on both sides of the bit line contact structure 301. The top of the bit line contact structure 301 contacts the bottom of the bit line stack structure 302, and the bit line contact structure 301 contacts the active area 101 below the bit line contact hole 2011.

[0131] The material of the second isolation structure 104 may include nitride, for example, silicon nitride (SiN). The material of the second dielectric layer 202 may include at least one of silicon oxide, silicon oxynitride, silicon oxycarbide, and silicon oxynitride and carbon oxynitride.

[0132] The step of patterning the initial bit line stack in step S1022 includes etching the passivation material layer and the conductive material layer to obtain a plurality of spaced-apart bit line stack structures.

[0133] like Figure 11-12 As shown, the passivation material layer 3022 a and the conductive material layer 3021 a are etched to obtain a plurality of spaced-apart bit line stack structures 302 , wherein the remaining passivation material layer 3022 a serves as the passivation layer 3022 , and the remaining conductive material layer 3021 a serves as the conductive layer 3021 .

[0134] In step S1023, if Figure 13 as well as Figure 14 As shown, a second isolation structure 104 is formed in the second gap trench 103 , a second dielectric layer 202 is formed on the surface of the second isolation structure 104 and the substrate surface, and an isolation spacer 303 is formed on the sidewall of the bit line stack structure 302 .

[0135] in, Figure 14 Can be regarded as Figure 13 The cross-sectional structure diagram of the structure along the A-A' direction. In order to facilitate the understanding of this scheme, Figure 13 The positions of the first air gaps 3034 in the isolation sidewall 303 are shown in the top view of the structure. However, it should be noted that the first air gaps 3034 are not actually exposed. Figure 13 This is only an example of the semiconductor structure of the present application, and the embodiments of the present disclosure should not be limited to the following. Figure 13 The specific shapes shown are intended to include deviations in shapes that result, for example, from manufacturing techniques.

[0136] In one embodiment, Figure 15 As shown, the step of forming an isolation spacer on the sidewall of the bit line stack structure in step S1023 includes:

[0137] S1023a: forming a first spacer on a sidewall of the bit line stack structure;

[0138] S1023b: forming a first sacrificial layer on the surface of the first sidewall spacer;

[0139] S1023c: forming a second sidewall spacer on a surface of the first sidewall spacer and a surface of the first sacrificial layer;

[0140] S1023d: Remove the first sacrificial layer to form a first air gap. The first sidewall, the first air gap and the second sidewall constitute an isolation sidewall.

[0141] In step S1023a, if Figure 16 As shown, a process combining deposition and etching can be used to form the first sidewall 3031 on the sidewall of the bit line stack structure 302. For example, a deposition process can be used to deposit the first sidewall 3031 material layer, and then an etching process (such as dry etching) can be used. The anisotropic characteristics of the dry etching process are utilized to retain the first sidewall 3031 material layer on the sidewall of the bit line stack structure 302, thereby forming the first sidewall 3031.

[0142] In step S1023b, if Figure 17 As shown, a first sacrificial layer 3032 is formed on the surface of the first sidewall 3031 .

[0143] In step S1023b, if Figure 18 As shown, a second sidewall spacer 3033 is formed on the surface of the first sidewall spacer 3031 and the surface of the first sacrificial layer 3032 .

[0144] In step S1023b, if Figure 19 As shown, the first sacrificial layer 3032 is removed to form a first air gap 3034 . The first spacer 3031 , the first air gap 3034 and the second spacer 3033 constitute the isolation spacer 303 .

[0145] The materials of the first sidewall spacer 3031 and the second sidewall spacer 3033 may be the same, and the material of the first sacrificial layer 3032 is different from the materials of the first sidewall spacer 3031 and the second sidewall spacer 3033 .

[0146] Optionally, a suitable removal process (such as a wet process) can be used to utilize the difference between the etching selectivity ratios of the first sacrificial layer 3032 and the first side wall 3031 and the second side wall 3033, so as to retain the first side wall 3031 and the second side wall 3033 while removing the first sacrificial layer 3032, thereby forming a first air gap 3034 located between the first side wall 3031 and the second side wall 3033, so that the first side wall 3031, the first air gap 3034 and the second side wall 3033 constitute the isolation side wall 303.

[0147] Optionally, there may be one or more first air gaps 3034 in the isolation spacer 303. Furthermore, when there are multiple first air gaps 3034 in the isolation spacer 303, the multiple first air gaps 3034 may still be formed by removing corresponding sacrificial layers.

[0148] In one embodiment, after the above step S102 and before the above step S103 , the method for preparing the semiconductor structure further includes: etching the second dielectric layer and the substrate to form contact holes.

[0149] like Figure 20 As shown, the contact hole 203 exposes a portion of the active area 101 ; the storage node contact structure material layer 501 also fills the contact hole 203 .

[0150] In step S103, refer to Figure 1 Step S103 in Figure 21 A storage node contact structure material layer 501 may be formed between adjacent bit line structures using a suitable deposition process (eg, PVD, CVD, or ALD, etc.).

[0151] In step S104, refer to Figure 1 Step S104 in Figure 22 The storage node contact structure material layer is then etched to form the storage node contact structure and a first gap trench 601. The first gap trench 601 is located between the bitline structure and the storage node contact structure. During the etching process to form the first gap trench 601, a portion of the isolation sidewall is also removed. The first gap trench 601 exposes the first air gap 3034 in the isolation sidewall. The bottom surface of the first gap trench 601 is higher than the top surface of the conductive layer 3021, leaving the isolation sidewalls on the sidewalls of the conductive layer 3021 to protect the conductive layer 3021.

[0152] In step S104, refer to Figure 1 Step S104 in Figure 23-Figure 32 A first isolation layer 60 is formed in the first gap groove 601, and a second air gap 602 is defined in the first isolation layer 60. The first isolation layer 60 seals the exposed first air gap 3034, preventing the etching solution from entering the first air gap 3034 and damaging the first sidewall 3031 and the conductive layer 3021 during the formation of the second air gap 602. The bottom of the second air gap 602 is higher than the top surface of the conductive layer 3021, and the second air gap 602 is not connected to the first air gap 3034.

[0153] In some embodiments, the first sacrificial layer 3032 may not be removed before forming the first gap groove 601. Instead, a portion of the isolation spacer 303 may be removed when forming the first gap groove 601. Then, the exposed first sacrificial layer 3032 may be removed along the first gap groove 601 to form the first air gap 3034. The first spacer 3031, the first air gap 3034, and the second spacer 3032 constitute the isolation spacer 303. Thus, there is no need to perform additional processing on the isolation spacer 303 to expose the first sacrificial layer 3032, thereby improving process efficiency.

[0154] like Figure 23 as well as Figure 24 As shown, Figure 23 This is a schematic top view of the structure in which the second air gap 602 is formed in some embodiments. Figure 24 Can be Figure 23 Schematic diagram of the cross-sectional structure of the structure along the A-A' direction. Figure 23 In the embodiment, the second air gap 602 may be an annular gap in a top view, resulting in Figure 24 The cross section in FIG. 6 shows two second air gaps 602, and the bottoms of the two second air gaps 602 can be connected or disconnected. In addition, in order to facilitate understanding of this solution, Figure 23 Schematically illustrates the position of each second air gap 602 in the top view of the structure, but it should be noted that, in practice, the second air gap 602 will not be exposed.

[0155] Due to the presence of the first air gap 3034 and the second air gap 602, the dielectric constant of air is relatively low. Therefore, the use of the first air gap 3034 and the second air gap 602 can reduce the capacitance, thereby reducing the capacitance (C_BL / NC) between the storage node contact structure 50 and the bit line structure 30 and the capacitance between adjacent storage node contact structures 50, thereby reducing the overall capacitance (C_BL) of the bit line structure 30, thereby improving the sensing margin of the chip.

[0156] In addition, the number of the second air gaps 602 in each first isolation layer 60 can be one or more, and the number of the second air gaps 602 in each first isolation layer 60 can be controlled by selecting a suitable process. Figure 24 In the embodiment, the number of the second air gaps 602 is two, but according to specific process requirements, multiple second air gaps 602 can also be formed in the first isolation layer 60 through some appropriate process steps. This embodiment does not limit the number of the second air gaps 602.

[0157] In one embodiment, the step S104 includes: forming a first isolation layer in the first gap groove using a deposition process, wherein the first isolation layer has a second air gap.

[0158] like Figure 25 as well as Figure 26 As shown, Figure 25 This is a schematic top view of a structure in which the second air gap 602 is formed by a deposition process in some other embodiments. Figure 26 Can be Figure 25 Schematic diagram of the cross-sectional structure of the structure along the A-A' direction. In order to facilitate the understanding of this scheme, Figure 25Schematically illustrates the position of each second air gap 602 in the top view of the structure, but it should be noted that, in practice, the second air gap 602 will not be exposed.

[0159] When forming the first isolation layer 60 in the first gap trench 601 using a deposition process, due to the characteristics of the deposition process, the first isolation layer 60 is first deposited on the sidewalls and bottom of the first gap trench 601. Subsequently, the first isolation layer 60 on both sidewalls of the same first gap trench 601 gradually converges toward the center of the first gap trench 601 as the deposition time increases. Generally, to ensure the integrity of the first isolation layer 60, the corresponding process parameters can be controlled (e.g., controlling the deposition time, or changing the ratio of various deposition gases, etc.) to maximize the convergence of the first isolation layer 60 on both sidewalls and avoid forming a void in the first isolation layer 60 in the center of the first gap trench 601. In this embodiment, by controlling the corresponding process parameters, the void formed by the first isolation layer 60 in the center of the first gap trench 601 can be cleverly retained, so that the void formed in the center of the first gap trench 601 can be directly used as the second air gap 602, thereby forming the second air gap 602 in the first isolation layer 60.

[0160] In one embodiment, Figure 27 As shown, the above step S104 includes:

[0161] S1041: forming a first sub-isolation layer on the sidewall and bottom of the first gap trench;

[0162] S1042: forming a second sacrificial layer on a surface of the first sub-isolation layer;

[0163] S1043: forming a second sub-isolation layer on the surface of the second sacrificial layer, wherein the first sub-isolation layer, the second sacrificial layer, and the second sub-isolation layer together fill the first gap groove;

[0164] S1044: removing the second sacrificial layer to form a sacrificial gap;

[0165] S1045: forming a third sub-isolation layer, wherein the third sub-isolation layer fills a portion of the sacrificial gap to form a second air gap.

[0166] In step S1041, if Figure 28 As shown, in order to facilitate the understanding of this solution, Figure 28 Can be regarded as Figure 24 FIG. 6 is an enlarged schematic diagram of a partial structure in FIG. 7 , in which a first sub-isolation layer 603 can be formed on the sidewall and bottom of the first gap groove 601 by a deposition process.

[0167] In step S1042, if Figure 29As shown, a second sacrificial layer 604 is formed on the surface of the first sub-isolation layer 603 .

[0168] In step S1043, if Figure 30 As shown, a second sub-isolation layer 605 is formed on the surface of the second sacrificial layer 604 , and the first sub-isolation layer 603 , the second sacrificial layer 604 , and the second sub-isolation layer 605 together fill the first gap 601 .

[0169] In step S1044, if Figure 31 As shown, the second sacrificial layer 604 is removed to form a sacrificial gap 602a.

[0170] The material of the first sub-isolating layer 603 may be the same as the material of the second sub-isolating layer 605, and the material of the second sacrificial layer 604 is different from the materials of the first sub-isolating layer 603 and the second sub-isolating layer 605. For example, the material of the second sacrificial layer 604 may include a metal material, such as tungsten (W).

[0171] Optionally, a suitable removal process (such as a wet process) can be used to utilize the difference between the etching selectivity ratios of the second sacrificial layer 604 and the first sub-isolation layer 603 and the second sub-isolation layer 605, so as to retain the first sub-isolation layer 603 and the second sub-isolation layer 605 while removing the first sacrificial layer 3032, thereby forming a sacrificial gap located between the first sub-isolation layer 603 and the second sub-isolation layer 605.

[0172] Furthermore, the number of the second air gaps 602 can be one or more. When the number of the second air gaps 602 is multiple, multiple second air gaps 602 can be formed by removing the sacrificial layer in a similar manner to the above steps or by combining the deposition process.

[0173] In step S1045, Figure 32 As shown, a third sub-isolation layer 606 is formed, and the third sub-isolation layer 606 fills a portion of the sacrificial gap 602 a to form a second air gap 602 .

[0174] It should be understood that, although the various steps in the flow charts of the various embodiments are shown in sequence according to the instructions of the arrows, these steps are not necessarily performed in sequence according to the order indicated by the arrows. Unless otherwise specified herein, the execution of these steps is not strictly limited in order, and these steps can be performed in other orders. Moreover, at least a portion of the steps in the flow charts of the various embodiments may include multiple steps or multiple stages, and these steps or stages are not necessarily performed at the same time, but can be performed at different times, and the execution order of these steps or stages is not necessarily performed in sequence, but can be performed in turn or alternately with at least a portion of other steps or steps or stages in other steps.

[0175] See also Figure 22 The present disclosure further provides a semiconductor structure comprising: a substrate, a plurality of bitline structures 30, a storage node contact structure 50, and a first isolation layer 60. The plurality of bitline structures 30 are located on the upper surface of the substrate. The bitline structures 30 include a bitline stack structure 302 and an isolation spacer 303 located on the sidewalls of the bitline stack structure 302. The isolation spacer 303 defines a first air gap 3034. The storage node contact structure 50 is located between the bitline structures 30. The first isolation layer 60 is located between the bitline structures 30 and the storage node contact structure 50. The first isolation layer 60 defines a second air gap 602.

[0176] like Figure 22 As shown, due to the existence of the first air gap 3034 and the second air gap 602, the capacitance (C_BL / NC) between the storage node contact structure 50 and the bit line structure 30 can be reduced, thereby reducing the overall capacitance (C_BL) of the bit line structure 30, thereby improving the sensing margin of the chip.

[0177] The semiconductor structure includes a substrate, multiple bitline structures 30, a storage node contact structure 50, and a first isolation layer 60. The multiple bitline structures 30 are located on the upper surface of the substrate. The bitline structures 30 include a bitline stack structure 302 and isolation spacers 303 located on the sidewalls of the bitline stack structure 302. The isolation spacers 303 define a first air gap 3034. The storage node contact structures 50 are located between the bitline structures 30. The first isolation layer 60 is located between the bitline structures 30 and the storage node contact structures 50. The first isolation layer 60 defines a second air gap 602. The presence of the first air gap 3034 and the second air gap 602 reduces the capacitance between the storage node contact structure 50 and the bitline structure 30, thereby reducing the overall capacitance of the bitline structure 30 and improving the chip's sensing margin.

[0178] Optionally, there are one or more first air gaps 3034 in the isolation spacer 303. Furthermore, when there are multiple first air gaps 3034 in the isolation spacer 303, the multiple first air gaps 3034 can still be formed by removing corresponding sacrificial layers to form the first air gaps 3034.

[0179] In one embodiment, the number of the second air gaps 602 in each first isolation layer 60 is one or more. Figure 26 As shown, in each first isolation layer 60, the number of the second air gap 602 is one; or Figure 24 As shown, there are two second air gaps 602 in each first isolation layer 60. Of course, the number of the second air gaps 602 can be further designed to be an appropriate number according to specific process requirements, and this embodiment does not limit this.

[0180] In one embodiment, Figure 14 As shown, the substrate includes: a base 10, a plurality of spaced-apart bitline contact holes 2011, a second isolation trench, and a dielectric layer 20. The base 10 includes a shallow trench isolation structure 102, which isolates a plurality of spaced-apart active areas 101 within the base 10. The plurality of spaced-apart bitline contact holes 2011 are located within the base 10. The second isolation trench is located within the bitline contact holes 2011. The dielectric layer 20 is located on the upper surface of the base 10. The semiconductor structure also includes a plurality of bitline contact structures 301 located within the bitline contact holes 2011, each corresponding to one of the bitline contact holes 2011. The bitline contact structures 301 extend through the dielectric layer 20 and the second isolation layer along the thickness direction. The top of the bitline contact structure 301 contacts the bottom of the bitline stack structure 302, and the bitline contact structure 301 contacts the active area 101 below the bitline contact holes 2011.

[0181] The material of the substrate 10 may be any suitable substrate material known in the art, for example, at least one of the following materials: silicon (Si), germanium (Ge), red phosphorus, silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI), or double-side polished silicon wafers (DSP), or ceramic substrates such as alumina, quartz or glass substrates, etc., which are not limited in this embodiment.

[0182] Optional, such as Figure 14 As shown, the dielectric layer 20 can be composed of a first dielectric layer 201 and a second dielectric layer 202 located on the same layer. The first dielectric layer 201 and the second dielectric layer 202 can be made of the same material and both serve to insulate the bit line structure 30 from the active area 101 to prevent a short circuit between the bit line structure 30 and the active area 101.

[0183] In one embodiment, Figure 14 As shown, the storage node contact structure 50 also penetrates the dielectric layer 20 along the thickness direction and extends into the substrate 10 to contact the active area 101 .

[0184] In one embodiment, Figure 21 As shown, the bit line stack structure 302 includes a conductive layer 3021 and a passivation layer 3022, and the storage node contact structure 50 includes a contact structure (not shown) and a contact pad (not shown), wherein the contact structure is located between the conductive layers 3021 of adjacent bit line structures 30. The contact pad is located between the upper surface of the contact structure and the passivation layer 3022 of the bit line structure 30, and partially covers the top of the passivation layer 3022.

[0185] The conductive layer 3021 may be made of tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or other metals. The passivation layer 3022 may be made of a nitride, such as silicon nitride (SiN).

[0186] In one embodiment, Figure 22 As shown, the first isolation layer 60 is located between the contact pad and the bit line structure 30 .

[0187] In one embodiment, Figure 23 As shown, a plurality of bit line structures 30 are arranged at intervals along the first direction and extend along the second direction, and a plurality of storage node contact structures 50 are arranged in an array along the first direction and the second direction; in two rows of storage node contact structures 50 arranged adjacent to each other along the second direction, a second air gap 602 is provided between one row of storage node contact structures 50 and the bit line structure 30 adjacent to the first side in the first direction, and a second air gap 602 is provided between the other row of storage node contact structures 50 and the bit line structure 30 adjacent to the second side in the first direction. The second air gap 602 may be a ring-shaped gap in a top view, resulting in Figure 24 The cross section in FIG. 3 shows two second air gaps 602 , and the bottoms of the two second air gaps 602 may be connected or disconnected.

[0188] The first direction may intersect with the second direction, and further, the first direction may be perpendicular to the second direction. Figure 23 In the first direction, Figure 23 The horizontal direction in the second direction can be Figure 23 In other suitable application scenarios, the first direction and the second direction may also be other suitable directions, which are not limited in this embodiment.

[0189] In one embodiment, the second air gap 602 may be a rectangular gap, a circular gap, or an irregular gap in a top view. Figure 25 Taking the structure shown as an example, the curvature of the sidewall close to the storage node contact structure 50 is greater than the curvature of the sidewall of the second air gap 602 close to the bit line structure 30 in a top view.

[0190] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0191] The above embodiments merely illustrate several implementations of the present disclosure, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art would be able to make numerous variations and improvements without departing from the spirit of the present disclosure, all of which fall within the scope of protection of the present disclosure. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate; forming a plurality of bit line structures on the upper surface of the substrate, wherein the bit line structures include a bit line stack structure and an isolation spacer located on a sidewall of the bit line stack structure, wherein a first air gap is formed in the isolation spacer; forming a storage node contact structure material layer between adjacent bit line structures; Etching the storage node contact structure material layer to obtain a storage node contact structure and a first gap trench, wherein the first gap trench is located between the bit line structure and the storage node contact structure; A first isolation layer is formed in the first gap groove, wherein the first isolation layer has a second air gap.

2. The method for preparing a semiconductor structure according to claim 1, wherein: Providing a substrate comprises: providing a substrate; forming a shallow trench isolation structure in the substrate, wherein the shallow trench isolation structure isolates a plurality of active areas arranged in an array at intervals in the substrate; forming a first dielectric layer on the upper surface of the substrate; A plurality of bit line contact holes are formed in the base and the first dielectric layer to form the substrate.

3. The method for preparing a semiconductor structure according to claim 2, wherein: A plurality of bit line structures are formed on the upper surface of the substrate, including: filling the bit line contact hole with a bit line contact structure material layer, and forming an initial bit line stack on the bit line contact structure material layer; Patterning the initial bit line stack, the bit line contact structure material layer, and the first dielectric layer to form a bit line stack structure, a bit line contact structure, and second gap grooves located on both sides of the bit line contact structure, wherein the top of the bit line contact structure contacts the bottom of the bit line stack structure, and the bit line contact structure contacts the active area exposed by the bit line contact hole; A second isolation structure is formed in the second gap groove, a second dielectric layer is formed on the surface of the second isolation structure and the surface of the substrate, and isolation sidewalls are formed on the sidewalls of the bit line stack structure.

4. The method for preparing a semiconductor structure according to claim 3, wherein: After forming a plurality of bit line structures on the upper surface of the substrate and before forming a storage node contact structure material layer between adjacent bit line structures, the method further includes: The second dielectric layer and the substrate are etched to form a contact hole, wherein the contact hole exposes a portion of the active area; the storage node contact structure material layer also fills the contact hole.

5. The method for preparing a semiconductor structure according to claim 3, wherein: The bit line stack structure includes a conductive layer and a passivation layer; the initial bit line stack is formed on the bit line contact structure material layer, including: forming a conductive material layer on the upper surface of the bit line contact structure material layer; forming a passivation material layer on the upper surface of the conductive material layer; The patterning of the initial bit line stack comprises: The passivation material layer and the conductive material layer are etched to obtain a plurality of the bit line stack structures arranged at intervals, the remaining passivation material layer serves as a passivation layer, and the remaining conductive material layer serves as a conductive layer.

6. The method for preparing a semiconductor structure according to claim 3, wherein: The step of forming an isolation spacer on the sidewall of the bit line stack structure includes: forming a first spacer on a sidewall of the bit line stack structure; forming a first sacrificial layer on a surface of the first sidewall; forming a second sidewall spacer on a surface of the first sidewall spacer and a surface of the first sacrificial layer; The first sacrificial layer is removed to form the first air gap, and the first sidewall spacer, the first air gap, and the second sidewall spacer constitute the isolation sidewall spacer.

7. The method for preparing a semiconductor structure according to any one of claims 1 to 6, characterized in that: The first isolation layer is formed in the first gap groove, wherein the first isolation layer has a second air gap, including: The first isolation layer is formed in the first gap groove by using a deposition process, and the second air gap is formed in the first isolation layer.

8. The method for preparing a semiconductor structure according to any one of claims 1 to 6, characterized in that: The first isolation layer is formed in the first gap groove, wherein the first isolation layer has a second air gap, including: forming a first sub-isolation layer on the sidewalls and bottom of the first gap groove; forming a second sacrificial layer on a surface of the first sub-isolating layer; forming a second sub-isolation layer on a surface of the second sacrificial layer, wherein the first sub-isolation layer, the second sacrificial layer, and the second sub-isolation layer together fill the first gap groove; removing the second sacrificial layer to form a sacrificial gap; A third sub-isolating layer is formed, wherein the third sub-isolating layer fills a portion of the sacrificial gap to form the second air gap.

9. A semiconductor structure, characterized in that include: substrate; A plurality of bit line structures are located on the upper surface of the substrate, wherein the bit line structures include a bit line stack structure and an isolation spacer located on a sidewall of the bit line stack structure, wherein a first air gap is formed in the isolation spacer; a storage node contact structure located between the bit line structures; The first isolation layer is located between the bit line structure and the storage node contact structure, and a second air gap is defined in the first isolation layer.

10. The semiconductor structure according to claim 9, wherein: The substrate comprises: A substrate having a shallow trench isolation structure therein, wherein the shallow trench isolation structure isolates a plurality of active areas arranged at intervals within the substrate; a plurality of spaced-apart bit line contact holes located in the substrate; a second isolation trench located in the bit line contact hole; a dielectric layer, located on the upper surface of the substrate; The semiconductor structure also includes a plurality of bit line contact structures located in the bit line contact holes, which are arranged in a one-to-one correspondence with the bit line contact holes. The bit line contact structures penetrate the dielectric layer and the second isolation trench along the thickness direction. The top of the bit line contact structure contacts the bottom of the bit line stack structure, and the bit line contact structure contacts the active area below the bit line contact hole.

11. The semiconductor structure according to claim 10, wherein: The storage node contact structure also penetrates the dielectric layer along the thickness direction and extends into the substrate to contact the active area.

12. The semiconductor structure according to claim 9, wherein: The bit line stack structure includes a conductive layer and a passivation layer, and the storage node contact structure includes: a contact structure located between conductive layers of adjacent bit line structures; The contact pad is located between the upper surface of the contact structure and the passivation layer of the bit line structure and partially covers the top of the passivation layer.

13. The semiconductor structure according to claim 12, wherein: The first isolation layer is located between the contact pad and the bit line structure.

14. The semiconductor structure according to any one of claims 9 to 13, characterized in that The plurality of bit line structures are arranged at intervals along a first direction and extend along a second direction, and the plurality of storage node contact structures are arranged in an array along the first direction and the second direction; In the two rows of storage node contact structures arranged adjacent to each other along the second direction, a second air gap is provided between one row of storage node contact structures and the bit line structure adjacent to the first side of the first direction, and a second air gap is provided between the other row of storage node contact structures and the bit line structure adjacent to the second side of the first direction.

15. The semiconductor structure according to any one of claims 9 to 13, characterized in that In each of the first isolation layers, the number of the second air gaps is one or more.

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