Display substrate and display panel

Abstract

This disclosure provides a display substrate and a display panel. The display substrate includes a display area, a first border area, and a second border area. The first border area is located between the display area and a first boundary of the display substrate, and the second border area is located between the display area and a second boundary of the display substrate. The first boundary and the second boundary are adjacent to and connected. The display substrate further includes: a signal trace located in the first border area and extending toward the second border area; a first bonding area located in the second border area and including a first bonding pin; and a connection trace including a first connection segment and a second connection segment. The first connection segment extends from one end of the signal trace near the second boundary toward the center of the second border area and is connected to the first bonding pin through the second connection segment. The angle between the first connection segment and the first boundary is greater than the angle between the second connection segment and the first boundary. The solution disclosed herein can reduce the risk of connection trace breakage due to fragmentation and improve product yield.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display substrate and a display panel. Background Technology

[0002] A liquid crystal display panel is composed of a color filter substrate and an array substrate bonded together. The color filter substrate is smaller than the array substrate, thus creating a stepped area where the array substrate protrudes from the color filter substrate. This stepped area is a single layer of glass, making it prone to breakage at the corners during panel transportation and handling. Multiple metal traces run along the stepped area; breakage at the corners can cause some of these traces to break, preventing signal transmission and causing the display panel to malfunction. This affects electrical testing and normal operation, ultimately impacting product yield. Summary of the Invention

[0003] This disclosure provides a display substrate and a display panel to solve or alleviate one or more technical problems in the prior art.

[0004] As a first aspect of the present disclosure, an embodiment of the present disclosure provides a display substrate, including a display area, a first border area, and a second border area. The first border area is located between the display area and a first boundary of the display substrate, and the second border area is located between the display area and a second boundary of the display substrate. The first boundary and the second boundary are adjacent to and connected to each other. The display substrate further includes:

[0005] The signal trace is located in the first border area and extends toward the second border area;

[0006] The first bonding area is located in the second border area and includes the first bonding pin;

[0007] The connection trace includes a first connection segment and a second connection segment. The first connection segment extends from one end of the signal trace near the second boundary toward the middle of the second frame area and is connected to the first bonding pin through the second connection segment. The angle between the first connection segment and the first boundary is greater than the angle between the second connection segment and the first boundary.

[0008] In some embodiments, the display substrate further includes a pad area located in the second border area and between the first bonding area and the first boundary, and the first connection segment is located on the side of the pad area away from the second boundary.

[0009] In some embodiments, the extension direction of the first connecting segment is perpendicular to the extension direction of the first boundary, and the first connecting segment is located between the edge line of the display area facing the second boundary and the second boundary.

[0010] In some embodiments, the display panel further includes multiple data lines located in the display area, and the display substrate further includes a fan-shaped trace area located in the second border area. The fan-shaped trace area is provided with multiple data connection lines, which are connected one-to-one with the multiple data lines. The connection lines are located outside the fan-shaped trace area.

[0011] In some embodiments, a second bonding area located in the second border area is also included. The second bonding area is used for bonding connection with the control chip. The connection trace also includes a third connection segment. The second connection segment is connected to the first bonding pin through the third connection segment. The second connection segment and the third connection segment enable the connection trace to avoid the second bonding area.

[0012] In some embodiments, the connection trace is also connected to a preset bonding pin in the second bonding area.

[0013] In some embodiments, the distance between the endpoint of the first connecting segment that connects to the second connecting segment and the first boundary is greater than or equal to 14.22 mm.

[0014] In some embodiments, a detection pad located in the pad area is also included, and the detection pad is connected to the first connection segment via a fourth connection segment;

[0015] The display substrate includes a first metal layer, a first insulating layer and a second metal layer stacked together, with one of the first connecting segment and the fourth connecting segment located in the first metal layer and the other located in the second metal layer.

[0016] In some embodiments, the system further includes a second insulating layer and a conductive layer, which are sequentially stacked on the side of the second metal layer away from the first insulating layer. The conductive layer includes a transition trace, which is connected to the first connection segment through a first via and to the fourth connection segment through a second via.

[0017] In some embodiments, the distance between the edge of the detection pad that is away from the first boundary and the first boundary is less than 14.22 mm.

[0018] In some embodiments, the display substrate includes a thin-film transistor and a pixel electrode layer located in the display area, a first metal layer is disposed on the same layer as the gate of the thin-film transistor, a second metal layer is disposed on the same layer as the source and drain of the thin-film transistor, and a conductive layer is disposed on the same layer as the pixel electrode layer.

[0019] In some embodiments, the display substrate includes a fragile area, which is located in the second frame area and includes the connection point between the first boundary and the second boundary, and the connecting traces avoid the fragile area.

[0020] In some embodiments, a gate driving circuit located in the first border area is further included, and the signal traces are connected to the gate driving circuit.

[0021] As a second aspect of the present disclosure, the present disclosure provides a display panel including the display substrate of the present disclosure, and further including a mating substrate disposed opposite to the display substrate, wherein a first connecting segment is located within the orthographic projection of the mating substrate on the display substrate.

[0022] The technical solution of this disclosure sets the included angle β1 between the first connecting segment and the first boundary to be greater than the included angle β2 between the second connecting segment and the first boundary. This ensures that the angle η1 formed by the connection of the first and second connecting segments is less than 180°, thus making the vertex of angle η1 farther away from the connection point A of the first and second boundaries relative to related technologies. This also keeps the connection traces away from the corner region near the connection point A of the display substrate. Therefore, when a fragment occurs in the corner region near the connection point A, the impact of the fragment on the connection trace can be reduced, lowering the risk of connection trace breakage caused by the fragment, ensuring signal transmission between the first bonding pin and the signal trace, ensuring normal product illumination, and improving product yield.

[0023] The above overview is for illustrative purposes only and is not intended to be limiting in any way. Further aspects, embodiments, and features of this disclosure will become readily apparent from the accompanying drawings and the following detailed description, in addition to the illustrative aspects, embodiments, and features described above. Attached Figure Description

[0024] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments according to this disclosure and should not be construed as limiting the scope of this disclosure.

[0025] Figure 1 This is a partial planar schematic diagram of a display panel in the related art;

[0026] Figure 2 This is a partial planar schematic diagram of another display panel in the related technology;

[0027] Figure 3 for Figure 1 or Figure 2 A cross-sectional schematic diagram of the display panel shown;

[0028] Figure 4 This is a plan view of the display panel according to one embodiment of the present disclosure;

[0029] Figure 5 This is a plan view of the display panel in another embodiment of the present disclosure;

[0030] Figure 6 This is a plan view of the display panel in yet another embodiment of the present disclosure;

[0031] Figure 7 It is a quadrilateral;

[0032] Figure 8 This is a plan view of the display panel in another embodiment of the present disclosure;

[0033] Figure 9 for Figure 4 or Figure 5 An enlarged schematic diagram of part B in the middle;

[0034] Figure 10 for Figure 9 Schematic diagram of the CC section in the diagram;

[0035] Figure 11 for Figure 4 or Figure 5 Another enlarged diagram of section B;

[0036] Figure 12 for Figure 11 Schematic diagram of the C-section;

[0037] Figure 13 for Figure 4 or Figure 5 Another enlarged schematic diagram of part B;

[0038] Figure 14 for Figure 13 Schematic diagram of the CC section in the diagram;

[0039] Figure 15 for Figure 4 or Figure 5 Another enlarged schematic diagram of section B;

[0040] Figure 16 for Figure 15 Schematic diagram of the CC section.

[0041] Explanation of reference numerals in the attached figures:

[0042] 10. Display substrate; 10a. First boundary; 10b. Second boundary; 20. Second substrate;

[0043] 31. First bonding area; 32. Second bonding area; 33. Solder pad area;

[0044] 40. Signal trace; 50. Connector trace; 50a. First connector segment; 50b. Second connector segment; 50c. Third connector segment; 54. Fourth connector segment; 55. Fifth connector segment;

[0045] BK1, first border area; BK2, second border area;

[0046] 61. First metal layer; 62. First insulating layer; 63. Second metal layer; 64. Second insulating layer; 65. Conductive layer. Detailed Implementation

[0047] In the following description, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of this disclosure, and different embodiments can be combined arbitrarily without conflict. Therefore, the drawings and description are considered to be exemplary in nature and not restrictive.

[0048] Figure 1 This is a partial planar schematic diagram of a display panel in related technologies. Figure 2 This is a partial planar schematic diagram of another display panel in the related technology. Figure 3 for Figure 1 or Figure 2 The diagram shows a cross-sectional view of the display panel. Figure 1 , Figure 2 and Figure 3 As shown, the display panel includes a display substrate 10 and a mating substrate 20, with the mating substrate 20 disposed opposite to the display substrate 10. The display substrate 10 includes a display area AA, a first border area BK1, and a second border area BK2. Figure 1 and Figure 2 In the diagram, the first boundary 10a is the left boundary of the display substrate 10, and the second boundary 10b is the lower boundary of the display substrate 10. The first border area BK1 is located between the display area AA and the first boundary 10a of the display substrate 10, and the second border area BK2 is located between the display area AA and the second boundary 10b of the display substrate 10. The first boundary 10a and the second boundary 10b are adjacent and connected.

[0049] like Figures 1-3 As shown, the size of the mating substrate 20 is smaller than that of the display substrate 10. Therefore, when the mating substrate 20 and the display substrate 10 are mated, the lower boundary 20b of the mating substrate 20 and the second boundary 10b of the display substrate 10 cannot be aligned, forming a stepped region TQ. The stepped region TQ is only a part of the display substrate 10, that is, the stepped region TQ is a single-layer substrate. The area near the corner of the stepped region TQ is the stepped corner region. Figure 1 and Figure 2 The boundary of the corner area of ​​the step is roughly indicated by the auxiliary line S. The corner area of ​​the step includes the connection point of the first boundary 10a and the second boundary 10b. Since the step area is a single layer of glass, it is easy to cause fragments to break during the transportation and handling of the panel.

[0050] It should be noted that the specific size of the corner area of ​​the steps can be set based on experience. In actual implementation, the vulnerable areas located at the corners of the steps can be determined based on experience, and the corner area of ​​the steps can be determined based on these vulnerable areas. For example, the vulnerable areas can be defined as the corner areas of the steps.

[0051] like Figure 1 and Figure 2 As shown, the first frame area BK1 is provided with a gate drive circuit (GOA circuit). The GOA circuit needs to be connected to drive signals; therefore, the first frame area BK1 also has multiple signal traces 40. These signal traces 40 are used to provide the GOA circuit with the required drive signals, such as power signals, clock signals, reset signals, or initial start signals. The second frame area BK2 is provided with a first bonding area 31, located in the stepped area. The first bonding area 31 is used for bonding with a flexible printed circuit (FPC).

[0052] In order to provide a drive signal to signal trace 40, Figure 1 and Figure 2 In the process, signal trace 40 is connected to the corresponding bonding pin of the first bonding area 31 via connection trace 50, so that the flexible circuit board can provide the required drive signal to the GOA circuit through connection trace 50 and signal trace 40.

[0053] exist Figure 1 In the process of electrical testing (ET), the probe of the ET fixture is pressed against the bonding pins of the first bonding area 31. Because the bonding pins of the first bonding area 31 have a small width and spacing, the accuracy of the probe insertion is poor, affecting the testing accuracy. Furthermore, this method may cause the probe of the ET fixture to scratch the bonding pins of the first bonding area 31, thereby affecting the bonding connection performance between the first bonding area 31 and the flexible circuit board.

[0054] In addition, such as Figure 1 As shown, the display substrate 10 also includes a pad area 33 located in the second bezel area BK2, where pads are provided. The pad area 33 is typically located between the first bonding area 31 and the first boundary 10a. To avoid the pad area 33, the connection trace 50 bypasses the pad area 33 from below in the second bezel area BK2. This causes the connection trace 50 to be close to the connection point A between the first boundary 10a and the second boundary 10b, resulting in a portion of the connection trace 50 being located in the corner region of the step. When a fragment appears in the corner region of the step, the connection trace 50 breaks, causing the connection between the signal trace 40 and the bonding pin of the first bonding area 31 to be disconnected, affecting signal transmission.

[0055] To avoid scratching the bonding pins of the first bonding area 31 during ET detection, such as... Figure 2 As shown, detection pads (TPs) can be set in pad area 33. The number of detection pads (TPs) can be the same as the number of signal traces (40), and the detection pads (TPs) are connected in series in the corresponding connection traces (50). Figure 2 In the structure shown, during electrical testing, the probe of the ET fixture is pressed onto the test pad TP, thus avoiding the influence of the ET fixture on the bonding pins of the first bonding area 31.

[0056] like Figure 2 As shown, since most of the area of ​​the second border region BK2 is occupied, the pad region 33 is typically located at least partially in the corner region of the step, for example, Figure 2 The detection pad TP portion is located in the left-side step corner area. Figure 2 In the structure shown, since the detection pad TP is at least partially located in the corner area of ​​the step, the fragments in the corner area of ​​the step caused by the display panel during transportation and handling will cause the detection pad TP to break, which in turn will cause the connection trace 50 between the signal trace 40 and the bonding pin of the first bonding area 31 to break, resulting in the inability to transmit the signal, causing the display panel to malfunction, affecting the electrical detection of the display substrate 10 and the normal lighting of the display panel, and affecting the product yield.

[0057] In this article, the electrical testing of the display substrate 10 can be understood as a test of the wiring connection of the display substrate 10, mainly to detect whether there are breaks in the metal wiring on the display substrate 10.

[0058] Figure 4 This is a plan view of the display panel according to one embodiment of the present disclosure. Figure 5 This is a plan view of the display panel in another embodiment of the present disclosure. Figure 6 This is a plan view of the display panel in another embodiment of the present disclosure, as shown below. Figures 4-6 As shown, the display panel includes a display substrate 10 and a mating substrate 20, which are disposed opposite to each other. Figures 4-6 The diagram shows a boundary 20b of the mating substrate 20.

[0059] The display substrate 10 may include a display area AA, a first border area BK1, and a second border area BK2. The first border area BK1 is located between the display area AA and the first boundary 10a of the display substrate 10. The second border area BK2 is located between the display area AA and the second boundary 10b of the display substrate 10. For example, the second border area BK2 may be the area between the edge line L of the display area AA facing the second boundary 10b and the second boundary 10b. The edge line of the display area AA facing the second boundary 10b may be the straight line containing the boundary (lower boundary in the figure) of the display area AA facing the second boundary 10b. The first boundary 10a and the second boundary 10b are adjacent and connected. Therefore, the connection between the first boundary 10a and the second boundary 10b forms a corner of the display substrate 10.

[0060] like Figures 4-6 As shown, the display substrate 10 also includes signal traces 40, a first bonding area 31, and connection traces 50. The signal traces 40 are located in the first border area BK1 and extend toward the second border area BK2. For example, the signal traces 40 may extend toward the second border area BK2 along the extension direction of the first boundary 10a. The number of signal traces 40 may be one or more.

[0061] The first binding area 31 can be located in the second border area BK2. The first binding area 31 includes first binding pins, and the number of first binding pins can be set as needed. When there are multiple first binding pins, the multiple first binding pins can be arranged sequentially and at intervals in the first binding area 31.

[0062] For example, such as Figure 4 As shown, the first bonding region 31 is used for connection with a chip-on-film (COF) film. Figure 5 and Figure 6 In this embodiment, the first binding area 31 is used to connect with the flexible circuit board.

[0063] The connection trace 50 may include a first connection segment 50a and a second connection segment 50b. The first connection segment 50a extends from one end of the signal trace 40 near the second boundary 10b (the lower end of the signal trace 40 in the figure) toward the center of the second border area BK2, and is connected to the first bonding pin through the second connection segment 50b. Thus, the signal trace 40 is connected to the first bonding pin through the first connection segment 50a and the second connection segment 50b. The angle β1 between the first connection segment 50a and the first boundary 10a is greater than the angle β2 between the second connection segment 50b and the first boundary 10a.

[0064] In related technologies, such as Figure 1 and Figure 2At least part of the connecting trace 50 or the detection pad TP is located in the corner area of ​​the step. When the corner area of ​​the step is broken, it is easy to cause the connection between the signal trace 40 and the first bonded pin to break, resulting in the inability to transmit the signal, causing the product to fail to light up normally and affecting the product yield.

[0065] In this embodiment of the display substrate 10, the signal trace 40 is connected to the first bonding pin of the first bonding area 31 via the connection trace 50. The connection trace 50 includes a first connection segment 50a and a second connection segment 50b. The first connection segment 50a extends from one end of the signal trace 40 near the second boundary 10b toward the middle of the second border area BK2, and is connected to the first bonding pin via the second connection segment 50b. The angle β1 between the first connection segment 50a and the first boundary 10a is greater than the angle β2 between the second connection segment 50b and the first boundary 10a.

[0066] Figure 7 For a quadrilateral, from Figure 7 As can be seen from this, angles α1 and α2 are two relative angles. From... Figure 7 As can be seen, when angle α2 and the side lengths remain constant, the larger angle α1 is, the closer the vertex E of angle α1 is to the vertex of angle α2. Figure 7 In the equation, angle α1' is greater than 180°, angle α1 is less than 180°, and the vertex E' of angle α1' is closer to the vertex of angle α2 than the vertex E of angle α1.

[0067] It is understood that, in this disclosure, the angle η1 formed by the connection of the first connecting segment 50a and the second connecting segment 50b, and the angle η2 formed by the connection of the first boundary 10a and the second boundary 10b, can be considered as two relative angles. Setting the included angle β1 between the first connecting segment 50a and the first boundary 10a to be greater than the included angle β2 between the second connecting segment 50b and the first boundary 10a ensures that the angle η1 formed by the connection of the first connecting segment 50a and the second connecting segment 50b is less than 180°. This results in the vertex of angle η1 being further away from the connection point A of the first boundary 10a and the second boundary 10b relative to related technologies. This also causes the connection trace 50 to be far away from the corner region near the connection point A of the display substrate 10. Therefore, when a fragment occurs in the corner region near the connection point A, the impact of the fragment on the connection trace 50 can be reduced, lowering the risk of the connection trace 50 breaking due to the fragment, ensuring signal transmission between the first bonding pin and the signal trace 40, ensuring normal product illumination, and improving product yield.

[0068] In one embodiment, the number of signal traces 40 can be one or more, and the multiple signal traces 40 can be parallel to each other.

[0069] The display substrate 10 also includes a gate driver on array (GOA) circuit located in the first border area BK1, and signal traces 40 can be connected to the gate driver circuit. Signal traces 40 can be used to transmit drive signals required by the gate driver circuit, such as power signals, clock signals, reset signals, or initial startup signals. Different signal traces 40 can transmit different drive signals.

[0070] The number of connecting traces 50 can be the same as the number of signal traces 40, and the connecting traces 50 and signal traces 40 are connected in a one-to-one correspondence.

[0071] In one embodiment, such as Figure 4 -and Figure 6 As shown, the display substrate 10 also includes a pad area 33, which is located in the second border area BK2 and between the first bonding area 31 and the first boundary 10a. The first connection segment 50a is located on the side of the pad area 33 facing away from the second boundary 10b. Figures 4-6 In this configuration, the first connection segment 50a is located on the upper side of the pad area 33. Typically, the fragile area is located in the corner region near connection point A. Placing the first connection segment 50a on the side of the pad area 33 away from the second boundary 10b allows the first connection segment 50a to be further away from the fragile area, which helps the connection trace 50 avoid the fragile area, prevents the connection trace 50 from breaking due to fragments, and further improves product yield.

[0072] For example, such as Figures 4-6 As shown, the display substrate 10 includes a fragile area, which is located in the second frame area BK2 and includes the connection point A between the first boundary 10a and the second boundary 10b. The connecting trace 50 avoids the fragile area.

[0073] In one embodiment, such as Figures 4-6 As shown, the extension direction of the first connecting segment 50a can be perpendicular to the extension direction of the first boundary 10a, that is, the angle β1 can be 90°. The first connecting segment 50a is located between the edge line L of the display area AA facing the second boundary 10b and the second boundary 10b. Setting the extension direction of the first connecting segment 50a to be perpendicular to the extension direction of the first boundary 10a allows the connecting trace 50 to be further away from the corner area near the connection point A of the display substrate 10, avoiding the easily breakable area, further reducing the risk of breakage of the connecting trace 50 due to breakage, ensuring signal transmission between the first bonding pin and the signal trace 40, ensuring normal product lighting, and improving product yield. Furthermore, the first connecting segment 50a is located between the edge line L of the display area AA facing the second boundary 10b and the second boundary 10b, that is, the first connecting segment 50a is located in the second border area BK2 and will not enter the display area AA, avoiding the influence of the first connecting segment 50a on the display area AA.

[0074] In one embodiment, the first connecting segment 50a can be an inclined line, and the end of the first connecting segment 50a connected to the signal trace 40 can be located in the first border area BK1 or the second border area BK2. The first connecting segment 50a is located outside the display area AA. When the end of the first connecting segment 50a connected to the signal trace 40 is located in the second border area BK2, the extension direction of the first connecting segment 50a can be perpendicular to the extension direction of the first boundary 10a, without causing the first connecting segment 50a to enter the display area AA.

[0075] Figure 8 This is a plan view of the display panel in another embodiment of the present disclosure, as shown below. Figure 8 As shown, the display substrate may also include multiple data lines DT located in the display area AA. The display substrate 10 also includes a fan-shaped trace area located in the second bezel area BK2, where multiple data connection lines DL are arranged, and each data connection line DL is connected to one of the multiple data lines DT. The connection trace 50 is located outside the fan-shaped trace area. Placing the connection trace 50 outside the fan-shaped trace area avoids the connection trace 50 affecting the transmission performance of the data connection lines, ensuring the data transmission performance of the product and guaranteeing display quality.

[0076] For example, such as Figure 8 As shown, the end of the data connection line DL furthest from the data line DT can be connected to the first bonding area 31. The first bonding area 31 may include multiple second bonding pins, and the end of the data connection line DL furthest from the data line DT can be connected to the corresponding second bonding pin.

[0077] For example, refer to Figure 5 and Figure 6 The display substrate 10 also includes a second bonding area 32 located in the second bezel area BK2. The end of the data connection cable furthest from the data cable can be connected to the second bonding area 32. The second bonding area 32 is used for bonding with a control chip. The second bonding area 32 can be located between the display area AA and the first bonding area 31. The second bonding area 32 can be connected to the first bonding area 31.

[0078] In one embodiment, such as Figure 5 and Figure 6As shown, the display substrate 10 also includes a second bonding area 32 located in the second bezel area BK2, which is used for bonding and connecting with the control chip. The connection trace 50 also includes a third connection segment 50c, through which the second connection segment 50b is connected to the first bonding pin of the first bonding area 31. The second connection segment 50b and the third connection segment 50c allow the connection trace 50 to avoid the second bonding area 32. If the second connection segment 50b is directly connected to the first bonding pin, the connection trace 50 may pass through the second bonding area 32, affecting the performance of the display substrate 10. By setting the second connection segment 50b to be connected to the first bonding pin of the first bonding area 31 through the third connection segment 50c, the connection trace 50 can avoid the second bonding area 32, ensuring the performance of the display substrate 10.

[0079] For example, the third connecting segment 50c is not collinear with the second connecting segment 50b. The third connecting segment 50c consists of multiple bent line segments relative to the second connecting segment 50b, thereby better avoiding the second binding area 32.

[0080] In one embodiment, the connection trace 50 is also connected to a preset bonding pin of the second bonding area 32, such as... Figure 6 As shown, the connection trace 50 is connected to the preset bonding pin of the second bonding area 32 through the fifth connection segment 55.

[0081] The distance D1 between the endpoint of the first connection segment 50a that connects to the second connection segment 50b (the right endpoint of the first connection segment 50a in the figure) and the first boundary 10a is greater than or equal to 14.22 mm. Typically, the distance D0 between the boundary of the pad area 33 on the side furthest from the first boundary 10a and the first boundary 10a is less than 14.22 mm. By setting the distance D1 to be greater than or equal to 14.22 mm, the second connection segment 50b can completely avoid the pad area 33 when forming the second connection segment 50b. This, in turn, allows the connection trace 50 to completely avoid the fragile area, preventing breakage of the connection trace 50 and ensuring product quality and yield.

[0082] In one embodiment, such as Figures 4-6 As shown, the display substrate 10 also includes a detection pad TP located in the pad area 33. The detection pad TP is connected to the first connection segment 50a via a fourth connection segment 54. The number of detection pads TP can be the same as the number of first connection segments 50a, so that multiple detection pads TP, multiple fourth connection segments 54 and multiple first connection segments 50a can be connected one-to-one.

[0083] The display substrate 10 includes a first metal layer 61, a first insulating layer 62 and a second metal layer 63 stacked together. One of the first connecting segment 50a and the fourth connecting segment 54 may be located in the first metal layer 61 and the other may be located in the second metal layer 63.

[0084] Figure 9 for Figure 4 or Figure 5 An enlarged schematic diagram of part B in the middle. Figure 10 for Figure 9 Schematic diagram of the CC section in the diagram; Figure 11 for Figure 4 or Figure 5 Another enlarged diagram of part B, Figure 12 for Figure 11 A schematic diagram of the C-section. In one embodiment, such as... Figures 9-12 As shown, the display substrate 10 further includes a second insulating layer 64 and a conductive layer 65, which are stacked sequentially on the side of the second metal layer 63 facing away from the first insulating layer 62. The conductive layer 65 includes a transition trace 651, which is connected to the first connecting segment 50a through a first via K1 and to the fourth connecting segment 54 through a second via K2, thereby enabling the first connecting segment 50a to be connected to the fourth connecting segment 54 via the transition trace 651.

[0085] exist Figure 9 and Figure 10 In this embodiment, the first connecting segment 50a is located in the second metal layer 63, and the fourth connecting segment 54 is located in the first metal layer 61. The first via K1 penetrates the second insulating layer 64, and the second via K2 penetrates the second insulating layer 64 and the first insulating layer 62.

[0086] For example, the second insulating layer 64 may include a first passivation layer 641, a planarization layer 642, and a second passivation layer 643 stacked sequentially, such as Figure 10 As shown.

[0087] exist Figure 11 and Figure 12 In this embodiment, the first connecting segment 50a is located in the first metal layer 61, and the fourth connecting segment 54 is located in the second metal layer 63. The first via K1 penetrates the second insulating layer 64 and the first insulating layer 62, and the second via K2 penetrates the second insulating layer 64.

[0088] Figure 13 for Figure 4 or Figure 5 Another enlarged diagram of part B. Figure 14 for Figure 13 A schematic diagram of the CC section. In one embodiment, such as... Figure 13 and Figure 14 As shown, the first connecting segment 50a can be located in the second metal layer 63, and the fourth connecting segment 54 can be located in the first metal layer 61. The first connecting segment 50a is connected to the fourth connecting segment 54 through a third via penetrating the first insulating layer 62.

[0089] Figure 15 for Figure 4 or Figure 5 Another enlarged diagram of section B. Figure 16 for Figure 15 A schematic diagram of the C-section. In one embodiment, such as... Figure 15 and Figure 16 As shown, the first connecting segment 50a can be located in the first metal layer 61, the fourth connecting segment 54 can be located in the second metal layer 63, and the fourth connecting segment 54 is connected to the second connecting segment 50b through a fourth through-hole penetrating the first insulating layer 62.

[0090] In one embodiment, the display substrate 10 includes a thin-film transistor and a pixel electrode layer located in the display area AA. A first metal layer 61 is disposed in the same layer as the gate of the thin-film transistor, a second metal layer 63 is disposed in the same layer as the source and drain of the thin-film transistor, and a conductive layer 65 is disposed in the same layer as the pixel electrode layer.

[0091] In a liquid crystal display panel, the conductive layer 65 can be made of a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO). The conductive layer 65 can be a pixel electrode layer.

[0092] In an organic light-emitting diode (OLED) display panel, the pixel electrode layer can be the anode layer of the OLED display substrate 10.

[0093] In one embodiment, the detection pad TP is located in the pad area 33, and the distance D0 between the edge of the detection pad TP away from the first boundary 10a and the first boundary 10a is less than 14.22 mm. Setting the distance D0 to less than 14.22 mm is beneficial for using conductive cloth in production to reduce the impact of static electricity.

[0094] For example, the display substrate may also include a third border area, which may be located on opposite sides of the display area from the first border area. Signal traces may also be provided in the third border area, and the traces located on both sides of the display area may be symmetrical.

[0095] This disclosure also provides a display panel, see reference. Figures 4-6 and Figure 8 , Figures 4-6 and Figure 8 A partial planar schematic diagram of a display panel is shown. The display panel includes the display substrate 10 as described in the above embodiments of this disclosure, and also includes a mating substrate 20 disposed opposite to the display substrate 10. The first connecting segment 50a is located within the orthographic projection of the mating substrate 20 onto the display substrate 10.

[0096] A cross-sectional view of the display panel of this disclosure embodiment is shown in reference to... Figure 3The mating substrate 20 is smaller than the display substrate 10. Therefore, when the mating substrate 20 and the display substrate 10 are mated, the lower boundary 20b of the mating substrate 20 and the second boundary 10b of the display substrate 10 cannot be aligned, forming a stepped region. The stepped region is a single-layer substrate, and the area near the corner of the stepped region is the stepped corner region. Figure 4 The boundary of the step corner area is roughly indicated by auxiliary lines. The step corner area includes the connection point A between the first boundary 10a and the second boundary 10b. Since the step area is made of single-layer glass, it is prone to breakage during the transportation and handling of the panel.

[0097] By employing the display substrate 10 of this embodiment, the connection trace 50 is moved away from the step corner region near the connection point A of the display substrate 10. Therefore, when a fragment occurs in the step corner region near the connection point A, the impact of the fragment on the connection trace 50 can be reduced, the risk of the connection trace 50 breaking due to the fragment being reduced, signal transmission between the first bonding pin and the signal trace 40 is guaranteed, normal product illumination is ensured, and product yield is improved.

[0098] In this embodiment, the first connecting segment 50a is located within the orthographic projection of the mating substrate 20 onto the display substrate 10. Thus, the mating substrate 20 can cover the first connecting segment 50a, thereby covering part of the connecting traces 50 in the second frame area BK2. This reduces the length of the connecting traces 50 exposed in the step area, making the connecting traces 50 further away from the corner area of ​​the step, further reducing the risk of the connecting traces 50 breaking due to fragments, and improving the overall product yield.

[0099] In a liquid crystal display panel, the display substrate 10 can be an array substrate, and the mating substrate 20 can be a color filter substrate.

[0100] In an exemplary embodiment, the first insulating layer 62, the first passivation layer, and the second passivation layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be single-layer, multi-layer, or composite layers. The first metal layer 61 and the second metal layer 63 may be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be single-layer structures or multi-layer composite structures, such as Ti / Al / Ti, etc.

[0101] Based on the inventive concept of the foregoing embodiments, this disclosure also provides a display device, which includes a display panel employing the foregoing embodiments. The display device can be any product or component with display functionality, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0102] In the description of this specification, it should be understood that the terms "center," "longitudinal," "transverse," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0103] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, "multiple" means two or more, unless otherwise explicitly specified.

[0104] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a communication connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0105] In this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0106] The foregoing disclosure provides many different implementations or examples for carrying out different structures of this disclosure. To simplify this disclosure, the components and arrangements of specific examples are described above. Of course, these are merely examples and are not intended to limit this disclosure. Furthermore, reference numerals and / or reference letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various implementations and / or arrangements discussed.

[0107] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any person skilled in the art can easily conceive of various variations or substitutions within the technical scope disclosed in this disclosure. Different parts of different embodiments can be combined with each other without conflict, and these should all be covered within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display substrate, characterized by, The display substrate comprises a display area, a first frame area and a second frame area, the first frame area is located between the display area and a first boundary of the display substrate, the second frame area is located between the display area and a second boundary of the display substrate, and the first boundary is adjacent to and connected with the second boundary. A signal trace is located in the first frame area and extends towards the second frame area. A first binding area is located in the second frame area and comprises a first binding pin. A connection trace comprises a first connection segment and a second connection segment, the first connection segment extends from one end of the signal trace close to the second boundary towards the middle of the second frame area, and is connected with the first binding pin through the second connection segment, the included angle between the first connection segment and the first boundary is greater than the included angle between the second connection segment and the first boundary. The extension direction of the first connection segment is perpendicular to the extension direction of the first boundary, and the first connection segment is located between the edge line of the display area on the side facing the second boundary and the second boundary.

2. The display substrate of claim 1, wherein, A pad area is further included, the pad area is located in the second frame area and between the first binding area and the first boundary, and the first connection segment is located on the side of the pad area away from the second boundary.

3. The display substrate of claim 1, wherein, The display substrate further comprises a plurality of data lines located in the display area, and further comprises a fan-shaped trace area located in the second frame area, the fan-shaped trace area is provided with a plurality of data connection lines, the plurality of data connection lines are connected one by one with the plurality of data lines, and the connection trace is located outside the fan-shaped trace area.

4. The display substrate of claim 1, wherein, A second binding area located in the second frame area is further included, the second binding area is used for binding connection with a control chip, the connection trace further comprises a third connection segment, the second connection segment is connected with the first binding pin through the third connection segment, and the second connection segment and the third connection segment enable the connection trace to avoid the second binding area.

5. The display substrate of claim 4, wherein, The connection trace is further connected with a preset binding pin of the second binding area.

6. The display substrate of claim 1, wherein, The distance between the end point of the first connection segment connected with the second connection segment and the first boundary is greater than or equal to 14.22 mm. 7.The display substrate of claim 2, wherein, A detection pad located in the pad area is further included, the detection pad is connected with the first connection segment through a fourth connection segment. The display substrate comprises a first metal layer, a first insulating layer and a second metal layer which are arranged in layers, one of the first connection segment and the fourth connection segment is located in the first metal layer, and the other is located in the second metal layer. 8.The display substrate of claim 7, wherein, A second insulating layer and a conductive layer are further included, the second insulating layer and the conductive layer are sequentially arranged on the side of the second metal layer away from the first insulating layer, the conductive layer comprises a relay trace, the relay trace is connected with the first connection segment through a first via, and is connected with the fourth connection segment through a second via. 9.The display substrate of claim 7, wherein, The distance between the edge of the detection pad away from the first boundary and the first boundary is less than 14.22 mm. 10.The display substrate of claim 8, wherein, The display substrate comprises a thin film transistor and a pixel electrode layer in the display area, the first metal layer is arranged in the same layer as a gate electrode of the thin film transistor, the second metal layer is arranged in the same layer as a source electrode and a drain electrode of the thin film transistor, and the conductive layer is arranged in the same layer as the pixel electrode layer. 11.The display substrate of claim 1, wherein, The display substrate comprises a breakable area, the breakable area is located in the second frame area and contains a connection point of the first boundary and the second boundary, and the connection trace avoids the breakable area. 12.The display substrate of claim 1, wherein, The display substrate further comprises a gate driving circuit in the first frame area, and the signal trace is connected with the gate driving circuit.

13. A display panel, characterized by The display substrate comprises a display substrate according to any one of claims 1-12, and a counter substrate arranged opposite to the display substrate, and the first connection section is located in the orthographic projection of the counter substrate on the display substrate.

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