Data input buffer with branched dfe reset path

Abstract

The present disclosure relates to data input buffers with branched DFE reset paths. Systems and methods are provided for a memory device including a decision feedback equalizer (DFE) reset generator configured to transmit a DFE reset signal to a reset tap of a DFE. The memory device also includes an input buffer. The input buffer includes a data branch configured to output data from the input buffer for use downstream in the memory device. The input buffer also includes a DFE reset branch configured to reset the tap of the DFE based on the DFE reset signal. Further, resetting the tap using the DFE reset branch does not reset output data of the data branch.

Description

[0001] Cross-reference of related applications

[0002] This application claims priority to U.S. Provisional Application No. 63 / 495,435, filed April 11, 2023, entitled “Data Input Buffer with a Branched DFE Reset Path,” the entire disclosure of which is incorporated herein by reference for all purposes. Technical Field

[0003] Embodiments of this disclosure generally relate to the field of input buffers and decision feedback equalizers (DFEs) for memory devices. More specifically, embodiments of this disclosure relate to resetting the taps of a DFE and branching the data path and tap path in the input buffer into a DFE reset path. Background Technology

[0004] Semiconductor devices (e.g., memory devices) utilize phase shifts of timing and data signals, data strobes, and / or other signals to perform operations (e.g., write operations). A multi-tap buffer (DFE) can be used to maintain a buffer of several (e.g., four) previous data bits to improve the accuracy of interpreting whether the current bit is high or low. For example, if the DFE stores four previous low data bits, the data line (DQ) will be at a lower voltage level, and the current data bit will be interpreted as logic high or low relative to said level. These multi-tap DFE input buffers are used to allow for resolution with a smaller external data eye. However, as speeds increase in memory devices, timing for resetting the DFE at the correct time becomes more challenging. The correct time is a point after the initial data latch and before or after the output clock that causes data to be output from the input buffer. Due to propagation delays when performing a DFE reset, the DFE can be reset before the pulse of the output clock occurs, especially when additional delays are added to the DFE reset to compensate for additional input buffer delays in high-speed implementations. These propagation delays can increase as additional buffers are included in the memory device to meet the demand for higher clock speeds in the memory device. However, if the DFE reset propagates to / through the input buffer before the output clock pulse, the data in the input buffer may be reset before it is output from the input buffer, which may result in data loss when attempting to capture the data in the input buffer.

[0005] The embodiments disclosed herein may address one or more of the problems raised above. Summary of the Invention

[0006] One aspect of this disclosure relates to a memory device comprising: a decision feedback equalizer (DFE) reset generator configured to transmit a DFE reset signal to a reset tap of the DFE; and an input buffer comprising: a data branch configured to generate output data from the input buffer for downstream use in the memory device; and a DFE reset branch configured to reset the tap of the DFE based on the DFE reset signal, wherein the data branch and the DFE reset branch are configured to receive branch data in parallel.

[0007] Another aspect of this disclosure relates to a semiconductor device comprising: a decision feedback equalizer (DFE) reset generator configured to transmit a DFE reset signal to a reset tap of the DFE; and an input buffer comprising: a data branch including a first set of circuitry configured to receive branch data and output data from the input buffer based on the branch data for downstream use in the semiconductor device; a DFE reset branch including a second set of circuitry configured to receive the branch data and reset the tap of the DFE based on the DFE reset signal, wherein the data branch and the DFE reset branch are configured to receive the branch data in parallel; and a common latch portion configured to generate the branch data.

[0008] Another aspect of this disclosure relates to a method comprising: receiving data (DQ) at an input buffer of a memory device; generating branch data from the DQ using a plurality of latch stages; transmitting the branch data in parallel to a data branch of the input buffer and a decision feedback equalizer (DFE) branch of the input buffer; using the data branch to generate output data of the input buffer based at least in part on the branch data; and using the DFE branch of the input buffer to generate a plurality of taps for the DFE of the memory device based at least in part on the branch data. Attached Figure Description

[0009] Figure 1 This is a simplified block diagram illustrating certain features of a memory device having a decision feedback equalizer (DFE) circuit system according to an embodiment, the decision feedback equalizer circuit system including a DFE that determines the level of data received by the memory device and including a DFE reset circuit system.

[0010] Figure 2 The embodiment includes a DFE reset mask that controls when to enable DFE reset, a DFE reset timing signal generator that controls the reset timing, and a DFE reset generator that uses a DFE reset enable signal and timing signals to generate a DFE reset signal and distribute the DFE reset signal to the DQ phase. Figure 1A schematic diagram of the DFE reset circuit system;

[0011] Figure 3 The DFE reset is selectively enabled by generating a DFE reset enable signal according to the embodiment. Figure 2 A schematic diagram of the DFE reset shield;

[0012] Figure 4 The timing signal for generating the DFE reset is according to the embodiment. Figure 2 A schematic diagram of a DFE reset timing generator;

[0013] Figure 5 According to the embodiment, when the DFE reset shield signal is active, it suppresses signals from... Figure 4 A schematic diagram of the DFE reset timing and suppression circuit for the DFE reset timing signal;

[0014] Figure 6 This is based on the use of the embodiments from Figure 5 A schematic diagram of a DFE reset generator that uses the delayed timing signal of the timing circuit to generate the DFE reset signal;

[0015] Figure 7 This is a schematic diagram of a buffer and chopper circuit according to an embodiment, one of which may be located in Figure 1 In each DQS phase of the memory device to from Figure 6 The reset generator receives the corresponding DFE reset signal to reset the DFE of the DQS phase;

[0016] Figure 8A According to the embodiment, input data is latched using data output from an output clock and using input data strobing. Figure 7 A block diagram of the first part of the input buffer for the DFE reset signal of the buffer and chopper circuit;

[0017] Figure 8B According to the embodiments Figure 8A A block diagram of the second part of the input buffer;

[0018] Figure 9 This is a diagram of a four-phase generation circuit according to an embodiment for generating multiple input data gatings, wherein the input data gatings are transformed into the input data gatings of FIG8 by phase-dividing the original input data gating clock with multiple input data gatings for capturing DFE data;

[0019] Figure 10 This is a timing diagram of the input buffer of FIG8 using the DFE reset signal, output clock, and input data gating of FIG8 according to an embodiment;

[0020] Figure 11This is a diagram of a four-phase generation circuit according to an embodiment for generating multiple input data gatings, wherein the input data gatings are transformed into the input data gatings of Figure 8 by phase-dividing the original input data gating clock with multiple input data gatings used to capture DFE data and individually output data and tap data; and

[0021] Figure 12 According to the embodiment, the separation of data output and tap data output is achieved by dividing the DFE reset path. Figure 7 Block diagram of the input buffer for the DFE reset signal of the buffer and chopper circuit. Detailed Implementation

[0022] One or more specific embodiments will be described below. To provide a concise description of these embodiments, not all features of the actual implementation are described in this specification. It should be understood that, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developer's specific goals, such as complying with system-related and business-related constraints that may vary with the implementation. Furthermore, it should be understood that this development effort may be complex and time-consuming, but will still be a routine design, fabrication, and manufacturing task for those of ordinary skill in the art to which this disclosure pertains.

[0023] A decision feedback equalizer (DFE) can utilize a DFE buffer to track previous data levels to interpret incoming data levels. Between write operations, a DFE reset circuitry can be used to reset this DFE buffer to its initial state (e.g., all high or all low values). Furthermore, as previously mentioned, as part of the DFE reset, the DFE reset circuitry can reset the data in the input buffer, but mistiming of this reset can lead to data loss in the input buffer. To mitigate this issue, the input buffer can be reset independently of the data latched in it. In other words, by separating the tap data from the data path, the tap data can be reset without affecting the data (e.g., the data path is not reset when the DFE is reset). This separation relaxes timing constraints, allowing the DFE reset to initiate faster, while providing more output clock hold time margin and more setup margin for the taps.

[0024] Please refer to the diagram below. Figure 1 This is a simplified block diagram illustrating specific features of the memory device 10. Specifically, Figure 1 The block diagram is a functional block diagram illustrating the specific functionality of the memory device 10. According to one embodiment, the memory device 10 may be a DDR5 SDRAM memory device. Compared to previous generations of DDR SDRAM, various features of DDR5 SDRAM allow for reduced power consumption, more bandwidth, and greater storage capacity.

[0025] Memory device 10 may include a plurality of memory banks 12. For example, memory banks 12 may be DDR5 SDRAM memory banks. Memory banks 12 may be disposed on one or more chips (e.g., SDRAM chips) arranged on a dual in-line memory module (DIMM). As will be understood, each DIMM may contain a plurality of SDRAM memory chips (e.g., x8 or x16 memory chips). Each SDRAM memory chip may contain one or more memory banks 12. Memory device 10 represents a portion of a single memory chip (e.g., an SDRAM chip) having a plurality of memory banks 12. For DDR5, memory banks 12 may be further arranged to form memory bank groups. For example, for 8 gigabyte (Gb) DDR5 SDRAM, the memory chip may contain 16 memory banks 12 arranged in 8 memory bank groups, each memory bank group containing 2 memory banks. For example, for 16 Gb DDR5 SDRAM, the memory chip may contain 32 memory banks 12 arranged in 8 memory bank groups, each memory bank group containing 4 memory banks. Depending on the application and design of the overall system, various other configurations, organization and sizes of the memory bank 12 on the memory device 10 may be utilized.

[0026] The memory device 10 may include a command interface 14 and an input / output (I / O) interface 16. The command interface 14 is configured to provide several signals (e.g., signal 15) from an external device (e.g., a processor or controller 17). The processor or controller 17 may provide various signals 15 (including the DQ signal) to the memory device 10 to facilitate the transfer and reception of data to be written to or read from the memory device 10.

[0027] As will be understood, command interface 14 may include several circuits (e.g., clock input circuitry 19 and command address input circuitry 20) to ensure proper handling of signal 15. Command interface 14 may receive one or more clock signals from an external device. Generally, Double Data Rate (DDR) memory utilizes a differential pair of system clock signals, referred herein as the true clock signal (Clk_t) and the bar clock signal (Clk_c). The positive clock edge of DDR refers to the point where the rising true clock signal Clk_t crosses the falling bar clock signal Clk_c, while the negative clock edge indicates the transition of the falling true clock signal Clk_t and the rise of the bar clock signal Clk_c. Commands (e.g., read commands, write commands, etc.) are typically entered on the positive edge of the clock signal, and data is transmitted or received on both the positive and negative clock edges.

[0028] Clock input circuit 19 receives a true clock signal (Clk_t) and a bar clock signal (Clk_c) and generates an internal clock signal CLK. The internal clock signal CLK is supplied to an internal clock generator, such as a delay-locked loop (DLL) circuit 30. DLL circuit 30 generates a phase-controlled internal clock signal LCLK based on the received internal clock signal CLK. The phase-controlled internal clock signal LCLK is supplied to, for example, I / O interface 16 and used as a timing signal to determine the output timing for reading data.

[0029] The internal clock signal / phase CLK can also be provided to various other components within the memory device 10 and can be used to generate various additional internal clock signals. For example, the internal clock signal CLK can be provided to the command decoder 32. The command decoder 32 can receive command signals from the command bus 34 and can decode the command signals to provide various internal commands. For example, the command decoder 32 can provide command signals to the DLL circuit 30 via bus 36 to coordinate the generation of the phase-controlled internal clock signal LCLK. The phase-controlled internal clock signal LCLK can be used for timing, for example, data via the I / O interface 16.

[0030] Furthermore, the command decoder 32 can decode commands (e.g., read commands, write commands, mode register setting commands, activation commands, etc.) and provide access to a specific memory bank 12 corresponding to the command via bus path 40. As will be understood, the memory device 10 may include various other decoders (e.g., row decoders and column decoders) to facilitate access to the memory bank 12. In one embodiment, each memory bank 12 includes a memory bank control block 22 that provides the necessary decoding (e.g., row decoders and column decoders) and other features (e.g., timing control and data control) to facilitate the execution of commands traveling to and from the memory bank 12.

[0031] Memory device 10 performs operations, such as read and write commands, based on command / address signals received from an external device (e.g., a processor). In one embodiment, the command / address bus may be a 14-bit bus that houses the command / address signals (CA<13:0>). Clock signals (Clk_t and Clk_c) are used to time the command / address signals to command interface 14. The command interface may include command address input circuitry 20, configured to receive and transmit commands to provide access to memory bank 12, for example, via command decoder 32. Additionally, command interface 14 may receive a chip select signal (CS_n). The CS_n signal enables memory device 10 to process commands input to the CA<13:0> bus. Access to a specific memory bank 12 within memory device 10 is encoded along with the command on the CA<13:0> bus.

[0032] Additionally, command interface 14 can be configured to receive several other command signals. For example, a die-terminated command / address (CA_ODT) signal can be provided to facilitate proper impedance matching within memory device 10. A reset command (RESET_n) can be used, for example, to reset command interface 14, status registers, state machines, and the like during power-on. Command interface 14 can also receive a command / address inverted (CAI) signal, which can be provided to, for example, depend on the state of the command / address signals CA<13:0> on the command / address bus for a particular memory device 10. A mirror (MIR) signal can also be provided to facilitate mirroring functionality. Based on the configuration of multiple memory devices in a particular application, the MIR signal can be used to multiplex the signal so that it can be switched to implement a specific route for signals to memory device 10. Various signals can also be provided to facilitate testing of memory device 10, such as a test-enabled (TEN) signal. For example, the TEN signal can be used to put memory device 10 into test mode for connectivity testing.

[0033] Command interface 14 can also be used to provide alarm signals (ALERT_n) to the system processor or controller for certain errors that may be detected. For example, if a cyclic redundancy check (CRC) error is detected, an alarm signal (ALERT_n) can be transmitted from memory device 10. Other alarm signals may also be generated. Furthermore, the bus and pins used for transmitting alarm signals (ALERT_n) from memory device 10 can be used as input pins during certain operations (e.g., connectivity test modes performed using the TEN signal), as described above.

[0034] By transmitting and receiving data signals 44 through I / O interface 16, data can be sent to and from memory device 10 using the commands and timing signals discussed above. More specifically, data can be sent to or retrieved from memory device 12 via data path 46, which includes multiple bidirectional data buses. Data I / O signals, commonly referred to as DQ signals, are typically transmitted and received on one or more bidirectional data buses. Data path 46 can convert DQ signals from serial bus 48 to parallel bus 49.

[0035] For some memory devices, such as DDR5 SDRAM memory devices, I / O signals can be divided into high and low bytes. For example, for x16 memory devices, I / O signals can be divided into high and low I / O signals corresponding to the high and low bytes of, for example, data signals (e.g., DQ<15:8> and DQ<7:0>).

[0036] To allow for higher data rates within memory device 10, some memory devices (e.g., DDR memory devices) may utilize data strobe signals, commonly referred to as DQS signals. The DQS signals are driven by an external processor or controller transmitting data (e.g., for write commands) or by memory device 10 itself (e.g., for read commands). For read commands, the DQS signals are actually additional data output (DQ) signals with a predetermined pattern. For write commands, the DQS signals are used as clock signals to capture the corresponding input data. Similar to the clock signals (Clk_t and Clk_c), the DQS signals may be provided as differential pairs (DQS_t and DQS_c) of data strobe signals to provide differential pair signaling during read and write operations. For some memory devices, such as DDR5 SDRAM memory devices, the differential pairs of DQS signals may be divided into high and low data strobe signals (e.g., UDQS_t and UDQS_c; LDQS_t and LDQS_c) corresponding to the high and low bytes of data transmitted to and from memory device 10.

[0037] The DQS signal is driven by controller 17 to memory device 10 to strobe data writing. When the write operation is complete, controller 17 stops driving the DQS and allows it to float to an indeterminate tri-state. When the DQS signal is no longer driven by controller 17, the external DQS signal from controller 17 to memory device 10 will be in an unknown / indeterminate state. This state can lead to undesirable behavior within memory device 10 because the internal DQS signal within memory device 10 can be at an intermediate level and / or oscillating. In some embodiments, even the external DQS signal may ring at I / O interface 16 when controller 17 stops driving it.

[0038] The DDR5 specification may include short postcode cycles, where the external DQS signal is still driven by controller 17 after the last written data bit, allowing time to disable the write circuitry before controller 17 stops driving the external DQS signal, preventing it from propagating. The DDR5 specification may define short (e.g., 0.5 tCK) and long (e.g., 1.5 tCK) postcode cycles selectable using the mode register. However, short postcode cycles provide a short time to reset the DFE buffer.

[0039] return Figure 1The impedance (ZQ) calibration signal can also be provided to the memory device 10 via I / O interface 16. The ZQ calibration signal can be provided to a reference pin and can be used to tune the output driver and ODT values ​​by adjusting the pull-up and pull-down resistors of the memory device 10 across process, voltage, and temperature (PVT) values. Since PVT characteristics can affect the ZQ resistor value, the ZQ calibration signal can be provided to the ZQ reference pin to adjust the resistance to calibrate the input impedance to a known value. As will be understood, a precision resistor is typically coupled between the ZQ pin on the memory device 10 and GND / VSS external to the memory device 10. This resistor acts as a reference for adjusting the drive strength of the internal ODT and I / O pins.

[0040] Additionally, a loopback signal can be provided to memory device 10 via I / O interface 16. The loopback signal can be used during testing or debugging to configure memory device 10 in a mode where signals loop back through memory device 10 via the same pins. For example, the loopback signal can be used to configure memory device 10 to test its data output. The loopback may include both data and strobe pulses or may only include data pins. This is typically intended for monitoring data captured by memory device 10 at I / O interface 16.

[0041] As will be understood, various other components, such as power supply circuitry (for receiving external VDD and VSS signals), mode registers (for defining various programmable operating modes and configurations), read / write amplifiers (for amplifying signals during read / write operations), and temperature sensors (for sensing the temperature of the memory device 10), may also be incorporated into the memory device 10. Therefore, it should be understood that... Figure 1 The block diagram is provided only to highlight certain functional features of the memory device 10 to aid in the subsequent detailed description.

[0042] DDR5 allows for sequential write operations, meaning data input is seamless between two consecutive writes. In this case, the normal suffix for the first write operation and / or the normal prefix for the second write operation can be completely eliminated. For some sequential write operations, there may be a periodic gap with a specific interval (e.g., 1, 2, 3, or more cycles) between the data burst of the first write operation and the data burst of the second write operation. For these cases, a specified portion of the suffix and / or a portion of the prefix can be used to support these operations.

[0043] In some consecutive write operations, the interval between the first and second write operations allows for the satisfaction of the entire first postcode and second precode, and there may even be additional clock cycles between the two write operations. When there are additional clock cycles between the first postcode and the second precode, the DQS strobe may be disabled (floated) or driven depending on the specification. Therefore, when there is sufficient reset time between write operations, the decision feedback equalizer (DFE) circuitry 50 can use the reset circuitry to reset the DFE 52 at the end of the write burst, but when there is insufficient time between write operations (e.g., less than 2 DQS cycles), the reset may be at least partially suppressed. As described below, when suppressing the DFE reset at the end of the write burst, the DFE buffer can be filled with data strobed during the available DQS cycles. For example, when suppressing the reset of the 4-bit DFE buffer in the case of 2 DQS cycles between write operations, 4 bits of "inactive" data present on the data lines (on the rising and falling edges of the DQS cycle) can be written into the DFE buffer. Furthermore, when the reset of the 4-bit DFE buffer is suppressed in the case of only a single cycle between write operations, 2 bits (on the rising and falling edges of the DQS cycle) can be written into the DFE buffer, even if the buffer may only be half-overwritten by "inactive" data.

[0044] Data path 46, I / O interface 16, and / or command interface 14 may include a DFE circuitry system 50 using a DFE 52. The DFE 52 includes input buffers for a number (e.g., 4) of preceding bits (e.g., high or low) of incoming data bits in a data I / O signal (typically referred to as a DQ signal). The DFE circuitry system 50 uses the preceding level in the DQ signal to improve the accuracy of interpreting incoming bits of the DQ signal. The DFE input buffers determine which input tap to use for the next data input based on the previous input history on the tracking channel. For gapless writes or writes between writes using the intermediate code (e.g., a postcode from an earlier write in a consecutive series and a precode from a later write in a consecutive series) or with a defined switching interval due to insufficient time to complete the switching intermediate code, the DFE 52 can continuously update and track each data bit on the channel. For writes with a sufficiently large interval that has a non-switching intermediate code, the DFE 52 will not be updated during the non-switching time between writes, and its registers will become invalid for the first data bit after collecting the intermediate code. In some embodiments, the non-switching intermediate code may occur when a specified switch occurs between writes, or may be specified to not contain a switch. In some embodiments, the specification of memory device 10 may define maintaining the non-switching intermediate code at a specified value (e.g., data high) such that memory device 10 is aware of the channel history even if memory device 10 does not collect channel history. Memory device 10 can update the DFE history to the specified value without data collection during the non-switching portion of the intermediate code by resetting the register to a specified (e.g., full-high data) state using the reset of DFE 52.

[0045] DFE circuitry 50 includes DFE reset circuitry 54 to perform a reset of DFE 52. However, as previously described, DFE circuitry 50 may not initiate / complete a reset when the reset duration between commands is insufficient. Therefore, DFE circuitry 50 may selectively disable / enable DFE reset based at least in part on the duration between commands.

[0046] Figure 2This is a schematic diagram of an embodiment of the DFE reset circuit system 54. The DFE reset circuit system 54 utilizes a centralized scheme to generate the DFE reset signal faster than by deriving the reset signal using local DS timing in a portion of the phase of each DQ. Instead, the DFE reset circuit system 54 generates DFE reset pulses usable for all phases (e.g., four phases) and is derived directly from an intermediate code DQS counter 70, which is a relative time domain faster than the aforementioned local DS timing used for the data load signal time domain in the memory device. The intermediate code DQS counter 70 can be used to block spurious data strobe signals generated in the unknown DQS region after the write postcode of a write operation and before the write precode of a subsequent write operation. The intermediate code DQS counter 70 effectively justifies the DQS timing, ensuring that all downstream clocks after the filter are considered legitimate clocks, rather than short-duration pulse interference caused by external DQS / DQSF pins in an unknown state. For example, the intermediate code DQS counter 70 can be any suitable intermediate code circuit system, such as the intermediate code circuit system in U.S. Patent Application No. 16 / 834,409, entitled "Write Interamble Filtering," filed March 30, 2020.

[0047] The intermediate code DQS counter 70 sends control signals to one or more DFE reset generators 72, which use the control signals to output a DFE reset signal 73 to a buffer and chopper (BC) circuitry system 74 allocated to each DQ phase 76 of the DFE reset signal 73. For example, eight DQ phases 76 (e.g., four phases having copies for each of the high and low bits) may be allocated to the DFE reset signal 73. For example, this number of DQ phases 76 may be half the prefetch (e.g., 16 bits) of the memory device 10 (e.g., 1 byte).

[0048] As explained, the intermediate code DQS counter 70 may include a DFE reset mask circuit 78, which can be used to control whether the DFE reset generator 72 is enabled to reset DFE 52. By positioning the DFE reset mask circuit 78 in the intermediate code DQ counter 70 according to the DFE reset signal 73, the die area and power consumption of the memory device 10 can be reduced compared to a memory device that includes the DFE reset mask circuit 78 in each DQ path. The intermediate code DQS counter 70 further includes a DFE reset timing signal generator 80, which is used to send timing signals to control the operation of the DFE reset generator 72.

[0049] Figure 3This is a schematic diagram of an embodiment of the DFE reset shield circuit 78. As illustrated, the DFE reset shield circuit 78 includes a NAND gate 100 that receives a TwoGapWrites signal 102 indicating the presence of two clock cycles between write operations. The NAND gate 100 also receives a WPre4 signal 104. The WPre4 signal 104 indicates that the memory device 10 is set to a longer write prepend mode (e.g., write prepend 4) than a shorter programmable mode of other write prepends (e.g., write prepend 2 or 3). The longer write prepend has one more DQS switch than the shorter write prepend, so consecutive writes can be spaced one more cycle in WPRE=4 and have a fully switched write intermediate code.

[0050] The DFE reset shielding circuit 78 also includes a NOR gate 106 that receives the GaplessWrite signal 108 and the OneGapWrite signal 110. The GaplessWrite signal 108 indicates that there is no clock cycle between consecutive write operations, and the OneGapWrite signal 110 indicates that there is a single clock signal between consecutive write operations.

[0051] The outputs from NAND gate 100 and NOR gate 106 are transmitted to multiplexer 112, which, together with burst chopper signal 114, controls the output of DFE reset enable signal 116. Chopper signal 114 can be a burst chopper signal indicating that the corresponding write operation uses less (e.g., 8 bits) than the full prefetch (e.g., 16 bits) of memory device 10, the full prefetch indicating that the write operation will inherently have sufficient cycles to reset DFE 52 after the write operation. DFE reset enable signal 116 is transmitted from DFE reset shield circuit 78 to DFE reset generator 72 to control whether DFE reset is enabled.

[0052] Figure 4This is a schematic diagram of an embodiment of the DFE reset timing signal generator 80. As illustrated, the DFE reset timing signal generator 80 receives a write end signal 120, a clock 122, a complementary clock 124, and a reset signal 126. The write end signal 120 indicates the end of a write operation. The clock 122 and the complementary clock 124 may be complementary system or local clocks used to control the switching of flip-flops 128, 130, 132, 134, and 136, which are used to buffer the write end signal 120 to generate a CircleWrEnd signal 138 indicating that the write end signal 120 has passed through a set number of flip-flops in the DFE reset timing signal generator 80. Flip-flops 128, 130, 132, and 134 output signals LastBitm3 140, LastBitm2 142, LastBitm1 144, and LastBitm0 146, respectively. LastBitm0 146 is the last bit minus zero cycles, LastBitm1 144 is the last bit minus one cycle, LastBitm2 142 is the last bit minus two clock cycles, and LastBitm3 is the last bit minus three clock cycles. In some embodiments, the output signals LastBitm3 140, LastBitm2 142, LastBitm1 144, and LastBitm0 146 can be amplified using one or more inverters 150 for transmission to other parts of the memory device 10 and / or inverted signals to obtain appropriate logic values.

[0053] The write end signal 120 and the outputs of flip-flops 128 and 132 are transmitted to multiplexer 152, which uses Add0 signal 154, Add1 signal 156 and Add2 signal 158 to select among the signals, which control how many flip-flops are included in the transmission of input 160 to control how many clock signals are added to write end signal 120 before being transmitted to flip-flop 136 to output CircleWrEnd signal 138.

[0054] Figure 5This is a schematic diagram of an embodiment of a DFE reset timing and suppression circuit 170 for delaying the output signals LastBitm3 140, LastBitm2 142, LastBitm1 144, and LastBitm0 146 from a DFE reset timing signal generator 80. The DFE reset timing and suppression circuit 170 may be located in the DFE reset generator 72 or in another location within the DFE reset circuit system 54. The output signals LastBitm3 140, LastBitm2 142, LastBitm1 144, and LastBitm0 146 are gated using corresponding NOR gates 172, 174, 176, and 178, which selectively enable the corresponding output signals LastBitm3 140, LastBitm2 142, LastBitm1 144, and LastBitm0 146 based on the value of the DFE reset enable signal 116. Specifically, the output signals LastBitm3 140, LastBitm2 142, LastBitm1 144 and LastBitm0 146 are selectively enabled by the DFE reset enable signal 116 to enable or disable the generation of the corresponding output signals DlydLastBitm3 182, DlydLastBitm2 184, DlydLastBitm1 186 and DlydLastBitm0 188.

[0055] Figure 6 This is a schematic diagram of an embodiment of a reset generator 200, which may be part of a DFE reset generator 72. As illustrated, the reset generator 200 receives a burst chop signal 114 and a complementary chop signal 202 that is complementary to the burst chop signal 114. The reset generator 200 also receives a FastDS180leads540 signal 204 indicating which phase of the DQS is first received for the corresponding write operation. The reset generator 200 further receives a CRC enable signal 206 indicating whether CRC is enabled for a write operation. The FastDS180leads540 signal 204 and the CRC enable signal 206 are inverted using inverters 208 and 210, wherein the inverted and non-inverted FastDS180lead540 signal 204 and the CRC enable signal 206 are respectively supplied to XOR gates 212 and 214. The output of XOR gate 212 is fed to NOR gates 216, 218, 220, and 222. NOR gates 216, 218, 220, and 222 also receive burst chopping signal 114. The output of XOR gate 214 is transmitted to NAND gates 224, 226, 228, and 230. NAND gates 224, 226, 228, and 230 also receive complementary chopping signal 202.

[0056] The outputs of NOR gate 216 and NAND gate 224 are transmitted to multiplexer 232. Multiplexer 232 uses DlydLastBitm3 182 and DlydLastBitm1 186 to control the output of multiplexer 232 as DFErst0U 234 and DFErst0L 236.

[0057] The outputs of NOR gate 218 and NAND gate 226 are transmitted to multiplexer 238. Multiplexer 238 uses DlydLastBitm2 184 and DlydLastBitm0 188 to control the output of multiplexer 238 as DFErst180U240 and DFErst180L 242.

[0058] The outputs of NOR gate 220 and NAND gate 228 are transmitted to multiplexer 244. Multiplexer 244 uses DlydLastBitm3 182 and DlydLastBitm1 186 to control the output of multiplexer 244 as DFErst360U246 and DFErst360L 248.

[0059] The outputs of NOR gate 222 and NAND gate 230 are transmitted to multiplexer 250. Multiplexer 250 uses DlydLastBitm2 184 and DlydLastBitm0 188 to control the output of multiplexer 250 as DFErst540U252 and DFErst540L 254.

[0060] In some embodiments, DFErst0U 234, DFErst0L 236, DFErst180U 240, DFErst180L242, DFErst360U 246, DFErst360L 248, DFErst540U 252 and DFErst540L 254 can utilize one or more inverters / amplifiers 256 to control the voltage amplitude and / or logic of DFErst0U 234, DFErst0L 236, DFErst180U 240, DFErst180L242, DFErst360U 246, DFErst360L 248, DFErst540U 252 and DFErst540L 254. Each of DFErst0U 234, DFErst180U 240, DFErst360U 246, and DFErst540U 252 corresponds to a corresponding reset of the DQ phase 76 of the "upper" DQ on the first side of the DFE reset circuit system 54. Similarly, each of DFErst0L 236, DFErst180L 242, DFErst360L 248, and DFErst540L 254 corresponds to a corresponding reset of the DQ phase 76 of the "lower" DQ on the second side of the DFE reset circuit system 54.

[0061] As illustrated, the DFE reset generator 72 may correspond to eight phases of DFE processing (e.g., four phases having copies of the upper and lower DQs for the DFE). For example, the upper and lower DQs of the DFE may form bytes. For example, a byte may be a portion (e.g., half) of a prefetch that causes two DFE reset generators 72 to be placed in the memory device 10. Additionally or alternatively, the DFE reset generator 72 may correspond to a different number of bits and / or the entire prefetch of the memory device 10. Regardless of the number of DQ phases 76 driven by the DFE reset generator 72, the DFE reset generator 72 uses the DFE reset enable signal 116 and timing signals (LastBitm3 140, LastBitm2 142, LastBitm1 144, and LastBitm0 146) created in the intermediate code DQS counter 70 to generate a four-phase DFE reset signal for each DQ. For driving purposes, the reset signal can be split into a higher-order signal and a lower-order signal to reduce the driving requirements of each reset signal. In summary, the DFE reset enable signal 116 and timing signals are used to generate DlydLastBitm3 182, DlydLastBitm2 184, DlydLastBitm1 186 and DlydLastBitm0 188, which are then used by the DFE reset generator 72 to generate the DFE reset signal.

[0062] Figure 7 This is a circuit diagram of an embodiment of the buffer and chopper circuit system 74 in the DQ phase 76. The buffer and chopper circuit system 74 receives the DFErst signal 262. For example, the DFErst signal 262 may be DFErst0U 234, DFErst0L 236, DFErst180U 240, DFErst180L 242, DFErst360U 246, DFErst360L 248, DFErst540U 252, or DFErst540L 254 received at the corresponding buffer and chopper circuit system 74 of the corresponding DQ phase 76. After a write operation, the last written bit may be fixed at a certain value. The buffer and chopper circuitry system 74 ensures that the signal is properly driven locally while allowing a wider DFE reset pulse to be transmitted through the DFE reset tree (e.g., using the data input buffer signal 263 across the four DQs in each direction from the DFE reset circuitry system 54). If the data input buffer signal 263 is deactivated, the DFE reset will persist until it is reactivated for the next write operation.

[0063] The buffer and chopper circuit system 74 also includes a split path for the DFErst signal 262. In one path, either the DFErst information 262 or the logic high voltage VDDQ 264 is selectively transmitted from switch 266. VDDQ 264 acts as a deactivation path for DFE reset. Switch 266 is coupled to a series of delays 268 that control the pulse width of the DFErst signal 262 (when the switch transmits the DFErst information 262). Specifically, delay 268 delays the DFErst signal 262 and inverter 270 inverts the DFErst signal 262. The inverted and non-inverted copies of the DFErst information 262 are passed to AND gate 272, which prevents the transmission of the pulse of the DFErst signal 262 for a period of time exceeding the duration set by the series of delays 268. The data input buffer signal 263 is inverted in inverter 274 and transmitted to NOR gate 276. NOR gate 276 ensures that the DFE reset controlled by the FastDFErstF signal 278 persists after the data input buffer signal 263 is disabled until the data input buffer signal 263 is re-enabled for the next write operation. When enabled, the FastDFErstF signal 278 is used to reset the DFE 52 of the corresponding DQ phase 76.

[0064] Figure 8A and 8BA block diagram illustrating input buffer 300 is provided. As previously described, input buffer 300 may be part of DFE 52. Input buffer 300 includes an enable circuitry (ibDQTapLogic) 302 that receives a tap enable signal 303 to enable the transmission of tap signals 304. Each of the tap signals 304 (and its corresponding tap enable signal 303) may correspond to a specific tap. As illustrated, tap signals 304 may be complementary to “p” corresponding to a positive or true signal and “m” corresponding to a negative or bar signal. Tap signals 304 are transmitted to latch stages 306 and 308 (ibDQLatStg1 and ibDQLatStg2) in input buffer 300. As illustrated, since there is not enough time for the signal to propagate before it is used in latch stages 306 or 308, the previous bit (e.g., Tap1p and Tap1m) may be skipped. Instead, latch stage 306 may present a first value (e.g., logic high), and latch stage 308 may present a second value (e.g., logic low), thereby providing two computations that can be selected between them at a later point to provide more time to propagate the previous bit before use. Furthermore, latch stages 306 and 308 may each contain one or more latch stages, for example... Figure 8A The two stages described herein. Latch stages 306 and 308 also receive input data DQ 310 (e.g., Figure 1 (any of DQ<15:0>) and the corresponding data strobe DQSd1 312. For example, as discussed below, DQSd1 312 can be a phased strobe signal from the raw, fast data strobe signal received from the host device at the memory device 10.

[0065] Latch stage 306 receives a high reference voltage (VRHi) 314 because it presents a logic high value. Similarly, latch stage 308 receives a low reference voltage (VRLo) 316. Both latch stages 306 and 308 receive a tap bias 318. In some embodiments, the bias may be the same for both latch stages 306 and 308. Alternatively, at least one of the biases may be different between latch stages 306 and 308. Latch stage 306 transmits an output signal 320 (e.g., complementary signals ypHi and ymHi) and a latch switching signal 350 (e.g., LatTogHi) switched via latch stage 306 based on DQSd1 312. Similarly, latch stage 308 transmits output signal 328 (e.g., complementary signals ypLo and ymLo) and latch switching signal 352 (e.g., LatTogLo) switched by latch stage 308 based on DQSd1 312.

[0066] exist Figure 8BIn this circuit, latch stage 322 receives output signal 320 along with DFE reset signal (DFErst) 324 as input. DFErst 324 can correspond to... Figure 7 The latch stage 322 outputs the DFErst signal 262 and / or the FastDFErstF signal 278 based on the input and DFErst 324. The latch stage 330 receives the output signal 328 along with DFErst 324 as input. The latch stage 330 outputs the ZpLo signal 332 and the complementary ZmLo signal 334 based on the input and DFErst 324.

[0067] Selection circuitry 338 (e.g., ibDQUnrollMux) and selection circuitry 340 (e.g., ibDQUnrollMux) generate Tap2 339 and complementary Tap2F 341 based on the selected input and Tap1 signal 336 (e.g., Tap1p and Tap1m). Selection circuitry 338 and 340 can be any circuitry suitable for selecting between high-presentation-based computation and low-presentation-based computation. For example, selection circuitry 338 and 340 may include multiplexers / demultiplexers or other suitable circuitry for selecting between the outputs of latch stages 322 and 330. If the true signal (e.g., Tap1p) is logic high, then selection circuitry 338 and selection circuitry 340 can select the outputs of latch stages 306 and 322 (e.g., zpHi signal 326 and zmHi signal 327) based on the complementary Tap1 signal 336. Alternatively, if the true signal (e.g., Tap1p) is logic low, then selection circuitry 338 and selection circuitry 340 can select the outputs of latch stages 308 and 330 (e.g., zpLo signal 332 and zmLo signal 334) based on the complementary Tap1 signal 336. Thus, Tap1 (e.g., the previous bit) can be used, even if it might not be usable in latch stages 306 and 308 due to propagation delay.

[0068] Latch switching signals 350 and 352 are transmitted from latch stages 306 and 308 to clock path circuit system 354. Clock path circuit system 354 generates output clock (OutClk) 356 and complementary output clock (OutClkF) 358 based on latch switching signals 350 and 352. Clock path circuit system 354 can also output DQSOut 359 based on latch switching signals 350 and 352.

[0069] Tap2F 341 (or Tap2 339), OutClk 356, and OutClkF 358 are transmitted to the data output flip-flop (DataOutFF) 360, which uses OutClk 356 and OutClkF 358 to latch Tap2F as DataOut 362. Tap2F 341 is also used to drive the remaining tap signal 304 back to other parts of the input buffer 300 via tap driver 364.

[0070] Figure 9 The four-phase generation to be input to DFE 52 is shown. As illustrated in timing diagram 400, memory device 10 uses data (DQ) 402 received from the host device (e.g., via any bit of DQ<15:0>). Memory device 10 also receives data strobes (DS or DQS) 404. Memory device 10 performs phase division of DS 404 among four signals: 406, 408, 410, and 412. Each of the DS signals 406, 408, 410, and 412 is used to capture data in buffer circuitry system 430. Buffer circuitry system receives DQ 402 and reference voltage bus 434 at input buffers 436, 438, 440, and 442. In operation, the rising edge 414 of DS 404 causes pulse 416, used to capture input buffer 436 of DQ 402, to output data 444 (e.g., logic high, attributed to a logic high value of DQ 402 when the rising edge 414 occurs). Similarly, the falling edge 418 causes pulse 420, used to capture input buffer 438 of DQ 402, to output data 446 (e.g., logic low, attributed to a logic low value of DQ 402 when the falling edge 418 occurs). Similarly, the rising edge 422 of DS 404 causes pulse 424, used to capture input buffer 440 of DQ 402, to output data 448 (e.g., logic high, attributed to a logic high value of DQ 402 when the rising edge 422 occurs). Similarly, falling edge 426 causes pulse 427 used to capture input buffer 442 to output data 450 (e.g., a logic low attributed to a logic low value of DQ 402 when falling edge 426 occurs).

[0071] Input buffer 436 receives data 450, 448, 446, and 444 (previous values) as the first, second, third, and fourth taps, respectively. Similarly, input buffer 438 receives data 444, 450, 448, and 446 (previous values) as the first, second, third, and fourth taps, respectively. Similarly, input buffer 440 receives data 446, 444, 450, and 448 (previous values) as the first, second, third, and fourth taps, respectively. Similarly, input buffer 442 receives data 448, 446, 444, and 450 (previous values) as the first, second, third, and fourth taps, respectively.

[0072] Figure 10 This is timing diagram 480 illustrating a data strobe (e.g., DS0) 482 with an output clock (OutClk) 484 and a DFErst 486. The DS0 482 can be used with... Figure 8A The same as DQSd1 312. OutClk 484 is compatible with Figure 8B The OutClk 356 is the same. The DFErst 486 is compatible with... Figure 8B The same as DFErst 324. At time 488, DS0 482 is toggleable to indicate data latching in the first latch in the input buffer (e.g., input buffer 300). At time 490, DFErst 486 occurs before time 492, when OutClk 484 is pulsed to indicate data latching in the last latch in the input buffer. In other words, DFErst 486 occurs between the latching in the first latch and the latching in the last latch of the input buffer. As memory devices become faster, the delay between the first latch and the last latch of the input buffer continues to increase. As previously stated, DFErst 486 must occur after time 488 and may occur before OutClk 484 is pulsed. However, if DFErst 486 is pulsed too early before OutClk 484 is pulsed, the data state of the input buffer may be reset before OutClk 484 can correctly capture the final data bits. In other words, Figure 8B Tap2F 341 must be held until OutClk 484 pulses. The DFErst 486 pulse appears after each successful write (non-switching intermediate code case). In the most tightly packed intermediate code write scenario, Figure 8BThe DFE reset of the Tap2F 341 occurs after the OutClk 484 switch to capture the final data bit, thus giving the tap signal enough time to set the reset to capture the next bit (e.g., the DS0 482 switch). However, if additional buffering for higher speeds causes the OutClk 484 pulse to be delayed to time 494, then the DFE reset in the input buffer may cause the data ( Figure 8B The Tap2F 341 is reset before it is latched from the input buffer.

[0073] To address this narrow time window and allow for more OutClk 484 hold time and more tap setting margin for future data bit captures, memory device 10 can decouple data from DFE reset. By decoupling DFE reset from data, DFE reset can occur faster relative to OutClk 484 switching without affecting data in the input buffer. In other words, the input buffer can provide separate branch paths for data and DFE reset. For example, Figure 11 Showing ready and Figure 10The timing diagram 400 is equivalent to the timing diagram 500 input to the 4-phase generation diagram of DFE 52. As illustrated in timing diagram 500, memory device 10 uses data (DQ) 402 received from the host device (e.g., via any bit of DQ<15:0>). Memory device 10 also receives data strobes (DS or DQS) 404. Memory device 10 performs phase division of DS 404 among the following four signals: 406, 408, 410, and 412. Each of the DS signals 406, 408, 410, and 412 is used to capture data in buffer circuitry system 502. Buffer circuitry system receives DQ 402 and reference voltage bus 434 at input buffers 504, 506, 508, and 510. In operation, the rising edge 414 of DS 404 causes pulse 416, used to capture input buffer 504 of DQ 402, to output data 444 (e.g., logic high, attributed to a logic high value of DQ 402 when the rising edge 414 occurs). Similarly, the falling edge 418 causes pulse 420, used to capture input buffer 506 of DQ 402, to output data 446 (e.g., logic low, attributed to a logic low value of DQ 402 when the falling edge 418 occurs). Similarly, the rising edge 422 of DS 404 causes pulse 424, used to capture input buffer 508 of DQ 402, to output data 448 (e.g., logic high, attributed to a logic high value of DQ 402 when the rising edge 422 occurs). Similarly, falling edge 426 causes pulse 427 used to capture input buffer 510 to output data 450 (e.g., a logic low attributed to a logic low value of DQ 402 when falling edge 426 occurs).

[0074] and Figure 9Unlike input buffers 436, 438, 440, and 442, input buffers 504, 506, 508, and 510 output tap data independently of their corresponding output data. Specifically, input buffer 504 outputs tap data 512, input buffer 506 outputs tap data 514, input buffer 508 outputs tap data 516, and input buffer 510 outputs tap data 518. Unless a DFE reset occurs, the output data and output tap data from each input buffer can be the same, but the output tap data is fed back as tap signal 304. For example, input buffer 504 receives tap data 518, 516, 514, and 512 (previous values) as the first, second, third, and fourth taps, respectively. Similarly, input buffer 506 receives tap data 512, 518, 516, and 514 (previous values) as the first, second, third, and fourth taps, respectively. Similarly, input buffer 508 receives data 514, 512, 518, and 516 (previous values) as the first, second, third, and fourth taps, respectively. Similarly, input buffer 510 receives data 516, 514, 512, and 518 (previous values) as the first, second, third, and fourth taps, respectively.

[0075] To implement the branch path for data and DFE reset, input buffer 300 can be modified. Figure 12 This describes a branch path similar to the second part of input buffer 300, which is the second part of input buffer 550. Figure 8A The first portion of input buffer 300 can be completely reproduced in branch path input buffer 550. The second portion of branch path input buffer 550 differs from the second portion of input buffer 300 in that branch path input buffer 550 includes additional latch stages 580 and 582, which are not included in the second portion of input buffer 300, as well as additional selection circuitry 592. Once a DFE reset (e.g., DFErst 324) is injected into the flow of branch path input buffer 550, the additional latch stages 580 and 582, along with the additional selection circuitry 592, provide a separate data path for the data. The circuitry prior to the injection point is identical between input buffers, where the branch begins at the injection point.

[0076] Latch stage 322 functions identically to the input buffer 300 in the DFE reset path and the branch path input buffer 550. In other words, latch stage 322 is in the path presenting the previous high bit of the DFE reset, while additional latch stage 580 is in the data path presenting the previous high bit. Additional latch stage 580 receives the same inputs as latch stage 322, except that additional latch stage 580 receives a setting voltage 584 (e.g., VSS or ground) independently of the DFE reset instead of DFErst 324. Additional latch stage 580 outputs a data path version of ZpHi 585 and a complementary data path version of ZmHi 586.

[0077] Latch stage 330 functions identically to the input buffer 300 in the DFE reset path and the branch path input buffer 550. In other words, latch stage 330 is in the path presenting the previous low bit of the DFE reset, while additional latch stage 582 is in the data path presenting the previous low bit. Additional latch stage 582 receives the same inputs as latch stage 330, except that it receives a setting voltage 584 (e.g., VSS or ground) independently of the DFE reset, instead of DFErst 324. Additional latch stage 582 outputs a data path version of ZpLo 588 and a complementary data path version of ZmLo 590.

[0078] Selection circuit systems 338 and 340 function identically in the input buffer 300 and branch path input buffer 550 of the DFE reset path. In other words, selection circuit system 338 selects between a reset version of the ZpHi signal 326 when Tap1p is logic high and a reset version of the ZpLo signal 332 when Tap1p is logic low. Similarly, selection circuit system 340 selects between a reset version of the ZmHi signal 327 when Tap1p is logic high and a reset version of the ZmLo signal 334 when Tap1p is logic low.

[0079] Additional selection circuitry 592 is used in the data path. Additional selection circuitry 592 receives the data path versions of ZmHi 586 and ZmLo 590 along with the Tap1 signal 336. When Tap1p is logic high, additional selection circuitry 592 outputs Tap2DataOutF 594 as the data path version of ZmHi 586. When Tap1p is logic low, additional selection circuitry 592 outputs Tap2DataOutF 594 as the data path version of ZmLo 590. In the branch path input buffer 550, the data output flip-flop (DataOutFF) 360 receives the data version of Tap2F 341 (e.g., Tap2DataOutF 594) from selection circuitry 340 instead of the data version of Tap2F 341. Therefore, the complete data path to DataOut 362 is independent of and unaffected by the DFE reset using DFErst 324. As previously mentioned, this decoupling of the reset from the state of DataOut 362 allows the DFE reset timing to be accelerated without having to worry about resetting the final data bits captured from each stage.

[0080] While various logic low and / or logic high assertion polarities have been discussed previously, in some embodiments, at least some of these polarities may be reversed. Furthermore, although complementary signaling has been discussed throughout the application, in some embodiments, at least some of the complementary signaling may be replaced or supplemented by signaling based on a single signal, and vice versa.

[0081] While this disclosure is readily available in various modifications and alternatives, specific embodiments have been shown by way of example in the drawings and described in detail herein. However, it should be understood that this disclosure is not intended to be limited to the specific forms disclosed. Rather, this disclosure is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of this disclosure as defined by the appended claims.

[0082] The techniques proposed and claimed in this document are referenced and applied to explicitly improve the field of technology and are therefore not abstract, intangible, or purely theoretical practical objects and concrete examples.

Claims

1. A memory device comprising: A decision feedback equalizer (DFE) reset generator, configured to transmit a DFE reset signal to the reset tap of the DFE; and The input buffer includes: A data branch, configured to generate output data from the input buffer for use downstream in the memory device; and A DFE reset branch is configured to reset the tap of the DFE based on the DFE reset signal, wherein the data branch and the DFE reset branch are configured to receive branch data in parallel.

2. The memory device of claim 1, wherein using the DFE reset branch to reset the tap does not reset the output data of the data branch.

3. The memory device of claim 1, wherein resetting the tap using the DFE reset signal does not reset any portion of the data branch.

4. The memory device of claim 1, wherein the input buffer includes an upstream portion of a common portion of the DFE reset insertion point that generates the branch data, and the data branch does not receive the DFE reset.

5. The memory device of claim 4, wherein the common portion includes a first or more latch levels and a second or more latch levels configured to generate the branch data.

6. The memory device of claim 5, wherein the first one or more latch stages are used for the preceding bit of logic high, and the second one or more latch stages are used for the preceding bit of logic low.

7. The memory device of claim 5, wherein the DFE reset branch comprises: A third or more latch stages receive the first output of the first or more latch stages; and A fourth latch stage or more, which receives a second output from the second latch stage or more, wherein the branch data includes the first output and the second output.

8. The memory device of claim 7, wherein the data branch includes a fifth or more latch stages, the fifth or more latch stages receiving the first output and the second output in parallel with the DFE reset branch.

9. The memory device of claim 8, wherein the DFE reset branch includes a selection circuitry to select the first output when the preceding bit is logic high and to select the second output when the preceding bit is logic low.

10. The memory device of claim 9, wherein the selection circuitry is configured to select a positive or true value, and the DFE reset branch includes an additional selection circuitry to select between the first output and the second output to produce a negative or inverted value.

11. The memory device of claim 9, wherein the data branch includes an additional selection circuitry to select between the first output and the second output to generate output data for the input buffer that is not reset by a DFE reset.

12. A semiconductor device comprising: A decision feedback equalizer (DFE) reset generator, configured to transmit a DFE reset signal to the reset tap of the DFE; and The input buffer includes: A data branch, comprising a first set of circuitry configured to receive branch data and, based on the branch data, output data from the input buffer for downstream use in the semiconductor device; A DFE reset branch includes a second set of circuitry configured to receive branch data and reset the taps of the DFE based on the DFE reset signal, wherein the data branch and the DFE reset branch are configured to receive the branch data in parallel; and The common latch section is configured to generate the branch data.

13. The semiconductor device of claim 12, wherein resetting the tap using the second set of circuitry does not reset the output data.

14. The semiconductor device of claim 12, comprising a plurality of input buffers including the input buffer, wherein each of the plurality of input buffers corresponds to a phase of a data strobe DQS for capturing data DQ received from a host device at the semiconductor device.

15. The semiconductor device of claim 14, further comprising an intermediate code DQS counter configured to block pseudo DQS signals that may be generated in an unknown DQS region after a write postcode of a write operation and before a write precode of a subsequent write operation.

16. The semiconductor device according to claim 12, wherein: The first group of circuit systems includes: The first latch stage is configured to receive the branch data and generate a first output; and A first selection circuit system is configured to select among the first outputs as the output data; and The second group of circuit systems includes: A second latch stage, configured to receive the branch data and generate a second output; and A second selection circuit system is configured to select one or more taps of the DFE between the second outputs.

17. A method comprising: Receive data DQ at the input buffer of the memory device; Branch data is generated from the DQ using multiple latch stages; The branch data is transmitted in parallel to the data branch of the input buffer and the decision feedback equalizer (DFE) branch of the input buffer; The data branch is used to generate the output data of the input buffer, at least in part based on the branch data; and The DFE branch of the input buffer is used to generate multiple taps for the DFE of the memory device, at least in part based on the branch data.

18. The method of claim 17, further comprising: The DFE reset signal is received at the input buffer of the memory device; The DFE reset signal is transmitted to the DFE branch of the input buffer; and Reset the plurality of taps of the DFE without resetting the output data.

19. The method of claim 17, wherein the input buffer is one of a plurality of input buffers each corresponding to a different data gating DQS phase of a plurality of DQS.

20. The method of claim 19, further comprising: A DFE reset generator is used to generate additional DFE reset signals for the plurality of DQS phases, wherein the DFE reset signals are; and The corresponding DFE reset signal is used to reset the DFE corresponding to the plurality of DQS phases.

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