Testability Value Calculation Method and System for FPGA Trojan Detection

Abstract

The present invention belongs to the technical field of hardware security, and specifically relates to a testability value calculation method and system for FPGA Trojan detection, aiming to solve the problem that the existing method for obtaining the testability value of an FPGA synthesis netlist cannot be calculated in the early design stage. The present invention includes: initializing all nodes of the FPGA synthesis netlist to obtain an initial netlist; setting CC0(I)=CC1(I)=1 for all primary inputs I of the initial netlist, and setting CO(O)=0 for all primary outputs O of the initial netlist; topologizing the initial netlist with the primary inputs and primary outputs set to obtain a topologized netlist; calculating the topological order of the topologized netlist according to the topologized netlist; calculating the controllability value of each node in turn starting from the primary input based on the topological order; calculating the observability value of each node in turn starting from the primary output based on the controllability value based on the topological order. The present invention can accurately calculate the testability index of the netlist at the primary stage of FPGA design, reducing the cost and risk of later modification.

Description

Background Art

[0002] Field-Programmable Gate Arrays (FPGAs) play a crucial role in various applications due to their high flexibility. Designers and engineers widely choose to use FPGAs because of their reconfigurable nature. However, the high programmability also opens the door to potential security risks, where untrusted third parties may insert malicious modules, namely hardware Trojans, into them.

[0003] Hardware Trojans may have attack functions such as changing functions, stealing information, and reducing reliability, posing a huge threat to personal information security and even national defense security. Moreover, hardware Trojans usually have concealment and rare triggering characteristics, increasing the difficulty of Trojan detection. Therefore, hardware Trojan detection has become a research hotspot in recent years.

[0004] In the research of Trojan detection, the testability value of non-Trojan nodes is significantly lower than that of Trojan nodes. To solve this problem, the SCOAP (Sandia Controllability / Observability Analysis Program) testability metric proposed by Goldstein in 1980 has been widely accepted, and Trojan detection methods based on SCOAP have emerged in an endless stream. However, the calculation method of testability metrics in the FPGA synthesis netlist is not mentioned in the SCOAP testability metric. Summary of the Invention

[0005] To solve the above problems in the prior art, that is, the problem that the existing method for obtaining the testability value of the FPGA synthesis netlist cannot be calculated in the early design stage, the present invention provides a testability value calculation method for FPGA Trojan detection, and the method includes:

[0006] Step S1, initialize all nodes of the FPGA synthesis netlist to obtain an initial netlist;

[0007] Step S2, set CC0(I)=CC1(I)=1 for all primary inputs I of the initial netlist, and set CO(O)=0 for all primary outputs O of the initial netlist;

[0008] Step S3, topologize the initial netlist with the primary inputs and primary outputs set, to obtain a topologized netlist;

[0009] Step S4, calculate the topological order of the topologized netlist according to the topologized netlist;

[0010] Step S5, based on the topological order, calculate the controllability value of each node in turn starting from the primary input;

[0011] Step S6: Based on the topological order, calculate the observability values of each node in sequence starting from the primary output based on the controllability values; the controllability values and observability values are used as testability values.

[0012] Further, the controllability values of each node and the observability values of each node are specifically as follows:

[0013] The controllability values of each node include the controllability value of the look-up table LUT, the controllability value of the carry logic chain CARRY, the controllability value of the flip-flop, and the controllability value of the latch.

[0014] The observability values of each node include the observability value of the look-up table LUT, the observability value of the carry logic chain CARRY, the observability value of the flip-flop, and the observability value of the latch.

[0015] Further, the calculation method of the controllability value is distinguished according to the number of input controllability values when the output of the logic gate can be determined;

[0016] When setting 1 input controllability value can determine the output of the logic gate:

[0017] Output controllability = min(input controllability) + logical depth

[0018] When all inputs are set to the control value to determine the output of the logic gate:

[0019] Output controllability = ∑(input controllability) + logical depth

[0020] When setting the output can be determined by multiple control sets for the logic gate:

[0021] Output controllability = min(input controllability set) + logical depth.

[0022] Further, the calculation method of the controllability value of the look-up table LUT is as follows:

[0023] Find all indexes that make the output value b i = 0(1) according to the look-up table LUT, and record the search index i;

[0024] For each input set (a in , a i(n-1) , …, a i1 ) corresponding to the search index i, calculate the input controllability value of the n-bit wide look-up table LUTn, and add the current logical depth 1 of the look-up table to obtain the input controllability value of the n-bit wide super bid LUTn:

[0025]

[0026]

[0027] Among them, CC0 LUT (O) represents the 0-controllability value of the current node of the LUT, CC1 LUT (O) The 1-controllability value of the current node of the LUT, a ij represents the value taken by the input of the LUT, I k represents the input, I j represents the j-th bit input of the lookup table LUTn with n-bit width, b i represents the value taken by the output corresponding to the i-th element of all inputs, i = 1, 2, …, 2 n where i represents the serial number of the element of the input, I j ∈I k and CC represents the input controllability value. Further, the calculation method of the observability value of the lookup table LUT is as follows:

[0028] CO LUT (I k ) = 1 + CO LUT (O) + min(∑(CCx LUT (I m ) + CCy LUT (O)))

[0029] Among them, CCx LUT (I m ) represents each non-current input value I k except the current input value I m in the truth table when the value taken is x (x = 0, 1), and y in CCy LUT (O) represents the output value taken in the corresponding row in the truth table, and CCy LUT (O) represents the controllability value when the output value taken is y.

[0030] Further, the calculation method of the controllability value of the carry logic chain CARRY is as follows:

[0031] Search for all first input combination pairs that make the addition / subtraction result output terminal of the carry logic chain CARRY zero, O[0] = 0;

[0032] Based on the controllability value of the pair with the minimum controllability value in the first input combination pair, plus the logical depth, obtain the controllability value of the carry logic chain CARRY:

[0033] CC0 CARRY (O[0]) =

[0034] min(CC0 CARRY (S[0]) + CC0 CARRY(CYINIT), CC1 CARRY (S[0]) +

[0035] CC1 CARRY (CYINIT)) + 1

[0036] CC1 CARRY (O[0]) =

[0037] min(CC0 CARRY (S[0]) + CC1 CARRY (CYINIT), CC1 CARRY (S[0]) +

[0038] CC0 CARRY (CYINIT)) + 1

[0039] CC0 CARRY (CO[0]) =

[0040] min(CC0 CARRY (S[0]) + CC0 CARRY (DI[0]), CC1 CARRY (S[0]) +

[0041] CC0 CARRY (CYINIT)) + 1

[0042] CC1 CARRY (CO[0]) =

[0043] min(CC0 CARRY (S[0]) + CC1 CARRY (DI[0]), CC1 CARRY (S[0]) +

[0044] CC1 CARRY (CYINIT)) + 1

[0045] CC0 CARRY (O[1]) =

[0046] min(CC0 CARRY (S[1]) + CC0 CARRY (CO[0]), CC1 CARRY (S[1]) +

[0047] CC1 CARRY (CO[0])) + 2

[0048] CC1 CARRY (O[1]) =

[0049] min(CC0 CARRY (S[1]) + CC1CARRY (CO[0]),CC1 CARRY (S[1])+

[0050] CC0 CARRY (CO[0]))+2

[0051] CC0 CARRY (CO[1])=

[0052] min(CC0 CARRY (S[1])+CC0 CARRY (DI[1]),CC1 CARRY (S[1])+

[0053] CC0 CARRY (CO[0]))+2

[0054] CC1 CARRY (CO[1])=

[0055] min(CC0 CARRY (S[1])+CC1 CARRY (DI[1]),CC1 CARRY (S[1])+

[0056] CC1 CARRY (CO[0]))+2

[0057] CC0 CARRY (O[2])=

[0058] min(CC0 CARRY (S[2])+CC0 CARRY (CO[1]),CC1 CARRY (S[2])+

[0059] CC1 CARRY (CO[1]))+3

[0060] CC1 CARRY (O[2])=

[0061] min(CC0 CARRY (S[2])+CC1 CARRY (CO[1]),CC1 CARRY (S[2])+

[0062] CC0 CARRY (CO[1]))+3

[0063] CC0 CARRY (CO[2])=

[0064] min(CC0 CARRY(S[2])+CC0 CARRY (DI[2]),CC1 CARRY (S[2])+

[0065] CC0 CARRY (CO[1]))+3

[0066] CC1 CARRY (CO[2])=

[0067] min(CC0 CARRY (S[2])+CC1 CARRY (DI[2]),CC1 CARRY (S[2])+

[0068] CC1 CARRY (CO[1]))+3

[0069] CC0 CARRY (O[3])=

[0070] min(CC0 CARRY (S[3])+CC0 CARRY (CO[2]),CC1 CARRY (S[3])+

[0071] CC1 CARRY (CO[2]))+4

[0072] CC1 CARRY (O[3])=

[0073] min(CC0 CARRY (S[3])+CC1 CARRY (CO[2]),CC1 CARRY (S[3])+

[0074] CC0 CARRY (CO[2]))+4

[0075] CC0 CARRY (CO[3])=

[0076] min(CC0 CARRY (S[3])+CC0 CARRY (DI[3]),CC1 CARRY (S[3])+

[0077] CC0 CARRY (CO[2]))+4

[0078] CC1 CARRY (CO[3])=

[0079] min(CC0CARRY (S[3]) + CC1 CARRY (DI[3]), CC1 CARRY (S[3]) +

[0080] CC1 CARRY (CO[2])) + 4

[0081] CC0 CARRY () represents the 0 - controllability value of the carry logic chain CARRY, CC1 CARRY (O[0]) represents the 1 - controllability value of the carry logic chain CARRY, S represents the synchronous setting terminal of the carry logic chain CARRY, CYINIT represents the initialization value of the carry logic chain CARRY, DI represents the data input of the carry logic chain CARRY, CO[] represents the output of the carry logic chain CARRY, and the 1, 2, and 3 in [] represent indexes.

[0082] Furthermore, the calculation method of the observability value of the carry logic chain CARRY is as follows:

[0083] CO CARRY (CYINIT) =

[0084] min(CC0 CARRY (O[0]) + CC0 CARRY (S[0]), CC1 CARRY (O[0]) +

[0085] CC0 CARRY (S[0]), CC0 CARRY (O[0]) + CC1 CARRY (S[0]), CC1 CARRY (O[0]) +

[0086] CC1 CARRY (S[0])) + CO CARRY (O[0]) + 1

[0087] CO CARRY (S[0]) =

[0088] min(CC0 CARRY (O[0]) + CC0 CARRY (CYINIT), CC1 CARRY (O[0]) +

[0089] CC0 CARRY (CYINIT), CC0 CARRY (O[0]) + CC1 CARRY (CYINIT), CC1 CARRY (O[0]) + CC1CARRY (CYINIT)) + CO CARRY (O[0]) + 1

[0090] CO CARRY (S[1]) =

[0091] min(CC0 CARRY (O[1]) + CC0 CARRY (CO[0]), CC1 CARRY (O[1]) +

[0092] CC0 CARRY (CO[0]), CC0 CARRY (O[1]) + CC1 CARRY (CO[0]), CC1 CARRY (O[1]) +

[0093] CC1 CARRY (CO[0])) + CO CARRY (O[1]) + 1

[0094] CO CARRY (S[2]) =

[0095] min(CC0 CARRY (O[2]) + CC0 CARRY (CO[1]), CC1 CARRY (O[2]) +

[0096] CC0 CARRY (CO[1]), CC0 CARRY (O[2]) + CC1 CARRY (CO[1]), CC1 CARRY (O[2]) +

[0097] CC1 CARRY (CO[1])) + CO CARRY (O[2]) + 1

[0098] CO CARRY (S[3]) =

[0099] min(CC0 CARRY (O[3]) + CC0 CARRY (CO[2]), CC1 CARRY (O[3]) +

[0100] CC0 CARRY (CO[2]), CC0 CARRY (O[3]) + CC1 CARRY (CO[2]), CC1 CARRY (O[3]) +

[0101] CC1 CARRY (CO[2]))+CO CARRY (O[3])+1

[0102] CO CARRY (DI[0])=

[0103] min(CC0 CARRY (S[0])+CC0 CARRY (CO[0]),CC0 CARRY (S[0])+

[0104] CC1 CARRY (CO[0]))+CO CARRY (CO[0])+1

[0105] CO CARRY (DI[1])=

[0106] min(CC0 CARRY (S[1])+CC0 CARRY (CO[1]),CC0 CARRY (S[1])+

[0107] CC1 CARRY (CO[1]))+CO CARRY (CO[1])+1

[0108] CO CARRY (DI[2])=

[0109] min(CC0 CARRY (S[2])+CC0 CARRY (CO[2]),CC0 CARRY (S[2])+

[0110] CC1 CARRY (CO[2]))+CO CARRY (CO[2])+1

[0111] CO CARRY (DI[3])=

[0112] min(CC0 CARRY (S[3])+CC0 CARRY (CO[3]),CC0 CARRY (S[3])+

[0113] CC1 CARRY (CO[3]))+CO CARRY (CO[3])+1

[0114] Among them, COCARRY () represents the observability value, CC0 CARRY () represents the 0-controllability value, CC1 CARRY () represents the 1-controllability value, S represents the synchronous setting terminal of the carry logic chain CARRY, CYINIT represents the initialization value of the carry logic chain CARRY, DI represents the data input of the carry logic chain CARRY, O represents the output of the carry logic chain CARRY, and CO[] represents the output of the carry logic chain CARRY. The 1, 2, and 3 in [] represent indexes.

[0115] Furthermore, the calculation methods for the controllability values of the flip-flop and the latch are as follows:

[0116] For the controllability values of the first type of flip-flop FDCE and the first type of latch LDCE:

[0117] CC0(Q) = min(CC0(CLR) + CC0(D) + CC0(C) + CC1(C)

[0118] + CC1(CE), CC1(CLR))

[0119] CC1(Q) = min(CC0(CLR) + CC1(D) + CC0(C) + CC1(C)

[0120] + CC1(CE), CC0(CE))

[0121] For the controllability values of the second type of flip-flop FDPE and the second type of latch LDPE: CC0(Q) = min(CC0(PRE) + CC0(D) + CC0(C) + CC1(C)

[0122] + CC1(CE), CC0(CE))

[0123] CC1(Q) = min(CC0(PRE) + CC1(D) + CC0(C) + CC1(C)

[0124] + CC1(CE), CC1(PRE))

[0125] For the controllability values of the third type of flip-flop FDRE:

[0126] CC0(Q) = min(CC0(R) + CC0(D) + CC0(C) + CC1(C) + CC1(CE), CC1(R))

[0127] CC1(Q) = min(CC0(R) + CC1(D) + CC0(C) + CC1(C) + CC1(CE), CC0(CE))

[0128] For the controllability value of the fourth type of flip - flop FDSE:

[0129] CC0(Q) = min(CC0(S)+CC0(D)+CC0(C)+CC1(C)+CC1(CE), CC0(CE))

[0130] CC1(Q) = min(CC0(S)+CC1(D)+CC0(C)+CC1(C)+CC1(CE), CC1(S))

[0131] Wherein, CC0() represents the 0 - controllability value, CC1() represents the 1 - controllability value, Q represents the output data of the flip - flop or latch, R represents the synchronous reset terminal, C represents the clock terminal, CE represents the clock enable terminal, and PRE represents the asynchronous preset terminal.

[0132] Furthermore, the calculation methods for the observability value of the flip - flop and the observability value of the latch are as follows:

[0133] For the observability value of the first type of flip - flop FDCE and the observability value of the first type of latch LDCE:

[0134] CO(D) = CO(Q)+CC1(C)+CC0(C)+CC0(CLR)+CC1(CE)

[0135] For the observability value of the second type of flip - flop FDPE and the observability value of the second type of latch LDPE:

[0136] CO(D) = CO(Q)+CC1(C)+CC0(C)+CC0(PRE)+CC1(CE)

[0137] For the observability value of the third type of flip - flop FDRE:

[0138] CO(D) = CO(Q)+CC1(C)+CC0(C)+CC0(R)+CC1(CE)

[0139] For the observability value of the fourth type of flip - flop FDSE:

[0140] CO(D) = CO(Q)+CC1(C)+CC0(C)+CC0(S)+CC1(CE)

[0141] Wherein, CO() represents the observability value, CC0() represents the 0 - controllability value, CC1() represents the 1 - controllability value, D represents the input data, Q represents the output data of the flip - flop or latch, R represents the synchronous reset terminal, C represents the clock terminal, S represents the synchronous set terminal, CE represents the clock enable terminal, and PRE represents the asynchronous preset terminal.

[0142] On the other hand, the present invention proposes a testability value calculation system for FPGA Trojan detection.

[0143] An initial netlist acquisition module, configured to initialize all nodes of the FPGA synthesis netlist to obtain an initial netlist.

[0144] An input / output initialization module, configured to set CC0(I)=CC1(I)=1 for all primary inputs I of the initial netlist and CO(O)=0 for all primary outputs O of the initial netlist.

[0145] A topologicalization module, configured to topologicalize the initial netlist with the primary inputs and primary outputs set, to obtain a topologicalized netlist.

[0146] A topological order acquisition module, configured to calculate the topological order of the topologicalized netlist according to the topologicalized netlist.

[0147] A controllability value calculation module, configured to sequentially calculate the controllability values of each node starting from the primary inputs based on the topological order.

[0148] An observability value calculation module, configured to sequentially calculate the observability values of each node starting from the primary outputs based on the topological order and based on the controllability values; the controllability values and observability values are used as testability values.

[0149] Advantages of the present invention:

[0150] (1) The present invention can accurately calculate the testability metrics of the netlist at the primary stage of FPGA design, enabling design engineers to promptly identify potential hardware Trojans. This early intervention strategy reduces the cost and risk of late-stage modifications and accelerates the product development process.

[0151] (2) By incorporating testability values at the initial stage of design, it is ensured that the hardware structure not only meets the functional requirements but also facilitates subsequent testing and verification, enhancing the overall system reliability and maintainability.

[0152] (3) For Trojan detection, it enables researchers to obtain more netlist circuit characteristic values, achieving better feature extraction and Trojan detection on the FPGA synthesis netlist. Description of the Drawings

[0153] By reading the detailed description of the non-limiting embodiments with reference to the following drawings, other features, objectives, and advantages of the present application will become more apparent:

[0154] Figure 1 It is a flowchart of the testability value calculation method for FPGA Trojan detection in an embodiment of the present invention;

[0155] Figure 2 It is a schematic structural diagram of the carry logic chain CARRY4 in an embodiment of the present invention. Specific implementation manners

[0156] The present application will be further described in detail below with reference to the accompanying drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the related invention, rather than limiting the invention. Additionally, it should be noted that, for the sake of convenience of description, only the parts related to the relevant invention are shown in the drawings.

[0157] It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. The present application will be described in detail below with reference to the drawings and embodiments.

[0158] For a clearer description of the testability value calculation method of the present invention for FPGA Trojan detection, the following combines Figure 1 to elaborate on each step in the embodiment of the present invention.

[0159] The testability value calculation method of the present invention for FPGA Trojan detection in the first embodiment includes steps S1 - S6, and each step is described in detail as follows:

[0160] Step S1, initialize all nodes of the FPGA synthesis netlist to obtain an initial netlist;

[0161] Step S2, set CC0(I) = CC1(I) = 1 for all primary inputs I of the initial netlist, and set CO(O) = 0 for all primary outputs O of the initial netlist;

[0162] Step S3, perform topologicalization on the initial netlist with the primary inputs and primary outputs set, to obtain a topologicalized netlist;

[0163] Step S4, calculate the topological order of the topologicalized netlist according to the topologicalized netlist;

[0164] Step S5, based on the topological order, calculate the controllability values of each node in sequence starting from the primary inputs;

[0165] The controllability values of each node include the controllability values of look-up tables (LUTs), the controllability values of carry logic chains (CARRYs), the controllability values of flip-flops, and the controllability values of latches;

[0166] The calculation method of the controllability values is distinguished according to the number of input controllability values when the output of a logic gate can be determined;

[0167] In this embodiment, based on the basic definitions and principles of controllability values and observability values in the SCOAP algorithm, the calculation method of the controllability values of each logic unit can be further derived as:

[0168] According to the definition of the controllability value: To set the value of node N to the combinational logic value 0 (1), the minimum number of assignments required to assign a definite combinational logic value to the relevant nodes is called the controllability value of the combinational logic value 0 (1) of node N, denoted by CC0(N) (CC1(N));

[0169] For the controllability value of logic devices, the SCOAP algorithm stipulates that the calculation formula is divided into:

[0170] When the output of a logic gate can be determined by setting the controllability value of 1 input:

[0171] Output controllability = min(input controllability) + logic depth

[0172] When the output of a logic gate can be determined by setting all inputs to the control value:

[0173] Output controllability = ∑(input controllability) + logic depth

[0174] When the output can be determined by multiple control sets for a logic gate:

[0175] Output controllability = min(input controllability set) + logic depth.

[0176] Furthermore, the calculation method for the controllability value of the lookup table LUT is as follows:

[0177] Find all indexes that make the output value b i = 0 (1) according to the lookup table LUT, and record them as the search index i;

[0178] The truth table of an n-input LUT is shown in Table 1:

[0179] Table 1 Truth table of an arbitrary n-input LUT

[0180]

[0181]

[0182] For the lookup table LUTn (n = 2, 3,..., 6) shown in Table 1, there are 2 n different combination methods. Connect all the b i to obtain a binary number with a length of 2 n which is the initialization vector of the LUT.

[0183] For each input set (a in , a i(n-1) , …, a i1)Calculate the input controllability value of the lookup table LUTn with n-bit width, and add 1 to the current logic depth of the lookup table to obtain the input controllability value of the over-bid LUTn with n-bit width:

[0184]

[0185]

[0186] Among them, CC0 LUT (O) represents the 0-controllability value of the current node of the LUT, CC1 LUT (O) The 1-controllability value of the current node of the LUT, a ij Represents the value taken by the input of the LUT, I k Represents the input, I j Represents the j-th bit input of the lookup table LUTn with n-bit width, b i Represents the value taken by the output corresponding to the i-th element of all inputs, i = 1, 2,..., 2 n , where i represents the serial number of the element of the input, I j ∈I k , CC represents the input controllability value. The essence of this step is to take the minimum value of the controllability values of all input sets corresponding to all i according to the definition, and finally add 1 to the logic depth of the LUT to obtain the 0(1) controllability value of this LUTn unit.

[0187] Take Figure 2 The CARRY structure in as an example. In Figure 2 the inputs are DI\S\CIN, and the outputs are CO\O\COUT(CO3).

[0188] Among them, O[3:0] provides the final result of addition / subtraction; the carry output CO[3:0] provides the carry output for each bit, and CO[3] is equivalent to COUT;

[0189] DI[3:0] is the data input;

[0190] S[3:0] is the selection input; CYINIT is the Carry initialization value. When it is 0, it means Carry does addition, and when it is 1, it means Carry does subtraction.

[0191] A method for obtaining the controllability value of its output can be derived according to the specific calculation method of Carry. Since the input and output of Carry are multi-bit wide, and the generation of each bit will participate in the calculation of the next bit, the logic depth added to each bit is also different.

[0192] To obtain the 0-controllability value of O[0], all input combinations that make O[0]=0 need to be found, that is, S[0]=0 and CYINIT=0, or S[0]=1 and CYINIT=1. Therefore, the 0-controllability value of O[0] is the minimum value of the two combinations plus the logical depth.

[0193] The calculation method for the controllability value of the carry logic chain CARRY is as follows:

[0194] Search for all first input combination pairs that make the addition / subtraction result output terminal of the carry logic chain CARRY zero, O[0]=0;

[0195] Based on the controllability value of the pair with the minimum controllability value in the first input combination pair, plus the logical depth, obtain the controllability value of the carry logic chain CARRY:

[0196] CC0 CARRY (O[0]) = min(CC0 CARRY (S[0]) + CC0 CARRY (CYINIT), CC1 CARRY (S[0]) + CC1 CARRY (CYINIT)) + 1

[0197] CC1 CARRY (O[0]) = min(CC0 CARRY (S[0]) + CC1 CARRY (CYINIT), CC1 CARRY (S[0]) + CC0 CARRY (CYINIT)) + 1

[0198] CC0 CARRY (CO[0]) = min(CC0 CARRY (S[0]) + CC0 CARRY (DI[0]), CC1 CARRY (S[0]) + CC0 CARRY (CYINIT)) + 1

[0199] CC1 CARRY (CO[0]) = min(CC0 CARRY (S[0]) + CC1 CARRY (DI[0]), CC1 CARRY (S[0]) + CC1 CARRY (CYINIT)) + 1

[0200] CC0 CARRY (O[1]) = min(CC0 CARRY (S[1]) + CC0 CARRY(CO[0]),CC1 CARRY (S[1])+CC1 CARRY (CO[0]))+2

[0201] CC1 CARRY (O[1])=min(CC0 CARRY (S[1])+CC1 CARRY (CO[0]),CC1 CARRY (S[1])+CC0 CARRY (CO[0]))+2

[0202] CC0 CARRY (CO[1])=min(CC0 CARRY (S[1])+CC0 CARRY (DI[1]),CC1 CARRY (S[1])+CC0 CARRY (CO[0]))+2

[0203] CC1 CARRY (CO[1])=min(CC0 CARRY (S[1])+CC1 CARRY (DI[1]),CC1 CARRY (S[1])+CC1 CARRY (CO[0]))+2

[0204] CC0 CARRY (O[2])=min(CC0 CARRY (S[2])+CC0 CARRY (CO[1]),CC1 CARRY (S[2])+CC1 CARRY (CO[1]))+3

[0205] CC1 CARRY (O[2])=min(CC0 CARRY (S[2])+CC1 CARRY (CO[1]),CC1 CARRY (S[2])+CC0 CARRY (CO[1]))+3

[0206] CC0 CARRY (CO[2])=min(CC0 CARRY (S[2])+CC0 CARRY (DI[2]),CC1 CARRY (S[2])+CC0 CARRY (CO[1]))+3

[0207] CC1 CARRY(CO[2]) = min(CC0 CARRY (S[2]) + CC1 CARRY (DI[2]), CC1 CARRY (S[2]) + CC1 CARRY (CO[1])) + 3

[0208] CC0 CARRY (O[3]) = min(CC0 CARRY (S[3]) + CC0 CARRY (CO[2]), CC1 CARRY (S[3]) + CC1 CARRY (CO[2])) + 4

[0209] CC1 CARRY (O[3]) = min(CC0 CARRY (S[3]) + CC1 CARRY (CO[2]), CC1 CARRY (S[3]) + CC0 CARRY (CO[2])) + 4

[0210] CC0 CARRY (CO[3]) = min(CC0 CARRY (S[3]) + CC0 CARRY (DI[3]), CC1 CARRY (S[3]) + CC0 CARRY (CO[2])) + 4

[0211] CC1 CARRY (CO[3]) = min(CC0 CARRY (S[3]) + CC1 CARRY (DI[3]), CC1 CARRY (S[3]) + CC1 CARRY (CO[2])) + 4

[0212] CC0 CARRY () represents the 0-controllability value of the carry logic chain CARRY, CC1 CARRY (O[0]) represents the 1-controllability value of the carry logic chain CARRY, S represents the synchronous setting terminal of the carry logic chain CARRY, CYINIT represents the initialization value of the carry logic chain CARRY, DI represents the data input of the carry logic chain CARRY, CO[] represents the output of the carry logic chain CARRY, and 1, 2, and 3 in [] represent the indexes.

[0213] In this embodiment, the calculation methods for the controllability values of the flip-flop and the latch are as follows:

[0214] The logic depth of flip - flops and latches is 0. Except for the reset terminals, the inputs and outputs of different flip - flops and latches are the same. The influence of different reset terminals on the output Q of flip - flops or latches is shown in Table 2;

[0215] Table 2 Influence of Different Reset Terminals on the Output Q of Flip - Flops or Latches

[0216] Logic gate Output after reset FDCE 0 FDPE 1 FDRE 0 FDSE 1 LDCE 0 LDPE 1

[0217] For the controllability values of the first - type flip - flop FDCE and the first - type latch LDCE:

[0218] CC0(Q) = min(CC0(CLR)+CC0(D)+CC0(C)+CC1(C)+CC1(CE), CC1(CLR))

[0219] CC1(Q) = min(CC0(CLR)+CC1(D)+CC0(C)+CC1(C)+CC1(CE), CC0(CE))

[0220] For the controllability values of the second - type flip - flop FDPE and the second - type latch LDPE:

[0221] CC0(Q) = min(CC0(PRE)+CC0(D)+CC0(C)+CC1(C)+CC1(CE), CC0(CE))

[0222] CC1(Q) = min(CC0(PRE)+CC1(D)+CC0(C)+CC1(C)+CC1(CE), CC1(PRE))

[0223] For the controllability values of the third - type flip - flop FDRE:

[0224] CC0(Q) = min(CC0(R)+CC0(D)+CC0(C)+CC1(C)+CC1(CE), CC1(R))

[0225] CC1(Q) = min(CC0(R)+CC1(D)+CC0(C)+CC1(C)+CC1(CE), CC0(CE))

[0226] For the controllability values of the fourth - type flip - flop FDSE:

[0227] CC0(Q) = min(CC0(S)+CC0(D)+CC0(C)+CC1(C)+CC1(CE), CC0(CE))

[0228] CC1(Q) = min(CC0(S) + CC1(D) + CC0(C) + CC1(C) + CC1(CE), CC1(S))

[0229] Among them, CC0() represents the 0-controllability value, CC1() represents the 1-controllability value, Q represents the output data of the flip-flop or latch, R represents the synchronous reset terminal, C represents the clock terminal, CE represents the clock enable terminal, and PRE represents the asynchronous preset terminal.

[0230] Step S6: Based on the topological order, calculate the observability values of each node in sequence starting from the primary output based on the controllability values; the controllability values and observability values are used as testability values.

[0231] The minimum number of times of assigning combinational logic values required for the information of node N to be propagated to the original output is called the combinational observability value of node N, denoted as CO(N).

[0232] In the SCOAP algorithm, it is stipulated that the difficulty of observing an input signal of a logic gate is equal to the observability of the output plus the difficulty of setting other inputs to non-control values, plus the logic depth of the logic device. Therefore, the algorithm for calculating the observability values of each logic unit in the FPGA synthesis netlist is deduced.

[0233] The observability values of each node include the observability value of the lookup table LUT, the observability value of the carry logic chain CARRY, the observability value of the flip-flop, and the observability value of the latch.

[0234] In this embodiment, for the lookup table LUTn, the difficulty of observing a current input value I k (k = 1, …, n) is equal to, for all outputs, the output observability plus the difficulty of setting other inputs to non-control values and taking the minimum value, plus the logic depth 1.

[0235] The calculation method for the observability value of the lookup table LUT is as follows:

[0236] CO LUT (I k ) = 1 + CO LUT (O) + min(∑(CCx LUT (I m ) + CCy LUT (O)))

[0237] Among them, CCx LUT (I m ) represents the controllability value when each non-current input value I k other than the current input value I m takes the value x (x = 0, 1) in the truth table, and CCyLUT The y in (O) represents the output value in a corresponding row of the truth table, CCy LUT (O) represents the controllability value when the output value is y.

[0238] In this embodiment, for the CARRY4 cell, the difficulty of observing one input is equivalent to the output observability plus the difficulty of setting other inputs to non-control values.

[0239] In this embodiment, the method for calculating the observability value of the carry logic chain CARRY is as follows:

[0240] CO CARRY (CYINIT) = min(CC0 CARRY (O[0]) + CC0 CARRY (S[0]), CC1 CARRY (O[0]) + CC0 CARRY (S[0]), CC0 CARRY (O[0]) + CC1 CARRY (S[0]), CC1 CARRY (O[0]) + CC1 CARRY (S[0])) + CO CARRY (O[0]) + 1

[0241] CO CARRY (S[0]) = min(CC0 CARRY (O[0]) + CC0 CARRY (CYINIT), CC1 CARRY (O[0]) + CC0 CARRY (CYINIT), CC0 CARRY (O[0]) + CC1 CARRY (CYINIT), CC1 CARRY (O[0]) + CC1 CARRY (CYINIT)) + CO CARRY (O[0]) + 1

[0242] CO CARRY (S[1]) = min(CC0 CARRY (O[1]) + CC0 CARRY (CO[0]), CC1 CARRY (O[1]) + CC0 CARRY (CO[0]), CC0 CARRY (O[1]) + CC1 CARRY (CO[0]), CC1 CARRY (O[1]) + CC1 CARRY (CO[0])) + CO CARRY (O[1]) + 1

[0243] CO CARRY (S[2]) = min(CC0 CARRY (O[2]) + CC0 CARRY (CO[1]), CC1 CARRY (O[2]) + CC0 CARRY (CO[1]), CC0 CARRY (O[2]) + CC1 CARRY (CO[1]), CC1 CARRY (O[2]) + CC1 CARRY (CO[1])) + CO CARRY (O[2]) + 1

[0244] CO CARRY (S[3]) = min(CC0 CARRY (O[3]) + CC0 CARRY (CO[2]), CC1 CARRY (O[3]) + CC0 CARRY (CO[2]), CC0 CARRY (O[3]) + CC1 CARRY (CO[2]), CC1 CARRY (O[3]) + CC1 CARRY (CO[2])) + CO CARRY (O[3]) + 1

[0245] CO CARRY (DI[0]) = min(CC0 CARRY (S[0]) + CC0 CARRY (CO[0]), CC0 CARRY (S[0]) + CC1 CARRY (CO[0])) + CO CARRY (CO[0]) + 1

[0246] CO CARRY (DI[1]) = min(CC0 CARRY (S[1]) + CC0 CARRY (CO[1]), CC0 CARRY (S[1]) + CC1 CARRY (CO[1])) + CO CARRY (CO[1]) + 1

[0247] CO CARRY (DI[2]) = min(CC0 CARRY (S[2]) + CC0 CARRY (CO[2]), CC0 CARRY (S[2]) + CC1CARRY (CO[2])) + CO CARRY (CO[2]) + 1

[0248] CO CARRY (DI[3]) = min(CC0 CARRY (S[3]) + CC0 CARRY (CO[3]), CC0 CARRY (S[3]) + CC1 CARRY (CO[3])) + CO CARRY (CO[3]) + 1

[0249] where CO CARRY () represents the observability value, CC0 CARRY () represents the 0 - controllability value, CC1 CARRY () represents the 1 - controllability value, S represents the synchronous setting terminal of the carry logic chain CARRY, CYINIT represents the initialization value of the carry logic chain CARRY, DI represents the data input of the carry logic chain CARRY, O represents the output of the carry logic chain CARRY, CO[] represents the output of the carry logic chain CARRY, and the 1, 2, and 3 in [] represent indexes.

[0250] In this embodiment, the calculation methods for the observability values of the flip - flops and the observability values of the latches are as follows:

[0251] For the observability values of the first - type flip - flop FDCE and the first - type latch LDCE:

[0252] CO(D) = CO(Q) + CC1(C) + CC0(C) + CC0(CLR) + CC1(CE)

[0253] For the observability values of the second - type flip - flop FDPE and the second - type latch LDPE:

[0254] CO(D) = CO(Q) + CC1(C) + CC0(C) + CC0(PRE) + CC1(CE)

[0255] For the observability values of the third - type flip - flop FDRE:

[0256] CO(D) = CO(Q) + CC1(C) + CC0(C) + CC0(R) + CC1(CE)

[0257] For the observability values of the fourth - type flip - flop FDSE:

[0258] CO(D) = CO(Q) + CC1(C) + CC0(C) + CC0(S) + CC1(CE)

[0259] Among them, CO() represents the observability value, CC0() represents the 0-controllability value, CC1() represents the 1-controllability value, D represents the input data, Q represents the output data of the flip-flop or latch, R represents the synchronous reset terminal, C represents the clock terminal, S represents the synchronous set terminal, CE represents the clock enable terminal, and PRE represents the asynchronous preset terminal

[0260] Although the various steps are described in the above order in the above embodiments, those skilled in the art can understand that in order to achieve the effects of this embodiment, different steps do not have to be executed in such an order. They can be executed simultaneously (in parallel) or in reverse order, and these simple changes are all within the protection scope of the present invention.

[0261] The testability value calculation system for FPGA Trojan detection according to the second embodiment of the present invention, the system includes:

[0262] An initial netlist acquisition module, configured to initialize all nodes of the FPGA synthesis netlist to obtain an initial netlist;

[0263] An input / output initialization module, configured to set CC0(I)=CC1(I)=1 for all primary inputs I of the initial netlist, and set CO(O)=0 for all primary outputs O of the initial netlist;

[0264] A topology module, configured to perform topology on the initial netlist with the primary inputs and primary outputs set to obtain a topological netlist;

[0265] A topological order acquisition module, configured to calculate the topological order of the topological netlist according to the topological netlist;

[0266] A controllability value calculation module, configured to sequentially calculate the controllability values of each node starting from the primary input based on the topological order;

[0267] An observability value calculation module, configured to sequentially calculate the observability values of each node starting from the primary output based on the topological order and based on the controllability value; the controllability value and the observability value are used as testability values.

[0268] Those skilled in the art of the technical field can clearly understand that for the convenience and conciseness of description, the specific working process and related descriptions of the above-described system can refer to the corresponding process in the foregoing method embodiment, and will not be repeated here.

[0269] It should be noted that the testability value calculation system for FPGA Trojan detection provided in the above embodiments is only illustrated by dividing the above functional modules. In actual applications, the above functions can be allocated to different functional modules according to needs, that is, the modules or steps in the embodiments of the present invention can be further decomposed or combined. For example, the modules in the above embodiments can be combined into one module, or further split into multiple sub-modules to complete all or part of the functions described above. The names of the modules and steps involved in the embodiments of the present invention are only for distinguishing each module or step, and are not regarded as an improper limitation of the present invention.

[0270] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes and related descriptions of the above-described storage device and processing device can refer to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0271] Those skilled in the art should be able to realize that the modules and method steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. The programs corresponding to the software modules and method steps can be placed in a random access memory (RAM), memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, register, hard disk, removable disk, CD-ROM, or any other form of storage medium well-known in the art. To clearly illustrate the interchangeability of electronic hardware and software, the components and steps of each example have been generally described according to their functions in the above description. Whether these functions are executed in the form of electronic hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.

[0272] The terms "first", "second", etc. are used to distinguish similar objects, rather than to describe or represent a specific order or sequence.

[0273] The term "including" or any other similar term is intended to cover non-exclusive inclusion, so that a process, method, article, or device / equipment including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or also includes elements inherent in these processes, methods, articles, or devices / equipment.

[0274] So far, the technical solution of the present invention has been described in conjunction with the preferred embodiments shown in the accompanying drawings. However, it is easily understood by those skilled in the art that the protection scope of the present invention is obviously not limited to these specific embodiments. Without departing from the principle of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will fall within the protection scope of the present invention.

Claims

1. A testability value calculation method for FPGA Trojan detection, characterized in that The method includes: Step S1, initialize all nodes of the FPGA synthesis netlist to obtain an initial netlist; Step S2, set CC0(I)=CC1(I)=1 for all primary inputs I of the initial netlist, and set CO(O)=0 for all primary outputs O of the initial netlist; Step S3, perform topological transformation on the initial netlist with set primary inputs and primary outputs to obtain a topological netlist; Step S4, calculate the topological order of the topological netlist according to the topological netlist; Step S5, based on the topological order, calculate the controllability values of each node in sequence starting from the primary input; Step S6, based on the topological order, calculate the observability values of each node in sequence starting from the primary output based on the controllability values; the controllability values and observability values are used as testability values.

2. The testability value calculation method for FPGA Trojan detection according to claim 1, characterized in that The controllability values of each node include the controllability value of the lookup table LUT, the controllability value of the carry logic chain CARRY, the controllability value of the flip-flop, and the controllability value of the latch; The observability values of each node include the observability value of the lookup table LUT, the observability value of the carry logic chain CARRY, the observability value of the flip-flop, and the observability value of the latch.

3. The testability value calculation method for FPGA Trojan detection according to claim 2, characterized in that The calculation method of the controllability value is distinguished according to the number of input controllability values that can determine the output of the logic gate; When setting 1 input controllability value can determine the output of the logic gate: Output controllability = min(input controllability) + logic depth When all inputs are set to control values to determine the output of the logic gate: Output controllability = ∑(input controllability) + logic depth When setting the output to be determined by multiple control sets for the logic gate: Output controllability = min(input controllability set) + logic depth.

4. The testability value calculation method for FPGA Trojan detection according to claim 3, characterized in that The calculation method of the controllability value of the lookup table LUT is: Find all indices that make the output value b i = 0(1) according to the look-up table LUT, and denote them as search indices i; For the input set (a in , a i(n-1) , …, a i1 ) corresponding to each search index i, calculate the input controllability value of the lookup table LUTn with n-bit width, and add the current logic depth 1 of the lookup table to obtain the input controllability value of the over-bidding LUTn with n-bit width: Among them, CC0 LUT (O) represents the 0-controllability value of the current node of the LUT, CC1 LUT (O) The 1-controllability value of the current node of the LUT, a ij represents the value of the input of the LUT, I k represents the input, I j represents the j-th bit input of the lookup table LUTn with n-bit width, b i represents the value of the output corresponding to the i-th element of all inputs, i = 1, 2, …, 2 n , where i represents the serial number of the element of the input, I j ∈I k , CC represents the input controllability value.

5. The testability value calculation method for FPGA Trojan detection according to claim 4, characterized in that The calculation method of the observability value of the lookup table LUT is: CO LUT (I k ) = 1 + CO LUT (O) + min(∑(CCx LUT (I m ) + CCy LUT (O))) Among them, CCx LUT (I m ) represents the value in the truth table except the current input value I k Every non-current input value other than I m Controllability value when the value is x (x = 0, 1), CCy LUT The y in (O) represents the output value in the corresponding row of the truth table, CCy LUT (O) represents the controllability value when the output value is y.

6. The testability value calculation method for FPGA Trojan detection according to claim 3, characterized in that, The calculation method of the controllability value of the carry logic chain CARRY is: Search all first input combinations that make the addition / subtraction result output terminal of the carry logic chain CARRY be zero, i.e., O[0]=0; Based on the controllability value of the pair with the minimum controllability value in the first input combination, add the logic depth to obtain the controllability value of the carry logic chain CARRY: CC0 CARRY (O[0]) = min(CC0 CARRY (S[0]) + CC0 CARRY (CYINIT), CC1 CARRY (S[0]) +CC1 CARRY (CYINIT)) + 1 CC1 CARRY (O[0]) = min(CC0 CARRY (S[0]) + CC1 CARRY (CYINIT), CC1 CARRY (S[0]) +CC0 CARRY (CYINIT)) + 1 CC0 CARRY (CO[0]) = min(CC0 CARRY (S[0]) + CC0 CARRY (DI[0]), CC1 CARRY (S[0]) +CC0 CARRY (CYINIT)) + 1 CC1 CARRY (CO[0]) = min(CC0 CARRY (S[0]) + CC1 CARRY (DI[0]), CC1 CARRY (S[0]) +CC1 CARRY (CYINIT)) + 1 CC0 CARRY (O[1]) = min(CC0 CARRY (S[1]) + CC0 CARRY (CO[0]), CC1 CARRY (S[1]) + CC1 CARRY (CO[0])) + 2 CC1 CARRY (O[1]) = min(CC0 CARRY (S[1]) + CC1 CARRY (CO[0]), CC1 CARRY (S[1]) + CC0 CARRY (CO[0])) + 2 CC0 CARRY (CO[1]) = min(CC0 CARRY (S[1]) + CC0 CARRY (DI[1]), CC1 CARRY (S[1]) + CC0 CARRY (CO[0])) + 2 CC1 CARRY (CO[1]) = min(CC0 CARRY (S[1]) + CC1 CARRY (DI[1]), CC1 CARRY (S[1]) + CC1 CARRY (CO[0])) + 2 CC0 CARRY (O[2]) = min(CC0 CARRY (S[2]) + CC0 CARRY (CO[1]), CC1 CARRY (S[2]) + CC1 CARRY (CO[1])) + 3 CC1 CARRY (O[2]) = min(CC0 CARRY (S[2]) + CC1 CARRY (CO[1]), CC1 CARRY (S[2]) + CC0 CARRY (CO[1])) + 3 CC0 CARRY (CO[2]) = min(CC0 CARRY (S[2]) + CC0 CARRY (DI[2]), CC1 CARRY (S[2]) + CC0 CARRY (CO[1])) + 3 CC1 CARRY (CO[2]) = min(CC0 CARRY (S[2]) + CC1 CARRY (DI[2]), CC1 CARRY (S[2]) + CC1 CARRY (CO[1])) + 3 CC0 CARRY (O[3]) = min(CC0 CARRY (S[3]) + CC0 CARRY (CO[2]), CC1 CARRY (S[3]) +CC1 CARRY (CO[2]))+4 CC1 CARRY (O[3]) = min(CC0 CARRY (S[3]) + CC1 CARRY (CO[2]), CC1 CARRY (S[3]) +CC0 CARRY (CO[2]))+4 CC0 CARRY (CO[3]) = min(CC0 CARRY (S[3]) + CC0 CARRY (DI[3]), CC1 CARRY (S[3]) +CC0 CARRY (CO[2]))+4 CC1 CARRY (CO[3]) = min(CC0 CARRY (S[3]) + CC1 CARRY (DI[3]), CC1 CARRY (S[3]) +CC1 CARRY (CO[2]))+4 CC0 CARRY () represents the 0-controllability value of the carry logic chain CARRY, CC1 CARRY (O[0]) represents the 1-controllability value of the carry logic chain CARRY, S represents the synchronous setting terminal of the carry logic chain CARRY, CYINIT represents the initialization value of the carry logic chain CARRY, DI represents the data input of the carry logic chain CARRY, CO[] represents the output of the carry logic chain CARRY, and 1, 2, and 3 in [] represent indexes.

7. The testability value calculation method for FPGA Trojan detection according to claim 6, characterized in that The calculation method of the observability value of the carry logic chain CARRY is: CO CARRY (CYINIT) = min(CC0 CARRY (O[0]) + CC0 CARRY (S[0]), CC1 CARRY (O[0]) +CC0 CARRY (S[0]),CC0 CARRY (O[0]) +CC1 CARRY (S[0]),CC1 CARRY (O[0])+CC1 CARRY (S[0])) +CO CARRY (O[0])+1 CO CARRY (S[0]) = min(CC0 CARRY (O[0]) + CC0 CARRY (CYINIT), CC1 CARRY (O[0]) + CC0 CARRY (CYINIT), CC0 CARRY (O[0]) +CC1 CARRY (CYINIT),CC1 CARRY (O[0])+CC1 CARRY (CYINIT))+CO CARRY (O[0])+1 CO CARRY (S[1]) = min(CC0 CARRY (O[1]) + CC0 CARRY (CO[0]), CC1 CARRY (O[1]) + CC0 CARRY (CO[0]), CC0 CARRY (O[1]) +CC1 CARRY (CO[0]),CC1 CARRY (O[1])+CC1 CARRY (CO[0])) +CO CARRY (O[1])+1 CO CARRY (S[2]) = min(CC0 CARRY (O[2]) + CC0 CARRY (CO[1]), CC1 CARRY (O[2]) + CC0 CARRY (CO[1]), CC0 CARRY (O[2]) +CC1 CARRY (CO[1]),CC1 CARRY (O[2])+CC1 CARRY (CO[1])) +CO CARRY (O[2])+1 CO CARRY (S[3]) = min(CC0 CARRY (O[3]) + CC0 CARRY (CO[2]), CC1 CARRY (O[3]) + CC0 CARRY (CO[2]), CC0 CARRY (O[3]) +CC1 CARRY (CO[2]),CC1 CARRY (O[3])+CC1 CARRY (CO[2])) +CO CARRY (O[3])+1 CO CARRY (DI[0]) = min(CC0 CARRY (S[0]) + CC0 CARRY (CO[0]), CC0 CARRY (S[0]) + CC1 CARRY (CO[0])) + CO CARRY (CO[0]) + 1 CO CARRY (DI[1]) = min(CC0 CARRY (S[1]) + CC0 CARRY (CO[1]), CC0 CARRY (S[1]) + CC1 CARRY (CO[1])) + CO CARRY (CO[1]) + 1 CO CARRY (DI[2]) = min(CC0 CARRY (S[2]) + CC0 CARRY (CO[2]), CC0 CARRY (S[2]) +CC1 CARRY (CO[2]))+CO CARRY (CO[2])+1 CO CARRY (DI[3]) = min(CC0 CARRY (S[3]) + CC0 CARRY (CO[3]), CC0 CARRY (S[3]) +CC1 CARRY (CO[3]))+CO CARRY (CO[3])+1 Among them, CO CARRY () represents the observability value, CC0 CARRY () represents the 0-controllability value, CC1 CARRY () represents the 1-controllability value, S represents the synchronous setting terminal of the carry logic chain CARRY, CYINIT represents the initialization value of the carry logic chain CARRY, DI represents the data input of the carry logic chain CARRY, O represents the output of the carry logic chain CARRY, CO[] represents the output of the carry logic chain CARRY, and 1, 2, and 3 in [] represent indexes.

8. The testability value calculation method for FPGA Trojan detection according to claim 3, characterized in that, The calculation method of the controllability values of the flip-flop and the latch is: For the controllability values of the first type of flip-flop FDCE and the first type of latch LDCE: CC0(Q) = min(CC0(CLR) + CC0(D) + CC0(C) + CC1(C) + CC1(CE), CC1(CLR)) CC1(Q) = min(CC0(CLR) + CC1(D) + CC0(C) + CC1(C) + CC1(CE), CC0(CE)) For the controllability values of the second type of flip-flop FDPE and the second type of latch LDPE: CC0(Q) = min(CC0(PRE) + CC0(D) + CC0(C) + CC1(C) + CC1(CE), CC0(CE)) CC1(Q) = min(CC0(PRE) + CC1(D) + CC0(C) + CC1(C) + CC1(CE), CC1(PRE)) For the controllability values of the third type of flip - flop FDRE: CC0(Q) = min(CC0(R) + CC0(D) + CC0(C) + CC1(C) + CC1(CE), CC1(R)) CC1(Q) = min(CC0(R) + CC1(D) + CC0(C) + CC1(C) + CC1(CE), CC0(CE)) For the controllability values of the fourth type of flip - flop FDSE: CC0(Q) = min(CC0(S) + CC0(D) + CC0(C) + CC1(C) + CC1(CE), CC0(CE)) CC1(Q) = min(CC0(S) + CC1(D) + CC0(C) + CC1(C) + CC1(CE), CC1(S)) Where CC0() represents the 0 - controllability value, CC1() represents the 1 - controllability value, Q represents the output data of the flip - flop or latch, R represents the synchronous reset terminal, C represents the clock terminal, CE represents the clock enable terminal, PRE represents the asynchronous preset terminal.

9. The testability value calculation method for FPGA Trojan detection according to claim 8, characterized in that The calculation methods for the observability values of the said flip - flop and latch are as follows: For the observability values of the first type of flip - flop FDCE and the first type of latch LDCE: CO(D) = CO(Q) + CC1(C) + CC0(C) + CC0(CLR) + CC1(CE) For the observability values of the second type of flip - flop FDPE and the second type of latch LDPE: CO(D) = CO(Q) + CC1(C) + CC0(C) + CC0(PRE) + CC1(CE) For the observability values of the third type of flip - flop FDRE: CO(D) = CO(Q) + CC1(C) + CC0(C) + CC0(R) + CC1(CE) For the observability values of the fourth type of flip - flop FDSE: CO(D) = CO(Q) + CC1(C) + CC0(C) + CC0(S) + CC1(CE) Where, CO() represents the observability value, CC0() represents the 0 - controllability value, CC1() represents the 1 - controllability value, D represents the input data, Q represents the output data of the flip - flop or latch, R represents the synchronous reset terminal, C represents the clock terminal, S represents the synchronous set terminal, CE represents the clock enable terminal, PRE represents the asynchronous preset terminal.

10. A testability value calculation system for FPGA Trojan detection, characterized in that, The said system includes: An initial netlist acquisition module, configured to initialize all nodes of the FPGA synthesis netlist to obtain an initial netlist; An input - output initialization module, configured to set CC0(I) = CC1(I) = 1 for all primary inputs I of the initial netlist, and set CO(O) = 0 for all primary outputs O of the initial netlist; A topology module, configured to perform topology on an initial netlist with the main input and main output set, to obtain a topology netlist; A topological order obtaining module, configured to calculate the topological order of the topology netlist according to the topology netlist; A controllability value calculation module, configured to sequentially calculate the controllability values of each node starting from the main input based on the topological order; An observability value calculation module, configured to sequentially calculate the observability values of each node starting from the main output based on the topological order and based on the controllability value; the controllability value and the observability value are used as testability values.

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