A pulse charging system for capacity-dividing equipment, a battery management system and a charging method

Abstract

The present invention relates to the field of charging, and discloses a pulse charging system for capacity-dividing equipment, a battery management system, and a charging method. In the charging system, an FPGA processor generates a first PWM signal with a predetermined duty cycle through a counter, and a DSP processor generates a second PWM signal with an adjustable duty cycle based on its own PWM module, and sends it to the FPGA processor. The FPGA processor performs a logical operation on the first PWM signal and the second PWM signal to obtain a target PWM signal; the PWM controller drives a gate driver IC according to the target PWM signal, so that the corresponding power switch for connecting the battery charging circuit works according to the duty cycle of the target PWM signal. The present invention mainly realizes the precise control of outputting different charging currents in different charging stages based on the output control of PWM signals based on the FPGA plus DSP dual processor architecture.

Description

Technical Field

[0001] The present invention relates to the field of charging of capacity-dividing equipment, and in particular to a pulse charging system for capacity-dividing equipment, a battery management system and a charging method. Background Art

[0002] Driven by environmental protection policies, global new energy technologies have rapidly emerged and continued to innovate. New energy vehicles (such as electric vehicles) with long driving range have been launched one after another, which has greatly alleviated people's anxiety about the short driving range of electric vehicles. However, defects such as slow battery charging rate, long charging time, reduced battery life, or weakened battery storage capacity still exist, and there is currently no effective solution to this problem.

[0003] Currently, electric vehicles in the industry use 800V, 220KW high-power charging and high current output to the battery pack. Such fast charging greatly increases the requirements for the charging system.

[0004] The disclosure of the above background technology content is only used to assist in understanding the concept and technical solution of the present application. It does not necessarily belong to the prior art of the present application, nor does it necessarily provide technical guidance. In the absence of clear evidence that the above content has been disclosed before the filing date of the present application, the above background technology should not be used to evaluate the novelty and creativity of the present application. Summary of the invention

[0005] The object of the present invention is to provide an improved pulse charging system for a capacity-dividing device to charge a battery quickly and safely.

[0006] To achieve the above object, the technical solution adopted by the present invention is as follows:

[0007] A pulse charging system for a capacity-dividing device, comprising a DSP processor, an FPGA processor, a PWM controller, a gate drive IC and a power switch for connecting a battery charging circuit, wherein the FPGA processor generates a first PWM signal with a predetermined duty cycle through a counter, and the DSP processor generates a second PWM signal with an adjustable duty cycle based on its own PWM module;

[0008] The DSP processor sends the second PWM signal to the FPGA processor, and the FPGA processor performs a logic operation on the first PWM signal and the second PWM signal to obtain a target PWM signal;

[0009] The FPGA processor sends the target PWM signal to the PWM controller, and the PWM controller drives the gate drive IC according to the target PWM signal so that the corresponding power switch operates according to the duty cycle of the target PWM signal.

[0010] Further, based on any one of the above-mentioned technical solutions or a combination of multiple technical solutions, the charging system pre-designs the charging process into multiple charging stages, and the charging currents of at least two adjacent charging stages are different;

[0011] During the charging process, the PWM module of the DSP processor always acts on the first PWM signal generated by the FPGA processor, and the PWM signal for controlling charging is always sent by the FPGA processor to the PWM controller;

[0012] According to the charging current of the next charging stage, the DSP processor determines in advance the duty cycle setting value of its own PWM module in the next charging stage, and sends it to the FPGA processor;

[0013] The FPGA processor performs logic operations to obtain a target PWM signal for the next charging stage and stores it in a FIFO buffer area;

[0014] At the end of the current charging phase, the FPGA processor directly switches to the target PWM signal in the FIFO buffer area.

[0015] Further, according to any one of the above-mentioned technical solutions or a combination of multiple technical solutions, after directly switching to the target PWM signal in the FIFO buffer area, it also includes:

[0016] The DSP processor determines in advance again a new duty cycle setting value for the next charging stage;

[0017] The FPGA performs logic operation again to obtain a new target PWM signal for the next charging stage, and updates the target PWM signal in the FIFO buffer area to the new target PWM signal.

[0018] Further, based on any one of the technical solutions or a combination of multiple technical solutions mentioned above, the charging stage at least includes a constant current charging stage, a constant voltage charging stage and a trickle charging stage in sequence, wherein the PWM duty cycle setting value of the constant current charging stage is greater than the PWM duty cycle setting value of the constant voltage charging stage, and the PWM duty cycle setting value of the trickle charging stage is less than the PWM duty cycle setting value of the constant voltage charging stage.

[0019] Further, based on any one of the technical solutions or a combination of multiple technical solutions described above, the charging system further includes a process step acquisition module, which is configured to collect voltage and / or current information of the battery during the charging process and send the collected information to the DSP processor;

[0020] The DSP monitors the charging state of the battery in real time according to the information collected by the process step collection module to determine whether the current charging stage is completed to enter the next charging stage.

[0021] Further, based on any one of the technical solutions or a combination of multiple technical solutions described above, the charging system also includes a multi-channel control circuit, the DSP processor is connected to multiple battery data channels through the multi-channel control circuit, and the multi-channel control circuit is configured to control the analog switches set on each battery data channel to control the data transmission of each battery data channel.

[0022] Further, based on any one of the technical solutions or a combination of multiple technical solutions mentioned above, the charging system also includes an RS485 circuit module, which is configured to provide an RS485 communication interface to perform data communication with the intermediate computer by connecting the RS485 communication line.

[0023] According to another aspect of the present invention, a battery management system is provided, comprising a host computer, a middle computer and the capacity division device pulse charging system as described above, wherein the middle computer communicates with the capacity division device pulse charging system via RS485, and the middle computer communicates with the host computer via Ethernet.

[0024] Further, based on any one of the above-mentioned technical solutions or a combination of multiple technical solutions, the intermediate computer is configured with 64 RS485 interfaces to be able to simultaneously connect 64 of the divided capacity equipment pulse charging systems;

[0025] The battery management system also includes a bidirectional inverter power supply connected to an external power grid, and the bidirectional inverter power supply provides a DC power supply for the pulse charging systems of each capacity-dividing device.

[0026] According to another aspect of the present invention, a pulse charging method for a capacitance-dividing device is provided, comprising the following steps:

[0027] The charging process is designed to be divided into multiple charging stages, and the charging currents of at least two adjacent charging stages are different;

[0028] The FPGA processor generates a first PWM signal with a predetermined duty cycle through a counter; the PWM module of the DSP processor generates a second PWM signal with an adjustable duty cycle, which always acts on the first PWM signal generated by the FPGA processor;

[0029] According to the charging current of the next charging stage, the DSP processor determines in advance the duty cycle setting value of its own PWM module in the next charging stage, and sends it to the FPGA processor; the FPGA processor performs logical operations to obtain the target PWM signal of the next charging stage, and saves it in the FIFO buffer area;

[0030] At the end of the current charging phase, the FPGA processor directly switches to the target PWM signal in the FIFO buffer area;

[0031] The PWM controller controls the duty cycle of the power switch of the battery charging circuit according to the target PWM signal.

[0032] The beneficial effects brought by the technical solution provided by the present invention are as follows:

[0033] a. Pulse charging can use higher currents for charging without damaging the battery, thereby shortening the charging time and extending the battery life. By reducing heat accumulation and optimizing the charging process, pulse charging helps slow down the battery aging process and extend its service life;

[0034] b. The PWM signal generated by the DSP processor and the PWM signal generated by the FPGA processor logic control each other and provide status feedback. The battery charge state is different, and the required charging current range is different, so that the battery charging current presents a pulse state, and the constant current positive pulse charging has different charging currents in different time periods;

[0035] c. The FPGA processor generates pulses through a counter to ensure precise control of PWM; the DSP processor sets the duty cycle of the next charging stage in advance and caches it in the FPGA, so that the transition between the two charging stages is seamless, ensuring the stability of the charging current and preventing transient changes in current and voltage that affect the health of the battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0037] Figure 1 A schematic diagram of the architecture of a pulse charging system for a capacity-dividing device provided by an exemplary embodiment of the present invention;

[0038] Figure 2 A basic architecture diagram of a battery management system provided for an exemplary embodiment of the present invention;

[0039] Figure 3 For the corresponding Figure 2 Schematic diagram of the specific architecture;

[0040] Figure 4A schematic diagram of the corresponding relationship between the PWM waveform and the charging current at different charging stages provided by an exemplary embodiment of the present invention;

[0041] Figure 5 A schematic flow chart of a pulse charging method for a capacity division device provided as an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0042] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0043] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, device, product or equipment that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0044] Capacity grading equipment usually refers to equipment used to test the capacity and performance of batteries during the production process of lithium batteries. The process of lithium battery capacity grading includes charging and discharging the battery in a standardized manner, and measuring the time taken to fully discharge the battery multiplied by the discharge current to determine the battery capacity. Only batteries with a capacity that meets or exceeds the designed capacity are considered qualified. Capacity grading equipment usually needs to charge and discharge a large number of batteries at the same time, and accurately measure and analyze the capacity and performance of each battery through a computer management system.

[0045] This embodiment provides a pulse charging system for a high-precision large-current capacity-dividing device, which is an advanced battery charging management system, mainly used to improve battery charging efficiency and extend battery life. This type of system integrates modern power electronics technology, control theory, and high-precision sensing technology, and aims to achieve efficient and safe charging of batteries by accurately controlling the current and voltage parameters during the charging process. The pulse charging system of the high-precision large-current capacity-dividing device represents the forefront of battery charging technology, and is not only suitable for formation and capacity-dividing testing during battery production, but is also gradually applied to a wider range of fields such as electric vehicle charging stations and energy storage systems.

[0046] The pulse charging system of the high-precision, large-current capacity-dividing equipment represents the forefront of battery charging technology. It can quickly and efficiently charge the battery while extending the battery life. It is not only suitable for formation and capacity-dividing testing during the battery production process, but can also be applied to a wider range of fields such as electric vehicle charging stations and energy storage systems.

[0047] In one embodiment of the present invention, a pulse charging system for a capacitance-dividing device is provided, such as Figure 1 As shown, the pulse charging system includes a DSP processor, an FPGA processor, a PWM controller, a gate drive IC and a power switch for connecting a battery charging circuit, wherein the FPGA processor generates a first PWM signal with a predetermined duty cycle through a counter, and the DSP processor generates a second PWM signal with an adjustable duty cycle based on its own PWM module;

[0048] The DSP processor sends the second PWM signal to the FPGA processor, and the FPGA processor performs a logic operation on the first PWM signal and the second PWM signal to obtain a target PWM signal;

[0049] The FPGA processor sends the target PWM signal to the PWM controller, and the PWM controller drives the gate drive IC according to the target PWM signal so that the corresponding power switch operates according to the duty cycle of the target PWM signal.

[0050] The DSP+FPGA dual processor architecture design is adopted to realize the output control of the PWM signal. While charging with pulse current, the target PWM signal can be adjusted through the adjustable second PWM signal to achieve different charging currents in different charging stages. Specifically, the DSP processor can use a device with model number 320F280049, which mainly generates PWM signals to drive the external MOS and adjust the charging rate at the same time. The PWM signal adjusts the duty cycle to set the output voltage, and the voltage is converted into the output current. The FPGA processor mainly generates PWM signals through the counter. The two PWM signals are processed by logic and the signals after the logic operation are interconnected with the gate drive IC of the subsequent stage to control the power switch (ie, the external MOS) to conduct and realize the charging of the battery (ie, the battery charging circuit is turned on). The FPGA+DSP architecture can mainly achieve precise control, so that the output current is in the form of pulses, and different currents are output at different stages.

[0051] The FPGA processor uses the counter to time the pulse. The pulse generated by the FPGA timing can be used as a carrier for transmission. The PWM signal generated by the FPGA timing can achieve precise power control, making the PWM signal generated by the DSP processor dependent on the operation of the FPGA processor. FPGA is very suitable for implementing this pulse charging function because of its rich internal logic resources and high programmability. By designing a counter that can accumulate clock pulses, the timing is determined according to its size range. The increment counter is used to trigger the pulse when the count value reaches the set value. The PWM pulse signal generated by the FPGA logic through the counter is the basic signal for controlling the external PWM controller. On the PWM signal generated by the logic, the DSP will also generate a PWM signal. The two PWMs are logically ANDed and then output to the PWM controller. This design concept is mainly combined with pulse charging and upgraded on this basis. High-precision control can monitor and feedback the battery charging status in real time to ensure that the current and voltage during the charging process are maintained at the preset precise level. This is crucial to avoid overcharging, overheating and other situations that damage the battery.

[0052] The multi-stage charging strategy combined with PWM (Pulse Width Modulation) technology is an efficient and battery-protecting charging method in the battery charging system. This strategy is particularly suitable for lead-acid batteries, lithium-ion batteries, etc., and optimizes the charging process through different charging stages to ensure fast, safe, and maximize battery life. In one embodiment, the entire charging process is divided into three charging stages: First, the constant current charging stage (strong charging / fast charging stage), that is, when the battery power is low, the charging system charges the battery with a relatively large constant current, the purpose is to quickly restore most of the battery's energy. At this time, the PWM controller maintains the target charging current by adjusting the duty cycle. Even if the battery voltage gradually rises with charging, a constant charging current can be guaranteed. However, the charging current is in the form of pulses, which better controls the polarization effect of the battery and prolongs the battery life. Second, the constant voltage charging stage (balanced charging stage), that is, when the battery voltage reaches the preset conversion point (such as 14.4V for lead-acid batteries or 4.2V for lithium-ion batteries), the charging system switches to the constant voltage mode, and the signal output by the PWM module of the DSP processor itself is logically ANDed with the signal generated by the FPGA processor through the counter, and then the control signal (the target PWM signal) is output. At this time, the duty cycle is adjusted to keep the battery voltage constant, and the current will naturally decrease as the battery power gradually saturates. This charging stage helps the battery cells to achieve balance and prevent overcharging. Third, the floating charging stage (trickle charging stage), that is, after the above two stages, the battery is close to full power, and the charging system enters the floating charging stage, providing a voltage lower than the constant voltage charging and a very low current (usually 1% to 3% of the battery capacity). The PWM controller works at a low duty cycle to maintain the battery fully charged without causing overcharging, which is conducive to prolonging the battery life.

[0053] The DSP processor is combined with complex algorithms, and the charging system can adjust the charging strategy according to the real-time status of the battery, such as dynamically adjusting the pulse width, frequency, duty cycle, etc., to adapt to the different charging stages and changing conditions of the battery. The main goal of setting the FPGA processor is to achieve high-precision pulse control. Through the optimized pulse mode, the charging system of this embodiment can reduce energy consumption and improve the overall energy efficiency while ensuring the charging effect. The PWM module of the DSP processor adjusts the duty cycle, and the FPGA processor is responsible for mode switching and control. The two work together to achieve efficient and smooth charging of the battery, avoiding sudden large currents that affect the battery life.

[0054] In particular, during the charging process, the PWM module of the DSP processor itself always acts on the first PWM signal generated by the FPGA processor, and the PWM signal for controlling charging is always sent by the FPGA processor to the PWM controller;

[0055] According to the charging current of the next charging stage, the DSP processor determines in advance the duty cycle setting value of its own PWM module in the next charging stage, and sends it to the FPGA processor;

[0056] The FPGA processor performs logic operations to obtain a target PWM signal for the next charging stage and stores it in a FIFO buffer area;

[0057] At the end of the current charging phase, the FPGA processor directly switches to the target PWM signal in the FIFO buffer area.

[0058] As described above, the seamless switching of current changes can be achieved through hardware logic processing, which not only improves the charging efficiency, but also improves the stability of the charging current, avoids sudden changes in current and shortens the battery life, and even damages the performance of the capacity division device; compared with the method of using software to control current changes, software control will have certain instability, while the use of hardware logic switching is more stable and easier to implement pulse charging management: the embodiment of the present invention replaces the conventional operation of starting the next charging stage after the first stage of charging is completed, but sets the duty cycle of the next charging stage in advance in the previous stage, and obtains the target PWM signal of the next stage by FPGA processing and saves it in the cache area. While achieving high-precision control of the charging current, in the process of converting different charging stages, this delay is avoided to achieve seamless switching of the charging stage (the hardware delay is negligible), which will not cause the system charging current to be sometimes high and sometimes low, thereby affecting the battery life. Switching the charging stages of different charging currents in this cache form will not cause large currents, and the charging current curve is a smooth line, which greatly improves the battery charging life.

[0059] Traditional battery charging management systems usually use DSP to output PWM signals to drive the control chip to charge the battery. This mode requires adjusting the charging current or voltage, which can be achieved by controlling the PWM duty cycle. However, this mode has disadvantages. During the charging process, the current or voltage is always constant, which greatly reduces the life and endurance of the battery. Another disadvantage is that the DSP outputs a PWM signal to drive the control chip to charge the battery. The charging stage switches too quickly, and the current and voltage change suddenly, making it impossible to smoothly transition to the next charging stage. The FPGA+DSP architecture used in this embodiment uses pulse charging to charge the battery with intermittent current pulses. This method can reduce the polarization phenomenon inside the battery and improve charging efficiency. At the same time, it helps to activate inactive substances inside the battery, reduce battery water loss, and increase battery capacity.

[0060] An embodiment of the present invention is Figure 1As shown, the charging system also includes a step acquisition module (current sensor and voltage sampling circuit, etc.), which uses an external high-precision 24-bits ADC (ADS131M02) to collect the voltage and / or current information of the battery of each channel, and sends the collected information to the DSP processor. The current and voltage values ​​of the channel are amplified by the operational amplifier and selected by the analog switch, and then the voltage and current values ​​are collected by the DSP processor to further realize alarms for various abnormal conditions, such as undervoltage alarm, overvoltage alarm, current abnormality alarm, overcapacity alarm, and deviation from average voltage alarm.

[0061] The DSP monitors the charging state of the battery in real time according to the information collected by the process step collection module to determine whether the current charging stage is completed to enter the next charging stage.

[0062] Further, after directly switching to the target PWM signal in the FIFO buffer area, the method further includes:

[0063] The DSP processor determines in advance again a new duty cycle setting value for the next charging stage;

[0064] The FPGA performs logic operation again to obtain a new target PWM signal for the next charging stage, and updates the target PWM signal in the FIFO buffer area to the new target PWM signal.

[0065] The system can generate precisely controlled current pulses through DSP+FPGA dual processors. These pulses can be very short but extremely strong, thereby reducing battery heating and polarization while accelerating the migration of lithium ions and improving charging efficiency. At the same time, it integrates high-precision current sensors and voltage sampling circuits, combined with advanced digital signal processing technology, to monitor the battery status in real time to ensure that the output of current and voltage strictly conforms to the preset charging curve; it adopts intelligent charging strategies and multi-stage charging algorithms, such as pre-charging, constant current charging, constant voltage charging and trickle charging, etc., to automatically adjust pulse parameters according to the charging status of the battery to achieve the purpose of optimizing battery performance and life. Built-in temperature monitoring ensures that the battery temperature remains within a safe range during charging. At the same time, it has a variety of safety functions such as short-circuit protection, over-temperature protection, over-voltage protection, etc. to prevent any potential risks during charging, and optimize energy efficiency. By optimizing pulse frequency, width and amplitude, it reduces invalid energy loss and improves the energy utilization efficiency of the entire charging system. Such systems are widely used in electric vehicle fast charging, aerospace, military equipment, large energy storage systems and high-end consumer electronic products, and are of great significance for improving charging efficiency, shortening charging time, maintaining battery health and extending service life.

[0066] The embodiment of the present invention also provides a pulse charging method for a capacitance-dividing device, such as Figure 5As shown, the method comprises the following steps:

[0067] The charging process is designed to be divided into multiple charging stages, and the charging currents of at least two adjacent charging stages are different;

[0068] The FPGA processor generates a first PWM signal with a predetermined duty cycle through a counter; the PWM module of the DSP processor generates a second PWM signal with an adjustable duty cycle, which always acts on the first PWM signal generated by the FPGA processor;

[0069] The first charging stage is started, and the FPGA processor outputs a target PWM signal corresponding to the current stage, that is, a logic AND operation is performed on the first PWM signal and the second PWM signal, and the obtained target PWM signal meets the charging current required in the first charging stage;

[0070] According to the charging current of the next charging stage, the DSP processor determines in advance the duty cycle setting value of its own PWM module in the next charging stage, and sends it to the FPGA processor; the FPGA processor performs logical operations to obtain the target PWM signal of the next charging stage, and saves it in the FIFO buffer area;

[0071] If the current charging stage has not yet ended, the target PWM signal of the current charging stage is maintained;

[0072] At the end of the current charging phase, the FPGA processor directly switches to the target PWM signal in the FIFO buffer area;

[0073] The PWM controller controls the duty cycle of the power switch of the battery charging circuit according to the target PWM signal;

[0074] If the current charging stage is not the last charging stage, the above calculation of the new target PWM signal for the next charging stage is repeated and saved in the cache so as to switch directly when the next charging stage arrives;

[0075] If the current charging stage is the last charging stage, the target PWM signal of the current stage is maintained until the charging is completed.

[0076] In one embodiment of the present invention, the charging stage includes at least a constant current charging stage, a constant voltage charging stage and a trickle charging stage in sequence, wherein the PWM duty cycle setting value of the constant current charging stage is greater than the PWM duty cycle setting value of the constant voltage charging stage, and the PWM duty cycle setting value of the trickle charging stage is less than the PWM duty cycle setting value of the constant voltage charging stage.

[0077] like Figure 4As shown, different charging stages require different charging currents. Compared with when 5A charging current output is required, the duty cycle of the PWM signal generated by the PWM module of the DSP processor itself is larger when 10A charging current output is required. As the charging current demand decreases, the duty cycle of the PWM signal generated by the PWM module of the DSP processor itself becomes smaller and smaller.

[0078] correspond Figure 4 In the embodiment, in the program of the DSP processor, the correlation mapping relationship between the charging current and the duty cycle of each stage is preset, for example, the charging current of the first stage is 10A, and the corresponding duty cycle is 75%; the charging current of the second stage is 5A, and the corresponding duty cycle is 45%; the charging current of the third stage is 3A, and the corresponding duty cycle is 30%; the charging current of the fourth stage is 2A, and the corresponding duty cycle is 25%; the above correlation mapping relationship is only an example, and the specific setting value can be obtained according to the experiment.

[0079] An embodiment of the present invention is Figure 1 As shown, the charging system also includes a multi-channel control circuit, and the DSP processor is connected to multiple battery data channels through the multi-channel control circuit. The multi-channel control circuit is configured to control the analog switches set on each battery data channel to control the data transmission of each battery data channel.

[0080] An embodiment of the present invention is Figure 1 As shown, the charging system further includes an RS485 circuit module, which is configured to provide an RS485 communication interface to perform data communication with the intermediate computer by connecting an RS485 communication line.

[0081] In one embodiment of the present invention, a battery management system is provided. Figure 2 As shown, the battery management system includes a host computer, a middle computer and the capacity-dividing device pulse charging system as described above (i.e., a lower computer), wherein the middle computer communicates with the capacity-dividing device pulse charging system via RS485, and the middle computer communicates with the host computer via Ethernet.

[0082] like Figure 2 and Figure 3 As shown, the central computer is equipped with 64 RS485 interfaces to simultaneously connect 64 pulse charging systems of the capacity-dividing devices;

[0083] Specific as Figure 3 As shown, the battery management system also includes a bidirectional inverter power supply connected to an external power grid, and the bidirectional inverter power supply provides a DC power supply for the pulse charging system of each capacity-dividing device.

[0084] The battery management system of this embodiment includes 64 RS485 interfaces, which can connect to up to 64 lower computers (i.e., 64 pulse charging systems of the said capacity-dividing equipment). Each lower computer can charge 8 or 16 batteries. Taking the lower computer as a single-board 8-channel design as an example, this system manages a total of 512 batteries. When the middle computer sends a parallel instruction to the lower computer, the pulse charging of the 512 batteries below will begin. During the charging process, the battery status will be monitored in real time, and the charging current and voltage will be adjusted. At the same time, the lower computer data will be uploaded to the middle computer. The uploaded data will be parsed by protocol, mainly including removing the frame header, frame tail, function bit, data bit length, and check bit. Only the original data uploaded by the lower computer will be retained. At the same time, the original data will be encrypted. The processed data will be moved to the AXI bus through DMA and transmitted to the PS end. The PS will package the data and save it to the eMMC. Finally, the PS will send the saved data to the upper computer through Gigabit Ethernet. The upper computer will parse the data to complete the precise charging of the battery.

[0085] In summary, during the entire multi-stage charging process, the DSP processor controls the charging current and voltage by precisely adjusting the duty cycle, and the FPGA processor uses a counter that can accumulate clock pulses to time the trigger pulses to achieve precise control of the current pulses, so that the battery can be charged efficiently and safely, which not only speeds up the charging speed, but also effectively avoids battery overheating, reduces water loss and gas precipitation, thereby protecting the health of the battery.

[0086] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0087] The above is only a specific implementation of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A pulse charging system for a capacity-dividing device, characterized in that: It includes a DSP processor, an FPGA processor, a PWM controller, a gate drive IC, a work step acquisition module, a multi-channel control circuit and a power switch for connecting a battery charging circuit, wherein the FPGA processor generates a first PWM signal with a predetermined duty cycle through a counter, and the DSP processor generates a second PWM signal with an adjustable duty cycle based on its own PWM module; The DSP processor sends the second PWM signal to the FPGA processor, and the FPGA processor performs a logic operation on the first PWM signal and the second PWM signal to obtain a target PWM signal; The FPGA processor sends the target PWM signal to the PWM controller, and the PWM controller drives the gate drive IC according to the target PWM signal so that the corresponding power switch works according to the duty cycle of the target PWM signal, including: the charging system pre-designs the charging process into multiple charging stages, and the charging currents of at least two adjacent charging stages are different; during the charging process, the PWM module of the DSP processor always acts on the first PWM signal generated by the FPGA processor, and the PWM signal for controlling charging is always sent to the PWM controller by the FPGA processor; according to the charging current of the next charging stage, the DSP processor determines in advance the duty cycle setting value of its own PWM module in the next charging stage, and sends it to the FPGA processor; the FPGA processor performs logical operations to obtain the target PWM signal of the next charging stage, and saves it in the FIFO buffer area; at the end of the current charging stage, the FPGA processor directly switches to the target PWM signal in the FIFO buffer area; The work step acquisition module is configured to acquire voltage and / or current information of the battery during the charging process, and send the acquired information to the DSP processor; the DSP monitors the charging state of the battery in real time according to the information acquired by the work step acquisition module to determine whether the current charging stage is ended to enter the next charging stage; The DSP processor is connected to multiple battery data channels via the multi-channel control circuit, and the multi-channel control circuit is configured to control analog switches provided on each battery data channel to control data transmission of each battery data channel.

2. The pulse charging system for capacity-dividing equipment according to claim 1, characterized in that: After directly switching to the target PWM signal in the FIFO buffer area, the method further includes: The DSP processor determines in advance again a new duty cycle setting value for the next charging stage; The FPGA performs logic operation again to obtain a new target PWM signal for the next charging stage, and updates the target PWM signal in the FIFO buffer area to the new target PWM signal.

3. The pulse charging system for capacity-dividing equipment according to claim 1, characterized in that: The charging stage at least includes a constant current charging stage, a constant voltage charging stage and a trickle charging stage in sequence, wherein the PWM duty cycle setting value of the constant current charging stage is greater than the PWM duty cycle setting value of the constant voltage charging stage, and the PWM duty cycle setting value of the trickle charging stage is less than the PWM duty cycle setting value of the constant voltage charging stage.

4. The pulse charging system for capacity-dividing equipment according to claim 1, characterized in that: The charging system further comprises an RS485 circuit module, which is configured to provide an RS485 communication interface so as to perform data communication with the intermediate computer by connecting an RS485 communication line.

5. A battery management system, characterized in that: The invention comprises a host computer, a middle computer and a pulse charging system for a capacity-dividing device as claimed in any one of claims 1 to 4.

6. The battery management system according to claim 5, characterized in that: The intermediate machine communicates with the pulse charging system of the capacity division equipment via RS485.

7. The battery management system according to claim 5, characterized in that: The intermediate computer communicates with the upper computer via Ethernet.

8. The battery management system according to any one of claims 5 to 7, characterized in that: The central computer is equipped with 64 RS485 interfaces so as to be able to simultaneously connect 64 pulse charging systems of the capacity-dividing devices.

9. The battery management system according to any one of claims 5 to 7, characterized in that: It also includes a bidirectional inverter power supply connected to an external power grid, and the bidirectional inverter power supply provides a DC power supply for the pulse charging system of each capacity-dividing device.

10. A capacity-dividing device pulse charging method based on the capacity-dividing device pulse charging system according to any one of claims 1 to 4, characterized in that: The following steps are involved: The charging process is designed to be divided into multiple charging stages, and the charging currents of at least two adjacent charging stages are different; The FPGA processor generates a first PWM signal with a predetermined duty cycle through a counter; The PWM module of the DSP processor generates a second PWM signal with an adjustable duty cycle, which always acts on the first PWM signal generated by the FPGA processor; According to the charging current of the next charging stage, the DSP processor determines in advance the duty cycle setting value of its own PWM module in the next charging stage, and sends it to the FPGA processor; The FPGA processor performs logic operations to obtain a target PWM signal for the next charging stage and stores it in a FIFO buffer area; At the end of the current charging phase, the FPGA processor directly switches to the target PWM signal in the FIFO buffer area; The PWM controller controls the duty cycle of the power switch of the battery charging circuit according to the target PWM signal.

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