Three-level parallel inverter double phase shift modulation method and system

Abstract

The application provides a three-level parallel inverter double-phase shift modulation method and system, regions where divided phase modulation waves are located are obtained according to three-phase modulation waves, carrier correction angles of each phase are calculated through the regions where the phase modulation waves are located; total phase shift angles are obtained according to the carrier correction angles, circulating current phase shift angles and carrier initial angles; the peak value of common-mode voltage difference is reduced or the residence time of a switch sequence generating the common-mode voltage difference is reduced through reasonable arrangement of switch states of three-phase total voltage based on the added circulating current phase shift angle, high-frequency circulating current suppression is realized; first phase shift comparison values and second phase shift comparison values corresponding to upper carrier waves and lower carrier waves are obtained according to the total phase shift angles, and then each phase voltage of the upper carrier wave and each phase voltage of the lower carrier wave are obtained, the carrier segmented phase shift process is simplified and realized, and the improvement of output current ripple of the parallel three-level inverter system and the suppression of circulating current are realized.

Description

Technical Field

[0001] This invention relates to the field of vector modulation technology for parallel three-level inverters, specifically to a two-phase-shift modulation method for a three-level parallel inverter, a two-phase-shift modulation system for a three-level parallel inverter, a computer device, a computer-readable storage medium, and a computer program product. Background Technology

[0002] The statements in this section are merely background information related to the present invention and do not necessarily constitute prior art.

[0003] In recent years, with the rapid development of high-power AC power drive technology, neutral-point-clamped (NPC) three-level inverters have been widely used. Compared with the traditional three-phase two-level inverter topology, NPC three-level inverters have advantages such as lower voltage stress on power devices and better output waveform quality.

[0004] In high-power and rated-current applications, the capacity limitations of semiconductor devices often mean that a single inverter is insufficient. Parallel inverters offer an alternative topology for achieving higher rated power than a single three-level inverter. The flexibility of the voltage capability of parallel inverters can improve system efficiency under a wide range of application conditions. However, problems with parallel inverters are concentrated in areas such as zero-sequence circulating current suppression, carrier synchronization, reduction of switching losses, reduction of common-mode voltage (CMV), and improvement of output current ripple. To improve the overall output current quality of parallel inverters, segmented dual-carrier phase-shift (DPS-PWM) based on an interleaved scheme has been proposed. However, the carrier phase difference in the interleaved scheme can generate circulating current.

[0005] In power conversion systems, circulating current has disadvantages such as increased power loss and reduced system efficiency. Unexpected circulating current can cause filter inductor saturation. In addition, the harmonic components of circulating current increase the thermal stress on DC link capacitors and power semiconductors, resulting in a limitation on rated power. Furthermore, the carrier difference between inverters can cause high-frequency circulating current to be generated in the asynchronous switching sequence. Summary of the Invention

[0006] To address the shortcomings of existing technologies, this invention provides a dual-phase-shift modulation method and system for a three-level parallel inverter. By utilizing an improved dual-carrier phase-shift pulse width modulation (MDPS-PWM), the circulating current of the parallel three-level inverter is reduced, thereby achieving suppression of circulating current and improvement of output current ripple in the parallel three-level inverter system.

[0007] To achieve the above objectives, the present invention adopts the following technical solution:

[0008] In a first aspect, the present invention provides a dual phase-shift modulation method for a three-level parallel inverter.

[0009] A two-phase shift modulation method for a three-level parallel inverter includes the following steps:

[0010] Based on the regions where each phase modulation wave is located after being divided according to the three-phase modulation wave, the carrier correction angle of each phase is calculated through the regions where each phase modulation wave is located.

[0011] According to the corresponding rules of circulating current suppression, the circulating current phase shift angle is added to the carrier correction angle and the carrier initial angle to obtain the total phase shift angle;

[0012] Based on the total phase shift angle, the first phase shift comparison value and the second phase shift comparison value corresponding to the upper carrier and the lower carrier are obtained respectively. Based on the first phase shift comparison value and the second phase shift comparison value of the upper carrier, the phase voltage of each phase of the upper carrier is obtained. Based on the first phase shift comparison value and the second phase shift comparison value of the lower carrier, the phase voltage of each phase of the lower carrier is obtained.

[0013] The switching sequence of each power switch is generated based on the phase voltages of the upcarrier and the phase voltages of the downcarrier, and the control of the three-level parallel inverter is performed.

[0014] Among them, the parallel three-level inverter has a phase shift angle θ Circulation phase shift angle based on 0 θ cc The rules are set as follows:

[0015]

[0016] F x ( x = a, b, c () represents the distance from the absolute value of the modulated wave to 1 / 2. m a , m b and m c The modulated wave is s1 and s2, which are the regions where the modulated waves of each phase are divided.

[0017] As a further limitation of the first aspect of the invention, the amplitude direction axes of the upper carrier and the lower carrier are divided into two regions by 1 / 2 and -1 / 2 respectively. The upper region is region s1, and the lower region is region s2. In regions s1 and s2, the sinusoidal carrier... C r1 initial angle θ p1_1 180 Phase-shifted carrier C r2 initial angle θ p1_2 for π rad;

[0018] sinusoidal carrier C r1 and 180 Phase-shifted carrier C r2 The correction angle is the same in each region; in region s1, the sinusoidal carrier... C r1 and 180 Phase-shifted carrier C r2 The correction angle is 0 rad. In region s2, the sinusoidal carrier... C r1 and 180 Phase-shifted carrier C r2 The correction angle is π / 2 rad, all three phase carriers lag in region s2. π / 2 rad.

[0019] As a further limitation of the first aspect of the present invention, the total phase shift angle is the sum of the carrier correction angle, the circulating phase shift angle, and the carrier initial angle.

[0020] As a further limitation of the first aspect of the invention, the first phase shift comparison value m of the upper carrier... x1 Second phase shift comparison value m x2 for:

[0021] ;

[0022] Download the first phase shift comparison value m of the wave x1 Second phase shift comparison value m x2 for:

[0023] ;

[0024] in, , This is the total phase shift angle.

[0025] As a further limitation of the first aspect of the invention, the phase voltage of the upper carrier v xi for:

[0026] ;

[0027] Download wave phase voltage v xi for:

[0028] ;

[0029] in, This is the DC side voltage.

[0030] As a further limitation of the first aspect of the invention, the comprehensive five-level switching sequence corresponding to each region after carrier phase shift is obtained, and the reference vector is synthesized using the three most recent voltage vectors; only the circulating phase shift angle of the modulation wave whose absolute value is closest to 1 / 2 among the two-phase or three-phase modulation waves located in the same region is... π The phase shift angle of the other phase current is 0 rad; the carrier phase shift ensures that the average circulating current is zero for two consecutive cycles.

[0031] Secondly, the present invention provides a three-level parallel inverter dual-phase-shift modulation system.

[0032] A three-level parallel inverter dual-phase shift modulation system includes:

[0033] The carrier correction angle calculation unit is configured to: calculate the carrier correction angle of each phase based on the region where each phase modulation wave is located after being divided according to the three-phase modulation wave;

[0034] The total phase shift angle calculation unit is configured to: add the circulating phase shift angle to the carrier correction angle and the carrier initial angle according to the rules of circulating current suppression to obtain the total phase shift angle;

[0035] The phase voltage calculation unit is configured to: obtain the first phase shift comparison value and the second phase shift comparison value corresponding to the upper carrier and the lower carrier respectively according to the total phase shift angle; obtain the phase voltage of the upper carrier according to the first phase shift comparison value and the second phase shift comparison value of the upper carrier; and obtain the phase voltage of the lower carrier according to the first phase shift comparison value and the second phase shift comparison value of the lower carrier.

[0036] The dual phase-shift modulation unit is configured to generate the switching sequence of each power switch and control the three-level parallel inverter based on the phase voltages of the upcarrier and the downcarrier.

[0037] Thirdly, the present invention provides a computer device, comprising: a processor and a computer-readable storage medium;

[0038] A processor, adapted to execute computer programs;

[0039] A computer-readable storage medium storing a computer program, which, when executed by the processor, implements the three-level parallel inverter dual-phase shift modulation method as described in the first aspect of the present invention.

[0040] Fourthly, the present invention provides a computer-readable storage medium storing a computer program adapted to be loaded by a processor and executed as described in the first aspect of the present invention for a two-phase-shift modulation method for a three-level parallel inverter.

[0041] Fifthly, the present invention provides a computer program product comprising a computer program that, when executed by a processor, implements the three-level parallel inverter dual-phase shift modulation method as described in the first aspect of the present invention.

[0042] Compared with the prior art, the beneficial effects of the present invention are:

[0043] 1. This invention innovatively proposes an MDPS-PWM (Improved Dual-Phase Shift Pulse Width Modulation) strategy. By dividing the parallel three-level dual-carrier circuit into regions and setting the initial angle and correction angle of the carrier in each inverter, the total line voltage can be avoided. V LLT The ability to vary across three adjacent voltage levels improves the output current quality of parallel inverters.

[0044] 2. The two parallel three-level inverters of the present invention are regarded as a five-level inverter, which provides multiple levels and greater freedom in the switching sequence design. Through staggered carrier phase shift modulation, the available switching states of the parallel three-level inverters become 5. The switching sequence only uses one or two vector states located in the middle, which ensures the best switching performance and output line current quality.

[0045] 3. This invention utilizes the circulating phase shift angle θ cc By applying the appropriate method to rationally arrange the three-phase total voltage difference in the switching state, the peak value of the common-mode voltage difference is reduced, or the dwell time of the switching sequence that generates the common-mode voltage difference is reduced, thus achieving high-frequency circulating current suppression. The carrier phase shift of MDPS-PWM in the dual parallel three-level inverter is simplified by the sawtooth carrier modulation strategy (SCBM).

[0046] Advantages of additional aspects of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0047] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an improper limitation of the invention.

[0048] Figure 1 A schematic diagram of the topology of the parallel three-level inverter system provided by the present invention;

[0049] Figure 2 This is a five-level space vector diagram corresponding to the parallel three-level inverter of the present invention;

[0050] Figure 3This is a block diagram of the MDPS-PWM modulation method for the parallel three-level inverter of the present invention;

[0051] Figure 4 A comparison of the DPS-PWM method for parallel three-level inverters with the MDPS-PWM method of this invention;

[0052] Figure 5 Comparison of DPS-PWM and the MDPS-PWM method of this invention for parallel three-level inverters (Part 2);

[0053] Figure 6 The simulation results of the DPS-PWM modulation method for a parallel three-level inverter are shown in the figure.

[0054] Figure 7 The figure shows the simulation results of the MDPS-PWM modulation method of the three-level parallel inverter of the present invention. Detailed Implementation

[0055] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0056] It should be noted that the following detailed descriptions are exemplary and intended to provide further illustration of the invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0057] Example 1:

[0058] This implementation proposes a dual-phase-shift modulation method for three-level parallel inverters, primarily targeting parallel NPC three-level inverter systems, such as... Figure 1 As shown, each inverter includes phase A, phase B, and phase C bridge arms. Each phase bridge arm includes four power switching transistors and two clamping diodes. The DC side includes two series-connected filter capacitors, with a neutral point formed between them. The two clamping diodes of each phase bridge arm are connected to the neutral point in the middle. The power switching transistors here are insulated-gate bipolar transistors (IGBTs). It is understood that in some other implementations, other types of transistors can also be used for the power switching transistors, which will not be elaborated here.

[0059] Specifically, each three-level inverter generates three different voltage levels through different switching combinations. V dc / 2、0、- V dc / 2 is denoted as P, O, N or 2, 1, 0 respectively; where, V dc Given the amplitude of the DC power supply, for a dual-parallel inverter, the AC side output voltage can be expressed as:

[0060] (1);

[0061] because V x1N and V x2N Only one of the three values ​​can be obtained, therefore equation (1) has five possible results, which means the equivalent voltage V xpccN There are five voltage levels. Table 1 shows the parallel output states formed by the three-level inverter. We can analyze and modulate the dual parallel three-level inverters as a five-level system. The two inverters only need one current control loop, which is beneficial to the system cost.

[0062] Table 1: The three-level state of the parallel inverter forms a five-level output state.

[0063]

[0064] The power switching transistors are turned on and off by the control system.

[0065] The phase voltages of three-level inverters 1 and 2 can be expressed as:

[0066] (2);

[0067] in, V x1 and V x2 Inverter 1 and Inverter 2 respectively x Phase voltage, S x1 and S x2 Inverter 1 and Inverter 2 respectively x The switching state of the phase branch.

[0068] In each parallel inverter x Mutually( x = a , b , c The sum of the phase voltages of () is defined as the total phase voltage. V Px ( x = a , b , c ), the total phase voltage of two phases in the three phases V Px ( x = a , b , c The difference is defined as the total line voltage. V LLT Here will V Pa and VPb The difference between them is considered as V LLT Define phase x ( x = a , b , c Total output voltage V gTx .

[0069] (3);

[0070] (4);

[0071] (5);

[0072] The harmonic characteristics of the total output current of a parallel inverter are determined by the total output voltage. V gTx The decision is made that, at the same frequency, V gTx The harmonic amplitude and V LLT The harmonic amplitude is proportional to the harmonic amplitude; therefore, in this invention, the selected... V LLT To reflect the total output characteristics of the parallel inverter, because in practical applications, V LLT Compare V gTx It is easier to measure and calculate.

[0073] To further improve the output current quality of PS-PWM parallel inverters, a DPS-PWM (Dual Phase Shift Pulse Width Modulation) strategy is employed, which modifies the phase shift angle of the carrier wave in each inverter twice. θ 0 can avoid total line voltage V LLT In cases where the voltage levels may vary across three adjacent voltage levels, the following section describes the specific phase shift angle settings for the DPS-PWM strategy in parallel three-level modulation.

[0074] Phase shift angle of the carrier in each inverter θ 0 consists of two parts: the initial angle and the correction angle. θ p1_i Indicates the initial angle. θ p2_j This represents the correction angle, which is determined based on the region where each phase's modulation wave is located. The number of regions to be divided is determined by the number of parallel inverters, and the region s is the corrected angle. j ( j =1,2) Based on the modulation wave m x ( x = a , b ,c The calculation yields the following formula:

[0075] (6);

[0076] in, N This refers to the number of inverters connected in parallel. Specifically, for a dual-parallel three-level inverter, the amplitude direction axes of the upper and lower carrier waves are divided into two regions, with 1 / 2 and -1 / 2 as boundaries respectively. The upper region is region S1, and the lower region is region S2. In S1 and S2, the carrier waves... C r1 , C r2 initial angle θ p1_1 and θ p1_2 0 rad and π The correction angle is 0 rad, conforming to PS-PWM. Furthermore, the correction angle for both carriers is the same in each region. In s1, the correction angle for each carrier is 0 rad, equivalent to no change, while in s2, the correction angle for each carrier is... π / 2 rad (correction angle is) π At / 2 rad, V Px To achieve the same effect, all three phase carriers lag in this region. π / 2 rad. Therefore, the correction angle θ p2_j Represented as:

[0077] (7);

[0078] Phase shift makes V Pa and V Pb The high voltage level is in the middle, and the bus voltage is... V LLT It can change accordingly.

[0079] Table 2 shows the switching sequences of each sub-region in sector I after applying DPS-PWM, consistent with the most recent three-vector five-level SVPWM. DPS-PWM only uses the most recent three voltage vectors to synthesize the reference vector; for example, sub-region 5 of sector I uses the most recent three voltage vectors (310, 421), (311), and (300, 411). Furthermore, for vectors with more than two redundant states, the switching sequence only uses one or two states in the middle to ensure optimal switching performance and output line current quality. For example, if a vector has three redundant states (210, 321, and 432), only the middle state (321) is used. Figure 2 As shown. Therefore, it can effectively reduce VLLT and V gTx This effectively reduces harmonics in the output current, thereby mitigating harmonics in the output current.

[0080] Table 2: Switching sequence of sector I sub-region after applying DPS-PWM to parallel three-level inverters.

[0081]

[0082] like Figure 1 As shown, differential mode circulating current flows through the inductor of each inverter. L 1 and L 2. Therefore, x Phase differential mode circulation ( i cir,x , x = a, b, c ) can represent:

[0083] (8);

[0084] The sum of the differential mode circulations is the zero-sequence circulation (ZSCC), therefore, it can be expressed as:

[0085] (9);

[0086] Because of inductance L 1. L 2 and V dc The rate of change of zero-sequence circulating current remains constant. It depends on the sum of the three-phase switching state differences between inverter 1 and inverter 2. Only by minimizing the difference between the in-phase states of the two inverters can a small differential-mode circulating current be achieved. This requires the five-level states to be evenly distributed across the two three-level states. All even-numbered five-level states "0", "2", and "4" can be equally divided into two identical states "0", "1", and "2". In this case, the difference between the in-phase states of the two inverters is 0, and these states will not affect the rate of change of circulating current. For odd-numbered states, including states "1" and "3", which cannot be equally divided into three-level states, different combinations of three-level states should be used appropriately during the switching cycle to ensure that the differential-mode circulating current does not increase excessively in one direction or the other. Similarly, only by reasonably arranging and matching the three-phase switching state differences to minimize the sum of the three-phase switching state differences can a small zero-sequence circulating current be achieved.

[0087] The principle of high-frequency circulating current suppression is to reduce the peak value of the common-mode voltage difference or to reduce the dwell time of the switching sequence that generates the common-mode voltage difference. This is achieved by reducing the total three-phase voltage difference between parallel inverters ( V dcmThe improved DPS-PWM (MDPS-PWM) proposed in this invention reduces the suppression of circulating current in parallel inverters by employing a carrier phase-shifting method to reduce high-frequency circulating current. V dcm The calculation formula is:

[0088] (10);

[0089] In MDPS-PWM, the phase shift angle of DPS-PWM θ Add an extra angle at 0 θ cc To reduce the total three-phase voltage difference between parallel inverters ( V dcm This can reduce the circulation, and the total phase shift angle at this time is expressed as:

[0090] (11);

[0091] Analyzing the voltage difference between each phase involves analyzing the specific differences in the switching states of each phase of the two inverters. Generally, the method to reduce the total three-phase voltage difference is to analyze the modulation wave whose absolute value is closest to 1 / 2 in the three-phase modulation wave. θ cc 2 π / N rad, the rest are 0 rad, the carrier is a sinusoidal carrier ( C r1 ) and 180 Phase-shifted carrier ( C r2 There are two types. Under conventional PWM, the reference voltage of inverter 1 is... C r1 In comparison, the reference voltage of inverter 2 is compared with the phase-shifted carrier. C r2 Comparison, dual parallel N =2.

[0092] In this method, θ cc for π The corresponding phase sinusoidal carrier of rad ( C r1 180° lag, 180 Phase-shifted carrier ( C r2 It is still better than a sinusoidal carrier wave. C r1 A 180° lag is equivalent to adjusting the reference voltage of that phase of inverter 1 relative to... C r2 The reference voltage of this phase of inverter 2 is compared with... C r1By comparing and modifying the two parallel three-level switching sequences to reduce circulating current, when the carrier waves of inverter 1 and inverter 2 lag by 180°, the corresponding phase switch voltage difference... v x1 - v x2 Lag 180°, specifically θ cc As shown in Table 3 below, F x ( x = a, b, c () represents the distance from the absolute value of the modulated wave to 1 / 2, and the calculation formula is:

[0093] (12).

[0094] Table 3: Setting the Circulating Current Phase Shift Angle for Parallel Three-Level Inverters θ cc Initial rules.

[0095]

[0096] In the context of modern DPS-PWM, because a phase shift angle is already present... θ 0, within one period, it has already been determined according to the region s where the modulated wave is located. j Each phase carrier undergoes a phase shift at a different angle, which leads to different total voltage differences in the three phases at different periods. Therefore, it is necessary to classify and discuss which phase carrier to select for phase shifting.

[0097] Scenario 1: Within one cycle, all three-phase modulated waves lie within the same divided region. Whether in region s1 or s2, the carrier phase shift angles of the three phases are the same, and the differences in the switching states of each phase are relatively concentrated. Therefore, the modulated wave whose absolute value is closest to 1 / 2 can be set using conventional methods. θ cc for π 1 rad, the rest are 0 rad.

[0098] The other two scenarios are more complex, specifically... θ cc As shown in Table 4 below.

[0099] Scenario 2: Within one cycle, two phase modulated waves are located in the same region s1, while another phase is located alone in region s2. The carrier phase shift angles of the three phases are different, and the differences in the switching states of each phase are not concentrated, resulting in a non-symmetrical distribution of the total three-phase voltage difference within the cycle. If the modulated wave with the absolute value closest to 1 / 2 happens to be the modulated wave located alone in region s2, its... θ cc for πrad, the rest are 0 rad, at this time the carrier of this phase ( C r1 and C r2 The total phase shift angles are respectively - π / 2 rad and π / 2 rad. Compared to no addition θ cc At this time, only the switching states of this phase change from positive to negative, while the overall three-phase voltage difference remains unchanged, and the average value of the periodic zero-sequence circulating current remains constant. In this case, setting the modulation wave for this phase... θ cc For the other two identical modulated waves located in region s1, compare the modulated wave whose absolute value is closest to 1 / 2. The value is 0 rad. θ cc for π One phase is rad, and the other is 0 rad, so the difference in the switching states of the other two phases can cancel each other out to some extent. If the modulating wave with the absolute value closest to 1 / 2 in the three-phase modulated wave is not located separately in the s2 region, the general setting is used directly. θ cc .

[0100] Scenario 3: Within one cycle, two phases of the modulating wave are located in region s2, and the other phase is located in region s1. The carrier phase shift angles of the three phases are different, and the difference in the switching states of each phase is not concentrated, resulting in a non-symmetrical distribution of the total voltage difference within the cycle. If the modulating wave with the absolute value closest to 1 / 2 among the three-phase modulating waves happens to be the modulating wave located solely in region s1, its... θ cc for π rad, the rest are 0 rad, at this time the carrier of this phase ( C r1 and C r2 The total phase shift angles are respectively π rad and 0 rad. Compared to no rad. θ cc At this time, only the difference in switching states within a cycle changes from positive to negative, while the total three-phase voltage difference is equivalent to an interchange between the first and second half of the cycle, and the average value of the zero-sequence circulating current remains unchanged within the cycle. In this case, setting the modulation wave for this phase... θ cc The value is 0 rad. For the remaining two-phase modulated waves located in the same region s2, no voltage is applied. θ cc At that time, the difference in the switching states of the two-phase inverters is relatively similar, and the modulation wave setting with the absolute value closest to 1 / 2 is compared. θ cc for πOne phase is rad, and the other is 0 rad, so the difference in the switching states of the other two phases can cancel each other out to some extent. Similarly, if the modulating wave with the absolute value closest to 1 / 2 in the three-phase modulated wave is not located separately in region s1, the general setting is used directly. θ cc .

[0101] Table 4: Parallel Three-Level Inverters at Phase Shift Angle θ Circulation phase shift angle based on 0 θ cc Set rules.

[0102]

[0103] To see the effect of reducing the total three-phase voltage difference more specifically, it is necessary to analyze the specific three-phase modulation waveform. Figure 4 The DPS-PWM and the improved MDPS-PWM are shown respectively, where [P] and [N] represent... V dc / 2 and - V dc / 2. In this case, the switching sequence for half a cycle is 310-311-321-421-321-311-310. For example... Figure 4 As shown in the left part, when using DPS-PWM, V dcm The change from 3N to 3P will result in high circulation. For example... Figure 4 As shown in the right part, when applying MDPS-PWM, an additional angle is used. θ cc Due to the diagram m a and m b Located in S1 area, m c Located in region S2, the modulated wave requiring carrier phase shifting needs to be in m a , m b Choose from the options, where the modulated wave with the absolute value closest to 1 / 2 is... m a , m a 、m b and m c of θ cc They are respectively π rad, 0 rad, and 0 rad. Therefore, Figure 4 The right part m a carrier (C r1 and C r2 ) and voltage difference ( v a1 - v a2 ) lagging behind Figure 4 The left part π rad. and Figure 4 Compared to the left side, this results in a lower V dcm , V dcm The change from 2N to 2P reduces the peak value of the common-mode voltage difference. Let the action time of vectors 310 and 421 be T1, the action time of vector 311 be T2, and the action time of vector 321 be T3. By comparing the total voltage difference... V dcm The dwell time for a new switching sequence with a common-mode voltage difference of 0 is increased by T1 / 2, and overall... V dcm Reducing the dwell time of switching sequences with a 2N or 2P configuration, which have a significant impact on the change in circulating current, will result in a lower circulating current.

[0104] Figure 5 The images show another case of DPS-PWM and MDPS-PWM. In this case, the switching sequence for half a cycle is 310-410-411-421-411-410-310, as follows: Figure 5 As shown in the left part, when using DPS-PWM, V dcm From 2N to 2P, such as Figure 5 As shown in the right part, when applying MDPS-PWM, an additional angle is used. θ cc Since the modulated wave with the absolute value closest to 1 / 2 in the figure is m b and m a 、m b It is located in the S1 area, so m a 、m b and m c of θ cc 0 rad, respectively π rad and 0 rad. Therefore, Figure 5 The right part m b carrier ( C r1 andC r2 ) and voltage difference ( v b1 - v b2 ) lagging behind Figure 5 The left part π This allows the switching states of phase b of the two inverters to be interchanged using rad. Figure 5 Compared to the left side, although V dcm The voltage difference peak did not decrease when changing from 2N to 2P. However, by analyzing the specific switching sequence within this cycle, assuming the action time of vectors 310 and 421 is T1, the action time of vector 410 is T2, and the action time of vector 411 is T3, the peak voltage difference was compared. V dcm It can be seen that the common-mode voltage difference of the switching sequence with time T1 / 2 changes from 2N, 2P to 0. V dcm =2N, 2P corresponds to a reduction in time. V dcm The increased time corresponding to =0 means a reduction in the dwell time of the switching sequence that generates the common-mode voltage difference, which will result in lower circulating current.

[0105] Table 2 lists the total voltage difference for each sub-region, using sector I as an example. V dcm The changes, when using DPS-PWM, V dcm The range is from 3N to 3P or from 2N to 2P. An additional angle is used when applying MDPS-PWM. θ cc The range is from 3N to 3P. V dcm Decrease to vary between 2N and 2P, ranging from 2N to 2P. V dcm The variation decreases to between 2N and 2P or N and P, and analysis of the sequence reveals that most of the dwell time... V dcm The concentration is between N and P, with a reduced proportion of 2N and 2P. This lowers the peak value of the common-mode voltage difference, increases the dwell time of switching sequences that do not generate common-mode voltage differences and reduce the common-mode voltage differences that have a significant impact on circulating current changes, and reduces the occurrence of high circulating current.

[0106] use θ ccThis ensures that the circulating current value returns to its initial value at the beginning of the cycle at the last moment. However, the average value of the circulating current over a cycle cannot remain zero. To ensure that the zero-sequence circulating current average value is zero, the three-level switching states and switching sequences of the two inverters from the previous cycle must be interchanged in the second cycle. Specifically, in this method, for two consecutive cycles, the total phase shift angle is applied to the three-phase carrier in the first cycle. θ After that, the phase shift of all three phase carriers is 180° in the next cycle to obtain the total voltage difference and circulating current opposite to those of the previous cycle. This ensures that the average value of the circulating current for two consecutive cycles is 0, and the circulating current will not continuously increase or decrease.

[0107] Furthermore, the influence can be seen from the formula. V LLT It is the sum of the states of the switches in parallel. θ cc The use of it affects the switching voltage difference v x1 - v x2 and V dcm When the carrier waves of inverter 1 and inverter 2 lag by 180°, the voltage difference between each phase switch... v x1 - v x2 Lagging by 180° without changing the total phase voltage obtained by summing the states of the parallel phase switches. V px , V px constant, V LLT It remains unchanged. The integrated five-level switch state and sequence remain unchanged before and after, and the situation in each sub-region of sector I is still as shown in Table 2. Therefore, it can be noted that by applying MDPS-PWM, when... V dcm When decreasing, V LLT This will remain constant. This means that MDPS-PWM can achieve lower circulating current without affecting the overall output current quality.

[0108] Simplified Implementation of MDPS-PWM Carrier Phase Shift in a Dual-Parallel Three-Level Inverter: Since segmented phase shift of the carrier is difficult to achieve in practice, the carrier in MDPS-PWM cannot be directly applied. Therefore, a sawtooth carrier modulation strategy (SCBM) is proposed to achieve online modification of the phase shift angle. The upper and lower carriers of the three-level inverter are segmented and phase-shifted respectively. Unlike traditional triangular carrier comparison modulation, it can use a carrier with two comparison values ​​(…). m x1 , m x2The sawtooth carrier wave is used instead of the triangular carrier wave to achieve modulation, thus obtaining the phase voltage. v xi :

[0109] m x >0 (upward carrier):

[0110] (13);

[0111] m x <0 (download wave):

[0112] (14);

[0113] m x When >0, m x1 and m x2 satisfy,

[0114] (15);

[0115] m x When <0, m x1 and m x2 satisfy:

[0116] (16);

[0117] At this time, the output voltage waveform is located at the center of the carrier period, which can be modified... m x1 and m x2 The value can be freely changed to alter the position of the PWM pulse, enabling online modification of the phase shift angle. v xi Phase shift angle when the high voltage level is at the center of the carrier period θ Set to 0 rad, in m x1 and m x2 Add a factor related to the total phase shift angle. θ Corresponding intermediate variables m p To achieve the equivalent phase shift of the carrier, where . m x1 and m x2 Represented as:

[0118] m x >0 (upward carrier):

[0119] (17);

[0120] m x <0 (download wave):

[0121] (18);

[0122] Figure 6 and Figure 7 The figures show simulation results of DPS-PWM and the MDPS-PWM method of this invention in a parallel three-level inverter. Taking a modulation index MI of 0.9 as an example, the three-phase current and zero-sequence circulating current are recorded from top to bottom. i ZSCC Three-phase total voltage difference V dcm and total line voltage V LLT The simulated waveform. Figure 6 In the middle, circulation i ZSCC The root mean square value is 0.2898A. Figure 7 The MDPS-PWM method, three-phase total voltage difference V dcm It varies between 2N and 2P, and the circulation... i ZSCC The root mean square value was reduced to 0.1412A, which is significantly better than DPS-PWM in reducing the total three-phase voltage difference. V dcm It reduces high-frequency circulating current, and both V LLT The simulation results above effectively verify that the proposed MDPS-PWM method reduces circulating current while maintaining output current quality, demonstrating the effectiveness of the method.

[0123] Example 2:

[0124] This implementation proposes a three-level parallel inverter dual-phase shift modulation system, including:

[0125] The carrier correction angle calculation unit is configured to: calculate the carrier correction angle of each phase based on the region where each phase modulation wave is located after being divided according to the three-phase modulation wave;

[0126] The total phase shift angle calculation unit is configured to: add the circulating phase shift angle to the carrier correction angle and the carrier initial angle according to the rules of circulating current suppression to obtain the total phase shift angle;

[0127] The phase voltage calculation unit is configured to: obtain the first phase shift comparison value and the second phase shift comparison value corresponding to the upper carrier and the lower carrier respectively according to the total phase shift angle; obtain the phase voltage of the upper carrier according to the first phase shift comparison value and the second phase shift comparison value of the upper carrier; and obtain the phase voltage of the lower carrier according to the first phase shift comparison value and the second phase shift comparison value of the lower carrier.

[0128] The dual phase-shift modulation unit is configured to generate the switching sequence of each power switch and control the three-level parallel inverter based on the phase voltages of the upcarrier and the downcarrier.

[0129] The specific control methods for each unit are detailed in Example 1, and will not be repeated here.

[0130] It is understood that the above-mentioned modules can be individually or entirely combined into one or more other units, or some of the units can be further divided into multiple functionally smaller units. This can achieve the same operation without affecting the technical effects of the embodiments of this application. The above-mentioned units are based on logical function division. In practical applications, the function of one unit can also be implemented by multiple units, or the function of multiple units can be implemented by one unit. In other embodiments of this application, the dual phase shift modulation system may also include other units. In practical applications, these functions can also be implemented with the assistance of other units, and can be implemented collaboratively by multiple units.

[0131] According to another embodiment of this application, the system described in this embodiment and the dual phase-shift modulation method of this application can be constructed by running a computer program (including program code) capable of performing the steps involved in the corresponding method described in Embodiment 1 on a general-purpose computing device including processing elements and storage elements such as a central processing unit (CPU), random access memory (RAM), and read-only memory (ROM). The computer program can be recorded on, for example, a computer-readable recording medium, loaded into the aforementioned computing device through the computer-readable recording medium, and run therein.

[0132] Example 3:

[0133] This implementation provides an electronic device including a processor, a communication interface, and a computer-readable storage medium. The processor, communication interface, and computer-readable storage medium can be connected via a bus or other means.

[0134] The communication interface is used to receive and send data. The computer-readable storage medium can be stored in the memory of the electronic device. The computer-readable storage medium is used to store computer programs, which include program instructions. The processor is used to execute the program instructions stored in the computer-readable storage medium.

[0135] A processor (or CPU, Central Processing Unit) is the computing and control core of an electronic device. It is suitable for implementing one or more instructions, specifically for loading and executing one or more instructions to achieve the corresponding method flow or function.

[0136] The processor is configured to perform the following process:

[0137] Based on the regions where each phase modulation wave is located after being divided according to the three-phase modulation wave, the carrier correction angle of each phase is calculated through the regions where each phase modulation wave is located.

[0138] The total phase shift angle is obtained based on the carrier correction angle, the circulating phase shift angle, and the carrier initial angle.

[0139] Based on the total phase shift angle, the first phase shift comparison value and the second phase shift comparison value corresponding to the upper carrier and the lower carrier are obtained respectively. Based on the first phase shift comparison value and the second phase shift comparison value of the upper carrier, the phase voltage of each phase of the upper carrier is obtained. Based on the first phase shift comparison value and the second phase shift comparison value of the lower carrier, the phase voltage of each phase of the lower carrier is obtained.

[0140] The switching sequence of each power switch is generated based on the phase voltages of the upcarrier and the phase voltages of the downcarrier, and the control of the three-level parallel inverter is performed.

[0141] Example 4:

[0142] This implementation provides a computer-readable storage medium (Memory), which is a memory device in an electronic device used to store programs and data. It is understood that the computer-readable storage medium here can include both built-in storage media in the electronic device and extended storage media supported by the electronic device. The computer-readable storage medium provides storage space that stores the processing system of the electronic device.

[0143] Furthermore, this storage space also contains one or more instructions suitable for loading and execution by the processor. These instructions can be one or more computer programs (including program code). It should be noted that the computer-readable storage medium here can be high-speed RAM or non-volatile memory. (volatile memory), such as at least one disk storage; alternatively, it may also be at least one computer-readable storage medium located remotely from the aforementioned processor.

[0144] In one embodiment, the computer-readable storage medium stores one or more instructions; the processor loads and executes the one or more instructions stored in the computer-readable storage medium to perform the following process:

[0145] Based on the regions where each phase modulation wave is located after being divided according to the three-phase modulation wave, the carrier correction angle of each phase is calculated through the regions where each phase modulation wave is located.

[0146] The total phase shift angle is obtained based on the carrier correction angle, the circulating phase shift angle, and the carrier initial angle.

[0147] Based on the total phase shift angle, the first phase shift comparison value and the second phase shift comparison value corresponding to the upper carrier and the lower carrier are obtained respectively. Based on the first phase shift comparison value and the second phase shift comparison value of the upper carrier, the phase voltage of each phase of the upper carrier is obtained. Based on the first phase shift comparison value and the second phase shift comparison value of the lower carrier, the phase voltage of each phase of the lower carrier is obtained.

[0148] The switching sequence of each power switch is generated based on the phase voltages of the upcarrier and the phase voltages of the downcarrier, and the control of the three-level parallel inverter is performed.

[0149] Example 5:

[0150] This implementation provides a computer program product or computer program, which includes computer instructions stored in a computer-readable storage medium. The processor of an electronic device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the electronic device to perform the following process:

[0151] Based on the regions where each phase modulation wave is located after being divided according to the three-phase modulation wave, the carrier correction angle of each phase is calculated through the regions where each phase modulation wave is located.

[0152] The total phase shift angle is obtained based on the carrier correction angle, the circulating phase shift angle, and the carrier initial angle.

[0153] Based on the total phase shift angle, the first phase shift comparison value and the second phase shift comparison value corresponding to the upper carrier and the lower carrier are obtained respectively. Based on the first phase shift comparison value and the second phase shift comparison value of the upper carrier, the phase voltage of each phase of the upper carrier is obtained. Based on the first phase shift comparison value and the second phase shift comparison value of the lower carrier, the phase voltage of each phase of the lower carrier is obtained.

[0154] The switching sequence of each power switch is generated based on the phase voltages of the upcarrier and the phase voltages of the downcarrier, and the control of the three-level parallel inverter is performed.

[0155] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed in this application can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0156] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. A computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the flow or function according to the embodiments of this application is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in or transmitted through a computer-readable storage medium. The computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that a computer can access or a data processing device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state disk (SSD)).

[0157] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A dual-phase-shift modulation method for a three-level parallel inverter, characterized in that, Includes the following processes: Based on the regions where each phase modulation wave is located after being divided according to the three-phase modulation wave, the carrier correction angle of each phase is calculated through the regions where each phase modulation wave is located. According to the circulating current suppression rule, the circulating current phase shift angle is added to the carrier correction angle and the carrier initial angle to obtain the total phase shift angle; Based on the total phase shift angle, the first phase shift comparison value and the second phase shift comparison value corresponding to the upper carrier and the lower carrier are obtained respectively. Based on the first phase shift comparison value and the second phase shift comparison value of the upper carrier, the phase voltage of each phase of the upper carrier is obtained. Based on the first phase shift comparison value and the second phase shift comparison value of the lower carrier, the phase voltage of each phase of the lower carrier is obtained. The switching sequence of each power switch is generated based on the phase voltage of the upcarrier and the phase voltage of the downcarrier, and the control of the three-level parallel inverter is performed. The amplitude direction axes of the upcarrier and downcarrier waves are divided into two regions, with 1 / 2 and -1 / 2 as boundaries, respectively. The upper region is designated as region s1, and the lower region as region s2. Within regions s1 and s2, the sinusoidal carrier wave... C r1 initial angle θ p1_1 180 Phase-shifted carrier C r2 initial angle θ p1_2 for π rad; sinusoidal carrier C r1 and 180 Phase-shifted carrier C r2 The correction angle is the same in each region; in region s1, the sinusoidal carrier... C r1 and 180 Phase-shifted carrier C r2 The correction angle is 0 rad. In region s2, the sinusoidal carrier... C r1 and 180 Phase-shifted carrier C r2 The correction angle is π / 2 rad, all three phase carriers lag in region s2. π / 2 rad; After carrier phase shift, the corresponding integrated five-level switching sequence for each region is obtained, and the reference vector is synthesized using the three most recent voltage vectors; only the circulating phase shift angle of the modulated wave with the absolute value closest to 1 / 2 among the two-phase or three-phase modulated waves located in the same region is... π The phase shift angle of the other phase current is 0 rad; the carrier phase shift ensures that the average circulating current is zero for two consecutive cycles.

2. The dual-phase-shift modulation method for a three-level parallel inverter as described in claim 1, characterized in that, The total phase shift angle is the sum of the carrier correction angle, the circulating phase shift angle, and the carrier initial angle.

3. The dual-phase-shift modulation method for a three-level parallel inverter as described in claim 1, characterized in that, The first phase shift comparison value m of the upcarrier x1 Second phase shift comparison value m x2 for: ； Download the first phase shift comparison value m of the wave x1 Second phase shift comparison value m x2 for: ； in, , This is the total phase shift angle.

4. The dual-phase-shift modulation method for a three-level parallel inverter as described in claim 3, characterized in that, Phase voltage of the upcarrier v xi for: ； Download wave phase voltage v xi for: ； in, This is the DC side voltage.

5. A three-level parallel inverter dual-phase shift modulation system, characterized in that, The method for dual-phase-shift modulation of a three-level parallel inverter according to any one of claims 1-4 includes: The carrier correction angle calculation unit is configured to: calculate the carrier correction angle of each phase based on the region where each phase modulation wave is located after being divided according to the three-phase modulation wave; The total phase shift angle calculation unit is configured to: add the circulating phase shift angle to the carrier correction angle and the carrier initial angle according to the rules of circulating current suppression to obtain the total phase shift angle; The phase voltage calculation unit is configured to: obtain the first phase shift comparison value and the second phase shift comparison value corresponding to the upper carrier and the lower carrier respectively according to the total phase shift angle; obtain the phase voltage of the upper carrier according to the first phase shift comparison value and the second phase shift comparison value of the upper carrier; and obtain the phase voltage of the lower carrier according to the first phase shift comparison value and the second phase shift comparison value of the lower carrier. The dual phase-shift modulation unit is configured to generate the switching sequence of each power switch and control the three-level parallel inverter based on the phase voltages of the upcarrier and the downcarrier.

6. A computer device, characterized in that, include: Processor and computer-readable storage media; A processor, adapted to execute computer programs; A computer-readable storage medium storing a computer program, which, when executed by the processor, implements the three-level parallel inverter dual-phase shift modulation method as described in any one of claims 1 to 4.

7. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program adapted to be loaded by a processor and executed as described in any one of claims 1 to 4 for a two-phase-shift modulation method for a three-level parallel inverter.

8. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the three-level parallel inverter dual-phase shift modulation method as described in any one of claims 1 to 4.

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