ANPC three-level topology power module

Abstract

The present invention relates to the field of semiconductor technology, and in particular to an ANPC three-level topology power module, comprising an insulating plate, a metal layer, a metal pin and a power chip. Aiming at the problems that excessively high voltage spikes are generated when the module is switched due to large parasitic inductance of the module, affecting the working safety of the inverter, and that the all-silicon IGBT power module has large losses and low working efficiency when working, the voltage spikes are reduced and the working efficiency of the inverter is improved by folding the main power circuit of the power module in half and arranging them closely together and mixing silicon-based and silicon carbide-based power chips. The power module can be used in high-speed switching and high-frequency fields, and has significant practical value in high-power applications such as new energy and industrial frequency conversion that have high power density requirements.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an ANPC three-level topology power module. Background Art

[0002] High power, high frequency and high speed switching are an important development trend of power modules. Compared with two-level circuit topology, the power chip in three-level circuit topology has advantages such as low voltage stress, small voltage change rate and higher output power. The use of multi-level circuit topology is one of the effective means for power modules to achieve high efficiency and high power performance advantages.

[0003] The commonly used multi-level circuit topology is mainly the three-level circuit topology, which includes T-type three-level and I-type three-level circuit topologies, among which the I-type three-level circuit topology includes the diode neutral point clamped topology (NPC, Neutral Point Clamped) and the active neutral point clamped topology (ANPC, Active Neutral Point Clamped). The NPC three-level topology uses multiple capacitors on the neutral point to achieve multiple output voltage levels by using passive diodes to clamp the neutral point at a predefined voltage level. Since the device voltage stress is low, the switching loss is small; since no high-voltage power chip is required, its cost is relatively low; however, compared with the ANPC topology module, the NPC three-level module has higher conduction loss, the clamping diode is subjected to reverse recovery voltage, there is reverse recovery loss, and the DC bus capacitor charging and discharging is unbalanced. Usually an additional DC power supply is required to maintain the neutral point voltage.

[0004] The ANPC three-level topology uses active switches to clamp the neutral point voltage instead of relying on capacitors or passive diodes. The ANPC topology can also achieve multiple output voltage levels by dynamically adjusting the neutral point voltage, thereby improving the flexibility of the level output and optimizing the control performance. Due to the use of additional switches to control or clamp the neutral point voltage, the ANPC circuit topology power module usually has higher switching losses and better dynamic response.

[0005] Compared with silicon IGBT chips, silicon carbide MOSFET chips have high switching frequency and low switching loss. However, if the ANPC three-level topology power module adopts all silicon carbide chips, the module cost will increase significantly. The combination of silicon carbide MOSFET chips and silicon IGBT chips and their integration into the ANPC topology power module becomes a very effective and low-cost means to reduce the loss of the ANPC module. By constructing a power module with an ANPC topology structure that mixes silicon IGBT and silicon carbide MOSFET chips, combined with the optimization of the modulation strategy, the advantages of low switching loss of silicon carbide MOSFET and low on-state loss of silicon IGBT can be fully utilized, and the switching frequency and loss distribution of each device can be optimized, thereby improving the working efficiency and output switching frequency of the power module.

[0006] In order to give full play to the excellent potential of the power module with APNC circuit topology, how to build the ANPC circuit topology of the power module based on silicon IGBT chips and silicon carbide MOSFET chips is the main technical challenge that must be faced in the low-cost development of high-efficiency high-power modules. Summary of the invention

[0007] In view of this, the purpose of the present invention is to propose an ANPC three-level topology power module to solve the technical problem of how to build a low-cost, high-efficiency, high-power module based on silicon IGBT chips and silicon carbide MOSFET chips.

[0008] Based on the above purpose, the present invention provides an ANPC three-level topology power module, comprising:

[0009] An insulating plate, comprising a first insulating plate and a second insulating plate, wherein the second insulating plate and the first insulating plate are arranged side by side on the same plane along the X direction;

[0010] A metal layer, located on the upper surface of the insulating plate, including a patterned metal layer area, for realizing the circuit topology of the power module, wherein the metal layers on the first insulating plate and the second insulating plate are electrically connected via a metal layer connecting bridge;

[0011] Metal pins, including a "DC+" pin for inputting a positive DC bus, a "DC-" pin for inputting a negative DC bus, an "AC" pin for outputting an alternating current, and an "M" pin for midpoint potential clamping, wherein the metal pins are arranged on the metal layer;

[0012] A power chip, wherein the power chip is arranged on the metal layer and electrically connected to the metal layer;

[0013] The insulating plate, the metal layer, the metal pins and the power chip are connected to form a circuit topology structure of the power module, and the circuit topology structure is a three-level topology structure of active neutral point clamping (ANPC);

[0014] The "DC+" pin and the "DC-" pin of the main bridge arm of the three-level circuit topology are arranged on the right side of the module along the Y direction of the power module, and the "M" pin of the neutral point clamping of the clamping bridge arm of the three-level circuit topology and the "AC" pin of the main bridge arm outputting AC are arranged in the central area of ​​the module along the X direction of the module.

[0015] Preferably, the three-level topology structure includes a main bridge arm and a clamping bridge arm, wherein the main bridge arm includes four groups of power chips connected in series, wherein the first group of power chips includes a first silicon IGBT chip and a first freewheeling diode chip connected in anti-parallel thereto, the second group of power chips includes a first silicon carbide MOSFET chip connected in parallel and a second silicon carbide MOSFET chip connected in parallel, the third group of power chips includes a third silicon carbide MOSFET chip connected in parallel and a fourth silicon carbide MOSFET chip connected in parallel, the fourth group of power chips includes a fourth silicon IGBT chip and a fourth freewheeling diode chip connected in anti-parallel thereto, and the clamping bridge arm includes A fifth group of power chips and a sixth group of power chips are connected in series, wherein the fifth group of power chips includes a fifth silicon IGBT chip and a fifth freewheeling diode chip anti-parallel therewith, the collector of the fifth silicon IGBT chip is connected to the emitter of the first silicon IGBT chip and the drain of the silicon carbide MOSFET chip in the second group of power chips, and the sixth group of power chips includes a sixth silicon IGBT chip and a sixth freewheeling diode chip anti-parallel therewith, the emitter of the sixth silicon IGBT chip is connected to the source of the silicon carbide MOSFET in the third group of power chips and the collector of the fourth silicon IGBT chip.

[0016] Preferably, the "DC+" pin, the "DC-" pin, the first group of power chips, the fourth group of power chips, the first silicon carbide MOSFET chip, the fourth silicon carbide MOSFET chip and a portion of the "AC" pins are arranged on the metal layer on the upper surface of the first insulating board, and the fifth group of power chips, the sixth group of power chips and the second silicon carbide MOSFET chip, the third silicon carbide MOSFET chip, the "M" pin and another portion of the "AC" pins are arranged on the metal layer on the upper surface of the second insulating board.

[0017] Preferably, electrical connection is achieved between the metal layer area where the second silicon carbide MOSFET chip is arranged and the metal layer area where the first silicon carbide MOSFET chip is arranged, as well as between the metal layer area where the third silicon carbide MOSFET chip and the fourth silicon carbide MOSFET chip are arranged, through the metal layer connecting bridge.

[0018] Preferably, the metal layer area for layout of the first group of power chips and the metal layer area for layout of the fourth group of power chips are located on the side of the first insulating plate away from the second insulating plate, and the two metal layer areas are separated by the metal layer area for layout of the "DC-" pin, the metal layer area for layout of the first silicon carbide MOSFET chip and the metal layer area for layout of the fourth silicon carbide MOSFET chip are located in the half area of ​​the first insulating plate close to the second insulating plate and are close to each other, and the emitter strip metal layer area and the gate strip metal layer area corresponding to the emitter and gate of the fourth group of power chips are arranged in a direction opposite to the X direction and are arranged on one side of the metal layer area for layout of the "DC-" pin.

[0019] Preferably, the metal layer area for layout of the fifth group of power chips and the metal layer area for layout of the second silicon carbide MOSFET chips are a single connected area and are located on the upper surface of the upper half area of ​​the second insulating plate, the metal layer area for layout of the sixth group of power chips and the metal layer area for layout of the third silicon carbide MOSFET chips are arranged along the X direction and are located in the middle area of ​​the second insulating plate, the metal layer area corresponding to the emitter of the sixth group of power chips and the metal layer area corresponding to the source of the third silicon carbide MOSFET are a single connected area, the single connected area is arranged adjacent to the metal layer area for layout of the sixth group of power chips along the Y direction, and the pattern of the single connected area is in the shape of "⊥".

[0020] Preferably, the metal layer area corresponding to the layout of the third silicon carbide MOSFET chip, the layout of a part of the "AC" pins, and the source of the second silicon carbide MOSFET chip is a single connected area, and the single connected area is in a "T" shape. The metal layer area corresponding to the layout of the fourth silicon carbide MOSFET chip, the layout of another part of the "AC" pins, and the source of the first silicon carbide MOSFET chip is also a single connected area in a "T" shape. The two single connected areas are symmetrically distributed on both sides of the center line parallel to the Y direction of the power module.

[0021] Preferably, the first gate bar metal layer region corresponding to the gate of the first silicon carbide MOSFET chip and the second gate bar metal layer region corresponding to the gate of the second silicon carbide MOSFET chip are electrically connected through metal leads, the first source bar metal layer region corresponding to the source of the first silicon carbide MOSFET chip and the second source bar metal layer region corresponding to the source of the second silicon carbide MOSFET chip are electrically connected through metal leads, and the first gate bar metal layer region and the first source bar metal layer region are arranged adjacent to the metal layer region of the first silicon carbide MOSFET chip.

[0022] Preferably, the gate bar metal layer region corresponding to the gate of the third silicon carbide MOSFET chip and the gate of the fourth silicon carbide MOSFET chip is the same gate bar metal layer region, which is located on the upper surface of the second insulating plate, and the source bar metal layer region corresponding to the source of the third silicon carbide MOSFET chip and the source bar metal layer region is also the same source bar metal layer region, which is located on the upper surface of the first insulating plate, and the gate bar metal layer region and the source bar metal layer region are symmetrically distributed on both sides of a center line parallel to the Y direction of the power module.

[0023] Preferably, the metal layer area corresponding to the source of the third silicon carbide MOSFET chip and the metal layer area corresponding to the emitter of the sixth silicon IGBT chip are a single connected area, and the single connected area is in the shape of "⊥" and is arranged adjacent to the metal layer area of ​​the sixth group of power chips along the Y direction; the metal layer area corresponding to the source of the fourth silicon carbide MOSFET chip and the metal layer area of ​​the fourth group of power chips are a single connected area, and the single connected area is also in the shape of "⊥" and is arranged adjacent to the metal layer area of ​​the fourth silicon carbide MOSFET chip along the Y direction; the two "⊥"-shaped metal layer areas are also symmetrically distributed on both sides of the central axis parallel to the Y direction of the module, and are electrically connected to each other through the metal layer connecting bridge.

[0024] Beneficial effects of the present invention: The three-level circuit topology power module with active midpoint clamping feature proposed in the present invention aims to reduce voltage spikes and improve inverter working efficiency by folding the main power circuit of the power module in half and arranging them closely together and mixing silicon-based and silicon carbide-based power chips, in order to solve the problems of excessively high voltage spikes caused by large parasitic inductance of the module during module switching, which affects the working safety of the inverter, and large losses and low working efficiency of the all-silicon IGBT power module during operation. The power module can be used in high-speed switching and high-frequency fields, and has significant practical value in high-power applications such as new energy and industrial frequency conversion that have high power density requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only for the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0026] Figure 1 is a schematic diagram of the overall structure of a power module according to an embodiment of the present invention;

[0027] Figure 2 For the embodiment of the present invention Figure 1 A local enlarged schematic diagram of point A;

[0028] Figure 3 A schematic diagram of a circuit topology structure of a power module according to an embodiment of the present invention;

[0029] Figure 4 Schematic diagram of the projection structure of the power module of an embodiment of the present invention on the XY plane;

[0030] Figure 5 For the embodiment of the present invention Figure 4 A local enlarged schematic diagram of point B;

[0031] Figure 6 For the embodiment of the present invention Figure 4 A local enlarged schematic diagram of point C;

[0032] Figure 7 FIG. 4 is a schematic diagram of a design of a patterned metal layer of a power module according to an embodiment of the present invention. DETAILED DESCRIPTION

[0033] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments.

[0034] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the present invention should be understood by people with ordinary skills in the field to which the present invention belongs. The "first", "second" and similar words used in the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0035] like Figure 1 , Figure 2 As shown, an embodiment of the present specification provides an ANPC three-level topology power module, including: a first insulating plate 1, a second insulating plate 2, a metal layer connecting bridge 3, an input DC positive electrode "DC+" pin 4, an input DC negative electrode "DC-" pin 5, an output AC electrode "AC" pin 6, a midpoint potential clamping electrode "M" pin 7 and a metal lead 9.

[0036] like Figure 3The circuit topology of the power module is shown in the figure. The ports "DC+" and "DC-" are the positive and negative electrodes of the DC bus, respectively. The port "DC+" corresponds to Figure 1 The "DC+" pin 4 in the port corresponds to the "DC-" pin Figure 1 The "DC-" pin 5 in the port "AC" is mainly used to output the alternating current signal "AC", corresponding to Figure 1 The "AC" electrode in 6; port "M" corresponds to Figure 1 The midpoint clamping electrode "M" pin 7 in the middle; the IGBT1 chip and the freewheeling diode chip D1 connected in anti-parallel therewith constitute the first group of power chips; the IGBT4 chip and the freewheeling diode chip D4 connected in anti-parallel therewith constitute the fourth group of power chips; the IGBT5 chip and the freewheeling diode chip D5 connected in anti-parallel therewith constitute the fifth group of power chips, and the IGBT6 chip and the freewheeling diode chip D6 connected in anti-parallel therewith constitute the sixth group of power chips; MOS2 is the second group of power chips, which includes the first silicon carbide MOSFET chip and the second silicon carbide MOSFET chip connected in parallel therewith; MOS3 is the third group of power chips, which includes the third silicon carbide MOSFET chip and the fourth silicon carbide MOSFET chip connected in parallel therewith. The circuit topology of the main bridge arm formed by the first to fourth groups of power chips is connected in series, and the circuit topology of the clamping bridge arm formed by the fifth and sixth groups of power chips is also connected in series, wherein the collector of IGBT5 in the fifth group of power chips is connected to the emitter of IGBT1 in the first group of power chips and the drain of MOS2 in the second group of power chips, and the emitter of IGBT6 in the sixth group of power chips is connected to the source of MOS3 in the third group of power chips and the collector of IGBT4 in the fourth group of power chips.

[0037] like Figure 4-6 It is a schematic diagram of the structural projection of the power module in the XY plane, including: a first insulating layer 1, a second insulating layer 2, a metal layer connecting bridge 3, a "DC+" pin 4, a "DC-" pin 5, an "AC" pin 6, an "M" pin 7, a first freewheeling diode chip 11, a first silicon carbide MOSFET chip 21, a second silicon carbide MOSFET chip 22, a third silicon carbide MOSFET chip 32, a fourth silicon carbide MOSFET chip 31, a fifth silicon IGBT chip 50, and a sixth silicon IGBT chip 60.

[0038] like Figure 7 The figure shows the schematic diagram of the power mode patterned metal layer design, including:

[0039] The metal layer area located on the upper surface of the first insulating plate 1 includes: a single connected area 100 composed of a metal layer area 105 for arranging the "DC+" pin 4 and a metal layer area 110 for arranging the first group of power chips, a source strip metal layer area 111 corresponding to the source of the IGBT1 chip in the first group of power chips, and a gate strip metal layer area 112 corresponding to the gate;

[0040] Laying out the metal layer region 210 of the first silicon carbide MOSFET chip, the gate bar metal layer region 211 corresponding to the gate of the first silicon carbide MOSFET chip, and the source bar metal layer region 212 corresponding to the source in the second group of power chips;

[0041] A metal layer region 310 for arranging the fourth silicon carbide MOSFET chip in the third group of power chips, a source strip metal layer region 312 corresponding to the source of the fourth silicon carbide MOSFET chip and the source of the third silicon carbide MOSFET chip, and a single connected region 340 formed by the metal layer region 310 for arranging the fourth silicon carbide MOSFET chip and a metal layer region 315 for arranging a part of the "AC" pins;

[0042] A single connected metal layer region 400 consisting of a metal layer region 314 corresponding to the source of the fourth silicon carbide MOSFET chip and a metal layer region 410 for arranging the fourth group of power chips, a metal layer region 405 for arranging the "DC-" pin, and an emitter strip metal layer region 412 and a gate strip metal layer region 411 corresponding to the emitter and gate of the fourth silicon IGBT chip in the fourth group of power chips; and the metal layer region located on the upper surface of the second insulating plate 2 includes: a metal layer region 220 for arranging the second silicon carbide MOSFET chip, a gate strip metal layer region 221 corresponding to the gate of the second silicon carbide MOSFET chip, a source strip metal layer region 222 corresponding to the source of the second silicon carbide MOSFET chip, and a single connected metal layer region 500 consisting of a metal layer region 220 for arranging the second silicon carbide MOSFET chip and a metal layer region 510 for arranging the fifth group of power chips;

[0043] The metal layer region 320 for laying out the third silicon carbide MOSFET chip, the gate bar metal layer region 321 corresponding to the gate of the third silicon carbide MOSFET chip and the gate of the fourth silicon carbide MOSFET chip, the metal layer region 324 corresponding to the source of the third silicon carbide MOSFET chip, and the metal layer region 325 for laying out another part of the "AC" pins;

[0044] The metal layer region 610 for arranging the sixth group of power chips, the metal layer region 605 for arranging the midpoint clamping electrode "M" pin, and the single connected metal layer region 600 consisting of the metal layer region 605 for arranging the midpoint clamping electrode "M" pin, the region 610 for arranging the sixth group of power chips, and the metal layer region 514 corresponding to the emitter of the IGBT5 chip in the fifth group of power chips;

[0045] A single connected area 330 is formed by the metal layer area 320 for arranging the third silicon carbide MOSFET chip, the metal layer area 325 for arranging a part of the "AC" pins, and the metal layer area corresponding to the source of the second silicon carbide MOSFET chip, and the metal layer area is in a "T" shape as a whole; and a single connected metal layer area 420 is formed by the metal layer area 324 corresponding to the source of the third silicon carbide MOSFET chip and the metal layer area 614 corresponding to the emitter of the IGBT6 chip (sixth silicon IGBT chip) in the sixth group of power chips, and the metal layer area 420 is in a "⊥" shape as a whole.

[0046] A power module and a structural design thereof according to an embodiment of the present invention include:

[0047] An insulating plate, comprising a first insulating plate 1 and a second insulating plate 2, wherein the second insulating plate and the first insulating plate are arranged in parallel on the same plane along the X direction, and the sizes of the second insulating plate and the first insulating plate are consistent with each other; a metal layer, comprising various patterned metal layer areas with consistent thickness but different shapes, the metal layer is used to realize the circuit topology structure of the power module, and the metal layer is located on the upper surface of the insulating plate; a power chip, the power chip is arranged on the metal layer; metal pins, comprising a "DC+" pin 4 for inputting a positive DC bus, a "DC-" pin 5 for inputting a negative DC bus, an "AC" pin 6 for outputting an alternating current, and an "M" pin 7 for midpoint potential clamping, and the metal pins are also arranged on the metal layer; a metal layer connecting bridge 3, used to realize FIG. The metal layer regions are electrically connected to each other, and the metal layer connecting bridge is also arranged on the metal layer; the metal lead 9 is used to realize the electrical connection between the power chip and the patterned metal layer region; and the insulating board, the metal layer, the power chip, the metal pin, the metal layer connecting bridge 3 and the metal lead 9 are overlapped to form a circuit topology structure of the power module, the circuit topology structure of the power module is a three-level topology structure with active neutral point clamping, the "DC+" pin 4 and the "DC-" pin 5 of the main bridge arm of the three-level circuit topology are arranged on the right side of the module along the Y direction of the power module, and the neutral point clamping "M" pin 7 of the three-level circuit topology clamping bridge arm and the "AC" pin 6 of the main bridge arm outputting alternating current are arranged in the central area of ​​the module along the X direction of the module.

[0048] The three-level topology structure includes a main bridge arm and a clamping bridge arm, wherein the main bridge arm is formed by four groups of power chips connected in series, wherein the first group of power chips includes a first silicon IGBT chip 10 and a first freewheeling diode chip 11 connected in anti-parallel thereto, the second group of power chips includes a first silicon carbide MOSFET chip 21 connected in parallel and a second silicon carbide MOSFET chip 22 connected in parallel, the third group of power chips includes a third silicon carbide MOSFET chip 32 connected in parallel and a fourth silicon carbide MOSFET chip 31 connected in parallel, the fourth group of power chips includes a fourth silicon IGBT chip 40 and a fourth freewheeling diode chip 41 connected in anti-parallel thereto, and the clamping bridge arm is formed by a fifth group of power chips and a sixth group of power chips connected in series The fifth group of power chips includes a fifth silicon IGBT chip 50 and a fifth freewheeling diode chip 51 connected in anti-parallel thereto, the collector of the fifth silicon IGBT chip 50 in the fifth group of power chips is connected to the emitter of the first silicon IGBT chip 10 in the first group of power chips and the drain of the silicon carbide MOSFET chip in the second group of power chips, the sixth group of power chips includes a sixth silicon IGBT chip 60 and a sixth freewheeling diode chip 61 connected in anti-parallel thereto, the emitter of the sixth silicon IGBT chip 60 in the sixth group of power chips is connected to the source of the silicon carbide MOSFET in the third group of power chips and the collector of the fourth silicon IGBT chip 40 in the fourth group of power chips;

[0049] The “DC+” pin 4, the “DC-” pin 5, the first group of power chips, the fourth group of power chips, the first silicon carbide MOSFET chip 21, the fourth silicon carbide MOSFET chip 31 and a part of the “AC” pins are arranged on the metal layer on the upper surface of the first insulating board 1, and the fifth group of power chips, the sixth group of power chips and the second silicon carbide MOSFET chip 22, the third silicon carbide MOSFET chip 32, the “M” pin 7 and another part of the “AC” pins are arranged on the metal layer on the upper surface of the second insulating board 2;

[0050] The metal layer region where the second silicon carbide MOSFET chip 22 is arranged and the metal layer region where the first silicon carbide MOSFET chip 21 is arranged are electrically connected through the metal layer connecting bridge 3, and the metal layer region where the third silicon carbide MOSFET chip 32 is arranged and the fourth silicon carbide MOSFET chip 31 is also electrically connected through the metal layer connecting bridge 3;

[0051] The metal layer area on the upper surface of the first insulating plate 1, the metal layer area 110 for arranging the first group of power chips and the metal layer area 410 for arranging the fourth group of power chips are located on the upper surface of the right half area of ​​the first insulating plate 1, and the two are separated by the metal layer area 405 for arranging the "DC-" pin, the metal layer area 210 for arranging the first silicon carbide MOSFET chip and the metal layer area 310 for arranging the fourth silicon carbide MOSFET chip are located on the upper surface of the left half area of ​​the first insulating plate and are adjacent to each other, and the emitter bar metal area 412 and the gate bar metal area 411 corresponding to the emitter and gate of the fourth group of power chips are arranged in the direction opposite to the X direction and are arranged on the left side of the metal layer area 405 for arranging the "DC-" pin;

[0052] The metal layer area on the upper surface of the second insulating plate 2, the metal layer area 510 for arranging the fifth group of power chips and the metal layer area 220 for arranging the second silicon carbide MOSFET chip are a single connected area 500 and are located on the upper surface of the upper half of the second insulating plate 2, the metal layer area 610 for arranging the sixth group of power chips and the metal layer area 320 for arranging the third silicon carbide MOSFET chip are arranged along the X direction and are located in the middle area of ​​the second insulating plate 2, the metal layer area 614 corresponding to the emitter of the sixth group of power chips and the metal layer area 324 corresponding to the source of the third silicon carbide MOSFET are a single connected area 420, the single connected area 420 is arranged along the Y direction next to the metal layer area 610 for arranging the sixth group of power chips, and the pattern of the single connected area is in a "⊥" shape;

[0053] The area 320 where the third silicon carbide MOSFET chip is laid out, the metal layer area 325 where a part of the "AC" pins are laid out and the source of the second silicon carbide MOSFET chip corresponds to form a single connected area 330, and the single connected area is in a "T" shape. The metal layer area 310 where the fourth silicon carbide MOSFET chip is laid out, the metal layer area 315 where another part of the "AC" pins are laid out and the source of the first silicon carbide MOSFET chip corresponds to form a single connected area 340 in a "T" shape. The two single connected areas 330 and 340 are symmetrically distributed on both sides of the center line parallel to the Y direction of the power module.

[0054] The gate bar metal layer region 211 corresponding to the gate of the first silicon carbide MOSFET chip and the gate bar metal layer region 221 corresponding to the gate of the second silicon carbide MOSFET chip are electrically connected through metal wires, and the source bar metal layer region 212 corresponding to the source of the first silicon carbide MOSFET chip and the source bar metal layer region 222 corresponding to the source of the second silicon carbide MOSFET chip are electrically connected through metal wires, and the gate bar metal region 211 and the source bar metal layer region 212 are arranged adjacent to the metal layer region 210 of the first silicon carbide MOSFET chip. Specifically, the source bar metal layer region 212 is adjacent to the metal layer region 210 of the first silicon carbide MOSFET chip, and the gate bar metal region 211 is adjacent to the source bar metal layer region 212;

[0055] The gate bar metal layer region corresponding to the gate of the third silicon carbide MOSFET chip and the gate of the fourth silicon carbide MOSFET chip is the same gate bar metal layer region 321, and the gate bar metal layer region 321 is located on the upper surface of the second insulating plate 2. The source bar metal layer region corresponding to the source of the third silicon carbide MOSFET chip and the source of the fourth silicon carbide MOSFET chip is also the same source bar metal layer region, and the source bar metal layer region 312 is located on the upper surface of the first insulating plate 1. The gate bar metal layer region 321 and the source bar metal layer region 312 are symmetrically distributed on both sides of the center line parallel to the Y direction of the power module;

[0056] The metal layer region 324 corresponding to the source of the third silicon carbide MOSFET chip and the metal layer region 614 corresponding to the emitter of the silicon IGBT chip in the sixth group of power chips are a single connected region 420, which is in the shape of "⊥" and is arranged adjacent to the metal layer region 610 of the sixth group of power chips along the Y direction; the metal layer region 314 corresponding to the source of the fourth silicon carbide MOSFET chip and the metal layer region 410 of the fourth group of power chips are a single connected region 400, which is also in the shape of "⊥" and is arranged adjacent to the metal layer region 340 of the fourth silicon carbide MOSFET chip along the Y direction; the two metal layer regions 420 and 400 in the shape of "⊥" are also symmetrically distributed on both sides of the central axis parallel to the Y direction of the module, and are electrically connected to each other through the metal layer connecting bridge 3.

[0057] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present invention (including the claims) is limited to these examples. Under the concept of the present invention, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the present invention as described above, which are not provided in detail for the sake of simplicity.

[0058] The present invention is intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. An ANPC three-level topology power module, characterized in that: include: An insulating plate, comprising a first insulating plate and a second insulating plate, wherein the second insulating plate and the first insulating plate are arranged side by side on the same plane along the X direction; A metal layer, located on the upper surface of the insulating plate, including a patterned metal layer area, for realizing the circuit topology of the power module, wherein the metal layers on the first insulating plate and the second insulating plate are electrically connected via a metal layer connecting bridge; Metal pins, including a "DC+" pin for inputting a positive DC bus, a "DC-" pin for inputting a negative DC bus, an "AC" pin for outputting an alternating current, and an "M" pin for midpoint potential clamping, wherein the metal pins are arranged on the metal layer; A power chip, wherein the power chip is arranged on the metal layer and electrically connected to the metal layer; The insulating plate, the metal layer, the metal pins and the power chip are connected to form a circuit topology structure of the power module, and the circuit topology structure is a three-level topology structure with active neutral point clamping; The "DC+" pin and the "DC-" pin of the three-level topology main bridge arm are arranged on the right side of the module along the Y direction of the power module, and the "M" pin of the neutral point clamping of the three-level topology clamping bridge arm and the "AC" pin of the main bridge arm outputting AC are arranged in the central area of ​​the module along the X direction of the module; The three-level topology structure includes a main bridge arm and a clamping bridge arm, wherein the main bridge arm includes four groups of power chips connected in series, wherein the first group of power chips includes a first silicon IGBT chip and a first freewheeling diode chip connected in anti-parallel therewith, the second group of power chips includes a first silicon carbide MOSFET chip connected in parallel and a second silicon carbide MOSFET chip connected in parallel, the third group of power chips includes a third silicon carbide MOSFET chip connected in parallel and a fourth silicon carbide MOSFET chip connected in parallel, the fourth group of power chips includes a fourth silicon IGBT chip and a fourth freewheeling diode chip connected in anti-parallel therewith, and the clamping bridge arm includes a series of A fifth group of power chips and a sixth group of power chips connected in parallel, wherein the fifth group of power chips includes a fifth silicon IGBT chip and a fifth freewheeling diode chip connected in anti-parallel thereto, the collector of the fifth silicon IGBT chip is connected to the emitter of the first silicon IGBT chip and the drain of the silicon carbide MOSFET chip in the second group of power chips, the sixth group of power chips includes a sixth silicon IGBT chip and a sixth freewheeling diode chip connected in anti-parallel thereto, the emitter of the sixth silicon IGBT chip is connected to the source of the silicon carbide MOSFET in the third group of power chips and the collector of the fourth silicon IGBT chip; The "DC+" pin, the "DC-" pin, the first group of power chips, the fourth group of power chips, the first silicon carbide MOSFET chip, the fourth silicon carbide MOSFET chip and a portion of the "AC" pins are arranged on the metal layer on the upper surface of the first insulating board, and the fifth group of power chips, the sixth group of power chips and the second silicon carbide MOSFET chip, the third silicon carbide MOSFET chip, the "M" pin and another portion of the "AC" pins are arranged on the metal layer on the upper surface of the second insulating board.

2. The ANPC three-level topology power module according to claim 1, characterized in that: The metal layer areas where the second silicon carbide MOSFET chip is arranged and the metal layer areas where the first silicon carbide MOSFET chip is arranged, as well as the metal layer areas where the third silicon carbide MOSFET chip and the fourth silicon carbide MOSFET chip are arranged are electrically connected through the metal layer connecting bridge.

3. The ANPC three-level topology power module according to claim 1, characterized in that: The metal layer area for layout of the first group of power chips and the metal layer area for layout of the fourth group of power chips are located on the side of the first insulating plate away from the second insulating plate, and the two metal layer areas are separated by the metal layer area for layout of the "DC-" pin, the metal layer area for layout of the first silicon carbide MOSFET chip and the metal layer area for layout of the fourth silicon carbide MOSFET chip are located in the half area of ​​the first insulating plate close to the second insulating plate and are close to each other, and the emitter bar metal layer area and the gate bar metal layer area corresponding to the emitter and gate of the fourth group of power chips are arranged in a direction opposite to the X direction and are arranged on one side of the metal layer area for layout of the "DC-" pin.

4. The ANPC three-level topology power module according to claim 1, characterized in that: The metal layer area for laying out the fifth group of power chips and the metal layer area for laying out the second silicon carbide MOSFET chip are a single connected area and are located on the upper surface of the upper half area of ​​the second insulating plate, the metal layer area for laying out the sixth group of power chips and the metal layer area for laying out the third silicon carbide MOSFET chip are arranged along the X direction and are located in the middle area of ​​the second insulating plate, the metal layer area corresponding to the emitter of the sixth group of power chips and the metal layer area corresponding to the source of the third silicon carbide MOSFET are a single connected area, the single connected area is arranged adjacent to the metal layer area for laying out the sixth group of power chips along the Y direction, and the pattern of the single connected area is in a "⊥" shape.

5. The ANPC three-level topology power module according to claim 1, characterized in that: The metal layer area corresponding to the layout of the third silicon carbide MOSFET chip, the layout of a part of the "AC" pins, and the source of the second silicon carbide MOSFET chip is a single connected area, and the single connected area is "T" shaped. The metal layer area corresponding to the layout of the fourth silicon carbide MOSFET chip, the layout of another part of the "AC" pins, and the source of the first silicon carbide MOSFET chip is also a single connected area in a "T" shape. The two single connected areas are symmetrically distributed on both sides of the center line parallel to the Y direction of the power module.

6. The ANPC three-level topology power module according to claim 1, characterized in that: The first gate bar metal layer region corresponding to the gate of the first silicon carbide MOSFET chip and the second gate bar metal layer region corresponding to the gate of the second silicon carbide MOSFET chip are electrically connected through metal leads, the first source bar metal layer region corresponding to the source of the first silicon carbide MOSFET chip and the second source bar metal layer region corresponding to the source of the second silicon carbide MOSFET chip are electrically connected through metal leads, and the first gate bar metal layer region and the first source bar metal layer region are arranged adjacent to the metal layer region of the first silicon carbide MOSFET chip.

7. The ANPC three-level topology power module according to claim 1, characterized in that: The gate bar metal layer region corresponding to the gate of the third silicon carbide MOSFET chip and the gate of the fourth silicon carbide MOSFET chip is the same gate bar metal layer region, which is located on the upper surface of the second insulating plate. The source bar metal layer region corresponding to the source of the third silicon carbide MOSFET chip and the source bar metal layer region is also the same source bar metal layer region, which is located on the upper surface of the first insulating plate. The gate bar metal layer region and the source bar metal layer region are symmetrically distributed on both sides of a center line parallel to the Y direction of the power module.

8. The ANPC three-level topology power module according to claim 1, characterized in that: The metal layer area corresponding to the source of the third silicon carbide MOSFET chip and the metal layer area corresponding to the emitter of the sixth silicon IGBT chip are a single connected area, and the single connected area is in a "⊥" shape and is arranged adjacent to the metal layer area of ​​the sixth group of power chips along the Y direction; the metal layer area corresponding to the source of the fourth silicon carbide MOSFET chip and the metal layer area of ​​the fourth group of power chips are a single connected area, and the single connected area is also in a "⊥" shape and is arranged adjacent to the metal layer area of ​​the fourth silicon carbide MOSFET chip along the Y direction; the two "⊥"-shaped metal layer areas are also symmetrically distributed on both sides of the central axis parallel to the Y direction of the module, and are electrically connected to each other through the metal layer connecting bridge.

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