Semiconductor device performance degradation testing method and system

Abstract

The present invention provides a method and system for testing semiconductor device performance degradation, belonging to the field of semiconductors. The method includes measuring multiple sets of step voltage data using different voltage ramp rates, fitting the measured data to a log-normal distribution, and obtaining a first threshold voltage offset at a fixed voltage under different voltage ramp rates; obtaining a time factor based on the first threshold voltage offset and the voltage ramp rate; and obtaining a voltage acceleration factor based on the first threshold voltage offset and different applied voltages. By measuring multiple sets of step voltage data using different voltage ramp rates and fitting the data, the present invention obtains the time factor, the voltage acceleration factor, and the log-normal distribution σ2 of the failure time, thereby determining the failure time of the semiconductor device, significantly shortening the HCI and BTI testing time of the semiconductor device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method and system for testing performance degradation of a semiconductor device. Background Art

[0002] Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) are widely used test methods for semiconductor reliability performance characterization. They characterize the device performance degradation of field-effect transistors (MOSFETs) under the influence of temperature and voltage.

[0003] Ginseng Figure 1 As shown, Figure 1 This is a diagram of traditional HCI and BTI testing, where constant voltage stress (CVS) is applied to the MOSFET structure. The degradation of device parameters (such as voltage and current) is continuously monitored. For example, the Vt voltage is recorded at a series of time points, and the failure time until Vt degrades to a certain value (such as 50mV) is calculated. Three different drain voltages are typically applied, with more than five samples tested at each voltage. The failure time for each sample is recorded at each voltage.

[0004] After the three CVS voltage tests are completed, the voltage acceleration factor m is fitted based on a certain failure model, generally a power law model, that is, failure time Tbd = A*Vd^(-n), to calculate the failure time Tbd_use under normal use voltage Vuse conditions. At this time, the failure time Tbd_use is T50_use according to the log-normal distribution. All failed samples are fitted with the σ value of their distribution according to the log-normal distribution, and then the conversion from T50_use to T0.1_use is completed. T0.1_use is the final test failure time used to determine the failure of the device. Generally, due to the long CVS failure time of a structural test, the entire test takes an average of 2 to 3 days to complete, and the test is time-consuming.

[0005] It should be noted that the information disclosed in the background technology section of the invention is only intended to deepen the understanding of the general background technology of the invention, and should not be regarded as an admission or any form of implication that the information constitutes prior art already known to those skilled in the art. Summary of the Invention

[0006] The object of the present invention is to provide a method and system for testing performance degradation of a semiconductor device, so as to solve the problem of a long time consumption when testing the failure time of performance degradation of a semiconductor device.

[0007] To solve the above technical problems, the present invention provides a method for testing performance degradation of a semiconductor device, comprising:

[0008] Multiple sets of step voltage data are measured using different voltage increase rates, and the measured data are fitted with a logarithmic normal distribution to obtain the first threshold voltage offset at a fixed voltage under different voltage increase rates;

[0009] Obtaining a time factor based on the first threshold voltage offset and the voltage increase rate;

[0010] Obtaining a voltage acceleration factor based on the first threshold voltage shift and different applied voltages;

[0011] Obtain a second threshold voltage offset under a certain applied voltage, calculate a logarithmic normal distribution value σ1 of the second threshold voltage offset, and obtain a logarithmic normal distribution σ2 of the failure time based on σ1;

[0012] The failure time of the semiconductor device is obtained based on the time factor, the voltage acceleration factor and σ2.

[0013] Preferably, obtaining the time factor based on the first threshold voltage offset and the voltage increase rate includes:

[0014] Perform a linear fit on the first threshold voltage offset and different voltage increase rates to obtain a slope of the linear fit, and the slope is the time factor n.

[0015] Preferably, obtaining a voltage acceleration factor based on the first threshold voltage shift and different applied voltages includes:

[0016] A functional relationship between the first threshold voltage offset and different applied voltages is established, and the difference between the slope of the functional relationship and the time factor is the voltage acceleration factor m, that is, S=m+n, where S is the slope of the functional relationship, m is the voltage acceleration factor, and n is the time factor.

[0017] Preferably, the functional relationship between the threshold voltage shift and different applied voltages is established as follows:

[0018] Where ΔVT(RR,Vg) is the threshold voltage shift, Vg is the applied voltage, RR is the voltage increase rate, m is the voltage acceleration factor, n is the time factor, and A is a constant.

[0019] Preferably, obtaining the normal distribution σ2 of the failure time logarithm based on σ1 includes:

[0020] Where n is the time factor.

[0021] Preferably, obtaining the failure time of the semiconductor device based on the time factor, the voltage acceleration factor and σ2 includes:

[0022] The voltage acceleration factor and σ2 are used to fit the power law model to obtain the failure time of semiconductor devices.

[0023] Preferably, the voltage is a gate voltage.

[0024] Preferably, the voltage is a drain voltage.

[0025] Preferably, the multiple sets of step voltages are positive voltages or negative voltages.

[0026] Based on the same inventive concept, the present invention also provides a semiconductor device performance degradation testing system, comprising:

[0027] An acquisition module is used to measure multiple sets of step voltage data using different voltage increase rates, and perform logarithmic normal distribution fitting on the measured data to obtain a first threshold voltage offset at a fixed voltage under different voltage increase rates;

[0028] A processing module is used to obtain a time factor based on the first threshold voltage offset and the voltage increase rate; obtain a voltage acceleration factor based on the first threshold voltage offset and different applied voltages; obtain a second threshold voltage offset under a certain applied voltage, calculate the logarithmic normal distribution value σ1 of the second threshold voltage offset, and obtain the failure time logarithmic normal distribution σ2 based on σ1; and obtain the failure time of the semiconductor device based on the time factor, the voltage acceleration factor and σ2.

[0029] Compared with the prior art, the method for testing semiconductor device performance degradation of the present invention has the following advantages:

[0030] The present invention measures multiple sets of step voltage data using different voltage ramp rates and performs log-normal distribution fitting on the measured data to obtain a first threshold voltage offset at a fixed voltage under different voltage ramp rates. A time factor is obtained based on the first threshold voltage offset and the voltage ramp rate. A voltage acceleration factor is obtained based on the first threshold voltage offset and different applied voltages. A second threshold voltage offset is obtained under a certain applied voltage, and the log-normal distribution value σ1 of the second threshold voltage offset is calculated. Based on σ1, a log-normal distribution σ2 of the failure time is obtained. The failure time of the semiconductor device is obtained based on the time factor, voltage acceleration factor, and σ2. The semiconductor device performance degradation testing method of the present invention measures multiple sets of step voltage data using different voltage ramp rates instead of applying a constant drain and gate voltage to a MOSFET structure. The data are then fitted to obtain the time factor, voltage acceleration factor, and log-normal distribution σ2 of the failure time, thereby obtaining the failure time of the semiconductor device. The entire test takes 2-3 hours, significantly shortening the HCI and BTI test time of the semiconductor device and saving testing resources and time.

[0031] The semiconductor device performance degradation testing system provided by the present invention and the semiconductor device performance degradation testing method provided by the present invention belong to the same inventive concept. Therefore, the semiconductor device performance degradation testing system provided by the present invention has at least all the advantages of the semiconductor device performance degradation testing method provided by the present invention, and can greatly shorten the HCI and BTI testing time of semiconductor devices, saving testing resources and time. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 It is a schematic diagram of applying constant drain and gate voltages to the MOSFET structure;

[0033] Figure 2 is a flow chart of a method for testing performance degradation of a semiconductor device in one embodiment of the present invention;

[0034] Figure 3 This is a schematic diagram of a BTI test in one embodiment of the present invention;

[0035] Figure 4 is a schematic diagram of HCI measurement in one embodiment of the present invention;

[0036] Figure 5 is a schematic diagram of linear fitting of threshold voltage shift and voltage rise rate in one embodiment of the present invention;

[0037] Figure 6 is a functional relationship diagram of different voltage boost rates and threshold voltage shifts in one embodiment of the present invention;

[0038] Figure 7The following is a comparison chart of the results of measurement using CVS and VRS. DETAILED DESCRIPTION

[0039] To make the objects, advantages and features of the present invention clearer, the method and system for testing semiconductor device performance degradation proposed by the present invention are further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not in exact proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. It should be understood that the drawings in the specification do not necessarily show the specific structure of the present invention to scale, and the illustrative features used to illustrate certain principles of the present invention in the drawings in the specification may also be slightly simplified. The specific design features of the present invention disclosed herein, including, for example, specific dimensions, directions, positions and shapes, will be determined in part by the specific application and use environment. In addition, in the embodiments described below, the same figure mark is sometimes used in common between different drawings to represent the same part or part with the same function, and its repeated description is omitted. In this specification, similar numbers and letters are used to represent similar items. Therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0040] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0041] In the description of this specification, the reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0042] The core idea of ​​the present invention is to provide a method for testing performance degradation of a semiconductor device, which can shorten the test time of HCI and BTI.

[0043] In order to realize the above idea, the present invention provides a method for testing the performance degradation of a semiconductor device. Figures 2 to 7A specific embodiment of a method for testing semiconductor device performance degradation is disclosed. In the prior art, the failure time of HCI and BTI is measured by applying a constant drain and gate voltage (Constant Voltage Stress, CVS) to the MOSFET structure. In the present application, the failure time of HCI and BTI is measured by applying a step voltage (Voltage Ramp Stress, VRS) to the MOSFET structure. The present application converts the VRS model into a CVS model to obtain the time factor n and voltage acceleration factor m under the CVS model, and then calculates the final failure time using the power law distribution function model in the prior art.

[0044] The method for testing performance degradation of a semiconductor device includes the following steps S1 to S5.

[0045] Step S1: measuring multiple sets of step voltage data using different voltage increasing rates, and performing logarithmic normal distribution fitting on the measured data to obtain the threshold voltage offset at a fixed voltage under different voltage increasing rates.

[0046] Specifically, refer to Figures 1 to 4 As shown in FIG, multiple voltage ramp rates (RampRate, RR) are set, and multiple step voltages of semiconductor devices (such as MOSFET) are measured at different voltage ramp rates to form a graph as shown in FIG. Figure 3 and Figure 4 The schematic diagram is shown. Logarithmic normal distribution fitting is performed respectively to obtain the threshold voltage shift (Vt_shift) at a fixed voltage under different voltage increase rates. Figure 3 and Figure 4 It can be seen that when measuring the voltage of the MOSFET, it can be the gate voltage of the MOSFET or the drain voltage. Figure 3 The area shown in 10a is the electrical performance parameters of the MOSFET measured before measuring the step voltage of the MOSFET, such as gate current, drain current, etc., which are used to compare with the electrical performance parameters measured subsequently to determine the degradation of the MOSFET. Since the gate current and drain current are irrelevant to the content to be disclosed in this embodiment, they are not explained here. The schematic diagram shown after the area shown in 10a is a schematic diagram of the gate step voltage over time. Figure 4 It can be seen that when measuring the gate voltage of a MOSFET, either a positive voltage or a negative voltage can be applied.

[0047] Step S2: obtaining a time factor based on the first threshold voltage offset and the voltage increase rate.

[0048] Specifically, refer to Figure 2 and Figure 5As shown in FIG, the threshold voltage offset and the voltage rise rate are linearly fitted to obtain the slope of the linear fit, which is the time factor n. Figure 5 As shown, in this embodiment, the slopes of the threshold voltage shift (ie, ΔVt) and the voltage rise rate (ie, RR) are -0.18=-n, and the time factor n is 0.18.

[0049] Step S3: Obtaining a voltage acceleration factor based on the first threshold voltage shift and different applied voltages.

[0050] Specifically, refer to Figure 2 、 Figure 6 and Figure 7 As shown, taking the gate voltage as an example, the functional relationship between the threshold voltage shift and different applied voltages is established as follows:

[0051] The functional relationship between the threshold voltage shift and different applied voltages is established as:

[0052] Where, ΔV T (RR, Vg) is the threshold voltage offset, Vg is the applied voltage, RR is the voltage increase rate, m is the voltage acceleration factor, n is the time factor, and A is a constant. The difference between the slope of the function relationship and the time factor is the voltage acceleration factor m, that is, S = m + n, where S is the slope of the function relationship, m is the voltage acceleration factor, and n is the time factor. Figure 7 The measurement results show that in this embodiment, S = m + n = 5.6. From step S2, we know that the time factor n is 0.18, so the voltage acceleration factor m can be calculated to be 5.42. And in this step, when the voltage acceleration factor m and the time factor n are known, and ΔV is obtained by measurement T The value of (RR, Vg) can be used to calculate the value of constant A.

[0053] It should be noted that the values ​​of the time factor n and the voltage acceleration factor m measured for different MOSFETs are different. The time factor n of 0.18 and the voltage acceleration factor m of 0.542 disclosed in this embodiment are only one embodiment.

[0054] Step S4: obtaining a second threshold voltage offset under a certain applied voltage, calculating a logarithmic normal distribution value σ1 of the second threshold voltage offset, and obtaining a logarithmic normal distribution σ2 of the failure time based on σ1.

[0055] Specifically, refer to Figure 2 As shown, the second threshold voltage shift of N MOSFETs under a certain applied voltage is measured, the logarithmic normal distribution value σ1 of the second threshold voltage shift is calculated, and according to the formula Calculate the normal distribution of the failure time logarithm σ2. In this formula, n is the time factor, and the value of the time factor n has been calculated in step S2. It should be noted that the first threshold voltage offset and the second threshold voltage offset.

[0056] Step S5: Obtaining the failure time of the semiconductor device based on the time factor, the voltage acceleration factor and σ2.

[0057] Specifically, refer to Figure 2 and Figure 7 As shown in Figure 1, the time factor, voltage acceleration factor, and σ2 are used to fit the powerlaw model to obtain the failure time of the MOSFET. The device parameter degradation formula of CVS can be expressed as: ΔV T (t, Vg) = At n Vg m , where A is a constant, t is time, Vg is the gate voltage, ΔV T (t, Vg) is the threshold voltage shift.

[0058] The device parameter degradation calculated by CVS is the median value of ΔVt that satisfies the lognormal distribution, namely ΔVt_50%. The final CVS judgment standard is the device degradation value at the 99.9% distribution, ΔVt_99.9%. The conversion formula between the two is: ΔVt_99.9% = ΔVt_50% * exp(3.09 * σ_cvs). Substituting the values ​​of σ2, m, and n into the CVS device parameter degradation formula, the final CVS value corresponding to ΔVt_99.9% is obtained, which is the failure time of the semiconductor device.

[0059] Ginseng Figure 7 As shown in the figure, when measuring the MOSFET failure time using CVS, the measured time factor is 0.16-0.18, and the voltage acceleration factor m is 5.46. However, when measuring the MOSFET failure time using VRS, the measured time factor is 0.18, and the voltage acceleration factor m is 5.42. This data set shows that the two sets of data are nearly identical. Therefore, when measuring the BTI and HCI of a MOSFET, the VRS measurement can be converted into the time factor n and voltage acceleration factor m used for CVS measurement, enabling faster evaluation.

[0060] To achieve the above-mentioned concept, this embodiment further provides a semiconductor device performance degradation testing system, comprising: an acquisition module for measuring multiple sets of step voltage data using different voltage ramp rates, and performing lognormal distribution fitting on the measured data to obtain a first threshold voltage offset at a fixed voltage under different voltage ramp rates. A processing module for obtaining a time factor based on the first threshold voltage offset and the voltage ramp rate; obtaining a voltage acceleration factor based on the first threshold voltage offset and different applied voltages; obtaining a second threshold voltage offset under a certain applied voltage, calculating the lognormal distribution value σ1 of the second threshold voltage offset, and obtaining a failure time lognormal distribution σ2 based on σ1; and obtaining the failure time of the semiconductor device based on the time factor, voltage acceleration factor, and σ2.

[0061] The semiconductor device performance degradation testing system provided in this embodiment and the semiconductor device performance degradation testing method provided in this embodiment belong to the same inventive concept. Therefore, the semiconductor device performance degradation testing system provided in this embodiment has at least all the advantages of the semiconductor device performance degradation testing method provided in this embodiment, and can greatly shorten the HCI and BTI testing time of semiconductor devices, saving testing resources and time.

[0062] In summary, the above embodiments provide detailed descriptions of different configurations of the testing method and system for semiconductor device performance degradation. Of course, the above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. The present invention includes but is not limited to the configurations listed in the above embodiments. Those skilled in the art can draw inferences based on the contents of the above embodiments. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure are within the scope of protection of the claims.

Claims

1. A method for testing performance degradation of a semiconductor device, characterized in that: include: Multiple sets of step voltage data are measured using different voltage increase rates, and the measured data are fitted with a logarithmic normal distribution to obtain the first threshold voltage offset at a fixed voltage under different voltage increase rates; Obtaining a time factor based on the first threshold voltage offset and the voltage increase rate; Obtaining a voltage acceleration factor based on the first threshold voltage shift and different applied voltages; Obtain a second threshold voltage offset under a certain applied voltage, calculate a logarithmic normal distribution value σ1 of the second threshold voltage offset, and obtain a logarithmic normal distribution σ2 of the failure time based on σ1; The failure time of the semiconductor device is obtained based on the time factor, the voltage acceleration factor and σ2.

2. The method for testing semiconductor device performance degradation according to claim 1, wherein: The acquiring the time factor based on the first threshold voltage offset and the voltage increase rate includes: Perform a linear fit on the first threshold voltage offset and different voltage increase rates to obtain a slope of the linear fit, and the slope is the time factor n.

3. The method for testing semiconductor device performance degradation according to claim 1, wherein: The obtaining of a voltage acceleration factor based on the first threshold voltage shift and different applied voltages includes: A functional relationship between the first threshold voltage offset and different applied voltages is established, and the difference between the slope of the functional relationship and the time factor is the voltage acceleration factor m, that is, S=m+n, where S is the slope of the functional relationship, m is the voltage acceleration factor, and n is the time factor.

4. The method for testing semiconductor device performance degradation according to claim 3, wherein: The functional relationship between the threshold voltage shift and different applied voltages is established as follows: Where ΔVT(RR,Vg) is the threshold voltage shift, Vg is the applied voltage, RR is the voltage increase rate, m is the voltage acceleration factor, n is the time factor, and A is a constant.

5. The method for testing semiconductor device performance degradation according to claim 1, wherein: The method of obtaining the normal distribution σ2 of the failure time logarithm based on σ1 includes: Where n is the time factor.

6. The method for testing semiconductor device performance degradation according to claim 4, wherein: The obtaining of the failure time of the semiconductor device based on the time factor, the voltage acceleration factor and σ2 includes: The time factor, voltage acceleration factor and σ2 are used to fit the powerlaw model to obtain the failure time of semiconductor devices.

7. The method for testing semiconductor device performance degradation according to claim 1, wherein: The voltage is a gate voltage.

8. The method for testing semiconductor device performance degradation according to claim 1, wherein: The voltage is a drain voltage.

9. The method for testing semiconductor device performance degradation according to claim 1, wherein: The multiple sets of step voltages are positive voltages or negative voltages.

10. A semiconductor device performance degradation testing system, characterized in that: include: An acquisition module is used to measure multiple sets of step voltage data using different voltage increase rates, and perform logarithmic normal distribution fitting on the measured data to obtain a first threshold voltage offset at a fixed voltage under different voltage increase rates; a processing module, configured to obtain a time factor based on the first threshold voltage offset and the voltage increase rate; Obtaining a voltage acceleration factor based on the first threshold voltage shift and different applied voltages; Obtain a second threshold voltage offset under a certain applied voltage, calculate the logarithmic normal distribution value σ1 of the second threshold voltage offset, and obtain the failure time logarithmic normal distribution σ2 based on σ1; obtain the failure time of the semiconductor device based on the time factor, voltage acceleration factor and σ2.

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