Timing control method of amplifier circuit and electronic device

Abstract

The present application provides a timing control method and electronic device for an amplifier circuit. The method includes: generating a first control signal, wherein when the amplifier circuit is in a dormant phase, the first control signal includes a first on-signal that precedes the first in the time domain and a first off-signal that follows the first in the time domain; and when the amplifier circuit is in a holding phase, the first control signal includes a second on-signal that precedes the first in the time domain and a second off-signal that follows the first in the time domain, wherein the dormant phase is between the sensing phase and the holding phase; controlling the first control signal to be input to the gate of the first transistor, and controlling the first switch to be in an on state and the second switch to be in an off state during the dormant phase; and controlling the second switch to be in an on state and the first switch to be in an off state during the holding phase. This solution increases the voltage between the first node and the ground terminal, and at the same time, the off-signal in the holding phase is longer, providing a larger time margin for read and write operations.

Description

Technical Field

[0001] The present application relates to the field of semiconductors, and more specifically, to a timing control method for an amplifier circuit and an electronic device. Background Art

[0002] As the line width of semiconductor memories shrinks, the capacitance of storage cells in the semiconductor memories decreases, which makes the impact of noise on the normal operation of the semiconductor memories greater.

[0003] Sense amplifier circuits (SA circuits) eliminate noise caused by transistor manufacturing variations within semiconductor memory, enabling accurate data storage. However, the voltages of the amplifier circuit's low-level signal input nodes and high-level signal input nodes cannot be flexibly adjusted. Furthermore, in current semiconductor memory manufacturing, as the feature size of MOS transistors decreases, transistor leakage current has a more significant impact on the circuit, exacerbating power consumption issues. This results in high power consumption in SA circuits. Summary of the Invention

[0004] The main purpose of the present application is to provide a timing control method and an electronic device for an amplifier circuit, so as to at least solve the problem in the prior art that the voltage of the node of the amplifier circuit inputting a low-level signal cannot be flexibly adjusted.

[0005] To achieve the above objectives, according to one aspect of the present application, a timing control method for an amplifier circuit is provided. The amplifier circuit includes a sensing amplifier unit, a first transistor, a first power transistor unit, and a first switch unit. The sensing amplifier unit has a first node, the first node is used to receive a low-level signal, the drain of the first transistor is electrically connected to the first node, the source of the first transistor is connected to the drain of the first power transistor unit and the first end of the first switch unit, the second end of the first switch unit is connected to the gate of the first power transistor unit, and the source of the first power transistor unit is grounded. The method includes:

[0006] generating a first control signal, wherein when the amplifying circuit is in a dormant phase, the first control signal includes a first on-signal that precedes the first on-signal in time domain and a first off-signal that follows the first on-signal in time domain; and when the amplifying circuit is in a holding phase, the first control signal includes a second on-signal that precedes the first on-signal in time domain and a second off-signal that follows the first on-signal in time domain; a ratio of a duration of the first off-signal to a duration of the first on-signal is a first ratio; a ratio of a duration of the second off-signal to a duration of the second on-signal is a second ratio; the first ratio is smaller than the second ratio; wherein the dormant phase is between the sensing phase and the holding phase;

[0007] The first control signal is controlled to be input to the gate of the first transistor.

[0008] Optionally, the amplifier circuit further includes a fourth transistor, the drain of the fourth transistor is electrically connected to the first node, and the source of the fourth transistor is grounded, and the method further includes: generating a second control signal, when the amplifier circuit is in the sleep stage, the second control signal is a third cutoff signal, when the amplifier circuit is in the hold stage, the second control signal includes a fourth cutoff signal that precedes in time domain and a third conduction signal that follows in time domain, and the duration of the fourth cutoff signal is greater than the duration of the third conduction signal, and the duration of the third conduction signal is equal to the duration of the second cutoff signal; controlling the second control signal to be input to the gate of the fourth transistor.

[0009] Optionally, the method also includes: if the amplifier circuit is in the sleep stage, controlling the voltage of the first node to gradually rise from a preset low level to a first preset level, and then gradually drop from the first preset level to the preset low level, and after dropping to the preset low level, the duration of the preset low level is equal to the duration of the first cut-off signal; if the amplifier circuit is in the hold stage, controlling the voltage of the first node to gradually rise from the preset low level to a second preset level, and then gradually drop from the second preset level to the preset low level, and after dropping to the preset low level, the duration of the preset low level is equal to the duration of the second cut-off signal, and the first preset level is greater than the second preset level.

[0010] Optionally, the method further includes: if the amplifying circuit is in the dormant stage, controlling the voltage of the second node of the sensing amplifying unit to be maintained at a third preset level, the second node being used to receive a high-level signal; if the amplifying circuit is in the holding stage, controlling the voltage of the second node of the sensing amplifying unit to be maintained at the third preset level.

[0011] Optionally, the method further includes: when the amplifying circuit is in a sensing stage, the first control signal is a fifth cutoff signal.

[0012] Optionally, it also includes: when the amplification circuit is in the sensing stage, the second control signal includes a fourth on-state signal that precedes in time domain and a sixth off-state signal that follows in time domain, and the duration of the fourth on-state signal is greater than the duration of the sixth off-state signal.

[0013] Optionally, it also includes: in the transition stage between the sleep stage and the hold stage, the first control signal is the seventh cut-off signal, and the second control signal is used to control the conduction of the fourth transistor, or the second control signal includes the fifth conduction signal that comes first in the time domain and the eighth cut-off signal that comes later in the time domain, and the duration of the fifth conduction signal is greater than the duration of the eighth cut-off signal.

[0014] Optionally, the first power supply transistor unit includes a second transistor and a third transistor in parallel, the first switch unit includes a first switch and a second switch, the source of the first transistor is electrically connected to the drain of the second transistor, the drain of the third transistor, the first end of the first switch and the first end of the second switch, respectively, the second end of the first switch is electrically connected to the gate of the second transistor, the second end of the second switch is electrically connected to the gate of the third transistor, the source of the second transistor and the source of the third transistor are grounded respectively, the threshold voltage of the second transistor is greater than the threshold voltage of the third transistor, and, in the dormant stage, the first switch is controlled to be in the on state and the second switch is in the off state; in the holding stage, the second switch is controlled to be in the on state and the first switch is in the off state.

[0015] Optionally, the first transistor, the second transistor and the third transistor are NMOS transistors, the first turn-on signal and the second turn-on signal are high-level signals, and the first turn-off signal and the second turn-off signal are low-level signals.

[0016] According to another aspect of the present application, a timing control method for an amplifier circuit is provided. The amplifier circuit includes a sensing amplifier unit, a fifth transistor, a second power supply transistor unit, and a second switch unit. The sensing amplifier unit has a second node, the second node is used to receive a high-level signal, the drain of the fifth transistor is electrically connected to the second node, the source of the fifth transistor is electrically connected to the drain of the second power supply transistor unit and the first end of the second switch unit, the second end of the second switch unit is electrically connected to the gate of the second power supply transistor unit, and the source of the second power supply transistor unit is electrically connected to the power supply terminal. The method includes:

[0017] generating a third control signal, wherein when the amplifying circuit is in a dormant stage, the third control signal includes a sixth conduction signal that precedes in time domain and a ninth cutoff signal that follows in time domain; and when the amplifying circuit is in a hold stage, the third control signal includes a seventh conduction signal that precedes in time domain and a tenth cutoff signal that follows in time domain, a ratio of a duration of the ninth cutoff signal to a duration of the sixth conduction signal is a third ratio, a ratio of a duration of the tenth cutoff signal to a duration of the seventh conduction signal is a fourth ratio, and the third ratio is less than the fourth ratio, wherein the dormant stage is between the sensing stage and the hold stage;

[0018] The third control signal is controlled to be input to the gate of the fifth transistor.

[0019] Optionally, the amplifying circuit further includes an eighth transistor, the drain of the eighth transistor is electrically connected to the second node, and the source of the eighth transistor is electrically connected to the power supply terminal, and the method further includes:

[0020] generating a fourth control signal, wherein when the amplifying circuit is in the dormant stage, the fourth control signal is an eleventh cut-off signal; when the amplifying circuit is in the holding stage, the fourth control signal includes a twelfth cut-off signal that precedes in time domain and an eighth conduction signal that follows in time domain, and a duration of the twelfth cut-off signal is greater than a duration of the eighth conduction signal, and a duration of the eighth conduction signal is equal to a duration of the tenth cut-off signal;

[0021] The fourth control signal is controlled to be input to the gate of the eighth transistor.

[0022] Optionally, the second power supply transistor unit includes a sixth transistor and a seventh transistor in parallel, the second switch unit includes a third switch and a fourth switch, the source of the fifth transistor is electrically connected to the drain of the sixth transistor, the drain of the seventh transistor, the first end of the third switch and the first end of the fourth switch, respectively, the second end of the third switch is electrically connected to the gate of the sixth transistor, the second end of the fourth switch is electrically connected to the gate of the seventh transistor, the source of the sixth transistor and the source of the seventh transistor are electrically connected to the power supply end, respectively, the threshold voltage of the sixth transistor is greater than the threshold voltage of the seventh transistor, and, in the dormant stage, the third switch is controlled to be in the on state and the fourth switch is in the off state; in the holding stage, the fourth switch is controlled to be in the on state and the third switch is in the off state.

[0023] According to another aspect of the present application, an electronic device is provided, comprising: a semiconductor memory device, comprising an amplifier circuit and a memory cell, the amplifier circuit being electrically connected to a bit line corresponding to the memory cell; and a controller, electrically connected to the semiconductor memory device, for executing any one of the above-mentioned timing control methods for the amplifier circuit.

[0024] In the amplifier circuit, by connecting a first transistor to the first node of the sensing amplifier unit, and setting a first power supply transistor unit and a first switch unit connected to the first transistor, the opening and closing of the first switch unit directly affects whether the gate and drain of the first power supply transistor unit are short-circuited. When the first control signal is a first turn-on signal or a second turn-on signal, the first transistor is turned on; when the first control signal is a first turn-off signal or a second turn-off signal, the first transistor is turned off; therefore, by controlling the conduction or cut-off of the first transistor, and controlling the opening and closing of the first switch unit, the transistor actually connected to the first node can be controlled to increase the voltage difference between the first node and the ground terminal, while keeping the cut-off signal of the stage longer, providing a larger time margin for read and write operations. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The drawings that constitute part of this application are used to provide a further understanding of this application. The illustrative embodiments of this application and their descriptions are used to explain this application and do not constitute an improper limitation on this application. In the drawings:

[0026] Figure 1 shows a schematic diagram of an amplifying circuit according to an embodiment of the present application;

[0027] Figure 2 A flow chart of a timing control method for an amplifier circuit according to an embodiment of the present application is shown;

[0028] Figure 3 shows a signal timing diagram according to an embodiment of the present application;

[0029] Figure 4 A flow chart of another timing control method for an amplifier circuit according to an embodiment of the present application is shown.

[0030] The above drawings include the following reference numerals:

[0031] 10. Sense amplifier unit; 20. First power transistor unit; 30. First switch unit; 40. Second power transistor unit; 50. Second switch unit. DETAILED DESCRIPTION

[0032] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the present application belongs.

[0033] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, they indicate the presence of features, steps, operations, devices, components and / or combinations thereof.

[0034] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element or intervening elements may be present. Moreover, in the specification and claims, when it is described that an element is "connected to" another element, the element may be "directly connected to" the other element or "connected to" the other element through a third element.

[0035] As introduced in the background technology, in the prior art, the voltage of the node of the input low-level signal of the amplifier circuit cannot be flexibly adjusted. In order to solve the problem that the voltage of the node of the input low-level signal of the amplifier circuit cannot be flexibly adjusted, the embodiments of the present application provide a timing control method and electronic device for the amplifier circuit.

[0036] In some embodiments of the present application, a timing control method for an amplifier circuit is provided, which is specifically applied in the following cases: Figure 1 In the amplifier circuit shown, the amplifier circuit includes a sensing amplifier unit 10, a first power transistor unit 20 and a first switch unit 30. The sensing amplifier unit 10 has a first node NCS, and the first node NCS is used to receive a low-level signal. The drain of the first transistor M1 is electrically connected to the first node NCS, the source of the first transistor M1 is connected to the drain of the first power transistor unit 20 and the first end of the first switch unit 30, the second end of the first switch unit 30 is connected to the gate of the first power transistor unit 20, and the source of the first power transistor unit 20 is grounded. The timing control method of the amplifier circuit is specifically as follows Figure 2 The specific timing is as shown in Figure 3 As shown, Figure 2 The steps include:

[0037] Step S201: Generate a first control signal. When the amplifier circuit is in a dormant phase, the first control signal includes a first on-signal that precedes the first on-signal in time domain and a first off-signal that follows the first on-signal in time domain. When the amplifier circuit is in a hold phase, the first control signal includes a second on-signal that precedes the first on-signal in time domain and a second off-signal that follows the first on-signal in time domain. A ratio of the duration of the first off-signal to the duration of the first on-signal is a first ratio, and a ratio of the duration of the second off-signal to the duration of the second on-signal is a second ratio. The first ratio is smaller than the second ratio. The dormant phase is between the sensing phase and the hold phase.

[0038] Step S202: Control the first control signal to be input to the gate of the first transistor, such as Figure 1 As shown, the controller inputs the first control signal SAN1 to the gate of the first transistor M1.

[0039] Specifically, the on in the on signal and the off in the off signal are both for the first transistor, that is, the first transistor is turned on when the first control signal is the first on signal and the second on signal, that is, the first transistor is turned off when the first control signal is the first off signal and the second off signal;

[0040] like Figure 3 As shown, the first control signal is Figure 3 Indicated as SAN1, Figure 3 Indicated by the thick black solid line; when the amplifier circuit is in the dormant stage, the dormant stage corresponds to Figure 3 In the power down state, the first control signal SAN1 includes a first on signal that precedes the first on signal in the time domain and a first off signal that follows the first on signal in the time domain;

[0041] Among them, the first conduction signal is Figure 3 In the dormant phase, the high level signal lasts longer, and the first cutoff signal is Figure 3 denoted as a low-level signal with a short duration, corresponds to the case where the first transistor in this embodiment is an NMOS transistor. In other embodiments, the high and low levels of the first on-state signal vary with the type of the first transistor, i.e., from a high-level on-state to a low-level on-state; similarly, the high and low levels of the first off-state signal also vary with the type of the first transistor, i.e., from a low-level off-state to a high-level off-state.

[0042] When the amplifier circuit is in the holding phase, the holding phase corresponds to Figure 3 In the Standby mode, the first control signal SAN1 includes a second on-signal that precedes the second on-signal in the time domain and a second off-signal that follows the second on-signal in the time domain;

[0043] Among them, the second conduction signal is Figure 3In the middle, it is represented as a high level signal with a longer duration in the holding phase, and the second cut-off signal is in Figure 3 The low-level signal with a short duration is represented in the figure, which corresponds to the case where the first transistor in this embodiment is an NMOS transistor. In other embodiments, the high and low levels of the second on-state signal vary with the type of the first transistor, that is, it changes from a high-level on-state to a low-level on-state. Similarly, the high and low levels of the second off-state signal also vary with the type of the first transistor, that is, it changes from a low-level off-state to a high-level off-state.

[0044] Figure 3 In the sleep phase, the proportion of the first cut-off signal in the power down phase is less than the proportion of the second cut-off signal in the standby phase; and the duration of the cut-off signal in the standby phase is longer than the duration of the cut-off signal in the power down phase, which provides a larger time margin for read and write operations. The sleep phase is between the sensing phase and the hold phase (see Figure 3 Power down is between Sensing and Standby);

[0045] The timing control method of the amplifier circuit disclosed in this solution connects a first transistor to the first node of the sensing amplifier unit, and sets a first power transistor unit and a first switch unit connected to the first transistor. The opening and closing of the first switch unit directly affects whether the gate and drain of the first power transistor unit are short-circuited, that is, affects the way in which the first power transistor unit is connected to the amplifier circuit; in addition, when the first control signal is the first on-signal or the second on-signal, the first transistor is turned on; when the first control signal is the first off-signal or the second off-signal, the first transistor is turned off; therefore, by controlling the on or off of the first transistor and controlling the opening and closing of the first switch unit, the equivalent resistance of the first transistor M1 and the first power transistor unit 20 connected in series between the first stage and the ground terminal can be controlled to adjust the voltage difference between the first node and the ground terminal, thereby adjusting the voltage of the first node.

[0046] More specifically, the first power transistor unit 20 includes a second transistor M2 and a third transistor M3 in parallel, and the first switch unit 30 includes a first switch K1 and a second switch K2. The source of the first transistor M1 is electrically connected to the drain of the second transistor M2, the drain of the third transistor M3, the first end of the first switch K1, and the first end of the second switch K2, respectively. The second end of the first switch K1 is electrically connected to the gate of the second transistor M2, the second end of the second switch K2 is electrically connected to the gate of the third transistor M3, and the source of the second transistor M2 and the source of the third transistor M3 are grounded, respectively.

[0047] like Figure 1As shown, the first transistor M1, the second transistor M2 and the third transistor M3 are all NMOS transistors; Figure 1 The sense amplifier unit 10 further includes a first N-type transistor NSA, a third N-type transistor OC1, a fourth N-type transistor ISO1, a fifth N-type transistor EQ, a sixth N-type transistor NA, a seventh N-type transistor OC2, and an eighth N-type transistor ISO2.

[0048] The threshold voltage N_Hv of the second transistor M2 is greater than the threshold voltage N_Lv of the third transistor M3. Furthermore, during the dormant phase, the first switch K1 is controlled to be in an on state, while the second switch K2 is controlled to be in an off state. During the hold phase, the second switch K2 is controlled to be in an on state, while the first switch K1 is controlled to be in an off state. That is, during the dormant phase, when both the first transistor M1 and the second transistor M2 are turned on, the potential of the first node NCS is increased. During the hold phase, when both the first transistor M1 and the third transistor M2 are turned on, the potential of the first node NCS is also increased. Because the threshold voltage of the second transistor M2 is greater than the threshold voltage of the third transistor M3, the highest potential of the first node NCS during the dormant phase is higher than the highest potential of the first node NCS during the hold phase. By setting the potential of the first node NCS to be higher than the ground terminal, it is beneficial to reduce the voltage difference between the bit line BLA connected to the amplifier circuit and the first node NCS, thereby reducing the leakage current ioff1 of the first N-type transistor NSA; accordingly, the bit line BLA is connected to the local data line IO through the second N-type transistor CSL1, and the voltage of the first node NCS is higher, which is beneficial to reducing the voltage difference between the local data line and the first node NCS, thereby reducing the leakage current ioff2 of the second N-type transistor CSL1; in addition, the potential of the first node NCS in the sleep stage is set to be higher than the potential in the hold stage because a write operation (including external data writing and write-back during the refresh process) may be required in the hold stage, but not in the sleep stage. In order to ensure that the write operation has a higher execution efficiency, it is necessary to set the potential of the first node NCS in the hold stage to be lower, thereby reducing the leakage current in each stage while making the leakage current in the sleep stage smaller and making the write speed in the hold stage faster, and adaptively optimizing the characteristics of different stages.

[0049] Furthermore, the amplifier circuit further includes a fourth transistor M4 ( Figure 1 ), the drain of the fourth transistor M4 is electrically connected to the first node NCS, the source of the fourth transistor M4 is grounded, and the method further includes:

[0050] generating a second control signal, wherein the second control signal is a third cutoff signal when the amplifier circuit is in a dormant phase, and comprises a fourth cutoff signal that precedes the third cutoff signal in time domain and a third conduction signal that follows the fourth cutoff signal in time domain when the amplifier circuit is in a hold phase, wherein the fourth cutoff signal has a duration greater than the third conduction signal, and the third conduction signal has a duration equal to the second cutoff signal; and furthermore, the second conduction signal has a duration equal to the fourth cutoff signal;

[0051] Figure 3 As shown in FIG, when the amplifier circuit is in the power-down phase, the second control signal SAN2 is the third cut-off signal. When the amplifier circuit is in the standby phase, the second control signal SAN2 includes the fourth cut-off signal that precedes it in time domain and the third on-signal that follows it in time domain.

[0052] The second control signal is controlled to be input to the gate of the fourth transistor M4. Specifically, when the second control signal is an on signal, the fourth transistor M4 is turned on. When the second control signal is an off signal, the fourth transistor M4 is turned off.

[0053] Specifically, the second control signal SAN2 corresponds to two operating modes: high-efficiency mode IDD3N and low-power mode IDD3P. In high-efficiency mode IDD3N, the second control signal SAN2 uses the second strong control signal SAN2_strong, while in low-power mode IDD3P, the second control signal SAN2 uses the second weak control signal SAN2_weak. Setting the level of the second strong control signal SAN2_strong to a greater level than the level of the second weak control signal SAN2_weak helps reduce the conduction level of the fourth transistor M4, raising the potential of the first node NCS. This reduces transistor leakage current in the low-power mode and increases the conduction level of the fourth transistor M4 in the high-efficiency mode IDD3N, ensuring smooth reading and writing. In other words, when the second control signal SAN2 is on, different potentials can be selected based on actual power consumption or performance requirements.

[0054] Specifically, when the amplifier circuit is in the high efficiency mode IDD3N and the low power consumption mode IDD3P, there is usually a large leakage current in the first N-type transistor NSA, the first P-type transistor PSA and the external second N-type transistor CSL1 in the amplifier circuit. Figure 1, the leakage current in the first N-type transistor NSA is shown as the first leakage current ioff1, the leakage current in the second N-type transistor CSL1 is shown as the second leakage current ioff2, and the leakage current in the first P-type transistor PSA is shown as the third leakage current ioff3. Using the solution of the present application, in the low-power mode IDD3P, the fourth transistor M4 is less conductive, the voltage of the first node NCS is higher, and the voltage at the first node NCS is pulled up to reduce the voltage difference between the bit line and the first node NCS, thereby reducing the voltage difference between the gate and source of the first N-type transistor NSA and reducing the leakage current in the first N-type transistor NSA. At the same time, since it is beneficial to prevent the charge of the bit line BLA from leaking through M4, it is equivalent to raising the potential at the reference bit line Bla, which is beneficial to reducing the voltage difference between the gate and source of the second N-type transistor CSL1, thereby reducing the leakage current in the second N-type transistor CSL1.

[0055] In addition, in the high-efficiency mode IDD3N, the fourth transistor M4 is more conductive and the voltage of the first node NCS is smaller, so that the voltage difference between the gate and the source of the first N-type transistor NSA is larger and the current is larger; to balance the requirements of the low-power mode IDD3P and the high-efficiency mode IDD3N, that is, low power consumption is required in the low-power mode, so the leakage current must be small, but it also makes the transistor conductive lower or the speed reduced. The high-efficiency mode requires the transistor to be turned on faster or the conductive degree is higher, so a larger leakage current is allowed.

[0056] It should be noted that Figure 1 There is only one fourth transistor M4. Figure 1 The two fourth transistors M4 in the circuit only play the role of corresponding to the two working modes.

[0057] Specifically, the second strong control signal SAN2_strong and the second weak control signal SAN2_wake may be selected by the power switching module.

[0058] It should be noted that, throughout the text, references to the second control signal being a cut-off signal all indicate that the fourth transistor is cut off, and references to the second control signal being a turn-on signal all indicate that the fourth transistor is turned on.

[0059] Under the above setting of the first control signal, it is obtained:

[0060] like Figure 3As shown, if the amplifier circuit is in the power down stage, the voltage of the first node NCS is controlled to gradually rise from a preset low level to a first preset level HighVtn, and then gradually drop from the first preset level HighVtn to a preset low level. After dropping to the preset low level, the duration of the preset low level is equal to the duration of the first cut-off signal.

[0061] like Figure 3 As shown, if the amplifier circuit is in the standby stage, the voltage of the first node NCS is controlled to gradually rise from the preset low level to the second preset level LowVtn, and then gradually drop from the second preset level LowVtn to the preset low level. After dropping to the preset low level, the duration of the preset low level is equal to the duration of the second cut-off signal, and the first preset level is greater than the second preset level. Figure 3 HighVtn>LowVtn in.

[0062] Specifically, the preset low level may be set to 0V;

[0063] That is, when the first control signal is the first turn-on signal, that is, when the first transistor M1 is controlled to be turned on, the first node NCS gradually increases and then gradually decreases; when the first control signal is the second turn-on signal, that is, when the first transistor M1 is controlled to be turned on, the first node NCS gradually increases and then gradually decreases; and, setting the first preset level HighVtn> the second preset level LowVtn is to ensure that the voltage difference between the gate and the source of the first N-type transistor NSA is smaller in the sleep stage, so that the leakage current in the first N-type transistor NSA is reduced to reduce power consumption; in order not to affect the read and write operations in the hold stage, a smaller second preset level LowVtn is set to make the voltage difference between the gate and the source of the first N-type transistor NSA larger, thereby speeding up the conduction speed.

[0064] Furthermore, the method further comprises: Figure 3 As shown, if the amplifier circuit is in the sleep phase, the voltage at the second node PCS of the sense amplifier unit is controlled to remain at a third preset level, and the second node is used to receive a high-level signal. If the amplifier circuit is in the hold phase, the voltage at the second node PCS of the sense amplifier unit is controlled to remain at the third preset level. That is, under the settings of the first control signal and the second control signal, the voltage at the second node PCS remains constant during the sleep phase and the hold phase.

[0065] The setting for the sensing stage is: when the amplifier circuit is in the sensing stage, the first control signal is the fifth cut-off signal; when the amplifier circuit is in the sensing stage, the second control signal includes the fourth conduction signal that precedes in time domain and the sixth cut-off signal that follows in time domain, and the duration of the fourth conduction signal is greater than the duration of the sixth cut-off signal.

[0066] like Figure 3 As shown, in the sensing stage Sensing, the first control signal SAN1 is a low-level signal, corresponding to the case where the first transistor in this embodiment is an NMOS transistor. In other embodiments, the high and low levels of the first control signal SAN1 in the sensing stage Sensing vary with the type of the first transistor;

[0067] like Figure 3 As shown, during the sensing phase, the second control signal SAN2 is a high-level signal followed by a low-level signal. This corresponds to the case where the fourth transistor in this embodiment is an NMOS transistor. In other embodiments, the high and low levels of the second control signal SAN2 during the sensing phase vary depending on the type of the fourth transistor. The high-level signal of the second control signal SAN2 ensures a high sensing amplification speed for the amplifier circuit, while the low-level signal serves as a buffer to prevent the second control signal SAN2 and the first control signal SAN1 from switching states simultaneously and generating significant noise.

[0068] like Figure 3 As shown, in the transition phase Tr between the sleep phase Power down and the hold phase Standby, the first control signal is the seventh cut-off signal. Figure 3 The middle is a low-level signal, corresponding to the case where the first transistor in this embodiment is an NMOS transistor. In other embodiments, the high and low levels of the seventh cutoff signal change with the type of the first transistor, that is, it changes from high-level conduction to low-level conduction.

[0069] like Figure 3 As shown, in the transition phase Tr between the sleep phase Power down and the hold phase Standby, the second control signal includes the fifth on-signal that comes first in the time domain and the eighth off-signal that comes later in the time domain, and the duration of the fifth on-signal is greater than the duration of the eighth off-signal. Figure 3 The high level signal corresponds to the case where the fourth transistor in this embodiment is an NMOS transistor. In other embodiments, the high and low levels of the fifth conduction signal vary with the type of the fourth transistor; the eighth cut-off signal is Figure 3The eighth cutoff signal is a low-level signal corresponding to the case where the fourth transistor is an NMOS transistor in this embodiment. In other embodiments, the high and low levels of the eighth cutoff signal vary depending on the type of the fourth transistor. The purpose of providing the eighth cutoff signal is to prevent the first control signal and the second control signal from switching simultaneously, thereby preventing the generation of large noise.

[0070] In other embodiments, during the transition phase Tr between the power down phase and the standby phase, the second control signal controls the fourth transistor to be turned on. That is, the fourth transistor is controlled to be turned on during the entire transition phase Tr, and there is no situation where the fourth transistor is turned on or off.

[0071] like Figure 3 As shown, in the transition phase Tr between the sleep phase Power down and the standby phase, the voltage of the first node NCS is controlled to be maintained at a preset low level.

[0072] like Figure 3 As shown, in the transition phase Tr between the sleep phase Power down and the hold phase Standby, the voltage of the second node PCS of the sense amplifier unit is controlled to be maintained at a third preset level.

[0073] In addition to the sensing phase (Sensing), the power-down phase (Power Down), the transition phase (Tr), and the standby phase (Standby), there are also the idle phase (IDEL), the bias cancellation phase (OC), the discharge phase (CS), and the precharge phase (Precharge). The bias cancellation phase (OC) is used to eliminate voltage mismatches in the amplifier transistors in the amplifier circuit due to process variations. The discharge phase (CS) is used to transfer the potential in the memory cell to the bit line. The precharge phase (Precharge) pulls the potentials of the bit line (Blb) and the reference bit line (Bla) to an intermediate state, returning to the idle state (IDEL) and awaiting the next activation. During the idle phase (IDEL), the first node (NCS) and the second node (PCS) of the amplifier circuit also return to an intermediate level.

[0074] In some other embodiments of the present application, a timing control method for an amplifier circuit is provided, which is specifically applied in the following embodiments: Figure 1In the amplifier circuit shown, the amplifier circuit includes a sense amplifier unit 10, a fifth transistor M5, a second power transistor unit 40, and a second switch unit 50. The sense amplifier unit 10 has a second node PCS for receiving a high-level signal. The drain of the fifth transistor M5 is electrically connected to the second node PCS, the source of the fifth transistor M5 is electrically connected to the drain of the second power transistor unit 40 and the first end of the second switch unit 50, the second end of the second switch unit 50 is electrically connected to the gate of the second power transistor unit 40, and the source of the second power transistor unit 40 is electrically connected to the power supply terminal. The timing control method is specifically as follows: Figure 4 As shown, the following steps are included:

[0075] Step S401: Generate a third control signal. When the amplifier circuit is in a dormant stage, the third control signal includes a sixth conduction signal that precedes the amplifier circuit in time and a ninth cutoff signal that follows the amplifier circuit in time. When the amplifier circuit is in a hold stage, the third control signal includes a seventh conduction signal that precedes the amplifier circuit in time and a tenth cutoff signal that follows the amplifier circuit in time. A ratio of the duration of the ninth cutoff signal to the duration of the sixth conduction signal is a third ratio, and a ratio of the duration of the tenth cutoff signal to the duration of the seventh conduction signal is a fourth ratio. The third ratio is smaller than the fourth ratio. The dormant stage is between the sensing stage and the hold stage.

[0076] Step S402 , controlling the third control signal to be input to the gate of the fifth transistor M5 .

[0077] Specifically, the turn-on in the turn-on signal and the turn-off in the turn-off signal are both for the fifth transistor, that is, the fifth transistor is turned on when the third control signal is the sixth turn-on signal and the seventh turn-on signal, that is, the fifth transistor is turned off when the third control signal is the ninth turn-off signal and the tenth turn-off signal; the high and low levels of the sixth turn-on signal and the seventh turn-on signal change with the type of the fifth transistor, and the high and low levels of the ninth turn-off signal and the tenth turn-off signal change with the type of the fifth transistor.

[0078] The timing control method for the amplifier circuit of this solution connects a fifth transistor to the second node of the sensing amplifier unit, and provides a second power supply transistor unit and a second switch unit connected to the fifth transistor. The opening and closing of the second switch unit directly affects whether the gate and drain of the second power supply transistor unit are short-circuited, that is, affects the manner in which the second power supply transistor unit is connected to the amplifier circuit. In addition, when the third control signal is the sixth on-signal or the seventh on-signal, the fifth transistor is turned on; when the third control signal is the ninth off-signal or the tenth off-signal, the fifth transistor is turned off. Therefore, by controlling the on or off of the fifth transistor and controlling the opening and closing of the second switch unit, the transistor actually connected to the second node can be controlled to lower the potential at the second node.

[0079] Specifically, the second power supply transistor unit 40 includes a sixth transistor M6 and a seventh transistor M7 connected in parallel. The second switch unit 50 includes a third switch K3 and a fourth switch K4. The source of the fifth transistor M5 is electrically connected to the drain of the sixth transistor M6, the drain of the seventh transistor M7, the first end of the third switch K3, and the first end of the fourth switch K4, respectively. The second end of the third switch K3 is electrically connected to the gate of the sixth transistor M6, and the second end of the fourth switch K4 is electrically connected to the gate of the seventh transistor M7. The source of the sixth transistor M6 and the source of the seventh transistor M7 are electrically connected to the power supply terminal, respectively. The threshold voltage of the sixth transistor M6 is greater than the threshold voltage of the seventh transistor M7. In addition, in the dormant phase, the third switch K3 is controlled to be in an on state and the fourth switch K4 is controlled to be in an off state. In the hold phase, the fourth switch K4 is controlled to be in an on state and the third switch K3 is controlled to be in an off state.

[0080] Specifically, the fifth transistor M5 , the sixth transistor M6 , and the seventh transistor M7 are PMOS transistors, the sixth conduction signal and the seventh conduction signal are low-level signals, and the ninth cutoff signal and the tenth cutoff signal are high-level signals.

[0081] Analogously to the relevant settings for the first node, the threshold voltage of the sixth transistor M6 is set to be greater than the threshold voltage of the seventh transistor M7 in order to reduce the leakage current ioff3 in the first P-type transistor PSA during the sleep phase and save energy. A larger voltage difference is set during the hold phase to speed up the conduction speed while reducing the leakage current, thereby facilitating reading and writing.

[0082] like Figure 1 As shown, the sensing amplifier unit 10 further includes a first P-type transistor PSA and a second P-type transistor PA.

[0083] Furthermore, if Figure 1 As shown, the amplifier circuit further includes an eighth transistor M8, the drain of the eighth transistor M8 is electrically connected to the second node, and the source of the eighth transistor M8 is electrically connected to the power supply terminal VDD. The method further includes:

[0084] generating a fourth control signal, wherein the fourth control signal is an eleventh cut-off signal when the amplifier circuit is in a dormant phase, and comprises a twelfth cut-off signal that precedes the first cut-off signal in the time domain and an eighth conduction signal that follows the last cut-off signal in the time domain when the amplifier circuit is in a hold phase, and the duration of the twelfth cut-off signal is greater than the duration of the eighth conduction signal, and the duration of the eighth conduction signal is equal to the duration of the tenth cut-off signal;

[0085] The fourth control signal is controlled to be input to the gate of the eighth transistor M8 , that is, when the fourth control signal is an on signal, the eighth transistor M8 is turned on, and when the fourth control signal is an off signal, the eighth transistor M8 is turned off.

[0086] Similar to the second control signal, the fourth control signal also has two operating modes: a high-efficiency mode IDD3N and a low-power mode IDD3P. In the two operating modes, control signals with different potentials are used to control the eighth transistor M8. This reduces leakage current in the first P-type transistor PSA or the second P-type transistor PA in the low-power mode, and increases current in the first P-type transistor PSA in the high-efficiency mode to ensure smooth reading and writing.

[0087] It should be noted that the remaining settings of the second node can be based on the corresponding settings of the first node, and will not be explained one by one in this article.

[0088] In some further embodiments of the present application, an electronic device is provided, including:

[0089] A semiconductor memory device includes an amplifier circuit and a memory cell, wherein the amplifier circuit is electrically connected to a bit line corresponding to the memory cell;

[0090] The controller is electrically connected to the semiconductor memory device and is used to execute any one of the timing control methods for the amplifier circuit.

[0091] From the above description, it can be seen that the embodiments of the present application achieve the following technical effects:

[0092] 1) The present application provides a timing control method for an amplifier circuit. By connecting a first transistor to a first node of a sensing amplifier unit, and providing a first power transistor unit and a first switch unit connected to the first transistor, the opening and closing of the first switch unit directly affects whether the gate and drain of the first power transistor unit are short-circuited, that is, affects the manner in which the first power transistor unit is connected to the amplifier circuit. In addition, when the first control signal is a first on-signal or a second on-signal, the first transistor is turned on; when the first control signal is a first off-signal or a second off-signal, the first transistor is turned off. Therefore, by controlling the on or off of the first transistor and controlling the opening and closing of the first switch unit, the voltage of the first node can be adjusted, thereby reducing the voltage difference between the first node and the bit line or even the local data line, thereby reducing leakage current.

[0093] 2) Another timing control method for an amplifier circuit disclosed herein connects a fifth transistor to the second node of the sense amplifier unit, and provides a second power transistor unit and a second switch unit connected to the fifth transistor. The opening and closing of the second switch unit directly affects whether the gate and drain of the second power transistor unit are short-circuited, thereby affecting the manner in which the second power transistor unit is connected to the amplifier circuit. Furthermore, when the third control signal is the sixth on-signal or the seventh on-signal, the fifth transistor is turned on; when the third control signal is the ninth off-signal or the tenth off-signal, the fifth transistor is turned off. Therefore, by controlling the on / off state of the fifth transistor and the opening and closing state of the second switch unit, the voltage at the second node can be adjusted, thereby reducing the voltage difference between the second node and the bit line, or even the local data line, and thus reducing leakage current.

[0094] The above description is merely a preferred embodiment of the present application and is not intended to limit the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application shall be included within the scope of protection of the present application.

Claims

1. A timing control method for an amplifier circuit, characterized in that: The amplifier circuit includes a sense amplifier unit, a first transistor, a first power transistor unit, and a first switch unit. The sense amplifier unit has a first node, the first node is used to receive a low-level signal, the drain of the first transistor is electrically connected to the first node, the source of the first transistor is connected to the drain of the first power transistor unit and the first end of the first switch unit, the second end of the first switch unit is connected to the gate of the first power transistor unit, and the source of the first power transistor unit is grounded. The method includes: generating a first control signal, wherein when the amplifying circuit is in a dormant phase, the first control signal includes a first on-signal that precedes the first on-signal in time domain and a first off-signal that follows the first on-signal in time domain; and when the amplifying circuit is in a holding phase, the first control signal includes a second on-signal that precedes the first on-signal in time domain and a second off-signal that follows the first on-signal in time domain; a ratio of a duration of the first off-signal to a duration of the first on-signal is a first ratio; a ratio of a duration of the second off-signal to a duration of the second on-signal is a second ratio; the first ratio is smaller than the second ratio; wherein the dormant phase is between the sensing phase and the holding phase; The first control signal is controlled to be input to the gate of the first transistor.

2. The method according to claim 1, characterized in that The amplifier circuit further includes a fourth transistor, a drain of the fourth transistor is electrically connected to the first node, and a source of the fourth transistor is grounded. The method further includes: generating a second control signal, wherein when the amplifying circuit is in the dormant stage, the second control signal is a third cut-off signal; when the amplifying circuit is in the holding stage, the second control signal includes a fourth cut-off signal that precedes the third cut-off signal in time domain and a third conduction signal that follows the third cut-off signal in time domain, and a duration of the fourth cut-off signal is greater than a duration of the third conduction signal, and a duration of the third conduction signal is equal to a duration of the second cut-off signal; The second control signal is controlled to be input to the gate of the fourth transistor.

3. The method according to claim 1 or 2, characterized in that The method further comprises: If the amplifier circuit is in the dormant stage, the voltage of the first node is controlled to gradually increase from a preset low level to a first preset level, and then gradually decrease from the first preset level to the preset low level, and after decreasing to the preset low level, the duration of the preset low level is equal to the duration of the first cut-off signal; If the amplifier circuit is in the holding stage, the voltage of the first node is controlled to gradually rise from the preset low level to the second preset level, and then gradually drop from the second preset level to the preset low level. After dropping to the preset low level, the duration of the preset low level is equal to the duration of the second cut-off signal, and the first preset level is greater than the second preset level.

4. The method according to claim 1 or 2, characterized in that The method further comprises: If the amplifier circuit is in the dormant stage, controlling the voltage of the second node of the sense amplifier unit to be maintained at a third preset level, the second node being used to receive a high-level signal; If the amplifying circuit is in the holding phase, the voltage of the second node of the sensing amplifying unit is controlled to be maintained at the third preset level.

5. The method according to claim 1, wherein Also includes: When the amplifying circuit is in a sensing phase, the first control signal is a fifth cutoff signal.

6. The method according to claim 2, characterized in that Also includes: When the amplifying circuit is in the sensing stage, the second control signal includes a fourth on-state signal that precedes the first on-state signal in time domain and a sixth off-state signal that follows the second on-state signal in time domain, and the duration of the fourth on-state signal is greater than the duration of the sixth off-state signal.

7. The method according to claim 2, characterized in that Also includes: In the transition phase between the sleep phase and the hold phase, the first control signal is the seventh cut-off signal, and the second control signal is used to control the conduction of the fourth transistor, or the second control signal includes the fifth conduction signal that precedes in time domain and the eighth cut-off signal that follows in time domain, and the duration of the fifth conduction signal is greater than the duration of the eighth cut-off signal.

8. The method according to claim 1, characterized in that The first power supply transistor unit includes a second transistor and a third transistor in parallel, and the first switch unit includes a first switch and a second switch. The source of the first transistor is electrically connected to the drain of the second transistor, the drain of the third transistor, the first end of the first switch, and the first end of the second switch, respectively. The second end of the first switch is electrically connected to the gate of the second transistor, and the second end of the second switch is electrically connected to the gate of the third transistor. The source of the second transistor and the source of the third transistor are grounded, respectively. The threshold voltage of the second transistor is greater than the threshold voltage of the third transistor. In addition, in the dormant stage, the first switch is controlled to be in the on state and the second switch is in the off state; in the holding stage, the second switch is controlled to be in the on state and the first switch is in the off state.

9. The method according to claim 1, characterized in that The first transistor, the second transistor and the third transistor are NMOS transistors, the first turn-on signal and the second turn-on signal are high-level signals, and the first turn-off signal and the second turn-off signal are low-level signals.

10. A timing control method for an amplifier circuit, characterized in that: The amplifier circuit includes a sense amplifier unit, a fifth transistor, a second power transistor unit, and a second switch unit. The sense amplifier unit has a second node, the second node is used to receive a high-level signal, the drain of the fifth transistor is electrically connected to the second node, the source of the fifth transistor is electrically connected to the drain of the second power transistor unit and the first end of the second switch unit, the second end of the second switch unit is electrically connected to the gate of the second power transistor unit, and the source of the second power transistor unit is electrically connected to the power supply terminal. The method includes: generating a third control signal, wherein when the amplifying circuit is in a dormant stage, the third control signal includes a sixth conduction signal that precedes in time domain and a ninth cutoff signal that follows in time domain; and when the amplifying circuit is in a hold stage, the third control signal includes a seventh conduction signal that precedes in time domain and a tenth cutoff signal that follows in time domain, a ratio of a duration of the ninth cutoff signal to a duration of the sixth conduction signal is a third ratio, a ratio of a duration of the tenth cutoff signal to a duration of the seventh conduction signal is a fourth ratio, and the third ratio is less than the fourth ratio, wherein the dormant stage is between the sensing stage and the hold stage; The third control signal is controlled to be input to the gate of the fifth transistor.

11. The method according to claim 10, characterized in that The amplifier circuit further includes an eighth transistor, the drain of the eighth transistor is electrically connected to the second node, and the source of the eighth transistor is electrically connected to the power supply terminal. The method further includes: generating a fourth control signal, wherein when the amplifying circuit is in the dormant stage, the fourth control signal is an eleventh cut-off signal; when the amplifying circuit is in the holding stage, the fourth control signal includes a twelfth cut-off signal that precedes in time domain and an eighth conduction signal that follows in time domain, and a duration of the twelfth cut-off signal is greater than a duration of the eighth conduction signal, and a duration of the eighth conduction signal is equal to a duration of the tenth cut-off signal; The fourth control signal is controlled to be input to the gate of the eighth transistor.

12. The method according to claim 10, characterized in that The second power supply transistor unit includes a sixth transistor and a seventh transistor in parallel, the second switch unit includes a third switch and a fourth switch, the source of the fifth transistor is electrically connected to the drain of the sixth transistor, the drain of the seventh transistor, the first end of the third switch and the first end of the fourth switch, respectively, the second end of the third switch is electrically connected to the gate of the sixth transistor, the second end of the fourth switch is electrically connected to the gate of the seventh transistor, the source of the sixth transistor and the source of the seventh transistor are electrically connected to the power supply end, respectively, the threshold voltage of the sixth transistor is greater than the threshold voltage of the seventh transistor, and in the dormant stage, the third switch is controlled to be in the on state and the fourth switch is in the off state; in the holding stage, the fourth switch is controlled to be in the on state and the third switch is in the off state.

13. An electronic device, characterized in that: include: A semiconductor memory device comprises an amplifier circuit and a memory cell, wherein the amplifier circuit is electrically connected to a bit line corresponding to the memory cell; A controller is electrically connected to the semiconductor memory device and is used to execute the timing control method for an amplifier circuit according to any one of claims 1 to 9 or the timing control method for an amplifier circuit according to any one of claims 10 to 12.

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