Memory, built-in self-test method and test system

Abstract

The present disclosure provides a memory, a built-in self-test method and a test system. The memory includes a counter for counting erroneous data bits obtained by data verification. During the built-in self-test process of the memory, a flag pulse signal is generated each time a data error is detected, and the flag pulse signal is counted using the counter.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and in particular to a memory, a built-in self-test method, and a test system. Background Art

[0002] Memory Built-In-Self Test (MBIST) is a Design For Test (DFT) technology that places the device's test structure inside the device. It automatically generates test vectors for the target circuit and compares the output results to obtain the chip's final test results. Currently, due to chip area limitations, only two error addresses are recorded during MBIST testing. These errors are then repaired using Memory Post Package Repair (MPPR) technology. Summary of the Invention

[0003] The present disclosure provides a memory, a built-in self-test method, and a test system.

[0004] The technical solution of the present disclosure is achieved as follows:

[0005] In a first aspect, an embodiment of the present disclosure provides a memory, comprising a counter, and the counter is used to count the erroneous data bits obtained by data verification; the memory also comprises a built-in self-test module; the built-in self-test module is configured to perform self-testing using built-in self-test logic, and during the execution of the self-test, outputs a flag pulse signal for each data error detected; the counter is connected to the built-in self-test module, and is configured to receive the flag pulse signal and count the flag pulse signal during the self-test.

[0006] In some embodiments, the counter includes a first counter and a second counter; the counter is configured to, when the count value of the first counter has not reached the maximum value, add one to the count value of the first counter each time one of the flag pulse signals is received; and after the count value of the first counter reaches the maximum value, when the next flag pulse signal is received, add one to the count value of the second counter and the count value of the first counter respectively.

[0007] In some embodiments, the counter is further configured to receive a first type of pulse signal and a second type of pulse signal, and to count the first type of pulse signal using the first counter and to count the second type of pulse signal using the second counter; wherein each of the first type of pulse signals represents that an error is found in data transmitted using an odd clock after data verification, and each of the second type of pulse signals represents that an error is found in data transmitted using an even clock after data verification, and the phases of the system odd clock signal and the system even clock signal are opposite.

[0008] In some embodiments, the counter also includes a first logic unit; the input end of the first logic unit is used to receive the flag pulse signal and the first type of pulse signal, and the output end of the first logic unit is connected to the first counter; the first logic unit is configured to output a first processing signal if it receives one flag pulse signal or one first type of pulse signal; the first counter is configured to count the first processing signal.

[0009] In some embodiments, the first counter is further configured to output a low-order carry signal of a first state if its own count value reaches a maximum value; and output a carry signal of a second state if its own count value does not reach a maximum value; the counter also includes a gating unit and a second logic unit, the input end of the gating unit receives the flag pulse signal and the carry signal, and the output end of the gating unit is used to output an intermediate pulse signal; the input end of the second logic unit receives the intermediate pulse signal and the second type of pulse signal; the gating unit is configured to output the flag pulse signal as an intermediate pulse signal when the carry signal is in the first state; or, to shield the flag pulse signal when the carry signal is in the second state; the second logic unit is connected to the gating unit, and is configured to receive the intermediate pulse signal and output the intermediate pulse signal as a second processing signal; or, to receive the second type of pulse signal and output the second type of pulse signal as the second processing signal; the second counter is configured to count the second processing signal.

[0010] In some embodiments, the first type of pulse signal includes a first result signal and a second result signal, the three input ends of the first logic unit are used to receive the first result signal, the second result signal and the flag pulse signal respectively, and the output end of the first logic unit is used to output the first processing signal; the first result signal indicates that an error is found after data verification of the low-byte data transmitted using an odd clock, and the second result signal indicates that an error is found after data verification of the high-byte data transmitted using an odd clock.

[0011] In some embodiments, the second type of pulse signal includes a third result signal and a fourth result signal, the three input ends of the second logic unit are used to receive the third result signal, the fourth result signal and the intermediate pulse signal respectively, and the output end of the second logic unit is used to output the second processing signal; the third result signal indicates that an error is found after data verification of the low-byte data transmitted using an even clock, and the fourth result signal indicates that an error is found after data verification of the high-byte data transmitted using an even clock.

[0012] In some embodiments, the first counter is further configured to receive a first enable signal; wherein the first enable signal in the enabled state is used to enable the first counter, and the first enable signal is in the enabled state during at least part of the self-test and at least part of the data verification; the second counter is further configured to receive a second enable signal; wherein the second enable signal in the enabled state is used to enable the second counter, and the second enable signal is in the enabled state during at least part of the self-test and at least part of the data verification.

[0013] In some embodiments, the counter is further configured to combine the count value of the first counter and the count value of the second counter and output them as a final error value after the self-test is completed, so as to indicate the total number of errors detected in the self-test.

[0014] In a second aspect, an embodiment of the present disclosure provides a testing method, which is applied to a memory including a counter, wherein the counter is used to count erroneous data bits obtained by data verification; the method comprises:

[0015] In a built-in self-test mode, a self-test is performed using a built-in self-test logic; and during the self-test, the counter is used to count detected data errors.

[0016] In some embodiments, the counter includes a first counter and a second counter; and counting the detected data errors using the counter includes:

[0017] If the count value of the first counter has not reached the maximum value, the count value of the first counter is increased by one each time a data error is detected; if the count value of the first counter reaches the maximum value, the count value of the second counter and the count value of the first counter are each increased by one when the next data error is detected.

[0018] In some embodiments, the method further comprises:

[0019] The first counter is used to count and process the first type of errors; the second counter is used to count and process the second type of errors; wherein, each of the first type of pulse signals represents an error found after data verification using the odd clock transmission, and each of the second type of pulse signals represents an error found after data verification using the even clock transmission, and the phases of the system odd clock signal and the system even clock signal are opposite.

[0020] In some embodiments, the method further comprises:

[0021] After the self-test is completed, the count value of the first counter and the count value of the second counter are combined and output as a final error value to indicate the total number of errors detected in this self-test.

[0022] In a third aspect, an embodiment of the present disclosure provides a test system, which includes a memory controller and a memory, wherein the memory controller is connected to the memory; the memory controller is configured to send a self-test instruction to the memory; the memory is configured to perform a self-test using built-in test logic after receiving the self-test instruction, and during the self-test process, a counter is used to count the detected data errors.

[0023] The embodiments of the present disclosure provide a memory, a built-in self-test method, and a test system, which can reuse the counter of the data verification process to count data errors detected by the built-in self-test, so that the built-in self-test can provide more test result information, improve test efficiency, enrich test functions, and have little impact on the circuit area of ​​the memory, and will not reduce the performance of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A schematic diagram of the structure of a memory provided by an embodiment of the present disclosure;

[0025] Figure 2 A schematic diagram of the structure of another memory provided in an embodiment of the present disclosure;

[0026] Figure 3 A schematic diagram of a partial structure of a first counter provided in an embodiment of the present disclosure;

[0027] Figure 4 A schematic diagram of a partial structure of a second counter provided in an embodiment of the present disclosure;

[0028] Figure 5 A schematic diagram of the local structure of a counter provided in an embodiment of the present disclosure Figure 1 ;

[0029] Figure 6 A schematic diagram of the local structure of a counter provided in an embodiment of the present disclosure Figure 2 ;

[0030] Figure 7 A flow chart of a built-in self-test method provided in an embodiment of the present disclosure;

[0031] Figure 8 A schematic diagram of the structure of a test system provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0032] The following, in conjunction with the accompanying drawings, provides a clear and complete description of the technical solutions in the embodiments of the present disclosure. It should be understood that the specific embodiments described herein are intended solely to illustrate the related applications and are not intended to limit those applications. It should also be noted that, for ease of description, only portions of the drawings related to the related applications are shown. Unless otherwise defined, all technical and scientific terms used herein have the same meanings as commonly understood by those skilled in the art to which the present disclosure relates. The terms used herein are for the purpose of describing the embodiments of the present disclosure only and are not intended to limit the present disclosure. In the following description, references to "some embodiments" describe a subset of all possible embodiments. However, it should be understood that "some embodiments" may refer to the same or different subsets of all possible embodiments and may be combined with each other without conflict. It should be noted that the terms "first," "second," and "third" in the embodiments of the present disclosure are used solely to distinguish similar objects and do not represent a specific ordering of the objects. It should be understood that "first," "second," and "third" may be interchanged in a specific order or sequential order, where permitted, to enable the embodiments of the present disclosure described herein to be implemented in an order other than that illustrated or described.

[0033] As aforementioned, the mbist test can only record 2 false addresses in a first-in-first-out mode.Like this, in the process of testing after the chip is produced, can only be included in wafer test (Chip Probing, CP) / semiconductor process (Final Test, FT) the false address caught in the test and verify whether the mbist function is correct by comparing 2 false addresses caught at last in the mbist test, but can't judge whether other false address mbist test detects, causes and can't judge whether the mbist function is correct; In addition, when system level test, some test pattern (Test Mode) can make the part error disappear by part means (for example, relaxing sequential timing), but the mbist test can only record last 2 false addresses, can't also embody the effect that improvement means brings, thereby causes the improvement means of test pattern can't normally use.

[0034] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0035] In one embodiment of the present disclosure, see Figure 1 , which shows a schematic diagram of the structure of a memory 10 provided by an embodiment of the present disclosure. The memory 10 supports an error checking and correction (ECC) function, which performs data verification on the stored data through the parity check principle to improve the data stability of the memory 10. Figure 1 As shown, the memory 10 includes a counter 11, and the counter 11 is used to count the erroneous data bits obtained by data verification. In other words, the counter 11 is used to count the erroneous data bits detected during the ECC process, and can also be called an ECC counter.

[0036] The memory 10 further includes a built-in self-test module 12. The built-in self-test module 12 is configured to perform a self-test using a built-in self-test logic and output a flag pulse signal each time a data error is detected during the self-test process.

[0037] The counter 11 is connected to the built-in self-test module 12 and is configured to receive the flag pulse signal and count the flag pulse signal during the self-test process.

[0038] It should be noted that the memory 10 can be various types of memories that support ECC function, such as dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate memory (DDR), and low power DDR (LPDDR).

[0039] It should be understood that the built-in self-test and data check (or ECC operation) do not occur simultaneously. Therefore, the counter 11 in the ECC function can be reused for error counting during the built-in self-test. In other words, when the memory 10 performs an ECC operation, the counter 11 is used to count errors detected by the data check; and when the memory 10 performs a built-in self-test, the counter 11 is used to count errors detected during the self-test process.

[0040] In this way, on the one hand, the total number of errors detected by the built-in self-test will be recorded. Combined with the test results of the final wafer test, it can be accurately determined whether the built-in self-test module 12 is working normally, and the specific impact of the improvement measures on data errors can also be reflected during system-level testing. On the other hand, since the error count of the built-in self-test reuses the counter in the ECC function, the area occupied by the built-in self-test module 12 is almost not increased, avoiding additional costs or reducing chip performance.

[0041] Since the ECC operation generates result signals indicating different types of data errors, counter 11 needs to support counting of these result signals separately. Therefore, counter 11 includes at least two sub-counters capable of supporting independent counting. However, the built-in self-test only generates a result signal indicating one type of data error (i.e., a flag pulse signal), so different sub-counters in counter 11 can be combined to achieve a larger counting range.

[0042] Therefore, in some embodiments, Figure 2 As shown, the counter 11 includes a first counter 111 and a second counter 112; the counter 11 is configured to, when the count value of the first counter 111 has not reached the maximum value, increase the count value of the first counter 111 (i.e. Figure 2 and, after the count value of the first counter 111 reaches the maximum value, upon receiving the next flag pulse signal, the count value of the second counter 112 (ie Figure 2 The second count value in (the second count value in) and the count value of the first counter 111 are each increased by one.

[0043] That is, the counter 11 is further configured to combine the count value of the first counter 111 and the count value of the second counter 112 and output them as a final error value after the self-test is completed, so as to indicate the total number of errors detected in this self-test.

[0044] It should be noted that the first counter 111 includes a plurality of cascaded asynchronous counters. For example, Figure 3 As shown, the first counter 111 includes A cascaded flip-flops, the input end of each flip-flop is connected to its own inverting output end, the clock end of the first flip-flop constitutes the input end of the entire counter 111, the clock end of the i-th flip-flop is connected to the inverting output end of the i-1-th flip-flop, and the output end of each flip-flop outputs the first count value. <a-1:0>The structure of the second counter 112 is similar, as shown in FIG. Figure 4 As shown, the second counter 112 includes B cascaded triggers, which are connected in a similar manner to the above, and the output terminal of each trigger outputs the second count value <b-1:0>The trigger can be a D-type trigger, and A and B are both positive integers.

[0045] Thus, when the first counter 111 and the second counter 112 perform independent counting, the counting range of the first counter 111 is 0 to 2. A -1, the counting range of the second counter 112 is 0 to 2 B -1. Since there is only one type of error in the built-in self-test, the first counter 111 can be regarded as a low-bit counter and the second counter 112 can be regarded as a high-bit counter. That is, when the first counter 111 is full, it carries the second counter 112, and the count values ​​of the two can be combined to represent the final count value.<A+B-1:0> , that is, the second count value <a-1:0>Considered as terminal count value <a-1:0>, the second count value<B-1:0> Considered as terminal count value<A+B-1:A> The final count value range is 0 to 2 A+B -1, which extends the counting range and makes full use of counter 11.

[0046] It should be understood that Figure 3 The diagram only simplifies the counting-related circuit portion of the first counter 111 and does not limit the structure of the first counter 111. Figure 4 The diagram only illustrates the counting-related circuit portion of the second counter 112, and does not limit the structure of the second counter 112. The first counter 111 and the second counter 112 may include other logic processing devices.

[0047] In some embodiments, the counter 11 is further configured to receive a first type of pulse signal and a second type of pulse signal, and to count the first type of pulse signal using the first counter 111 and to count the second type of pulse signal using the second counter 112 .

[0048] It should be noted that both the first-class pulse signal and the second-class pulse signal are result signals generated during ECC operations and are used to indicate different types of errors detected by data verification. Specifically, each first-class pulse signal indicates an error detected during data verification of data transmitted using an odd clock, and each second-class pulse signal indicates an error detected during data verification of data transmitted using an even clock. The phases of the system odd and even clock signals are opposite.

[0049] Thus, during the ECC operation, the counter 11 counts the first type pulse signal and the second type pulse signal independently; during the built-in self-test, the counter 11 only counts the flag pulse signal.

[0050] In particular, the index pulse signal, the first type pulse signal, and the second type pulse signal can each be a positive pulse or a negative pulse, and the pulse types of the three are not necessarily the same. Furthermore, generally speaking, a index pulse signal comprises one pulse, but in other embodiments, a index pulse signal may comprise multiple pulses; the same applies to a first type pulse signal and a second type pulse signal.

[0051] In some embodiments, as Figure 2 As shown, the counter 11 also includes a first logic unit 13; the input end of the first logic unit 13 is used to receive a flag pulse signal and a first type pulse signal, and the output end of the first logic unit 13 is connected to the first counter 111; the first logic unit 13 is configured to output a first processing signal if it receives a flag pulse signal or a first type pulse signal; the first counter 111 is configured to count the first processing signal.

[0052] It should be noted that the first logic unit 13 may include but is not limited to the following devices: an AND gate, a NOT gate, an OR gate, a NAND gate, a NOR gate, an XNOR gate, and an XOR gate.

[0053] Here, the specific circuit structure of the first logic unit 13 needs to be determined according to the pulse type and pulse number of the flag pulse signal and the first type pulse signal. For example, assuming that the flag pulse signal and the first type pulse signal are both positive pulses, the first logic unit 13 can use a first OR gate with two inputs to output the enabled signal as the first processing signal when the first type pulse signal or the flag pulse signal is enabled. The first OR gate can be formed by a combination of a NOR gate and a NOT gate. For another example, assuming that the flag pulse signal and the first type pulse signal are both negative pulses, the first logic unit 13 can use a first AND gate with two inputs. If, in order to ensure the accuracy of the logic processing and accurately capture each enabled flag pulse signal and the first type pulse signal, each flag pulse signal and each first type pulse signal is composed of multiple pulses, the first logic unit 13 also needs to output only one pulse to facilitate the counting of the first counter 11 and the second counter 12, or control the first counter 11 and the second counter 12 to count only once within a specific period, thereby improving the counting accuracy while avoiding counting omissions. It is understandable that the above-mentioned outputting only one pulse or counting only once within a specific period can be achieved by setting a sampling unit and controlling the sampling clock period of the sampling unit.

[0054] Thus, during the ECC operation, the first counter 111 counts the first type pulse signal; during the internal self-test, the first counter 111 counts the mark pulse signal.

[0055] In some embodiments, as Figure 2 As shown, the first counter 111 is further configured to output a carry signal of a first state if its count value reaches a maximum value, and output a carry signal of a second state if its count value does not reach the maximum value. Here, the first state and the second state are different.

[0056] The counter 11 also includes a gating unit 14 and a second logic unit 15. The input end of the gating unit 14 receives a flag pulse signal and a carry signal, and the output end of the gating unit 14 is used to output an intermediate pulse signal; the input end of the second logic unit 15 receives the intermediate pulse signal and the second type of pulse signal; specifically, the gating unit 14 is configured to output the flag pulse signal as the intermediate pulse signal when the carry signal is in the first state; or, to shield the flag pulse signal when the carry signal is in the second state; the second logic unit 15 is connected to the gating unit 14, and is configured to receive the intermediate pulse signal and output the intermediate pulse signal as a second processing signal; or, to receive the second type of pulse signal and output the second type of pulse signal as a second processing signal; the second counter 112 is configured to count the second processing signal.

[0057] It should be noted that the gate control unit 14 may include, but is not limited to, the following devices: an AND gate, a NOT gate, an OR gate, a NAND gate, or a NOR gate, depending on the definition of the first state and the second state. For example, if the first state is a high level and the second state is a low level, the gate control unit 14 may be a second AND gate; for another example, if the first state is a low level and the second state is a high level, the gate control unit 14 may be an XOR gate.

[0058] The second logic unit 15 may include, but is not limited to, the following devices: an AND gate, a NOT gate, an OR gate, a NAND gate, a NOR gate, an XNOR gate, and an XOR gate, depending on the pulse type and number of the second type pulse signal and the intermediate pulse signal. For example, assuming that the second type pulse signal and the intermediate pulse signal are both positive pulses, the second logic unit 15 may use a second OR gate with two inputs, and the second OR gate may be formed by a NOR gate + a NOT gate combination. For another example, assuming that the second type pulse signal and the intermediate pulse signal are both negative pulses, the second logic unit 15 may use a third AND gate with two inputs; if each second type pulse signal or each intermediate pulse signal is composed of multiple pulses, the second logic unit may be set to adopt the structure of the above-mentioned first logic unit, or the second counter may be set to adopt the structure of the above-mentioned first counter and the sampling clock signal.

[0059] Thus, during the ECC operation, the second counter 112 counts the second type of pulse signals. During the built-in self-test, after the count value of the first counter 111 reaches the maximum value, the next flag pulse signal will trigger the second counter 112 to count and reset the count value of the first counter 111. It can be understood that after the count value of the first counter 111 is reset to zero, the carry signal returns to the dormant state. In other words, the carry signal is enabled only when the first counter 111 records a full carry.

[0060] See also Figure 5 , the following provides a local structure of the counter 11 in a specific scenario. Figure 5 In FIG, the flag pulse signal is represented as mBistErrCnt, the carry signal is represented as LowerAllHigh, the first processing signal is represented as ErrCntLo, and the second processing signal is represented as ErrCntHi.

[0061] In some embodiments, as Figure 5 As shown, the first type of pulse signal includes a first result signal OddLo and a second result signal OddHi. The first result signal OddLo indicates that an error is found after data verification of the low-byte data transmitted using an odd clock, and the second result signal OddHi indicates that an error is found after data verification of the high-byte data transmitted using an odd clock.

[0062] It should be noted that when the first result signal OddLo and the second result signal OddHi are enabled at the same time, their input timings should be staggered according to the number of counts per unit time of the first counter 111 to avoid omissions.

[0063] Correspondingly, the three input terminals of the first logic unit 13 are respectively used to receive the first result signal OddLo, the second result signal OddHi and the flag pulse signal mBistErrCnt, and the output terminal of the first logic unit 13 is used to output the first processing signal ErrCntLo.

[0064] Since the first result signal OddLo and the second result signal OddHi both belong to the first type of pulse signals, "receiving one first result signal OddLo or receiving one second result signal OddHi at the same time or in the counting cycle of the first counter" is equivalent to "receiving one first type of pulse signal".

[0065] In a specific embodiment, the first logic unit 13 is specifically configured to generate a first processing signal ErrCntLo if any one of the first result signal OddLo, the second result signal OddHi and the flag pulse signal mBistErrCnt is received.

[0066] It should be noted that the first result signal OddLo and the second result signal OddHi can be non-pulse signals or pulse signals. When the first result signal OddLo and the second result signal OddHi are pulse signals, their pulse type and specific number of pulses are not limited. Accordingly, the specific circuit structure of the first logic unit 13 needs to be determined based on the pulse type and specific number of pulses of the flag pulse signal mBistErrCnt, the first result signal OddLo, and the second result signal OddHi.

[0067] For example, Figure 5 As shown, assuming that the flag pulse signal mBistErrCnt, the first result signal OddLo, and the second result signal OddHi are all positive pulses, the first logic unit 13 can select a three-input first NOR gate 211 and a first NOT gate 212. The three input ends of the first NOR gate 211 respectively receive the first result signal OddLo, the second result signal OddHi, and the flag pulse signal mBistErrCnt. The output end of the first NOR gate 211 outputs the first inverted signal ErrCntLoN. The first inverted signal ErrCntLoN generates the first processing signal ErrCntLo through the first NOT gate 212.

[0068] In some embodiments, as Figure 3 As shown, the second type of pulse signal includes a third result signal EvenLo and a fourth result signal EvenHi. The three input ends of the second logic unit 15 are respectively used to receive the third result signal EvenLo, the fourth result signal EvenHi and the intermediate pulse signal, and the output end of the second logic unit 15 is used to output the second processing signal ErrCntHi; the third result signal EvenLo indicates that an error is found in the low-byte data transmitted using an even clock after data verification, and the fourth result signal EvenHi indicates that an error is found in the high-byte data transmitted using an even clock after data verification.

[0069] It should be noted that when the third result signal EvenLo and the fourth result signal EvenHi are enabled at the same time, their input timings should be staggered according to the number of counts per unit time of the first counter 111 to avoid omissions.

[0070] It should be noted that since both the third result signal EvenLo and the fourth result signal EvenHi are second-class pulse signals, "receiving one third result signal EvenLo or one fourth result signal EvenHi at the same time or during a counting cycle of the second counter" is equivalent to "receiving one second-class pulse signal." It should be understood that the third result signal EvenLo / fourth result signal EvenHi can be either a non-pulse signal or a pulse signal, and the pulse type and specific number of pulses are not limited. Accordingly, the specific circuit structure of the second logic unit 15 needs to be determined based on the pulse types of the intermediate pulse signal, the third result signal EvenLo, and the fourth result signal EvenHi.

[0071] For example, Figure 5 As shown, assuming that the intermediate pulse signal, the third result signal EvenLo, and the fourth result signal EvenHi are all positive pulses, the second logic unit 15 can select a three-input second NOR gate 214 and a second NOT gate 215. The three input ends of the second NOR gate 214 receive the intermediate pulse signal, the third result signal EvenLo, and the fourth result signal EvenHi respectively. The output end of the second NOR gate 214 outputs the second inverted signal ErrCntHiN. The first inverted signal ErrCntLoN generates the second processed signal ErrCntHi through the second NOT gate 215.

[0072] It should also be noted that the ECC operation has multiple verification modes. Under different verification modes, the specific error types represented by the first result signal OddLo, the second result signal OddHi, the third result signal EvenLo, and the fourth result signal EvenHi may be different, such as corrected errors, uncorrected errors, single-byte errors, multi-byte errors, etc.

[0073] In a specific embodiment, Figure 5 As shown, the memory 10 further includes a first logic unit 221, a second logic unit 222, a third logic unit 223, and a fourth logic unit 224. Specifically:

[0074] A first input terminal of the first logic unit 221 receives the first check signal DsfUeOdNLo, a second input terminal of the first logic unit 221 receives the second check signal DsfCeOdNLo, and an output terminal of the first logic unit 221 outputs a first result signal OddLo;

[0075] A first input terminal of the second logic unit 222 receives the third check signal DsfCeOdNHi, a second input terminal of the second logic unit 222 receives the fourth check signal DsfUeOdNHi, and an output terminal of the second logic unit 222 outputs a second result signal OddHi;

[0076] A first input terminal of the third logic unit 223 receives the fifth check signal SBECntNLo, a second input terminal of the third logic unit 223 receives the sixth check signal DBETrgNLo, and an output terminal of the third logic unit 223 outputs a third result signal EvenLo;

[0077] A first input terminal of the fourth logic unit 224 receives the seventh inspection signal SBECntNHi, a second input terminal of the fourth logic unit 224 receives the eighth inspection signal DBETrgNHi, and an output terminal of the fourth logic unit 224 outputs a fourth result signal EvenHi.

[0078] It should be noted that the error correction conditions indicated by the first check signal DsfUeOdNLo and the second check signal DsfCeOdNLo are different, so the two are generated at different times; the error correction conditions indicated by the third check signal DsfCeOdNHi and the fourth check signal DsfUeOdNHi are different, so the two are not generated at the same time; the error quantities indicated by the fifth check signal SBECntNLo and the sixth check signal DBETrgNLo are different, and the two are generated at different periods; the error quantities indicated by the seventh check signal SBECntNHi and the eighth check signal DBETrgNHi are different, and the two are generated at different periods.

[0079] Exemplarily, the first check signal DsfUeOdNLo indicates that the low byte data transmitted using the odd clock is found to have an error after data verification and the error has not been corrected; the second check signal DsfCeOdNLo indicates that the low byte data transmitted using the odd clock is found to have an error after data verification and the error has been corrected; the third check signal DsfCeOdNHi indicates that the high byte data transmitted using the odd clock is found to have an error after data verification and the error has not been corrected; the fourth check signal DsfUeOdNHi indicates that the high byte data transmitted using the odd clock is found to have an error after data verification and the error has been corrected; the fifth check signal SBECntNLo indicates that the low byte data transmitted using the even clock is found to have a single data bit error after data verification; the sixth check signal DBETrgNLo indicates that the low byte data transmitted using the even clock is found to have a double data bit error after data verification. When a single data bit error exists, the fifth check signal SBECntNLo is enabled. When the error data bit continues to increase and reaches an even number, that is, when a double data bit error exists, the sixth check signal D BETrgNLo is enabled, that is, the double data bit error here refers to an even number of erroneous data bits. When the number of erroneous data bits continues to increase, the number of erroneous data bits returns to an odd number. At this time, it is considered that a single data bit error exists, and the fifth check signal SBECntNLo is enabled, and so on. The seventh check signal SBECntNHi indicates that a single data bit error is found after data verification of the high byte data transmitted using an even clock. The eighth check signal DBETrgNHi indicates that a double data bit error is found after data verification of the high byte data transmitted using an even clock. Similarly, as above, when a single data bit error exists, the seventh check signal SBECntNHi is enabled. When the number of erroneous data bits continues to increase and reaches an even number, that is, when a double data bit error exists, the eighth check signal DBETrgNHi is enabled. That is, the double data bit error here refers to an even number of erroneous data bits. When the number of erroneous data bits continues to increase, the number of erroneous data bits returns to an odd number. At this time, it is considered that a single data bit error exists, and the seventh check signal SBECntNHi is enabled, and so on. The above is only an example. According to the actual circuit and the specific function of ECC, the meanings of the first check signal DsfUeOdNLo to the eighth check signal DBETrgNHi may vary. Accordingly, the meanings of the first result signal OddLo to the fourth result signal EvenHi may also vary.

[0080] In other embodiments, the fifth check signal SBECntNLo indicates that an odd-numbered data error is found after data verification of the low-byte data transmitted using an even clock, such as the 1st bit and the 3rd bit; the sixth check signal DBETrgNLo indicates that an even-numbered data error is found after data verification of the low-byte data transmitted using an even clock, such as the 2nd bit and the 4th bit; the seventh check signal SBECntNHi indicates that an odd-numbered data error is found after data verification of the high-byte data transmitted using an even clock; the eighth check signal DBETrgNHi indicates that an even-numbered data error is found after data verification of the high-byte data transmitted using an even clock.

[0081] In particular, the first inspection signal DsfUeOdNLo to the eighth inspection signal DBETrgNHi can each be a non-pulse signal or a pulse signal, and the pulse type and the number of pulses are not limited. In the case where the first inspection signal DsfUeOdNLo to the eighth inspection signal DBETrgNHi are all negative pulses, such as Figure 5 As shown, the first logic unit 221 can use a first NAND gate with two inputs, the second logic unit 222 can use a second NAND gate with two inputs, the third logic unit 223 can use a third NAND gate with two inputs, and the fourth logic unit 224 can use a fourth NAND gate with two inputs.

[0082] See Figure 6 , which shows a signal connection diagram of the first counter 111 and the second counter 112. Figure 6 Taking A=16 and B=16 as an example, the first count value is represented as ErrCountLo<15:0>, and the second count value is represented as ErrCountHi<15:0>.

[0083] In some embodiments, as Figure 6 As shown, the first counter 111 is further configured to receive a first enable signal EnErrCntLo; wherein the first enable signal EnErrCntLo in the enabled state is used to enable the first counter 111, and the first enable signal EnErrCntLo is in the enabled state during at least part of the self-test phase and at least part of the data verification phase;

[0084] The second counter 112 is further configured to receive a second enable signal EnErrCntHi; wherein the second enable signal EnErrCntHi in the enabled state is used to enable the second counter 112, and the second enable signal EnErrCntHi is in the enabled state during at least part of the self-test stage and at least part of the data verification stage.

[0085] It should be noted that the first enable signal EnErrCntLo can be enabled in a high level or a low level; and the second enable signal EnErrCntHi can be enabled in a high level or a low level. Thus, the first counter 111 and the second counter 112 are enabled during both the ECC operation and the MBIST test, thereby performing corresponding error counting, improving the efficiency of the device and enabling the MBIST test results to provide more information.

[0086] In some embodiments, the first counter 111 is further configured to receive a reset signal Rst and perform a reset operation based on the reset signal Rst; the second counter 112 is further configured to receive the reset signal Rst and perform a reset operation based on the reset signal Rst.

[0087] Thus, after each counting is completed, the first counter 111 and the second counter 112 perform a reset operation, that is, the count value ErrCountLo<15:0> of the first counter 111 and the count value ErrCountHi<15:0> of the second counter 112 are cleared to zero, waiting for the next counting process.

[0088] In summary, the embodiment of the present disclosure multiplexes the ECC counter (i.e., counter 11) to implement the error (Fail) counting in the MBIST test, such as Figure 5 As shown, the error count of the MBIST test is combined with the error count of the ECC, that is, the flag pulse signal mBistErrCnt is also input to the counter 11 (which is originally used to perform the error count of the ECC). Since the counter 11 includes a first counter 111 and a second counter 112, each of which outputs a 16-bit count value (the maximum count value is 2 16 -1), which can realize independent counting of different types of errors; however, the MBIST test only generates one type of error, so the first counter 111 and the second counter 112 are combined, and the first counter 111 carries the second counter 112 after it is full, and a total of 32-bit count values ​​can be output (the maximum count value is 2 32 -1) to represent the total number of errors in the MBIST test. The disclosed embodiment has advantages in at least the following aspects: on the one hand, by comparing the total number of errors recorded in the MBIST test with the total number of errors obtained in the CP / FT test under the same conditions, test engineers can more accurately verify whether the MBIST function is operating normally; on the other hand, the test mode (Test Mode) provided by the MBIST test can be used to perform a data retention stress test on the storage cells of the memory, and the retention performance of the chip is obtained based on the total number of errors recorded in the MBIST test, thereby correlating it with the test results of the automatic test equipment (ATE); on the other hand, the test unit Test Mode provided by the MBIST can be used to quickly correct chips with storage failures (coretiming fails) caused by tight timing (implemented by relaxing the timing); if the error disappears after relaxing the timing, it indicates that the data was written incorrectly or not written normally due to the tight timing, and the verification result is determined based on the total number of errors recorded in the MBIST test; on the other hand, the error counting multiplexing circuit of the MBIST test is implemented by the existing ECC counter, so the chip area overhead is very small and no additional counting circuit is introduced.

[0089] In another embodiment of the present disclosure, see Figure 7 , which shows a flow chart of a built-in self-test method provided by an embodiment of the present disclosure. The method is applied to a memory including a counter, and the counter is used to count the error data bits obtained by data verification, that is, the counter is used to count errors in ECC operations. Figure 7 As shown, the process includes:

[0090] S301: In a built-in self-test mode, perform a self-test using built-in self-test logic.

[0091] S302: During the self-test process, a counter is used to count the detected data errors.

[0092] In some embodiments, the counter includes a first counter and a second counter; and counting the detected data errors using the counter includes:

[0093] If the count value of the first counter has not reached the maximum value, the count value of the first counter is increased by one each time a data error is detected;

[0094] If the count value of the first counter reaches the maximum value, when the next data error is detected, the count value of the second counter and the count value of the first counter are each increased by one.

[0095] In some embodiments, the method further comprises:

[0096] Counting the first type of errors using a first counter; and counting the second type of errors using a second counter;

[0097] Among them, each first-type pulse signal represents that an error is found in data transmitted using an odd clock after data verification, and each second-type pulse signal represents that an error is found in data transmitted using an even clock after data verification, and the phases of the system odd clock signal and the system even clock signal are opposite.

[0098] In some embodiments, the method further comprises:

[0099] After the self-test is completed, the count value of the first counter and the count value of the second counter are combined and output as a final error value to indicate the total number of errors detected in this self-test.

[0100] In this way, the disclosed embodiment utilizes the counter in the ECC operation to count data errors detected in the built-in self-test. On the one hand, the total number of errors detected by the built-in self-test will be recorded. Combined with the test results of the CP / FT test, it can be accurately determined whether the built-in self-test is working properly. In addition, the specific impact of the improvement measures on data errors can be reflected during system-level testing. On the other hand, because the error counting of the built-in self-test reuses the counter in the ECC function, no additional chip area is required.

[0101] In another embodiment of the present disclosure, see Figure 8 , which shows a schematic diagram of the structure of a test system 40 provided by an embodiment of the present disclosure. Figure 8 As shown, the test system 40 includes a memory controller 401 and the aforementioned memory 10, and the memory controller 401 is connected to the memory 10;

[0102] The memory controller 401 is configured to send a self-test instruction to the memory 10;

[0103] The memory 10 is configured to perform a self-test using built-in test logic after receiving a self-test instruction, and to count detected data errors using a counter during the self-test process.

[0104] The above are only preferred embodiments of the present disclosure and are not intended to limit the scope of protection of the present disclosure. It should be noted that in the present disclosure, the terms "include", "comprise" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element. The above serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in the several method embodiments provided in the present disclosure can be arbitrarily combined to obtain new method embodiments if there is no conflict. The features disclosed in the several product embodiments provided in the present disclosure can be arbitrarily combined to obtain new product embodiments if there is no conflict. The features disclosed in the several method or device embodiments provided in the present disclosure can be arbitrarily combined to obtain new method embodiments or device embodiments if there is no conflict. The above are only specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A memory, characterized in that: The memory includes a counter, and the counter is used to count the erroneous data bits obtained by data verification; The memory also includes a built-in self-test module; The built-in self-test module is configured to perform a self-test using a built-in self-test logic, and output a flag pulse signal each time a data error is detected during the self-test process; The counter is connected to the built-in self-test module and is configured to receive the flag pulse signal and count the flag pulse signal during the self-test process; The counter includes a first counter and a second counter; The counter is configured to increase the count value of the first counter by one each time the flag pulse signal is received when the count value of the first counter has not reached a maximum value; and, after the count value of the first counter reaches a maximum value, upon receiving the next flag pulse signal, adding one to the count value of the second counter and the count value of the first counter; The counter is further configured to receive a first type of pulse signal and a second type of pulse signal, count the first type of pulse signal using the first counter, and count the second type of pulse signal using the second counter; Among them, each of the first-type pulse signals represents that an error is found in data transmitted using an odd clock after data verification, and each of the second-type pulse signals represents that an error is found in data transmitted using an even clock after data verification, and the phases of the odd clock and the even clock are opposite.

2. The memory according to claim 1, wherein The counter further includes a first logic unit; an input end of the first logic unit is used to receive the flag pulse signal and the first type pulse signal, and an output end of the first logic unit is connected to the first counter; The first logic unit is configured to output a first processing signal if it receives one of the flag pulse signals or one of the first type pulse signals; The first counter is configured to count the first processed signal.

3. The memory according to claim 1, wherein: The first counter is further configured to output a low-order carry signal of a first state if its count value reaches a maximum value; and output a carry signal of a second state if its count value does not reach the maximum value; The counter further comprises a gate control unit and a second logic unit, wherein the input end of the gate control unit receives the flag pulse signal and the carry signal, and the output end of the gate control unit is used to output the intermediate pulse signal; An input end of the second logic unit receives the intermediate pulse signal and the second type pulse signal; The gate control unit is configured to output the flag pulse signal as an intermediate pulse signal when the carry signal is in a first state; Alternatively, when the carry signal is in the second state, shielding the flag pulse signal; The second logic unit is connected to the gate control unit and configured to receive the intermediate pulse signal and output the intermediate pulse signal as a second processed signal; Alternatively, receiving the second-type pulse signal and outputting the second-type pulse signal as the second processed signal; The second counter is configured to perform counting processing on the second processing signal.

4. The memory according to claim 2, wherein: The first type of pulse signal includes a first result signal and a second result signal, the three input terminals of the first logic unit are respectively used to receive the first result signal, the second result signal and the flag pulse signal, and the output terminal of the first logic unit is used to output the first processing signal; The first result signal indicates that an error is found in the low-byte data transmitted using the odd clock after data verification, and the second result signal indicates that an error is found in the high-byte data transmitted using the odd clock after data verification.

5. The memory according to claim 3, wherein: The second type of pulse signal includes a third result signal and a fourth result signal, the three input terminals of the second logic unit are respectively used to receive the third result signal, the fourth result signal and the intermediate pulse signal, and the output terminal of the second logic unit is used to output the second processed signal; The third result signal indicates that an error is found in the low-byte data transmitted using an even clock after data verification, and the fourth result signal indicates that an error is found in the high-byte data transmitted using an even clock after data verification. The memory according to claim 1 , wherein: The first counter is further configured to receive a first enable signal; wherein the first enable signal in an enabled state is used to enable the first counter, and the first enable signal is in an enabled state during at least a portion of the self-test and at least a portion of the data verification; The second counter is further configured to receive a second enable signal; wherein the second enable signal in the enabled state is used to enable the second counter, and the second enable signal is in the enabled state during at least part of the self-test and at least part of the data verification.

7. The memory according to any one of claims 1 to 6, characterized in that: The counter is further configured to combine the count value of the first counter and the count value of the second counter and output them as a final error value after the self-test is completed, so as to indicate the total number of errors detected in the self-test.

8. A built-in self-test method, characterized in that: The method is applied to a memory including a counter, wherein the counter is used to count erroneous data bits obtained by data verification; the method comprises: In built-in self-test mode, performing self-test using built-in self-test logic; and During the self-test, the counter is used to count the detected data errors; The counter includes a first counter and a second counter; and counting the detected data errors using the counter includes: If the count value of the first counter has not reached the maximum value, the count value of the first counter is increased by one each time a data error is detected; If the count value of the first counter reaches a maximum value, then when the next data error is detected, the count value of the second counter and the count value of the first counter are each increased by one; The counter is configured to receive a first type of pulse signal and a second type of pulse signal; and the method further comprises: Counting the first type of pulse signal using the first counter; and counting the second type of pulse signal using the second counter; Among them, each of the first-type pulse signals represents that an error is found in data transmitted using an odd clock after data verification, and each of the second-type pulse signals represents that an error is found in data transmitted using an even clock after data verification, and the phases of the odd clock and the even clock are opposite.

9. The method according to claim 8, characterized in that The method further comprises: After the self-test is completed, the count value of the first counter and the count value of the second counter are combined and output as a final error value to indicate the total number of errors detected in this self-test.

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