Semiconductor structure manufacturing method, semiconductor structure, and semiconductor bonding structure

Abstract

The present disclosure provides a method for manufacturing a semiconductor structure, a semiconductor structure, and a semiconductor bonding structure. The manufacturing method includes: providing a metal layer; forming a passivation layer, the passivation layer covering the top surface of the metal layer; forming at least one groove, the groove at least penetrating the passivation layer; forming a dielectric material layer, the dielectric material layer filling the groove and covering the top surface of the passivation layer; grinding the dielectric material layer with the top surface of the passivation layer as the grinding stop point, and forming a dielectric layer in the groove by grinding the retained dielectric material layer. The present disclosure adjusts the process sequence, forms a passivation layer on the entire metal layer before etching the metal layer, reduces the thickness of the film layer formed on the metal layer, and then performs the steps of forming the groove and forming the dielectric material layer to fill the groove, and grinds the dielectric material layer with the top surface of the passivation layer as the grinding stop point, thereby optimizing the process, improving processing efficiency, and improving the quality of the formed semiconductor structure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor structure, a semiconductor structure, and a semiconductor bonding structure. Background Art

[0002] With the development of integrated circuit manufacturing technology, the integration of integrated circuits continues to increase, and the precision requirements for various components in integrated circuits are also increasing. In the semiconductor manufacturing process, it is easy for protrusions to form on the top surface of the wafer in the back-end process, resulting in a large height difference on the top surface of the wafer, resulting in gaps on the bonding surface after the wafer is bonded to other wafers, and the wafers cannot be tightly bonded. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0004] The present disclosure provides a method for manufacturing a semiconductor structure, a semiconductor structure, and a semiconductor bonding structure.

[0005] A first aspect of the present disclosure provides a method for manufacturing a semiconductor structure, the method comprising:

[0006] providing a metal layer;

[0007] forming a passivation layer, wherein the passivation layer covers a top surface of the metal layer;

[0008] forming at least one trench, wherein the trench at least penetrates the passivation layer;

[0009] forming a dielectric material layer, wherein the dielectric material layer fills the trench and covers the top surface of the passivation layer;

[0010] The dielectric material layer is ground with the top surface of the passivation layer as a grinding stop point, and the dielectric material layer retained by grinding forms a dielectric layer in the groove.

[0011] Optionally, the metal layer is formed on the interlayer dielectric layer, and forming at least one trench includes:

[0012] A first trench is formed, wherein the first trench penetrates the passivation layer and the metal layer, and the first trench exposes a top surface of the interlayer dielectric layer.

[0013] Optionally, the manufacturing method includes:

[0014] Depositing a dielectric material to fill the first trench and cover the top surface of the passivation layer to form a first dielectric material layer;

[0015] The first dielectric material layer is ground with the top surface of the passivation layer as a grinding stop point to form a first dielectric layer. The first dielectric layer is located in the first trench and divides the metal layer into a metal circuit layer.

[0016] Optionally, forming at least one trench comprises:

[0017] A second trench is formed, wherein the second trench penetrates the passivation layer and exposes a top surface of the metal layer.

[0018] Optionally, the manufacturing method includes:

[0019] Depositing a dielectric material to fill the second trench and cover the top surface of the passivation layer to form a second dielectric material layer;

[0020] The second dielectric material layer is ground with the top surface of the passivation layer as a grinding stop point to form a second dielectric layer in the second trench.

[0021] Optionally, the manufacturing method further includes:

[0022] removing a portion of the second dielectric layer to form a first through hole in the second dielectric layer, wherein the first through hole exposes a top surface of the metal layer;

[0023] A metal interconnect structure is formed in the first through hole.

[0024] Optionally, forming a metal interconnection structure in the first through hole includes:

[0025] forming a first metal material layer, wherein the first metal material layer fills the first through hole and covers a top surface of the passivation layer;

[0026] The first metal material layer is ground with the top surface of the passivation layer as a grinding stop point, and the ground first metal material layer forms the metal interconnection structure.

[0027] A second aspect of the present disclosure provides a semiconductor structure, comprising:

[0028] Metal layer;

[0029] a passivation layer, the passivation layer covering a top surface of the metal layer;

[0030] at least one trench, the trench at least penetrating the passivation layer;

[0031] a dielectric layer located in the trench;

[0032] The semiconductor structure includes a first surface including a top surface of the dielectric layer and a top surface of the passivation layer.

[0033] Optionally, the metal layer is provided on the interlayer dielectric layer, and the semiconductor structure includes:

[0034] a first trench, penetrating the passivation layer and the metal layer;

[0035] The dielectric layer includes a first dielectric layer, the first dielectric layer fills the first trench, the first dielectric layer is connected to the interlayer dielectric layer, and the first dielectric layer divides the metal layer into metal circuit layers.

[0036] Optionally, the semiconductor structure includes:

[0037] a second trench penetrating the passivation layer;

[0038] The dielectric layer includes a second dielectric layer, the second dielectric layer fills the second trench, and the second dielectric layer covers a portion of the top surface of the metal layer.

[0039] Optionally, the semiconductor structure further includes:

[0040] A metal interconnection structure is provided in the second dielectric layer, and the metal interconnection structure penetrates the second dielectric layer and is in contact with and connected to the metal layer.

[0041] Optionally, the first surface also includes the top surface of the metal interconnect structure

[0042] Optionally, an air gap is provided in the first dielectric layer, and a top surface of the air gap is lower than the first surface.

[0043] A third aspect of the present disclosure provides a semiconductor bonding structure, comprising a first semiconductor structure and a second semiconductor structure, wherein the first semiconductor structure and the second semiconductor structure both adopt the semiconductor structure according to the second aspect of the present disclosure;

[0044] The first surface of the first semiconductor structure and the first surface of the second semiconductor structure are arranged opposite to each other, the first surface of the first semiconductor structure and the first surface of the second semiconductor structure are connected together, and at the connection surface between the first semiconductor structure and the second semiconductor structure, the dielectric layer of the first semiconductor structure and the dielectric layer of the second semiconductor structure are bonded and connected, and the passivation layer of the first semiconductor structure and the passivation layer of the second semiconductor structure are bonded and connected.

[0045] In the semiconductor structure manufacturing method, semiconductor structure, and semiconductor bonding structure provided by the embodiments of the present disclosure, by adjusting the process sequence, a passivation layer is formed on the entire metal layer before the metal layer is etched, thereby reducing the thickness of the film layer formed on the metal layer, and then performing the steps of forming a groove and forming a dielectric material layer to fill the groove. The dielectric material layer is ground with the top surface of the passivation layer as the grinding stop point, thereby optimizing the process, improving processing efficiency, and improving the quality of the formed semiconductor structure.

[0046] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The accompanying drawings, which are incorporated into and constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the description, are used to explain the principles of the embodiments of the present disclosure. In these drawings, similar reference numerals are used to represent similar elements. The drawings described below are some embodiments of the present disclosure, not all embodiments. For those skilled in the art, other drawings can be derived from these drawings without inventive effort.

[0048] Figure 1 FIG. 1 is a schematic diagram of a metal layer formed in the related art.

[0049] Figure 2 It is a schematic diagram after the metal circuit layer is formed in the related art.

[0050] Figure 3 It is a schematic diagram after forming a dielectric material layer and a passivation layer in the related art.

[0051] Figure 4 This is a schematic diagram of the related art after the top surface of the passivation layer is ground into a plane.

[0052] Figure 5 It is a schematic diagram after the second trench is formed in the related art.

[0053] Figure 6 It is a schematic diagram of forming a polymer layer to fill the second trench in the related art.

[0054] Figure 7 It is a schematic diagram of a metal interconnection structure formed in the related art.

[0055] Figure 8 is a schematic diagram of a semiconductor structure formed in the related art.

[0056] Figure 9 It is a schematic diagram of the bonding connection between a semiconductor structure and other structures in the related art.

[0057] Figure 10The figure is a flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment.

[0058] Figure 11 The figure is a flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment.

[0059] Figure 12 is a schematic diagram of a metal layer according to an exemplary embodiment.

[0060] Figure 13 FIG. 1 is a schematic diagram showing a structure after a passivation layer is formed according to an exemplary embodiment.

[0061] Figure 14 FIG. 1 is a schematic diagram showing a structure after trenches are formed according to an exemplary embodiment.

[0062] Figure 15 FIG. 1 is a schematic diagram showing a dielectric material layer formed according to an exemplary embodiment.

[0063] Figure 16 FIG. 1 is a schematic diagram showing a dielectric layer formed according to an exemplary embodiment.

[0064] Figure 17 FIG. 1 is a schematic diagram showing a structure after trenches are formed according to an exemplary embodiment.

[0065] Figure 18 FIG. 1 is a schematic diagram showing a dielectric material layer formed according to an exemplary embodiment.

[0066] Figure 19 FIG. 1 is a schematic diagram showing a dielectric layer formed according to an exemplary embodiment.

[0067] Figure 20 FIG. 1 is a schematic diagram showing a process after forming a first trench according to an exemplary embodiment.

[0068] Figure 21 FIG. 1 is a schematic diagram showing a first dielectric material layer formed according to an exemplary embodiment.

[0069] Figure 22 FIG. 1 is a schematic diagram showing a structure after forming a first dielectric layer according to an exemplary embodiment.

[0070] Figure 23 FIG. 1 is a schematic diagram showing a second trench formed according to an exemplary embodiment.

[0071] Figure 24 FIG. 4 is a schematic diagram showing a second dielectric material layer formed according to an exemplary embodiment.

[0072] Figure 25 FIG. 1 is a schematic diagram showing a second dielectric layer formed according to an exemplary embodiment.

[0073] Figure 26 FIG. 1 is a schematic diagram showing a first through hole formed according to an exemplary embodiment.

[0074] Figure 27 FIG. 1 is a schematic diagram showing a process after forming a first metal material layer according to an exemplary embodiment.

[0075] Figure 28 FIG. 1 is a schematic diagram showing a metal interconnect structure formed according to an exemplary embodiment.

[0076] Figure 29 FIG. 1 is a schematic diagram showing a semiconductor bonding structure according to an exemplary embodiment.

[0077] Reference numerals:

[0078] 10. Metal layer; 11. First barrier layer; 12. Second barrier layer; 20. Passivation layer; 21. Groove; 121. First groove; 221. Second groove; 30. Dielectric material layer; 130. First dielectric material layer; 230. Second dielectric material layer; 40. Dielectric layer; 140. First dielectric layer; 141. Air gap; 240. Second dielectric layer; 241. First via; 50. Interlayer dielectric layer; 60. Metal interconnect structure; 61. Metal conductor; 62. Contact pad; 70. First metal material layer; 80. Metal circuit layer; 100a. First surface;

[0079] h1, first preset height; h2, second preset height;

[0080] 110, first semiconductor structure; 210, second semiconductor structure; 110a, first surface of the first semiconductor structure; 210a, first surface of the second semiconductor structure; 120, passivation layer of the first semiconductor structure; 220, passivation layer of the second semiconductor structure; 160, metal interconnection structure of the first semiconductor structure; 260, metal interconnection structure of the second semiconductor structure;

[0081] 10', metal layer; 20', passivation layer; 121', first trench; 221', second trench; 30', dielectric material layer; 50', interlayer dielectric layer; 60', metal interconnect structure; 80', metal circuit layer; 90', polymer layer. DETAILED DESCRIPTION

[0082] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present disclosure. It should be noted that, in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0083] In the related art, metal circuit layers and metal interconnect structures are formed in the semiconductor back-end process using the following implementation methods:

[0084] like Figure 1 As shown, after forming the metal layer 10' on the interlayer dielectric layer 50', the metal layer 10' is patterned, as shown in FIG. Figure 2 As shown, a first trench 121' is formed in the metal layer 10', and the first trench 121' divides the metal layer 10' into a metal line layer 80'. Then, as shown in FIG. Figure 3 As shown, a dielectric material is deposited to fill the first trench 121' and cover the top surface of the metal wiring layer 80', forming a dielectric material layer 30'. The thickness of the dielectric material layer 30' located on the top surface of the metal wiring layer 80' is generally between 850 nm and 1000 nm. However, during the deposition of the dielectric material, the first trench 121' may not be fully filled, resulting in the top surface of the dielectric material layer 30' in the area filling the first trench 121' being higher than the top surface of the dielectric material layer 30' in other areas, resulting in a height difference on the top surface of the dielectric material layer 30'.

[0085] Then, if Figure 3 As shown, a passivation layer 20' is formed on the top surface of the dielectric material layer 30'. The thickness of the passivation layer 20' is generally 850nm-1000nm. Affected by the height difference of the top surface of the dielectric material layer 30', the top surface of the passivation layer 20' also has a height difference.

[0086] like Figure 4 As shown, the passivation layer 20' is processed by chemical mechanical polishing (CMP) to grind the top surface of the passivation layer 20' into a flat surface. After grinding, the total thickness of the dielectric material layer 30' and the passivation layer 20' on the metal circuit layer 80' is about 1700nm-2000nm. Then, as shown in FIG. Figure 5As shown, the passivation layer 20' and the dielectric material layer 30' located on the top surface of the metal wiring layer 80' are etched to form a second trench 221'. The second trench 221' penetrates the passivation layer 20' and the first dielectric layer 140' located on the top surface of the metal wiring layer 80'. The second trench 221' exposes the top surface of the metal wiring layer 80'. The depth of the second trench 221' is 1700nm-2000nm.

[0087] Then, if Figure 6 As shown, refer to Figure 5 , forming a polymer layer 90', the polymer layer 90' fills the second trench 221' and covers the top surface of the passivation layer 20'. Figure 7 As shown, a metal interconnection structure 60 ′ is formed in the second trench 221 ′.

[0088] Since the depth of the second trench 221' is very deep, after the polymer layer 90' is formed, the top surface of the polymer layer 90' in the second trench 221' is lower than the top surface of the polymer layer 90' on the passivation layer 20'. In addition, the texture of the polymer layer 90' is generally soft and is not suitable for bonding semiconductor structures and other structures. A chemical mechanical polishing process is required to polish and remove the polymer layer 90' on the top surface of the passivation layer 20'. However, the texture of the polymer layer 90' is soft, and it is impossible to polish the polymer layer 90' and the dielectric material layer 30' at the same polishing rate. Figure 8 As shown, even after grinding, the height difference of the top surface of the semiconductor structure cannot be completely eliminated, that is, the top surface of the finally formed semiconductor structure still has a height difference. Figure 9 As shown, voids are likely to appear at the connection interface between a semiconductor structure and another semiconductor structure. In particular, when a hybrid bonding (HB) process is used to bond the semiconductor structure to another semiconductor structure, the void problem becomes more serious.

[0089] In view of this, an exemplary embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, comprising the following steps: providing a metal layer; forming a passivation layer, the passivation layer covering the top surface of the metal layer, the passivation layer having a first preset height, and the top surface of the passivation layer being a plane; forming at least one groove, the groove at least penetrating the passivation layer; forming a dielectric material layer, the dielectric material layer filling the groove and covering the top surface of the passivation layer; grinding the dielectric material layer with the top surface of the passivation layer as the grinding stop point, and forming a dielectric layer in the groove by grinding the retained dielectric material layer. The present disclosure adjusts the process sequence, forms a passivation layer on the entire metal layer before etching the metal layer, reduces the thickness of the film layer formed on the metal layer, and then performs the steps of forming the groove and forming the dielectric material layer to fill the groove, and grinds the dielectric material layer with the top surface of the passivation layer as the grinding stop point, thereby optimizing the process, improving processing efficiency, and improving the quality of the formed semiconductor structure.

[0090] In an exemplary embodiment of the present disclosure, a method for manufacturing a semiconductor structure is provided. Figure 10 As shown, Figure 10 FIG2 shows a flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure. Figure 12-Figure 19 The schematic diagram of each stage of the semiconductor structure manufacturing method is shown below. Figure 12-Figure 19 The fabrication method of semiconductor structures is introduced.

[0091] This embodiment does not limit the semiconductor structure. The semiconductor structure will be described below using a dynamic random access memory (DRAM) as an example, but this embodiment is not limited thereto. The semiconductor structure in this embodiment may also be other structures.

[0092] like Figure 10 As shown, an exemplary embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, comprising the following steps:

[0093] Step S110: providing a metal layer.

[0094] like Figure 12 As shown, the metal layer 10 can be set on a semiconductor substrate or a semiconductor wafer. The metal layer 10 is a material layer used to form a semiconductor element. The material of the metal layer 10 can include aluminum or aluminum alloy layer, tungsten or tungsten alloy layer, titanium or titanium alloy layer, etc.

[0095] Step S120: forming a passivation layer, where the passivation layer covers the top surface of the metal layer.

[0096] like Figure 13As shown, a passivation layer 20 may be formed on the top surface of the metal layer 10 by a deposition process. It is understood that after deposition, a grinding process may be used to grind the top surface of the passivation layer 20 to grind the top surface of the passivation layer 20 into a plane.

[0097] Step S130: forming at least one trench, wherein the trench at least penetrates the passivation layer.

[0098] In some examples, such as Figure 14 As shown, the groove 21 may penetrate the passivation layer 20 and the metal layer 10, and the groove 21 may expose the film layer below the metal layer 10. Alternatively, in other examples, such as Figure 17 As shown, a trench 21 may be formed in the passivation layer 20 , the trench 21 penetrating the passivation layer 20 and exposing the top surface of the metal layer 10 .

[0099] Step S140 : forming a dielectric material layer, where the dielectric material layer fills the trench and covers the top surface of the passivation layer.

[0100] like Figure 15 , reference Figure 14 As shown, or, as Figure 18 , refer to Figure 17 As shown, a deposition process can be used to deposit a dielectric material, which fills the trench 21 and covers the top surface of the passivation layer 20 to form a dielectric material layer 30. The presence of the trench 21 causes a concave defect or a convex defect to form on the top surface of the dielectric layer 40 located above the trench 21, and the top surface of the dielectric layer 40 has a height difference.

[0101] Step S150 : grinding the dielectric material layer with the top surface of the passivation layer as a grinding stop point, and forming a dielectric layer in the groove by grinding the remaining dielectric material layer.

[0102] like Figure 16 , reference Figure 15 As shown, or, as Figure 19 , refer to Figure 18 As shown in the figure, the dielectric material layer 30 is ground with the top surface of the passivation layer 20 as the grinding stop point. For example, white light endpoint detection or advanced process control (APC) technology can be used to detect the top surface of the passivation layer 20. When the top surface of the passivation layer 20 is detected, the grinding is stopped, and the dielectric material layer 30 located on the top surface of the passivation layer 20 is removed. The dielectric material layer 30 located in the groove 21 is retained to form a dielectric layer 40.

[0103] The method for manufacturing a semiconductor structure of this exemplary embodiment adjusts the process sequence. Before etching the metal layer, a passivation layer is formed on the entire metal layer to reduce the thickness of the film layer formed on the metal layer. Then, the steps of forming a groove and forming a dielectric material layer to fill the groove are performed. The portion of the top of the dielectric material layer with a height difference is located above the passivation layer. The portion of the dielectric material layer with a height difference can be removed by grinding the dielectric material layer with the top surface of the passivation layer as the grinding stop point. By optimizing the process, the processing efficiency is improved and the quality of the formed semiconductor structure is improved.

[0104] The top surface of the semiconductor structure formed in this embodiment is composed of the top surface of the passivation layer and the top surface of the dielectric layer. The top surface of the semiconductor structure has good bonding ability, ensuring that after the conductor is bonded and connected to other structures, the connection surfaces of the semiconductor structure and the other structures are tightly connected, and the connection surfaces have no gap defects, so that the semiconductor structure and the other structures can be bonded and connected more firmly.

[0105] In an exemplary embodiment of the present disclosure, a method for manufacturing a semiconductor structure is provided. Figure 11 As shown, Figure 11 FIG2 shows a flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure. Figure 12-13 、 Figures 20-28 The schematic diagram of each stage of the semiconductor structure manufacturing method is shown below. Figure 12-13 、 Figures 20-28 The fabrication method of semiconductor structures is introduced.

[0106] like Figure 11 As shown, an exemplary embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, comprising the following steps:

[0107] Step S210: providing a metal layer, wherein the metal layer is formed on the interlayer dielectric layer.

[0108] This exemplary embodiment is described by taking a process of forming a metal wiring layer ML (Metal Layer) in a back-end process of a DRAM memory as an example.

[0109] like Figure 12 As shown, the metal layer 10 is a whole film layer covering the interlayer dielectric layer 50, and no patterning process is performed on the metal layer 10. The material of the interlayer dielectric layer 50 may include at least one of silicon oxide, silicon nitride, or silicon oxynitride. The metal layer 10 is an aluminum metal layer 10 or an aluminum alloy metal layer 10. The thickness of the metal layer 10 is 550nm-700nm. For example, the thickness of the metal layer 10 can be 550nm, 600nm, 650nm, or 700nm. In this embodiment, the thickness of the metal layer 10 is 600nm.

[0110] The interlayer dielectric layer 50 is disposed on a semiconductor substrate or semiconductor wafer (not shown). The material of the semiconductor substrate or semiconductor wafer can be silicon (Si), germanium (Ge), silicon germanium (GeSi), or silicon carbide (SiC); it can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it can be other materials with semiconductor properties, such as III-V compounds such as gallium arsenide. The semiconductor substrate or semiconductor wafer may include one or more stacked semiconductor device layers, wherein each semiconductor device layer may be formed with multiple semiconductor devices and multiple metal devices. The semiconductor device may include at least one of a metal oxide semiconductor field effect transistor, a bipolar junction transistor, a resistor, an inductor, a diode, and an optical device.

[0111] like Figure 12 As shown, the bottom surface of the metal layer 10 is covered by a first barrier layer 11, and the top surface of the metal layer 10 is covered by a second barrier layer 12. The first barrier layer 11 and the second barrier layer 12 are used to protect the metal layer 10 to prevent the metal layer 10 from being oxidized when exposed to the process environment, thereby degrading the electrical properties of the metal layer 10. At the same time, the first barrier layer 11 and the second barrier layer 12 are also used to prevent the metal material in the metal layer 10 from diffusing into other film layers and causing contamination of other film layers of the semiconductor structure. The materials of the first barrier layer 11 and the second barrier layer 12 can include titanium or titanium nitride.

[0112] Step S220: forming a passivation layer, where the passivation layer covers the top surface of the metal layer.

[0113] like Figure 13 As shown, any one of the deposition processes of chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or sputtering can be used to deposit an insulating material to cover the top surface of the metal layer 10 to form a passivation layer 20. Then, a chemical mechanical polishing process can be used to polish the top surface of the insulating material layer to polish the top surface of the passivation layer 20 into a flat surface. The thickness of the passivation layer 20 is between 500nm and 1000nm. For example, the thickness of the passivation layer 20 can be 500nm, 600nm, 700nm, 800nm, 900nm or 1000nm. In this embodiment, the thickness of the passivation layer 20 is 1000nm.

[0114] The material of the passivation layer 20 includes silicon nitride, which is hard and has good grinding resistance. In the subsequent process, the top surface of the passivation layer 20 is used as the grinding stop point, which can avoid damaging the top surface of the passivation layer 20 during the grinding process, forming defects and height differences on the top surface of the passivation layer 20, and ensuring that the top surface of the formed semiconductor structure is flat.

[0115] Step S230: forming a first trench, wherein the first trench penetrates the passivation layer and the metal layer, and the first trench exposes the top surface of the interlayer dielectric layer.

[0116] like Figure 20 As shown, refer to Figure 13 A first mask layer (not shown) is formed on the top surface of the passivation layer 20. The first mask layer defines a pattern for forming the first trench 121. The passivation layer 20, the second barrier layer 12, the metal layer 10, and the first barrier layer 11 are sequentially etched (either dry or wet etching can be used) using the first mask layer until the top surface of the interlayer dielectric layer 50 is exposed, and the etching is stopped to form the first trench 121.

[0117] It is understandable that this embodiment does not limit the number, shape, and layout of the formed first trenches 121 , and one first trench 121 or multiple first trenches 121 can be formed according to the design and application requirements of the semiconductor structure.

[0118] Step S240 : depositing a dielectric material to fill the first trench and cover the top surface of the passivation layer to form a first dielectric material layer.

[0119] like Figure 21 As shown, refer to Figure 20 A dielectric material can be deposited using a chemical vapor deposition process or a physical vapor deposition process to form a first dielectric material layer 130. The first dielectric material layer 130 fills the first trench 121 and covers the top surface of the passivation layer 20. Due to the large depth-to-width ratio of the first trench 121, the first dielectric material layer 130 may not fully fill the first trench 121, resulting in an air gap 141 in the first trench 121. This results in a raised defect on the top surface of the first dielectric material layer 130 located above the first trench 121, resulting in a height difference on the top surface of the first dielectric material layer 130. In this embodiment, the material of the first dielectric material layer 130 includes silicon oxide.

[0120] Step S250: grinding the first dielectric material layer with the top surface of the passivation layer as the grinding stop point to form a first dielectric layer. The first dielectric layer is located in the first trench and divides the metal layer into a metal circuit layer.

[0121] like Figure 22 As shown, refer to Figure 21The first dielectric material layer 130 can be polished using a chemical mechanical polishing process, with the top surface of the passivation layer 20 serving as the polishing stop point. During the polishing process, white light endpoint detection or advanced control technology can be used to detect the top surface of the passivation layer 20. When the top surface of the passivation layer 20 is detected, polishing is stopped and the first dielectric material layer 130 located on the top surface of the passivation layer 20 is removed. The retained first dielectric material layer 130 forms a first dielectric layer 140. The first dielectric layer 140 fills the first trench 121. The top surface of the first dielectric layer 140 is flush with the top surface of the passivation layer 20. The bottom surface of the first dielectric layer 140 is connected to the interlayer dielectric layer 50 located below the metal layer 10. The first dielectric layer 140 divides the metal layer 10 into a metal circuit layer 80.

[0122] In the method for manufacturing a semiconductor structure of this embodiment, after forming a passivation layer, the metal layer is patterned to form a metal circuit layer, thereby preventing the portion of the top of the first dielectric material layer with a height difference from being directly formed on the top surface of the metal layer. The first dielectric material layer located on the top surface of the passivation layer is removed by grinding to form the first dielectric layer. The top surface of the formed semiconductor structure is flat, ensuring that there are no gaps at the connection surface where the semiconductor structure is bonded to other structures, and the semiconductor structure can be firmly connected to the other structures.

[0123] According to an exemplary embodiment, the method for manufacturing the semiconductor structure of this embodiment further performs the following steps after forming the first dielectric layer:

[0124] Step S260 : forming a second trench, wherein the second trench penetrates the passivation layer and exposes the top surface of the metal layer.

[0125] like Figure 23 As shown, refer to Figure 22 A second mask layer (not shown) is formed on the top surface of the passivation layer 20. The second mask layer defines a pattern for forming the second trench 221. The passivation layer 20 and the second barrier layer 12 are sequentially etched using the second mask layer until the top surface of the metal wiring layer 80 formed by the metal layer 10 is exposed, forming the second trench 221 penetrating the passivation layer 20.

[0126] This embodiment does not limit the number, shape, and layout of the formed second trenches 221 , and one or more second trenches 221 may be formed according to the design and application requirements of the semiconductor structure.

[0127] In this embodiment, during the formation of the second trench 221 , only the passivation layer 20 needs to be etched, which reduces the time cost of forming the second trench 221 and reduces the aspect ratio of the second trench 221 .

[0128] Step S270 : depositing a dielectric material to fill the second trench and cover the top surface of the passivation layer to form a second dielectric material layer.

[0129] like Figure 24 As shown, refer to Figure 23 A dielectric material can be deposited using a chemical vapor deposition process or a physical vapor deposition process to fill the second trench 221 to form a second dielectric material layer 230. The second dielectric material layer 230 also covers the top surface of the passivation layer 20. The area where the second dielectric material layer 230 fills the second trench 221 is lower than the top surface of the second dielectric material layer 230 in other areas, forming a height difference on the top surface of the second dielectric material layer 230.

[0130] Step S280 : grinding the second dielectric material layer with the top surface of the passivation layer as a grinding stop point to form a second dielectric layer in the second trench.

[0131] like Figure 25 As shown, refer to Figure 24 The second dielectric material layer 230 can be polished using a chemical mechanical polishing process, with the top surface of the passivation layer 20 serving as the polishing stop point. During the polishing process, white light endpoint detection or advanced control technology can be used to detect the top surface of the passivation layer 20. Polishing is stopped when the top surface of the passivation layer 20 is exposed, and the second dielectric material layer 230 located on the top surface of the passivation layer 20 is removed. The retained second dielectric material layer 230 forms a second dielectric layer 240, which fills the second trench 221. The top surface of the second dielectric layer 240, the top surface of the passivation layer 20, and the top surface of the first dielectric layer 140 are located in the same plane. The top surface of the semiconductor structure formed in this embodiment is flat.

[0132] In this embodiment, by adjusting the process sequence of the semiconductor back-end process, the process of forming the first trench patterned metal layer to form the metal circuit layer and the process of forming the second trench on the metal circuit layer are performed after the formation of the passivation layer. Only one passivation layer needs to be formed above the metal circuit layer, which reduces the thickness of the film layer located on the metal circuit layer, reduces the thickness of the film layer required to be etched to form the second trench on the metal circuit layer, and reduces the depth of the second trench formed on the metal circuit layer. As a result, the height difference formed on the top surface of the second dielectric material layer is reduced, and the difficulty of removing the height difference on the top surface of the second dielectric material layer is reduced. By grinding the second dielectric material layer with the top surface of the passivation layer as the grinding stop point, the portion of the second dielectric material layer with the height difference can be removed. At the same time, the top surface of the formed semiconductor structure is ensured to be planar, and the connection surface between the semiconductor structure and the other structure is ensured to have no gaps, and the semiconductor structure and the other structure are firmly connected.

[0133] This embodiment reduces the depth of the second trench, which is beneficial to improving the process efficiency of subsequently forming a metal interconnection structure and saving process time.

[0134] According to an exemplary embodiment, the method for manufacturing the semiconductor structure of this embodiment further performs the following steps after forming the second dielectric layer:

[0135] Step S290: removing a portion of the second dielectric layer to form a first through hole in the second dielectric layer, wherein the first through hole exposes the top surface of the metal layer.

[0136] like Figure 26 As shown, refer to Figure 25 , a portion of the second dielectric layer 240 is etched away until the top surface of the metal wiring layer 80 is exposed, and a first through hole 241 is formed in the second dielectric layer 240 .

[0137] Step S300: forming a metal interconnection structure in the first through hole.

[0138] In some examples, reference Figure 28 As shown, a dual damascene process can be used to form a metal interconnect structure 60, which penetrates the second dielectric layer 240. The metal interconnect structure 60 includes a metal wire 61 that contacts and connects to the metal line layer 80, and a contact pad 62 disposed on the metal wire 61. The top surface of the contact pad 62 is flush with the top surface of the second dielectric layer 240. In other examples, a single damascene process is used to form the metal interconnect structure 60, and the metal structure includes a metal wire that penetrates the second dielectric layer 240 (this example is not shown in the drawings).

[0139] In this embodiment, the metal interconnection structure 60 is formed in the first through hole 241, and the following implementation methods can be adopted:

[0140] First, an atomic layer deposition is used to form a diffusion barrier layer (not shown in the figure), which covers the first through hole 241 (refer to FIG. Figure 26 ) of the pore wall, the material of the diffusion barrier layer may include tantalum, titanium, tantalum oxide or titanium oxide.

[0141] Then, copper metal is deposited on the diffusion barrier layer using a physical vapor deposition process to form a seed layer (not shown in the figure). For example, the following embodiment can be used: the seed layer is pre-annealed for 20 seconds to 40 seconds at a temperature of 180° C. to 250° C. to promote the growth of the copper lattice of the seed layer, fill the gaps between the copper lattices in the seed layer, make the copper lattice of the seed layer uniform and continuous, reduce the resistance of the seed layer, and improve the conductivity of the seed layer, so that the formed metal interconnect structure 60 has good conductivity.

[0142] Then, if Figure 27 As shown, refer to Figure 26A first metal material layer 70 is formed by an electroplating process. The first metal material layer 70 grows on the seed layer. The first metal material layer 70 fills the first through hole 241 and covers the top surface of the passivation layer 20 .

[0143] Then, if Figure 28 As shown, refer to Figure 27 The first metal material layer 70 is ground with the top surface of the passivation layer 20 as the grinding stop point. During the grinding process, white light endpoint detection or advanced control technology can be used to detect the top surface of the passivation layer 20. Grinding is stopped when the top surface of the passivation layer 20 is exposed. The first metal material layer 70 located after the passivation layer is ground is removed. The ground first metal material layer 70 forms a metal interconnect structure 60. The metal interconnect structure 60 is embedded in the second dielectric layer 240. The peripheral surface of the metal interconnect structure 60 is covered by a seed layer. The metal interconnect structure 60 and the second dielectric layer 240 are separated by a barrier diffusion layer. The barrier diffusion layer is used to prevent the copper element in the metal interconnect structure 60 from diffusing into other structures and causing contamination of the semiconductor structure.

[0144] The top surface of the metal interconnect structure 60 formed in this embodiment is flush with the top surface of the passivation layer 20 and the top surface of the second dielectric layer 240 .

[0145] The method for manufacturing the semiconductor structure of this embodiment reduces the process depth for forming the metal interconnect structure, reduces the height of the metal interconnect structure, and reduces the resistance of the metal interconnect structure, which is beneficial for improving the conductivity and response speed of the semiconductor structure, avoiding response delays in the semiconductor structure, and at the same time shortening the process time for forming the metal interconnect structure and improving process efficiency. The top surface of the semiconductor structure formed in this embodiment is composed of the first dielectric layer, the second dielectric layer, the passivation layer, and the top surface of the metal interconnect structure. The top surface of the semiconductor structure is planar, and the material of the top surface of the semiconductor structure does not contain polymer materials with poor bonding ability. When the semiconductor structure of this embodiment and other structures are bonded and connected using a hybrid bonding process, the gap between the connection surfaces can be reduced, ensuring a more secure connection between the semiconductor structure and the other structures.

[0146] According to an exemplary embodiment, the difference between this embodiment and the above-mentioned embodiments is that, in the process of grinding the first metal material layer 70, after the top surface of the passivation layer 20 is exposed, the first metal material layer 70 and the passivation layer 20, the first dielectric layer 140, and the second dielectric layer 240 are ground together to the target height, thereby further reducing the height of the metal interconnect structure, reducing the contact resistance of the metal interconnect structure, improving the conductivity and response speed of the semiconductor structure, and avoiding response delay of the semiconductor structure.

[0147] In this embodiment, the target height is higher than the air gap 141 in the first dielectric layer 140 to avoid exposure of the air gap 141 and adverse effects on the semiconductor structure.

[0148] According to an exemplary embodiment, the present exemplary embodiment provides a semiconductor structure such as Figure 16 、 Figure 19 or Figure 28 As shown, the semiconductor structure includes a metal layer 10, a passivation layer 20, at least one trench 21 (refer to Figure 14 or Figure 17 ) and a dielectric layer 40, the passivation layer 20 covers the top surface of the metal layer 10; the trench 21 at least penetrates the passivation layer 20, and the dielectric layer 40 is located in the trench 21. The semiconductor structure includes a first surface 100a, which includes the top surface of the dielectric layer 40 and the top surface of the passivation layer 20.

[0149] In some embodiments, as Figure 28 As shown, the metal layer 10 (refer to Figure 16 or Figure 19 ) is disposed on the interlayer dielectric layer 50. The semiconductor structure includes a first trench 121 that penetrates the passivation layer 20 and the metal layer 10. The dielectric layer 40 includes a first dielectric layer 140 that fills the first trench 121. The first dielectric layer 140 is connected to the interlayer dielectric layer 50 and divides the metal layer 10 into metal circuit layers 80.

[0150] In some embodiments, as Figure 28 As shown, the semiconductor structure includes a second trench 221 penetrating the passivation layer 20 , and the dielectric layer 40 includes a second dielectric layer 240 . The second dielectric layer 240 fills the second trench 221 and covers a portion of the top surface of the metal layer 10 .

[0151] In some embodiments, as Figure 28 As shown, the semiconductor structure further includes a metal interconnection structure 60 . The metal interconnection structure 60 is disposed in the second dielectric layer 240 . The metal interconnection structure 60 penetrates the second dielectric layer 240 and is in contact with the metal layer 10 .

[0152] In some embodiments, as Figure 28 As shown, the first surface 100 a also includes the top surface of the metal interconnect structure 60 .

[0153] In some embodiments, as Figure 28 As shown, the first dielectric layer 140 has an air gap 141 , the top surface of the air gap 141 is lower than the first surface 100 a , and the air gap 141 is sealed in the first dielectric layer 140 , which can improve the insulation effect of the first dielectric layer 140 and prevent the metal layer 10 from short-circuiting.

[0154] In some embodiments, as Figure 28 As shown, the first surface 100a is a plane. The first surface 100a of the semiconductor structure of this embodiment is a flat and uniform plane. After the semiconductor structure of this embodiment is bonded to another structure, the first surface 100a is more tightly connected to the other structure, and there is no gap at the connection surface between the semiconductor structure and the other structure, so the semiconductor structure is more firmly bonded to the other structure.

[0155] According to an exemplary embodiment, Figure 29 As shown, this exemplary embodiment provides a semiconductor bonding structure. The semiconductor structure of this embodiment includes a first semiconductor structure 100 and a second semiconductor structure 200. The first semiconductor structure 100 and the second semiconductor structure 200 both adopt the semiconductor structure of the above-mentioned embodiment. Among them, the first semiconductor structure 100 can be a semiconductor chip that adopts the structure of the above-mentioned embodiment, and the second semiconductor structure 200 can be a semiconductor wafer that adopts the structure of the above-mentioned embodiment. The semiconductor bonding structure of this embodiment can be formed in a chip-on-wafer (COW) manner. Alternatively, the semiconductor structure of this embodiment can also be formed in a chip-on-chip (COC) manner or a wafer-on-wafer (WOW) manner.

[0156] like Figure 29 As shown, the first surface 110a of the first semiconductor structure 110 and the first surface 210a of the second semiconductor structure 210 are arranged opposite to each other, the first surface 110a of the first semiconductor structure 110 and the first surface 210a of the second semiconductor structure 210 are connected together, and at the connecting surface of the first semiconductor structure 110 and the second semiconductor structure 210, the metal interconnection structure 160 of the first semiconductor structure 110 and the metal interconnection structure 260 of the second semiconductor structure 210 are bonded and connected, and the passivation layer 120 of the first semiconductor structure 110 and the passivation layer 220 of the second semiconductor structure 210 are bonded and connected.

[0157] In the semiconductor bonding structure of this embodiment, there is no gap between the first surface 110 a of the first semiconductor structure 110 and the bonding surface of the second semiconductor structure 210 , thereby improving the robustness of the semiconductor bonding structure.

[0158] The various embodiments or implementation methods in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.

[0159] In the description of this specification, reference to the terms "embodiment", "exemplary embodiment", "some embodiments", "illustrative embodiment", "example", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure.

[0160] In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any suitable manner in any one or more embodiments or examples.

[0161] In the description of the present disclosure, it should be noted that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they cannot be understood as limitations on the present disclosure.

[0162] It is to be understood that the terms "first", "second", etc. used in the present disclosure can be used to describe various structures in the present disclosure, but these structures are not limited by these terms. These terms are only used to distinguish a first structure from another structure.

[0163] In one or more of the accompanying drawings, identical elements are represented by similar reference numerals. For clarity, many parts in the accompanying drawings are not drawn to scale. In addition, certain well-known parts may not be shown. For simplicity, a structure obtained after several steps may be described in a single figure. Many specific details of the present disclosure, such as device structure, materials, dimensions, processing techniques, and technologies, are described below to facilitate a clearer understanding of the present disclosure. However, as will be appreciated by those skilled in the art, the present disclosure may be practiced without following these specific details.

[0164] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: The method for manufacturing the semiconductor structure comprises: providing a metal layer; forming a passivation layer, wherein the passivation layer covers a top surface of the metal layer; forming at least one trench, wherein the trench at least penetrates the passivation layer; forming a dielectric material layer, wherein the dielectric material layer fills the trench and covers the top surface of the passivation layer; The dielectric material layer is ground with the top surface of the passivation layer as a grinding stop point, and the dielectric material layer retained by grinding forms a dielectric layer in the groove.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein: The metal layer is formed on the interlayer dielectric layer, and forming at least one trench includes: A first trench is formed, wherein the first trench penetrates the passivation layer and the metal layer, and the first trench exposes a top surface of the interlayer dielectric layer.

3. The method for manufacturing a semiconductor structure according to claim 2, wherein: The production method comprises: Depositing a dielectric material to fill the first trench and cover the top surface of the passivation layer to form a first dielectric material layer; The first dielectric material layer is ground with the top surface of the passivation layer as a grinding stop point to form a first dielectric layer. The first dielectric layer is located in the first trench and divides the metal layer into a metal circuit layer.

4. The method for manufacturing a semiconductor structure according to any one of claims 1 to 3, wherein: Forming at least one trench includes: A second trench is formed, wherein the second trench penetrates the passivation layer and exposes a top surface of the metal layer.

5. The method for manufacturing a semiconductor structure according to claim 4, wherein: The production method comprises: Depositing a dielectric material to fill the second trench and cover the top surface of the passivation layer to form a second dielectric material layer; The second dielectric material layer is ground with the top surface of the passivation layer as a grinding stop point to form a second dielectric layer in the second trench.

6. The method for manufacturing a semiconductor structure according to claim 5, wherein: The production method further comprises: removing a portion of the second dielectric layer to form a first through hole in the second dielectric layer, wherein the first through hole exposes a top surface of the metal layer; A metal interconnect structure is formed in the first through hole.

7. The method for manufacturing a semiconductor structure according to claim 6, wherein: forming a metal interconnection structure in the first through hole, comprising: forming a first metal material layer, wherein the first metal material layer fills the first through hole and covers a top surface of the passivation layer; The first metal material layer is ground with the top surface of the passivation layer as a grinding stop point, and the ground first metal material layer forms the metal interconnection structure.

8. A semiconductor structure, characterized in that The semiconductor structure comprises: Metal layer; a passivation layer, the passivation layer covering a top surface of the metal layer; at least one trench, the trench at least penetrating the passivation layer; a dielectric layer located in the trench; The semiconductor structure includes a first surface including a top surface of the dielectric layer and a top surface of the passivation layer.

9. The semiconductor structure according to claim 8, wherein: The metal layer is provided on the interlayer dielectric layer, and the semiconductor structure comprises: a first trench, penetrating the passivation layer and the metal layer; The dielectric layer includes a first dielectric layer, the first dielectric layer fills the first trench, the first dielectric layer is connected to the interlayer dielectric layer, and the first dielectric layer divides the metal layer into metal circuit layers.

10. The semiconductor structure according to claim 9, wherein: The semiconductor structure comprises: a second trench penetrating the passivation layer; The dielectric layer includes a second dielectric layer, the second dielectric layer fills the second trench, and the second dielectric layer covers a portion of the top surface of the metal layer.

11. The semiconductor structure according to claim 10, wherein: The semiconductor structure further comprises: A metal interconnection structure is provided in the second dielectric layer, and the metal interconnection structure penetrates the second dielectric layer and is in contact with and connected to the metal layer.

12. The semiconductor structure according to claim 11, wherein: The first surface also includes a top surface of the metal interconnect structure.

13. The semiconductor structure according to any one of claims 9 to 12, characterized in that: The first dielectric layer has an air gap therein, and a top surface of the air gap is lower than the first surface.

14. A semiconductor bonding structure, characterized in that: comprising a first semiconductor structure and a second semiconductor structure, wherein the first semiconductor structure and the second semiconductor structure both adopt the semiconductor structure according to any one of claims 8 to 12; The first surface of the first semiconductor structure and the first surface of the second semiconductor structure are arranged opposite to each other, the first surface of the first semiconductor structure and the first surface of the second semiconductor structure are connected together, and at the connection surface between the first semiconductor structure and the second semiconductor structure, the dielectric layer of the first semiconductor structure and the dielectric layer of the second semiconductor structure are bonded and connected, and the passivation layer of the first semiconductor structure and the passivation layer of the second semiconductor structure are bonded and connected.

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