Back contact cell with specific second semiconductor film layer and its manufacturing method and application

Abstract

The present invention belongs to the technical field of back contact batteries, and specifically relates to a back contact battery with a specific second semiconductor film layer, a manufacturing method and an application thereof, comprising a silicon wafer, a first semiconductor film layer and a second semiconductor film layer alternately arranged on the back of the silicon wafer, the first semiconductor film layer comprising a tunneling oxide layer and an N-type doped polysilicon layer, the second semiconductor film layer comprising an amorphous molybdenum oxide film layer and a crystalline molybdenum oxide film layer sequentially arranged along the back outward, the crystallization rate of the crystalline molybdenum oxide film layer is 60%-90%, the thickness ratio of the amorphous molybdenum oxide film layer and the crystalline molybdenum oxide film layer is 1:0.6-3, and the ratio of the thickness of the tunneling oxide layer to the thickness of the amorphous molybdenum oxide film layer is 1:5-30. The present invention can take into account both good passivation effect and conductive effect, thereby improving the battery conversion efficiency, and the available deposition equipment has low cost, which is conducive to large-scale promotion of production lines.

Description

Technical Field

[0001] The present invention belongs to the technical field of back contact batteries, and in particular relates to a back contact battery with a specific second semiconductor film layer, a manufacturing method and an application thereof. Background Art

[0002] At present, the back-contact battery includes various film layers arranged on the back and the front, wherein the first semiconductor film layer and the second semiconductor film layer are alternately arranged on the back of the silicon wafer. The second semiconductor film layer on the back generally includes an intrinsic amorphous or microcrystalline silicon layer and a P-type doped amorphous or microcrystalline silicon layer, and is often formed by PECVD or Hot-wire method.

[0003] However, the high cost of PECVD equipment is not conducive to large-scale promotion of production lines. The existing P-type amorphous or microcrystalline silicon layer has serious parasitic absorption, which will affect the current to a certain extent.

[0004] It should be noted that this part of the present invention only provides background technology related to the present invention and does not necessarily constitute prior art or known technology. Summary of the invention

[0005] The purpose of the present invention is to overcome the defect of the prior art that the P-type amorphous or microcrystalline silicon layer of the back-contact battery has serious parasitic absorption and affects the current, and to provide a back-contact battery with a specific second semiconductor film layer and a manufacturing method and application, which can take into account good passivation effect and conductive effect, thereby improving the battery conversion efficiency, and the available deposition equipment is low in cost, which is conducive to large-scale promotion of production lines.

[0006] In order to achieve the above-mentioned purpose, in a first aspect, the present invention provides a back-contact battery with a specific second semiconductor film layer, comprising a silicon wafer, a first semiconductor film layer and a second semiconductor film layer alternately arranged on the back side of the silicon wafer, the first semiconductor film layer comprising a tunneling oxide layer and an N-type doped polycrystalline silicon layer, the second semiconductor film layer comprising an amorphous molybdenum oxide film layer and a crystalline molybdenum oxide film layer sequentially arranged along the back side outward, the crystallization rate of the crystalline molybdenum oxide film layer is 60%-90%, the ratio of the thickness of the amorphous molybdenum oxide film layer to the crystalline molybdenum oxide film layer is 1:0.6-3, and the ratio of the thickness of the tunneling oxide layer to the thickness of the amorphous molybdenum oxide film layer is 1:5-30.

[0007] In some preferred embodiments of the present invention, the thickness of the amorphous molybdenum oxide film layer is 10-30 nm, and the thickness of the crystalline molybdenum oxide film layer is 20-30 nm.

[0008] In some preferred embodiments of the present invention, the total thickness of the amorphous molybdenum oxide film layer and the crystalline molybdenum oxide film layer is 30-60 nm.

[0009] In some preferred embodiments of the present invention, both ends of the second semiconductor film layer extend outward to cover part of the back side of the adjacent first semiconductor film layer, and a first semiconductor opening region not covering the second semiconductor film layer is opened on the back side of the first semiconductor film layer, and a second semiconductor opening region is formed between adjacent first semiconductor film layers. The second semiconductor opening region is spaced apart from the first semiconductor opening region, and the area between them is a spacer region; in the spacer region, an isolation layer is provided between the first semiconductor film layer and the second semiconductor film layer, or no isolation layer is provided.

[0010] Preferably, the thickness of the N-type doped polysilicon layer is 75-160 nm.

[0011] In some preferred embodiments of the present invention, the N-type doped polysilicon layer is thickened to a ratio of its thickness to the total thickness of the amorphous molybdenum oxide film layer and the crystalline molybdenum oxide film layer of 1.7-5:1.

[0012] In some preferred embodiments of the present invention, the thickness of the tunnel oxide layer is 1-2 nm, and the thickness of the N-type doped polysilicon layer is 100-160 nm.

[0013] In some preferred embodiments of the present invention, the back-contact battery with a specific second semiconductor film layer also includes a metal electrode and a conductive film layer laid on the outer surfaces of the first semiconductor film layer and the second semiconductor film layer, and an isolation groove is opened on the portion of the conductive film layer located in the spacing area; the metal electrode is arranged on the outer surface of the conductive film layer corresponding to the second semiconductor opening area and the first semiconductor opening area.

[0014] In some preferred embodiments of the present invention, the back-contact cell having a specific second semiconductor film layer further comprises a passivation layer and an anti-reflection layer sequentially arranged on the front side of the silicon wafer, the passivation layer is at least one of an amorphous silicon passivation layer, a silicon oxide passivation layer and an aluminum oxide passivation layer, and the anti-reflection layer is one of a silicon nitride layer, an aluminum oxide layer and a silicon oxide layer.

[0015] In a second aspect, the present invention provides a method for manufacturing a back contact battery having a specific second semiconductor film layer, comprising the following steps:

[0016] S1, provide double-sided polished silicon wafers;

[0017] S2, forming a first semiconductor film layer and an isolation layer on the back side of the silicon wafer in sequence; the first semiconductor film layer comprises a tunneling oxide layer and an N-type doped polysilicon layer, and the thickness of the N-type doped polysilicon layer is 100-160 nm;

[0018] S3, performing a first etching opening on the back surface obtained in S2 to form a second semiconductor opening region;

[0019] S4, then performing texturing cleaning, and then selecting whether to perform a step of removing the isolation layer outside the second semiconductor opening area on the back side of the silicon wafer through cleaning according to needs;

[0020] S6, depositing an amorphous molybdenum oxide film layer and a crystalline molybdenum oxide film layer in sequence on the back side by magnetron sputtering to form a second semiconductor film layer;

[0021] The deposition conditions of the amorphous molybdenum oxide film layer include: a deposition temperature of 150-200° C., a sputtering power of 500-1000W, and a ratio of the thickness of the tunneling oxide layer to the thickness of the amorphous molybdenum oxide film layer of 1:5-30;

[0022] The deposition conditions of the crystalline molybdenum oxide film layer include: a deposition temperature of 250-300° C., a sputtering power of 1000-1500W, a crystallization rate of the crystalline molybdenum oxide film layer of 60%-90%; and a thickness ratio of the amorphous molybdenum oxide film layer to the crystalline molybdenum oxide film layer of 1:0.6-3;

[0023] S7. Use laser to perform a second etching opening on part of the second semiconductor film layer on the back of the silicon wafer to form a first semiconductor opening area spaced apart from the second semiconductor opening area; control the laser power to be 35-50kW.

[0024] In some preferred embodiments of the present invention, a physical vapor deposition technique is used to perform magnetron sputtering on a molybdenum oxide target to sequentially deposit an amorphous molybdenum oxide film layer and a crystalline molybdenum oxide film layer.

[0025] In some preferred embodiments of the present invention, the conditions for depositing the amorphous molybdenum oxide film layer and the crystalline molybdenum oxide film layer independently include: the sputtering power is 500W-1500W, the working gas comprises an argon-oxygen mixture and the volume content of oxygen in the argon-oxygen mixture is 2%-20%, and the working voltage is 150-300V.

[0026] In some preferred embodiments of the present invention, the sputtering power of the crystalline molybdenum oxide film layer is greater than the sputtering power of the amorphous molybdenum oxide film layer, and / or the N-type doped polysilicon layer in S2 is thickened to a thickness that is in a ratio of 1.7-5:1 to the total thickness of the amorphous molybdenum oxide film layer and the crystalline molybdenum oxide film layer.

[0027] In some preferred embodiments of the present invention, the method for manufacturing a back contact battery having a specific second semiconductor film layer further comprises:

[0028] S5, forming a passivation layer and an anti-reflection layer in sequence on the front side of the silicon wafer after the texturing and cleaning in S4, and then proceeding to S6;

[0029] S8, depositing a conductive film layer on the back surface obtained in S7;

[0030] S9, performing a third etching opening on a portion of the conductive film layer between the first semiconductor opening region and the second semiconductor opening region to form an isolation groove;

[0031] S10, forming metal electrodes on the outer surfaces of the corresponding conductive film layers in the areas where the first semiconductor opening region and the second semiconductor opening region are located.

[0032] In a third aspect, the present invention provides a back-contact battery having a specific second semiconductor film layer, which is manufactured by the method for manufacturing a back-contact battery having a specific second semiconductor film layer described in the second aspect.

[0033] In a fourth aspect, the present invention provides a photovoltaic module, which includes the back-contact cell with a specific second semiconductor film layer as described in the first aspect, or includes the back-contact cell with a specific second semiconductor film layer as described in the third aspect.

[0034] Beneficial effects:

[0035] The present invention adopts the above technical scheme, especially adopts amorphous molybdenum oxide film layer and crystalline molybdenum oxide film layer as the second semiconductor film layer, replacing the traditional amorphous or microcrystalline silicon film layer. Since molybdenum oxide is a semiconductor material with a wide band gap, it can increase the light flux, which is conducive to exciting more hole carriers, and is conducive to improving the utilization rate of light and current density. The combination of amorphous molybdenum oxide film layer and crystalline molybdenum oxide film layer is specifically adopted to mainly play the dual synergistic role of passivation interface and hole carrier transmission and conduction. Controlling the crystallization rate of the crystalline molybdenum oxide film layer in an appropriate range is conducive to improving the conductivity at a higher level. With the appropriate thickness ratio and the thickness ratio with the tunneling oxide layer, it can take into account the good passivation effect and the conductive effect, thereby improving the battery conversion efficiency; and the available deposition equipment cost of molybdenum oxide is low, which is conducive to large-scale promotion of production lines. Under the same conditions, if any layer of the amorphous molybdenum oxide film layer and the crystalline molybdenum oxide film layer is not set, the good passivation effect and the conductive effect cannot be taken into account, and the battery conversion efficiency is poor.

[0036] The second semiconductor film layer of the special molybdenum oxide combination of the present invention cooperates with a specific tunneling oxide layer and an N-type doped polysilicon layer as the first semiconductor film layer. The polycrystalline film layer has good compactness, which can prevent PVD sputtering damage of the deposited second semiconductor molybdenum oxide layer, ensure the passivation effect of the battery, and can take into account the passivation effect, optical performance and conductive performance of the film layer, avoid damage to the film layer during the process, and help improve the battery conversion efficiency; the thickness of the tunneling oxide layer and the thickness of the amorphous molybdenum oxide film layer are controlled to be appropriate, which can maximize the passivation effect of the battery and help improve the overall open circuit voltage of the battery. If under the same conditions, conventional intrinsic amorphous silicon and N-type amorphous silicon are used as the first semiconductor film layer, because intrinsic amorphous silicon and N-type amorphous silicon are not resistant to laser thermal damage, solution corrosion, and film damage, it is not conducive to the process and the passivation effect is poor.

[0037] In a preferred embodiment of the present invention, in a battery structure with a specific second semiconductor opening region and a first semiconductor opening region, the thickness of the N-type doped polysilicon layer is controlled to be within a suitable ratio to the total thickness of the amorphous molybdenum oxide film layer and the crystalline molybdenum oxide film layer. This can effectively prevent the possibility of local damage to the top layer of the first semiconductor film layer due to the removal of the molybdenum oxide film layer due to its wider band gap and better transmittance during the manufacturing process of the corresponding first semiconductor opening region.

[0038] In the manufacturing method of the present invention, magnetron sputtering is used to control the appropriate conditions for deposition to obtain a specific amorphous molybdenum oxide film layer and a crystalline molybdenum oxide film layer as the second semiconductor film layer, replacing conventional PECVD equipment, which is beneficial to reducing the equipment cost of the battery; and the N-type doped polysilicon layer is thickened at a higher thickness level (10%-20% thicker than the existing process thickness). When the second etching opening is used to remove the molybdenum oxide second semiconductor film layer, the laser power is at a lower level (20%-40% lower than the existing process power). This can compensate for the possibility that the top layer of the first semiconductor film layer may be locally damaged due to the wider band gap and better transmittance of the molybdenum oxide film layer, thereby minimizing the impact on the function of the first semiconductor film layer.

[0039] In a further preferred production method, the present invention uses physical vapor deposition technology to perform magnetron sputtering on the molybdenum oxide target to sequentially deposit an amorphous molybdenum oxide film layer and a crystalline molybdenum oxide film layer. Compared with the chemical deposition method (chemical deposition involves more chemical raw materials), the physical deposition method of the present invention is simple and efficient, with low equipment cost, and is more conducive to improving the uniformity of the corresponding film layer deposited on the silicon wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0041] Figure 1 It is a schematic structural diagram of a specific embodiment of the back contact battery of the present invention.

[0042] Description of Reference Numerals

[0043] Silicon wafer 1, tunneling silicon oxide layer 2, N-type doped polysilicon layer 3, passivation layer 5, silicon oxide passivation layer 5.1, aluminum oxide passivation layer 5.2, anti-reflection layer 6, amorphous molybdenum oxide film layer 7, crystalline molybdenum oxide film layer 8, transparent conductive film layer 9, metal electrode 10, second semiconductor opening area W1, first semiconductor opening area W2, isolation groove W3. DETAILED DESCRIPTION

[0044] In the present invention, unless otherwise specified, directional words such as "upper, lower, left, right" are generally understood in conjunction with the directions shown in the drawings and actual applications.

[0045] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0046] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0047] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of each range, the endpoint values ​​of each range and the individual point values, and the individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed in this article. Among them, the terms "optional" and "optional" all mean that they may be included or not included (or may be present or not).

[0048] In the present invention, the area close to the silicon wafer is referred to as the inside, and the area far from the silicon wafer is referred to as the outside.

[0049] In the first aspect, the present invention provides a back-contact battery with a specific second semiconductor film layer, comprising a silicon wafer, a first semiconductor film layer and a second semiconductor film layer alternately arranged on the back side of the silicon wafer, the first semiconductor film layer comprising a tunneling oxide layer and an N-type doped polysilicon layer, the second semiconductor film layer comprising an amorphous molybdenum oxide film layer and a crystalline molybdenum oxide film layer sequentially arranged along the back side outward, the crystallization rate of the crystalline molybdenum oxide film layer is 60%-90%, the ratio of the thickness of the amorphous molybdenum oxide film layer to the crystalline molybdenum oxide film layer is 1:0.6-3, and the ratio of the thickness of the tunneling oxide layer to the thickness of the amorphous molybdenum oxide film layer is 1:5-30, preferably 1:7.5-30.0, and further preferably 1:7.5-20.0.

[0050] In the present invention, the crystallinity ratio is obtained by Raman spectroscopy testing.

[0051] The amorphous molybdenum oxide film layer of the present invention is beneficial to improving the passivation level of the film layer, and the crystalline molybdenum oxide film layer is beneficial to improving the conductivity of the film layer and the carrier transmission capacity. Combined with a suitable crystallization rate and a suitable thickness ratio with the key film layer, it is beneficial to take into account both the passivation effect and the conductive effect, thereby improving the battery conversion efficiency.

[0052] The thickness ratio of the amorphous molybdenum oxide film layer and the crystalline molybdenum oxide film layer is 1:0.6-3. For example, it can be 1:0.6, 1:0.8, 1:1, 1:1.1, 1:1.2, 1:1.5, 1:1.8, 1:2.0, 1:2.3, 1:2.5, 1:2.6, 1:2.7, 1:3, etc., as well as the range between any two point values, for example, it can be preferably 1:1.1-2.5, and further preferably 1:1.1-2.2.

[0053] In some preferred embodiments of the present invention, the thickness of the amorphous molybdenum oxide film layer is 10-30 nm, and the thickness of the crystalline molybdenum oxide film layer is 20-30 nm. Using amorphous molybdenum oxide film layers and crystalline molybdenum oxide film layers in a suitable thickness range is more conducive to taking into account both the passivation effect and the conductive performance.

[0054] The thickness of the amorphous molybdenum oxide film layer is 10-30 nm, for example, it can be 10 nm, 12 nm, 15 nm, 17 nm, 20 nm, 23 nm, 25 nm, 28 nm, 29 nm, 30 nm, etc., and the range between any two point values.

[0055] The thickness of the crystalline molybdenum oxide film layer is 20-30 nm, for example, it can be 20 nm, 21 nm, 22 nm, 23 nm, 24 nm, 25 nm, 26 nm, 27 nm, 28 nm, 29 nm, 30 nm, etc., and the range between any two point values.

[0056] The crystallization rate of the crystalline molybdenum oxide film layer is 60%-90%, and specifically can be 60%, 65%, 70%, 75%, 80%, 85%, 90%, etc. and the range between any two point values, for example, preferably 70%-90%.

[0057] In some preferred embodiments of the present invention, the total thickness of the amorphous molybdenum oxide film layer and the crystalline molybdenum oxide film layer is 30-60 nm, preferably 42-60 nm. Controlling the total thickness of the amorphous molybdenum oxide film layer and the crystalline molybdenum oxide film layer within a suitable range is more conducive to reducing parasitic absorption of the film layer and improving optical performance.

[0058] In some preferred embodiments of the present invention, the two ends of the second semiconductor film layer extend outward to cover the back side of the adjacent first semiconductor film layer, and a first semiconductor opening region that does not cover the second semiconductor film layer is opened on the back side of the first semiconductor film layer, and a second semiconductor opening region is formed between adjacent first semiconductor film layers, and the second semiconductor opening region is arranged at intervals from the first semiconductor opening region, and the area between them is a spacing region. Two semiconductor film layers are stacked in the spacing region to form a stack.

[0059] Further preferably, in the spacing region, an isolation layer is disposed between the first semiconductor film layer and the second semiconductor film layer, or no isolation layer is disposed.

[0060] Preferably, in the present invention, the thickness of the N-type doped polysilicon layer is 75-160 nm.

[0061] In some preferred embodiments of the present invention, in the battery structure with the spacer region and the second semiconductor opening region and the first semiconductor opening region, the N-type doped polysilicon layer is thickened to a ratio of its thickness to the total thickness of the amorphous molybdenum oxide film layer and the crystalline molybdenum oxide film layer of 1.7-5:1, preferably 3.0-5.0:1, further preferably 3.0-4.0:1, further preferably 3.0-3.5:1. The use of the preferred thickness ratio of the N-type doped polysilicon layer to the amorphous molybdenum oxide film layer and the crystalline molybdenum oxide film layer can effectively prevent the possibility of local damage to the top layer of the first semiconductor film layer when the molybdenum oxide film layer is removed due to its wide band gap and good transmittance during the production process of the corresponding first semiconductor opening region, avoid excessive damage to the first semiconductor film layer, and be more conducive to ensuring that the passivation effect of the first semiconductor film layer is not affected.

[0062] Preferably, the thickness of the N-type doped polysilicon layer is 100-160 nm, and specifically can be, for example, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, 160 nm, etc., and a range between any two point values.

[0063] The present invention has no limitation on the effective doping concentration of the N-type doped polysilicon layer, and can be selected within the range of the prior art, for example, it can be greater than 5e18cm -3 .

[0064] In some preferred embodiments of the present invention, the thickness of the tunnel oxide layer is 1-2 nm.

[0065] In some preferred embodiments of the present invention, the back contact battery with a specific second semiconductor film layer further includes a metal electrode and a conductive film layer laid on the outer surfaces of the first semiconductor film layer and the second semiconductor film layer, and an isolation groove is provided on the portion of the conductive film layer located in the spacing area; the metal electrode is arranged on the outer surface of the conductive film layer corresponding to each of the second semiconductor opening area and the first semiconductor opening area. In the present invention, the types and thicknesses of the conductive film layer and the metal electrode can be made with reference to the prior art, and can be used in the present invention, and will not be repeated here.

[0066] Preferably, the width of the second semiconductor opening region is 400-600 μm, the width of the first semiconductor opening region is 150-300 μm, and the width of the isolation trench is 20-100 μm.

[0067] In some preferred embodiments of the present invention, the back-contact cell having a specific second semiconductor film layer further comprises a passivation layer and an anti-reflection layer sequentially arranged on the front side of the silicon wafer.

[0068] Preferably, the passivation layer is at least one of an amorphous silicon passivation layer, a silicon oxide passivation layer and an aluminum oxide passivation layer.

[0069] Further preferably, the passivation layer is a combination of a silicon oxide passivation layer and an aluminum oxide passivation layer disposed in sequence. More preferably, the thickness of the silicon oxide passivation layer is 1-2 nm, and the thickness of the aluminum oxide passivation layer is 3-4 nm. The use of this specific combination of passivation layers is more conducive to improving the passivation effect of the front side and reducing the parasitic absorption of the film layer.

[0070] Preferably, the anti-reflection layer is one of a silicon nitride layer, an aluminum oxide layer and a silicon oxide layer.

[0071] Further preferably, the anti-reflection layer is a combination of a silicon nitride layer and a silicon oxide layer disposed in sequence. More preferably, the thickness of the silicon nitride layer is 50-100 nm, and the thickness of the silicon oxide layer is 80-150 nm. The use of this specific combination of anti-reflection layers is more conducive to improving the current density of the battery.

[0072] In a second aspect, the present invention provides a method for manufacturing a back contact battery having a specific second semiconductor film layer, comprising the following steps:

[0073] S1, provide double-sided polished silicon wafers;

[0074] S2, forming a first semiconductor film layer and an isolation layer on the back side of the silicon wafer in sequence; the first semiconductor film layer comprises a tunneling oxide layer and an N-type doped polysilicon layer, and the thickness of the N-type doped polysilicon layer is 100-160 nm;

[0075] S3, performing a first etching opening on the back surface obtained in S2 to form a second semiconductor opening region;

[0076] S4, then performing texturing cleaning, and then selecting whether to perform a step of removing the isolation layer outside the second semiconductor opening area on the back side of the silicon wafer through cleaning according to needs;

[0077] S6, depositing an amorphous molybdenum oxide film layer and a crystalline molybdenum oxide film layer in sequence on the back side by magnetron sputtering to form a second semiconductor film layer;

[0078] S7, using laser to perform a second etching opening on a portion of the second semiconductor film layer on the back of the silicon wafer to form a first semiconductor opening region spaced apart from the second semiconductor opening region; the laser power is controlled to be 35-50kW. The laser in S7 is used until a portion of the second semiconductor film layer is removed to form the first semiconductor opening region.

[0079] The deposition conditions of the amorphous molybdenum oxide film layer include: a deposition temperature of 150-200°C, a sputtering power of 500-1000W, and a ratio of the thickness of the tunneling oxide layer to the thickness of the amorphous molybdenum oxide film layer of 1:5-30; the deposition conditions of the crystalline molybdenum oxide film layer include: a deposition temperature of 250-300°C, a sputtering power of 1000-1500W, preferably 1100-1500W, a crystallization rate of the crystalline molybdenum oxide film layer of 60%-90%; and a ratio of the thickness of the amorphous molybdenum oxide film layer to the crystalline molybdenum oxide film layer of 1:0.6-3. The present invention adopts the control of the deposition temperature and the sputtering power to obtain the amorphous molybdenum oxide film layer and the crystalline molybdenum oxide film layer.

[0080] In some preferred embodiments of the present invention, physical vapor deposition technology is used to perform magnetron sputtering on a molybdenum oxide target to sequentially deposit an amorphous molybdenum oxide film layer and a crystalline molybdenum oxide film layer; compared with chemical deposition technology, it is more conducive to reducing costs while improving the uniformity of film deposition.

[0081] Preferably, the purity of the molybdenum oxide target is ≥99.95%.

[0082] In some preferred embodiments of the present invention, the conditions for depositing the amorphous molybdenum oxide film layer and the crystalline molybdenum oxide film layer independently include: the sputtering power is 500W-1500W, the working gas contains an argon-oxygen mixture, and the working voltage is 150-300V.

[0083] Preferably, the volume content of oxygen in the argon-oxygen mixed gas is 2%-20%. Using an appropriate oxygen content is more conducive to controlling the band gap width of the corresponding film layer and improving the oxygen doping amount and transmittance of the corresponding film layer.

[0084] Preferably, the flow rate of the argon-oxygen mixed gas is 500-3000 sccm.

[0085] In some preferred embodiments of the present invention, the sputtering power of the crystalline molybdenum oxide film layer is greater than the sputtering power of the amorphous molybdenum oxide film layer, which is more conducive to improving the density of the film layer growth and improving the crystallization rate of the film layer.

[0086] In some preferred embodiments of the present invention, the N-type doped polysilicon layer in S2 is thickened to a thickness whose ratio to the total thickness of the amorphous molybdenum oxide film layer and the crystalline molybdenum oxide film layer is 1.7-5:1.

[0087] Preferably, in the present invention, the first etching opening can be performed by laser or mask etching. The specific conditions can be referred to those in the prior art, which can be used in the present invention and will not be described in detail here.

[0088] The texturing cleaning in S4 of the present invention is used to remove the residual isolation layer and the first semiconductor layer in the second semiconductor opening area, and at the same time form a texturing surface on the front side of the silicon wafer and the second semiconductor opening area.

[0089] In some preferred embodiments of the present invention, the method for manufacturing a back-contact battery having a specific second semiconductor film layer further includes: S5, sequentially forming a passivation layer and an anti-reflection layer on the front side of the silicon wafer after texturing and cleaning in S4, and then performing S6.

[0090] In some preferred embodiments of the present invention, the method for manufacturing a back-contact battery having a specific second semiconductor film layer further comprises: S8, depositing a conductive film layer on the back side obtained in S7.

[0091] In some preferred embodiments of the present invention, the method for manufacturing a back-contact battery having a specific second semiconductor film layer further includes: S9, performing a third etching opening on a portion of the conductive film layer between the first semiconductor opening region and the second semiconductor opening region to form an isolation groove.

[0092] In some preferred embodiments of the present invention, the method for manufacturing a back-contact battery having a specific second semiconductor film layer further includes: S10, forming metal electrodes on the outer surfaces of the corresponding conductive film layers in the areas where the first semiconductor opening region and the second semiconductor opening region are located.

[0093] In a third aspect, the present invention provides a back-contact battery having a specific second semiconductor film layer, which is manufactured by the method for manufacturing a back-contact battery having a specific second semiconductor film layer described in the second aspect.

[0094] In a fourth aspect, the present invention provides a photovoltaic module, which includes the back-contact cell with a specific second semiconductor film layer as described in the first aspect, or includes the back-contact cell with a specific second semiconductor film layer as described in the third aspect.

[0095] The embodiments of the present invention are described in detail below, which are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0096] Example 1

[0097] A back contact battery, such as Figure 1 As shown, it is prepared by the following preparation method:

[0098] S1, N-type single crystal silicon wafer 1 double-sided polishing;

[0099] S2, forming a first semiconductor film layer and an isolation layer on the back side of the silicon wafer 1;

[0100] The first semiconductor film layer includes a tunneling silicon oxide layer 2 and an N-type doped polysilicon layer 3. The isolation layer is silicon nitride. The thickness of the tunneling silicon oxide layer 2 is 1.5 nm, the thickness of the N-type doped polysilicon layer 3 is 150 nm, and the effective doping concentration is 3e20 cm -3 , the thickness of the isolation layer is 60nm.

[0101] S3, using laser to etch a first opening on the back side of the silicon wafer 1 to form a second semiconductor opening region W1; the width of the formed second semiconductor opening region W1 is 500 μm;

[0102] S4, texturing and cleaning the front and back sides of the silicon wafer 1;

[0103] S5, forming a passivation layer 5 and an anti-reflection layer 6 in sequence on the front side of the silicon wafer 1;

[0104] The passivation layer 5 is a combination of a silicon oxide passivation layer 5.1 and an aluminum oxide passivation layer 5.2. The thickness of the silicon oxide passivation layer 5.1 is 2 nm, and the thickness of the aluminum oxide passivation layer 5.2 is 3 nm.

[0105] The anti-reflection layer 6 is a combination of a silicon nitride layer and a silicon oxide layer. The thickness of the silicon nitride layer is 70 nm, and the thickness of the silicon oxide layer is 100 nm.

[0106] S6, forming a second semiconductor film layer on the back side;

[0107] The second semiconductor film layer comprises an amorphous molybdenum oxide film layer 7 and a crystalline molybdenum oxide film layer 8. Each molybdenum oxide film layer is deposited on the back side by using physical vapor deposition technology (PVD). Specifically, magnetron sputtering is performed on a molybdenum oxide target (purity ≥ 99.95%), the working gas is an argon-oxygen mixed gas, the volume content of oxygen in the argon-oxygen mixed gas is 10%, the flow rate of the argon-oxygen mixed gas is 2100sccm, and the working voltage is 200V.

[0108] The deposition temperature of the amorphous molybdenum oxide film layer 7 is 160° C., the sputtering power is 600 W, and the film thickness is 20 nm.

[0109] The deposition temperature of the crystalline molybdenum oxide film layer 8 is 270°C, the sputtering power is 1200W, the film thickness is 25nm, and the crystallization rate is 85%.

[0110] S7, using laser to etch a second opening on the back of silicon wafer 1 to form a first semiconductor opening area W2; the width of the formed first semiconductor opening area W2 is 200 μm. The power of the laser used is 40 kW. Molybdenum oxide is used as the second semiconductor film layer, which is a wide bandgap semiconductor material. The laser power is lower than that of the existing process to avoid excessive damage to the first semiconductor film layer.

[0111] S8, depositing a transparent conductive film layer 9 on the back side;

[0112] S9, a third etching opening is performed on the back side of the silicon wafer to form an isolation groove W3; the width of the isolation groove W3 is 90 μm, and the resistance between the first semiconductor and the second semiconductor after etching is greater than 1 kΩ.

[0113] S10 , forming metal electrodes 10 on the outer surfaces of the first semiconductor opening region W2 and the second semiconductor opening region W1 at the back side in corresponding regions.

[0114] Example 2

[0115] The method of Example 1 is referred to, except that the thickness of the amorphous molybdenum oxide film layer is adjusted to 10 nm, and the ratio of the thickness of the tunneling oxide layer to the thickness of the amorphous molybdenum oxide film layer is calculated to be 1:6.7. To meet the thickness adjustment, the preparation parameters of the corresponding film layer need to be adaptively adjusted to shorten the deposition time of the amorphous molybdenum oxide film layer by 48%.

[0116] Example 3

[0117] The method of Example 1 is referred to, except that the thickness of the crystalline molybdenum oxide film layer is adjusted to 20 nm, the crystallization rate remains unchanged, and the thickness ratio of the amorphous molybdenum oxide film layer to the crystalline molybdenum oxide film layer is calculated to be 1:1. To meet the thickness adjustment, the preparation parameters of the corresponding film layer need to be adaptively adjusted to shorten the deposition time of the crystalline molybdenum oxide film layer by 24%.

[0118] According to calculation, the total thickness of the amorphous molybdenum oxide film layer and the crystalline molybdenum oxide film layer is 40 nm, and the ratio of the thickness of the N-type doped polysilicon layer to the total thickness of the amorphous molybdenum oxide film layer and the crystalline molybdenum oxide film layer is 3.75:1.

[0119] Example 4

[0120] The method of Example 1 is referred to, except that the crystallization rate of the crystalline molybdenum oxide film layer is adjusted to 65% and the thickness remains unchanged. In order to meet the crystallization rate adjustment, the preparation parameters of the corresponding film layer need to be adaptively adjusted to reduce the sputtering power by 20%.

[0121] Example 5

[0122] The method of Example 1 is followed, except that the thickness of the N-type doped polysilicon layer is adjusted to 125 nm, so that the ratio of the thickness of the N-type doped polysilicon layer to the total thickness of the amorphous molybdenum oxide film layer and the crystalline molybdenum oxide film layer is 2.8:1.

[0123] Example 6

[0124] The method of Example 1 is followed, except that the thickness of the N-type doped polysilicon layer is adjusted to 76 nm, so that the ratio of the thickness of the N-type doped polysilicon layer to the total thickness of the amorphous molybdenum oxide film layer and the crystalline molybdenum oxide film layer is 1.69:1.

[0125] Comparative Example 1

[0126] The method of Example 1 is followed, except that the second semiconductor film layer is a conventional intrinsic amorphous silicon layer (10 nm thick) and a P-type doped amorphous silicon layer (15 nm thick, with an effective doping concentration of 1e19 cm -3 ), that is, no amorphous molybdenum oxide film layer and no crystalline molybdenum oxide film layer are deposited.

[0127] Comparative Example 2

[0128] The method of Example 1 is referred to, except that an amorphous molybdenum oxide film layer is not deposited, and only a crystalline molybdenum oxide film layer is deposited.

[0129] Comparative Example 3

[0130] The method of Example 1 is referred to, except that no crystalline molybdenum oxide film layer is deposited, and only an amorphous molybdenum oxide film layer is deposited.

[0131] Comparative Example 4

[0132] The method of Example 1 is referred to, except that the thickness of the crystalline molybdenum oxide film layer is adjusted to 5 nm, the crystallization rate remains unchanged, so that the thickness ratio of the amorphous molybdenum oxide film layer to the crystalline molybdenum oxide film layer is 1:0.25. To meet the thickness adjustment, the preparation parameters of the corresponding film layer need to be adaptively adjusted to shorten the deposition time of the crystalline molybdenum oxide film layer by 76%.

[0133] According to calculation, the total thickness of the amorphous molybdenum oxide film layer and the crystalline molybdenum oxide film layer is 25 nm, and the ratio of the thickness of the N-type doped polysilicon layer to the total thickness of the amorphous molybdenum oxide film layer and the crystalline molybdenum oxide film layer is 6:1.

[0134] Test Case

[0135] The back contact cells obtained in the above-mentioned embodiments and comparative examples were subjected to performance tests, and the results are shown in Table 1. The performance indicators of each embodiment and comparative example were converted using embodiment 1 as a reference benchmark, the data of embodiment 1 was normalized benchmark 1, and other examples were converted based on embodiment 1, such as the battery cost of comparative example 1 / battery cost of embodiment 1 was 1.15.

[0136] Table 1

[0137]

[0138] It can be seen from the above results that, compared with the comparative example, the embodiment scheme of the present invention can achieve both good passivation effect and conductive effect at a lower battery cost, thereby improving the battery conversion efficiency, and the available deposition equipment cost is low, which is conducive to large-scale promotion of production lines.

[0139] Furthermore, according to Example 1 and Examples 2-6, it can be seen that the preferred battery structure of the present invention is more conducive to improving the passivation effect and the conductive effect, thereby further improving the battery conversion efficiency.

[0140] The preferred embodiments of the present invention are described in detail above, but the present invention is not limited thereto. Within the technical concept of the present invention, the technical solution of the present invention can be subjected to a variety of simple modifications, including the combination of various technical features in any other suitable manner, and these simple modifications and combinations should also be regarded as the contents disclosed by the present invention and belong to the protection scope of the present invention.

Claims

1. A back-contact battery with a specific second semiconductor film layer, comprising a silicon wafer, a first semiconductor film layer and a second semiconductor film layer alternately arranged on the back of the silicon wafer, a metal electrode, and a conductive film layer laid on the outer surfaces of the first semiconductor film layer and the second semiconductor film layer; the first semiconductor film layer comprises a tunneling oxide layer and an N-type doped polysilicon layer, the two ends of the second semiconductor film layer respectively extend outward to the outside of the partial back surface covering the adjacent first semiconductor film layer, and a first semiconductor opening area not covering the second semiconductor film layer is opened on the back of the first semiconductor film layer, a second semiconductor opening area is formed between adjacent first semiconductor film layers, the second semiconductor opening area is arranged at intervals from the first semiconductor opening area, and the area between them is a spacing area; an isolation groove is opened on the portion of the conductive film layer located in the spacing area; the metal electrode is arranged on the outer surfaces of the conductive film layers corresponding to the second semiconductor opening area and the first semiconductor opening area; characterized in that The second semiconductor film layer comprises an amorphous molybdenum oxide film layer and a crystalline molybdenum oxide film layer which are sequentially arranged along the back side outward, and the amorphous molybdenum oxide film layer contacts the back side of the silicon wafer; the total thickness of the amorphous molybdenum oxide film layer and the crystalline molybdenum oxide film layer is 42-60nm, the crystallization rate of the crystalline molybdenum oxide film layer is 60%-90%, the thickness ratio of the amorphous molybdenum oxide film layer and the crystalline molybdenum oxide film layer is 1:0.6-3, and the ratio of the thickness of the tunneling oxide layer to the thickness of the amorphous molybdenum oxide film layer is 1:5-30, the thickness of the tunneling oxide layer is 1-2nm, the N-type doped polycrystalline silicon layer is thickened to a ratio of its thickness to the total thickness of the amorphous molybdenum oxide film layer and the crystalline molybdenum oxide film layer is 1.7-5:1, and the thickness of the N-type doped polycrystalline silicon layer is 100-160nm.

2. The back contact cell with a specific second semiconductor film layer according to claim 1, characterized in that: The thickness of the amorphous molybdenum oxide film layer is 10-30 nm, and the thickness of the crystalline molybdenum oxide film layer is 20-30 nm.

3. The back contact cell with a specific second semiconductor film layer according to claim 1, characterized in that: In the spacing region, an isolation layer is disposed between the first semiconductor film layer and the second semiconductor film layer, or no isolation layer is disposed.

4. The back contact cell with a specific second semiconductor film layer according to claim 1 or 3, characterized in that: The back-contact cell with a specific second semiconductor film layer also includes a passivation layer and an anti-reflection layer sequentially arranged on the front side of the silicon wafer, the passivation layer is at least one of an amorphous silicon passivation layer, a silicon oxide passivation layer and an aluminum oxide passivation layer, and the anti-reflection layer is one of a silicon nitride layer, an aluminum oxide layer and a silicon oxide layer.

5. A method for manufacturing a back contact battery having a specific second semiconductor film layer, characterized in that: The steps include: S1, provide double-sided polished silicon wafers; S2, forming a first semiconductor film layer and an isolation layer on the back side of the silicon wafer in sequence; the first semiconductor film layer comprises a tunneling oxide layer and an N-type doped polysilicon layer, and the thickness of the N-type doped polysilicon layer is 100-160 nm; S3, performing a first etching opening on the back surface obtained in S2 to form a second semiconductor opening region; S4, then performing texturing cleaning, and then selecting whether to perform a step of removing the isolation layer outside the second semiconductor opening area on the back side of the silicon wafer through cleaning according to needs; S6, depositing an amorphous molybdenum oxide film layer and a crystalline molybdenum oxide film layer in sequence on the back side by magnetron sputtering to form a second semiconductor film layer; The deposition conditions of the amorphous molybdenum oxide film layer include: a deposition temperature of 150-200° C., a sputtering power of 500-1000W, and a ratio of the thickness of the tunneling oxide layer to the thickness of the amorphous molybdenum oxide film layer of 1:5-30; The deposition conditions of the crystalline molybdenum oxide film layer include: a deposition temperature of 250-300° C., a sputtering power of 1000-1500W, a crystallization rate of the crystalline molybdenum oxide film layer of 60%-90%; and a thickness ratio of the amorphous molybdenum oxide film layer to the crystalline molybdenum oxide film layer of 1:0.6-3; S7. Use laser to perform a second etching opening on part of the second semiconductor film layer on the back of the silicon wafer to form a first semiconductor opening area spaced apart from the second semiconductor opening area; control the laser power to be 35-50kW.

6. The method for manufacturing a back contact battery having a specific second semiconductor film layer according to claim 5, characterized in that: Physical vapor deposition technology is used to perform magnetron sputtering on a molybdenum oxide target to deposit an amorphous molybdenum oxide film layer and a crystalline molybdenum oxide film layer in sequence.

7. The method for manufacturing a back contact battery having a specific second semiconductor film layer according to claim 5, characterized in that: The conditions for depositing the amorphous molybdenum oxide film layer and the crystalline molybdenum oxide film layer independently include: the sputtering power is 500W-1500W, the working gas contains an argon-oxygen mixture and the volume content of oxygen in the argon-oxygen mixture is 2%-20%, and the working voltage is 150-300V.

8. The method for manufacturing a back contact battery having a specific second semiconductor film layer according to any one of claims 5 to 7, characterized in that: The sputtering power of the crystalline molybdenum oxide film layer is greater than the sputtering power of the amorphous molybdenum oxide film layer.

9. The method for manufacturing a back contact battery having a specific second semiconductor film layer according to any one of claims 5 to 7, characterized in that: The N-type doped polysilicon layer in S2 is thickened to a thickness that is in a ratio of 1.7-5:1 to the total thickness of the amorphous molybdenum oxide film layer and the crystalline molybdenum oxide film layer.

10. The method for manufacturing a back contact battery having a specific second semiconductor film layer according to claim 5, characterized in that: The method for manufacturing the back contact battery having the specific second semiconductor film layer further includes: S5, forming a passivation layer and an anti-reflection layer in sequence on the front side of the silicon wafer after the texturing and cleaning in S4, and then proceeding to S6; S8, depositing a conductive film layer on the back surface obtained in S7; S9, performing a third etching opening on a portion of the conductive film layer between the first semiconductor opening region and the second semiconductor opening region to form an isolation groove; S10, forming metal electrodes on the outer surfaces of the corresponding conductive film layers in the areas where the first semiconductor opening region and the second semiconductor opening region are located.

11. A back contact battery having a specific second semiconductor film layer, characterized in that: The battery is manufactured by the method for manufacturing a back-contact battery having a specific second semiconductor film layer as claimed in any one of claims 5 to 10.

12. A photovoltaic module, characterized in that: It comprises the back-contact battery having a specific second semiconductor film layer as claimed in any one of claims 1 to 4, or comprises the back-contact battery having a specific second semiconductor film layer as claimed in claim 11.

Images