A power amplifier based on broadband predistortion

Abstract

This invention relates to the field of power amplifier technology, specifically providing a power amplifier based on broadband predistortion, comprising: an input matching module, the input terminal of which is coupled to an RF input; a broadband predistortion module, the input terminal of which is connected to the output terminal of the input matching module; a power amplification module, the input terminal of which is coupled to the output terminal of the broadband predistortion module; and an output matching module, the input terminal of which is coupled to the output terminal of the power amplification module, and the output terminal of which is coupled to an RF output. By adding a broadband predistortion circuit, the capacitive load of the power amplifier cancels out the inductive load of the main power amplifier. The opposite phase response effectively reduces the IMD3 distortion generated by the main power amplifier, improving the linearity and bandwidth of the circuit. Furthermore, by introducing a parallel feedback unit, the parallel resistor R3 can further broaden the bandwidth.

Description

Technical Field

[0001] This invention relates to the field of power amplifier technology, and more specifically to a power amplifier based on broadband predistortion. Background Technology

[0002] Modern communication systems focus on achieving higher data rates at flexible frequencies while maintaining high efficiency without sacrificing the stringent linearity requirements of communication protocols; examples include LTE and NB-IoT. Therefore, power amplifiers (PAs) have received significant attention for bandwidth enhancement, as well as efficiency, linearity, and output power performance.

[0003] Power amplifiers (PAs) have been widely explored due to their cost-effectiveness and system-on-chip (SoC) integration with transceivers. However, CMOS PAs have various drawbacks that make them difficult to achieve SoC goals. CMOS PAs need to overcome limitations inherent in CMOS technology, such as low transconductance, low breakdown voltage, high parasitic capacitance, and high-loss silicon substrates. Due to these limitations of CMOS processes, designing broadband, high-efficiency, and high-linearity CMOS PAs is more difficult than designing traditional narrowband CMOS PAs.

[0004] Currently popular broadband, high-efficiency and high-linearity power amplifier circuit designs include: (1) dual-mode power amplifier based on peak-to-average power ratio, (2) power amplifier circuit based on Class G Doherty architecture, and (3) digital predistortion power amplifier circuit.

[0005] (1) For dual-mode power amplifiers, the linearity and efficiency performance at a single frequency are significantly improved. When the operating frequency shifts from the center frequency, the linearity and efficiency performance of the power amplifier drops sharply, posing a significant challenge to broadband design.

[0006] (2) For the power amplifier circuit of Class G Doherty architecture, the overall bandwidth of the power amplifier is narrow due to the impedance transformation characteristics. The two power amplifiers based on active load modulation affect each other, making the overall circuit very sensitive and the design very difficult.

[0007] (3) Digital predistortion power amplifier circuits are very complex to integrate and consume a large chip area.

[0008] In summary, the present invention aims to extend the linear operating bandwidth of a power amplifier by designing a broadband predistortion linearization mechanism that compromises between minimal power increase efficiency (PAE) and reduced IMD3 problem. Summary of the Invention

[0009] To overcome the shortcomings of the prior art, the present invention provides a power amplifier based on broadband predistortion to solve the problems in the prior art.

[0010] One embodiment of the present invention provides a power amplifier based on broadband predistortion, comprising:

[0011] An input matching module, wherein the input terminal of the input matching module is coupled to an RF input;

[0012] A broadband predistortion module, wherein the input terminal of the broadband predistortion module is network-connected to the output terminal of the input matching module;

[0013] A power amplifier module, wherein the input terminal of the power amplifier module is coupled to the output terminal of the broadband predistortion module;

[0014] An output matching module, wherein the input terminal of the output matching module is coupled to the output terminal of the power amplifier module, and the output terminal of the output matching module is coupled to the radio frequency output;

[0015] The broadband predistortion module includes a first transistor Q1, a third transistor Q3, and a fourth transistor Q4; the gate of the first transistor Q1 is coupled to the output terminal of the input matching module, and a first DC power supply bias VG1 is coupled between the first transistor Q1 and the output terminal of the input matching module; the source of the first transistor Q1 is grounded.

[0016] The source of the third transistor Q3 is coupled to the drain of the fourth transistor Q4, and the connection node between the third transistor Q3 and the fourth transistor Q4 is coupled to the drain of the first transistor Q1.

[0017] The source of the fourth transistor Q4 is coupled to the gate of the first transistor Q1, and a feedback unit is coupled between the fourth transistor Q4 and the first transistor Q1.

[0018] The drain of the third transistor Q3 is coupled to a third capacitor C3, and a first power supply VDD is coupled between the third capacitor C3 and the drain of the third transistor Q3; the end of the third capacitor C3 away from the drain of the third transistor Q3 is coupled between the source of the fourth transistor Q4 and the feedback unit, and the gates of the third transistor Q3 and the fourth transistor Q4 are both coupled to the end of the third capacitor C3 away from the drain of the third transistor Q3.

[0019] The drain of the first transistor Q1 is coupled to the power amplifier module, and a fifth capacitor C5 is coupled between the drain of the first transistor Q1 and the power amplifier module.

[0020] In one embodiment, the first DC power supply bias VG1, which is coupled between the first transistor Q1 and the output of the input matching module, is coupled with a first resistor R1.

[0021] In one embodiment, the third capacitor C3 is coupled to a second resistor R2 at the end away from the drain of the third transistor Q3.

[0022] In one embodiment, the feedback unit includes a third resistor R3 and a fourth capacitor C4 connected in parallel;

[0023] The connection node of the third resistor R3 and the fourth capacitor C4 is respectively coupled to the gate of the first transistor Q1 and the source of the fourth transistor Q4.

[0024] In one embodiment, the power amplifier module includes a second transistor Q2, the gate of which is coupled to the end of a fifth capacitor C5 away from the drain of the first transistor Q1, the source of which is grounded, and the drain of which is coupled to the input of an output matching module.

[0025] In one embodiment, the power amplifier module further includes a sixth transistor Q6 and a seventh transistor Q7 connected in series, the connection node of the sixth transistor Q6 and the seventh transistor Q7 being coupled to the gate of the second transistor Q2 for detecting the radio frequency voltage input to the second transistor Q2;

[0026] The gate of the sixth transistor Q6 is coupled to a sixth capacitor C6, and the end of the sixth capacitor C6 away from the gate of the sixth transistor Q6 is grounded.

[0027] The drain of the sixth transistor Q6 is coupled to a second DC power supply bias VG2, which is coupled to the gate of the seventh transistor Q7 using a current mirror circuit to provide a stable gate bias voltage for the seventh transistor Q7.

[0028] A fifth resistor R5 is connected between the drain of the sixth transistor Q6 and the coupled second DC power supply bias VG2.

[0029] A sixth resistor R6 is coupled between the drain and gate of the sixth transistor Q6.

[0030] In one embodiment, the current mirror circuit includes a fourth resistor R4 and a fifth transistor Q5;

[0031] The gate of the fifth transistor Q5 is coupled to the gate of the seventh transistor Q7;

[0032] The fourth resistor R4 is coupled between the second DC power supply bias VG2 and the drain of the fifth transistor Q5, and the connection node between the gate of the fifth transistor Q5 and the gate of the seventh transistor Q7 is coupled between the fourth resistor R4 and the drain of the fifth transistor Q5.

[0033] The source of the fifth transistor Q5 is coupled to the source of the seventh transistor Q7 and then grounded.

[0034] In one embodiment, the input matching module includes a first capacitor C1, a second capacitor C2, and a first inductor L1;

[0035] One end of the first capacitor C1 is coupled to the radio frequency input, and the other end of the first capacitor C1 is connected in parallel with the second capacitor C2.

[0036] One end of the first inductor L1 is coupled to the connection node between the first capacitor C1 and the second capacitor C2, and the other end of the first inductor L1 is grounded.

[0037] The end of the second capacitor C2 furthest from the first capacitor C1 is connected to the input terminal of the broadband predistortion module.

[0038] In one embodiment, the output matching module includes a third inductor L3 and a ninth capacitor C9 connected in series;

[0039] The end of the third inductor L3 furthest from the ninth capacitor C9 is coupled to the output terminal of the power amplifier module, and the third inductor L3 at this end is coupled to the grounded seventh capacitor C7.

[0040] The end of the ninth capacitor C9 furthest from the third inductor L3 is coupled to the radio frequency output, and an eighth capacitor C8 is grounded between the third inductor L3 and the ninth capacitor C9.

[0041] The connection node between the third inductor L3 and the seventh capacitor C7 is coupled to the second power supply VDD1, and the second power supply VDD1 is coupled to the connection node to the second inductor L2 to prevent signals from flowing into the second power supply VDD1.

[0042] The broadband predistortion-based power amplifier provided in the above embodiments has the following beneficial effects:

[0043] By incorporating a broadband predistortion circuit, the capacitive load of the power amplifier cancels out the inductive load of the main power amplifier. The opposite phase response effectively reduces the IMD3 distortion generated by the main power amplifier, improving the circuit's linearity and bandwidth. Introducing a parallel feedback unit, the parallel resistor R3 further widens the bandwidth, reduces in-band ripple, and improves in-band gain flatness. The parallel capacitor C4 compensates for gain and increases circuit parameters, shortening transformer design and iteration time, and extending the capacitor response over a large bandwidth, thus generating broadband phase cancellation and resulting in a broadband linear and flat gain response. By adding an adaptive power stage amplifier circuit, the transistor bias is adjusted according to the input power, reducing DC losses and improving circuit efficiency. Attached Figure Description

[0044] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0045] Figure 1 A circuit block diagram of a power amplifier based on broadband predistortion provided for an embodiment of the present invention;

[0046] Figure 2 This is a schematic diagram of the overall circuit configuration of a power amplifier based on broadband predistortion provided in an embodiment of the present invention.

[0047] Figure 3 for Figure 2 The circuit diagram of the input matching module of the broadband predistortion-based power amplifier;

[0048] Figure 4 for Figure 2 The circuit diagram of the broadband predistortion module of the power amplifier based on broadband predistortion in the image;

[0049] Figure 5 for Figure 2 The circuit diagram of the power amplifier module based on the broadband predistortion power amplifier in the image;

[0050] Figure 6 for Figure 2 Circuit diagram of the output matching module of the broadband predistortion-based power amplifier;

[0051] Figure 7 A conceptual diagram of a broadband predistortion amplifier circuit based on a broadband predistortion power amplifier provided in an embodiment of the present invention;

[0052] Figure 8 The graph shows the variation of the simulated DC voltage Vx with the input power in a power amplifier based on broadband predistortion, as provided in an embodiment of the present invention.

[0053] Icon labels:

[0054] 100. Input matching module; 200. Wideband predistortion module; 300. Power amplification module; 400. Output matching module. Detailed Implementation

[0055] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0056] It should be noted that if the embodiments of the present invention involve directional indications (such as up, down, left, right, front, back, etc.), the directional indications are only used to explain the relative positional relationship and movement of the components in a specific posture. If the specific posture changes, the directional indications will also change accordingly.

[0057] Furthermore, if the embodiments of this invention involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the use of "and / or" or "and / or" throughout the text includes three parallel solutions. For example, "A and / or B" includes solution A, solution B, or a solution where both A and B are satisfied simultaneously. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0058] Reference Figures 1-8 One embodiment of the present invention provides a power amplifier based on broadband predistortion, comprising:

[0059] An input matching module 100, wherein the input terminal of the input matching module 100 is coupled to an RF input;

[0060] A broadband predistortion module 200, wherein the input terminal of the broadband predistortion module 200 is connected to the output terminal of the input matching module 100;

[0061] A power amplifier module 300, the input terminal of which is coupled to the output terminal of the broadband predistortion module 200;

[0062] An output matching module 400 is provided, wherein the input terminal of the output matching module 400 is coupled to the output terminal of the power amplifier module 300, and the output terminal of the output matching module 400 is coupled to the radio frequency output.

[0063] The broadband predistortion module 200 includes a first transistor Q1, a third transistor Q3 and a fourth transistor Q4; the gate of the first transistor Q1 is coupled to the output terminal of the input matching module 100, and a first DC power supply bias VG1 is coupled between the first transistor Q1 and the output terminal of the input matching module 100; the source of the first transistor Q1 is grounded.

[0064] The source of the third transistor Q3 is coupled to the drain of the fourth transistor Q4, and the connection node between the third transistor Q3 and the fourth transistor Q4 is coupled to the drain of the first transistor Q1.

[0065] The source of the fourth transistor Q4 is coupled to the gate of the first transistor Q1, and a feedback unit is coupled between the fourth transistor Q4 and the first transistor Q1.

[0066] The drain of the third transistor Q3 is coupled to a third capacitor C3, and a first power supply VDD is coupled between the third capacitor C3 and the drain of the third transistor Q3; the end of the third capacitor C3 away from the drain of the third transistor Q3 is coupled between the source of the fourth transistor Q4 and the feedback unit, and the gates of the third transistor Q3 and the fourth transistor Q4 are both coupled to the end of the third capacitor C3 away from the drain of the third transistor Q3.

[0067] The drain of the first transistor Q1 is coupled to the power amplifier module 300, and a fifth capacitor C5 is coupled between the drain of the first transistor Q1 and the power amplifier module 300.

[0068] Wherein, the first DC power supply bias VG1, which is coupled between the first transistor Q1 and the output terminal of the input matching module 100, is coupled with a first resistor R1.

[0069] The third capacitor C3 is coupled to a second resistor R2 at the end away from the drain of the third transistor Q3.

[0070] The feedback unit includes a third resistor R3 and a fourth capacitor C4 connected in parallel; the connection node of the third resistor R3 and the fourth capacitor C4 is respectively coupled to the gate of the first transistor Q1 and the source of the fourth transistor Q4.

[0071] In this embodiment, to address the problems commonly found in existing power amplifiers, a broadband predistortion-based power amplifier is provided. This power amplifier comprises an input matching module 100, a broadband predistortion module 200, a power amplification module 300, and an output matching module 400. The input matching module 100 employs an input matching circuit, the broadband predistortion module 200 employs a broadband predistortion amplification circuit, the power amplification module 300 employs an adaptive power stage amplification circuit, and the output matching module 400 employs an output matching circuit. The circuit connections are as follows: the RF input (RFIN) is connected to the input terminal of the input matching circuit; the output terminal of the input matching circuit is connected to the input terminal of the broadband predistortion amplification circuit; the output terminal of the broadband predistortion amplification circuit is connected to the input terminal of the adaptive power stage amplification circuit; the output terminal of the adaptive power stage amplification circuit is connected to the input terminal of the output matching circuit; and the output terminal of the output matching circuit is connected to the RF output (RFOUT). By adding the broadband predistortion amplification circuit, the capacitive load of the power amplifier cancels out the inductive load of the main power amplifier. The opposite phase response effectively reduces the IMD3 distortion generated by the main power amplifier, improving the linearity and bandwidth of the circuit. Furthermore, the broadband predistortion module 200 includes a feedback unit, which adopts an RC parallel feedback circuit to broaden the circuit bandwidth.

[0072] like Figure 4 As shown, specifically, the broadband predistortion amplifier circuit consists of transistors Q1, Q3 and Q4, capacitors C3, C4 and C5, resistors R1, R2 and R3, a first DC power supply bias VG1 and a first power supply VDD.

[0073] The first DC power supply bias VG1 provides DC bias to the gate of the first transistor Q1. The third transistor Q3 is a thick oxide PMOS transistor, and the fourth transistor Q4 is a thick oxide NMOS transistor. Transistors Q3 and Q4 act as capacitive loads, generating capacitive impedance at the output of the broadband predistortion amplifier circuit. This capacitive output impedance produces a phase response opposite to the inductive output impedance of the output matching circuit dominated by the second inductor L2. The third capacitor C3 is a DC blocking capacitor, ensuring that the DC power supply VDD is unaffected while forming an AC path. The second resistor R2 ensures stable voltages at the gates of the third transistor Q3 and the fourth transistor Q4. To ensure a higher breakdown voltage level for the thick oxide transistors, it is used to maintain a high drain voltage VDD supply, achieving higher linear output power. The fifth capacitor C5 blocks DC and also participates in circuit matching to reduce incoming signal loss.

[0074] An RC parallel feedback circuit is formed by the third capacitor R3 and the fourth capacitor C4. By adding the RC parallel feedback circuit, the parallel resistor R can further widen the bandwidth, reduce in-band ripple fluctuations, and improve in-band gain flatness. The parallel capacitor C can compensate for the gain and increase the circuit parameters, shorten the transformer design and iteration time, and extend the capacitor response over a large bandwidth, thereby generating broadband phase cancellation and resulting in a broadband linear and flat gain response.

[0075] Since third-order intermodulation products (IMD3) are the main contributors to the regeneration of sidelobe spectra in power amplifiers, predistortion is one of the techniques commonly used to minimize them. This is typically achieved by exciting distortion characteristics that are opposite to those of the power amplifier's distortion. Ideal IMD3 cancellation is achieved if the IMD3 generated by the predistorter is equal in amplitude but out of phase with the IMD3 of the adaptive power stage amplifier circuit. Figure 7 The diagram shown illustrates the concept of a broadband predistortion circuit.

[0076] By utilizing such Figure 7 The concept shown is derived using the following formula:

[0077]

[0078] Through formula derivation, let The proposed broadband predistortion line can achieve IMD3 cancellation over a wide frequency range. Essentially, the broadband predistortion line generates a third-order component that is equal in magnitude but 180° out of phase with the third-order component of the adaptive power stage circuit.

[0079] In one embodiment, the power amplifier module 300 includes a second transistor Q2, the gate of the second transistor Q2 is coupled to the end of the fifth capacitor C5 away from the drain of the first transistor Q1, the source of the second transistor Q2 is grounded, and the drain of the second transistor Q2 is coupled to the input terminal of the output matching module 400.

[0080] It also includes a sixth transistor Q6 and a seventh transistor Q7 connected in series, the connection node of which is coupled to the gate of the second transistor Q2 for detecting the radio frequency voltage input to the second transistor Q2;

[0081] The gate of the sixth transistor Q6 is coupled to a sixth capacitor C6, and the end of the sixth capacitor C6 away from the gate of the sixth transistor Q6 is grounded.

[0082] The drain of the sixth transistor Q6 is coupled to a second DC power supply bias VG2, which is coupled to the gate of the seventh transistor Q7 using a current mirror circuit to provide a stable gate bias voltage for the seventh transistor Q7.

[0083] A fifth resistor R5 is connected between the drain of the sixth transistor Q6 and the coupled second DC power supply bias VG2.

[0084] A sixth resistor R6 is coupled between the drain and gate of the sixth transistor Q6.

[0085] The current mirror circuit includes a fourth resistor R4 and a fifth transistor Q5.

[0086] The gate of the fifth transistor Q5 is coupled to the gate of the seventh transistor Q7;

[0087] The fourth resistor R4 is coupled between the second DC power supply bias VG2 and the drain of the fifth transistor Q5, and the connection node between the gate of the fifth transistor Q5 and the gate of the seventh transistor Q7 is coupled between the fourth resistor R4 and the drain of the fifth transistor Q5.

[0088] The source of the fifth transistor Q5 is coupled to the source of the seventh transistor Q7 and then grounded.

[0089] In this embodiment, as Figure 5 As shown, specifically, the power amplifier module 300 employs an adaptive power stage amplifier circuit. This circuit comprises a second DC bias VG2, transistors Q2, Q5, Q6, and Q7, resistors R4, R5, and R6, and a ground capacitor C6. The seventh transistor Q7 is biased by a current mirror circuit, which consists of the fifth transistor Q5 and the fourth resistor R4. The sixth transistor Q6 is connected as a diode, and the sixth capacitor C6 serves as an AC path to ground. The second DC bias VG2 provides the required DC voltage to the gate. The connection point between the sixth transistor Q6 and the seventh transistor Q7 is coupled to the gate of the second transistor Q2 at point Vx. Vx is connected to the output of the broadband predistortion amplifier circuit and is used to detect the RF voltage (radio frequency voltage) input to the second transistor Q2.

[0090] Under small-signal conditions, both transistors Q6 and Q7 operate in the saturation region, with a constant DC current. When the input power increases significantly, transistor Q7 enters the transistor region. Therefore, the DC current of transistor Q7 decreases. The longer transistor Q7 remains in the transistor region, the greater the decrease in its DC current. Since transistors Q6 and Q7 are connected in series, the DC current of transistor Q6 should decrease simultaneously. Therefore, the gate-to-source voltage of transistor Q6 decreases, and the DC voltage at the source of transistor Q6(Vx) increases.

[0091] like Figure 8As shown, the analog DC voltage Vx gradually increases with increasing input power. The adaptive bias circuit can effectively utilize the input power to control the bias voltage, thereby improving the circuit efficiency.

[0092] In a power amplifier with fixed bias, the DC current required for large-signal operation is determined. Therefore, the DC power dissipation in the backoff region becomes greater than the necessary DC power dissipation, resulting in reduced backoff efficiency. To overcome this problem, power amplifiers with adaptive bias circuitry effectively adjust the DC power through the input power, thereby achieving higher compensation efficiency. Furthermore, adaptive bias also improves gain compression.

[0093] In one embodiment, the input matching module 100 includes a first capacitor C1, a second capacitor C2, and a first inductor L1;

[0094] One end of the first capacitor C1 is coupled to the radio frequency input, and the other end of the first capacitor C1 is connected in parallel with the second capacitor C2.

[0095] One end of the first inductor L1 is coupled to the connection node between the first capacitor C1 and the second capacitor C2, and the other end of the first inductor L1 is grounded.

[0096] The end of the second capacitor C2 that is furthest from the first capacitor C1 is connected to the input terminal of the broadband predistortion module 200.

[0097] In this embodiment, as Figure 3 As shown, specifically, the input matching module 100 employs an input matching circuit. This circuit uses a traditional T-type matching to reduce signal bounce at the RF input and to match a suitable input impedance. The input matching circuit includes capacitors C1 and C2 and an inductor L1. The source terminal RFIN input signal is connected to the first capacitor C1, and the other terminal is connected to the second capacitor C2 via the first inductor L1 in parallel. The second capacitor C2 outputs the signal to the input A terminal of the broadband predistortion circuit.

[0098] In one embodiment, the output matching module 400 includes a third inductor L3 and a ninth capacitor C9 connected in series.

[0099] The end of the third inductor L3 furthest from the ninth capacitor C9 is coupled to the output terminal of the power amplifier module 300, and the third inductor L3 is coupled to the grounded seventh capacitor C7 at this end.

[0100] The end of the ninth capacitor C9 furthest from the third inductor L3 is coupled to the radio frequency output, and an eighth capacitor C8 is grounded between the third inductor L3 and the ninth capacitor C9.

[0101] The connection node between the third inductor L3 and the seventh capacitor C7 is coupled to the second power supply VDD1, and the second power supply VDD1 is coupled to the connection node to the second inductor L2 to prevent signals from flowing into the second power supply VDD1.

[0102] In this embodiment, as Figure 6 As shown, specifically, the output matching module 400 employs an output matching circuit, which includes capacitors C7 and C8 to ground, inductor L2, and a series capacitor C9 and inductor L3. The ninth capacitor, C9, acts as a DC blocking capacitor, preventing VDD DC from flowing into the RF path. The second inductor, L2, in addition to acting as a choke to prevent signal flow into the VDD terminal, also participates in circuit matching. Adding more parameters allows for a wider bandwidth and easier design of the matching circuit. The signal is output from the adaptive power stage amplifier circuit output terminal A to the load terminal RFOUT.

[0103] The above description is merely a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural transformations made using the contents of the present invention's specification and drawings under the inventive concept of the present invention, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.

Claims

1. A power amplifier based on broadband predistortion, characterized in that, include: An input matching module (100) is provided, wherein the input terminal of the input matching module (100) is coupled to an RF input; A broadband predistortion module (200) is provided, the input of which is connected to the output of the input matching module (100). A power amplifier module (300) is provided, the input of which is coupled to the output of the broadband predistortion module (200). An output matching module (400) is provided, wherein the input terminal of the output matching module (400) is coupled to the output terminal of the power amplifier module (300), and the output terminal of the output matching module (400) is coupled to the radio frequency output. The broadband predistortion module (200) includes a first transistor Q1, a third transistor Q3 and a fourth transistor Q4; the gate of the first transistor Q1 is coupled to the output terminal of the input matching module (100), and a first DC power supply bias VG1 is coupled between the first transistor Q1 and the output terminal of the input matching module (100), and the source of the first transistor Q1 is grounded. The drain of the third transistor Q3 is coupled to the drain of the fourth transistor Q4, and both the drain of the third transistor Q3 and the drain of the fourth transistor Q4 are coupled to the drain of the first transistor Q1. The source of the fourth transistor Q4 is connected to the gate of the first transistor Q1 via a feedback unit; The drain of the third transistor Q3 is coupled to a third capacitor C3, one end of which is coupled to a first power supply VDD; the gate of the third transistor Q3 and the gate of the fourth transistor Q4 are both connected to the other end of the third capacitor C3. The other end of the third capacitor C3 is connected to one end of the second resistor R2; the other end of the second resistor R2 is connected to the source of the fourth transistor Q4; The drain of the first transistor Q1 is connected to the power amplifier module (300) via the fifth capacitor C5. The gate of the first transistor Q1 and the output terminal of the input matching module (100) are both connected to the first DC power supply bias VG1 through the first resistor R1; The feedback unit includes a third resistor R3 and a fourth capacitor C4 connected in parallel; One end of the third resistor R3 and one end of the fourth capacitor C4 are both coupled to the gate of the first transistor Q1, and the other end of the third resistor R3 and the other end of the fourth capacitor C4 are both coupled to the source of the fourth transistor Q4.

2. The power amplifier based on broadband predistortion as described in claim 1, characterized in that: The power amplifier module (300) includes a second transistor Q2, the gate of which is coupled to one end of a fifth capacitor C5, the source of which is grounded, and the drain of which is coupled to the input of the output matching module (400).

3. The power amplifier based on broadband predistortion as described in claim 2, characterized in that: The power amplifier module (300) also includes a sixth transistor Q6 and a seventh transistor Q7 connected in series. The source of the sixth transistor Q6 and the drain of the seventh transistor Q7 are both coupled to the gate of the second transistor Q2 for detecting the radio frequency voltage input to the second transistor Q2. The gate of the sixth transistor Q6 is coupled to one end of the sixth capacitor C6, and the other end of the sixth capacitor C6 is grounded. The drain of the sixth transistor Q6 is coupled to a second DC power supply bias VG2, which is coupled to the gate of the seventh transistor Q7 using a current mirror circuit to provide a stable gate bias voltage for the seventh transistor Q7. A fifth resistor R5 is connected between the drain of the sixth transistor Q6 and the coupled second DC power supply bias VG2. A sixth resistor R6 is coupled between the drain and gate of the sixth transistor Q6.

4. The power amplifier based on broadband predistortion as described in claim 3, characterized in that: The current mirror circuit includes a fourth resistor R4 and a fifth transistor Q5; The gate of the fifth transistor Q5 is coupled to the gate of the seventh transistor Q7; One end of the fourth resistor R4 is coupled to the second DC power supply bias VG2, and the other end of the fourth resistor R4 is coupled to the drain of the fifth transistor Q5. The connection node between the gate of the fifth transistor Q5 and the gate of the seventh transistor Q7 is coupled to the other end of the fourth resistor R4. The source of the fifth transistor Q5 is coupled to the source of the seventh transistor Q7 and then grounded.

5. The power amplifier based on broadband predistortion as described in claim 1, characterized in that: The input matching module (100) includes a first capacitor C1, a second capacitor C2 and a first inductor L1; One end of the first capacitor C1 is coupled to the radio frequency input, and the other end of the first capacitor C1 is connected to one end of the second capacitor C2. One end of the first inductor L1 is coupled to the connection node between the first capacitor C1 and the second capacitor C2, and the other end of the first inductor L1 is grounded. The other end of the second capacitor C2 is connected to the input terminal of the broadband predistortion module (200).

6. The power amplifier based on broadband predistortion as described in claim 1, characterized in that: The output matching module (400) includes a third inductor L3 and a ninth capacitor C9 connected in series; One end of the third inductor L3 is coupled to the output terminal of the power amplifier module (300), and one end of the third inductor L3 is grounded through the seventh capacitor C7; The other end of the third inductor L3 is connected to the other end of the ninth capacitor C9; One end of the ninth capacitor C9 is coupled to the radio frequency output, and the other end of the ninth capacitor C9 is connected to one end of the eighth capacitor C8, and the other end of the eighth capacitor C8 is grounded. The connection node between the third inductor L3 and the seventh capacitor C7 is connected to the second power supply VDD1 via the second inductor L2 to prevent signals from flowing into the second power supply VDD1.

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