Method and apparatus for eliminating signal phase noise, electronic device and storage medium

Abstract

The present disclosure provides a method and device for eliminating signal phase noise, electronic equipment and storage medium, wherein the method comprises: processing a target analog signal transmitted by a transmitting end to obtain a first signal; wherein the first signal is a carrier signal obtained by demodulating a modulated first digital signal, and the first digital signal is a digital signal corresponding to the target analog signal; performing hard decision processing on the first signal to obtain a second signal; performing common phase error estimation and compensation processing based on the second signal to obtain a third signal; performing hard decision processing on the third signal to obtain a fourth signal, and performing inter-subcarrier interference estimation and compensation processing on the fourth signal to obtain a target digital signal.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of communication, and in particular, to a method and device for eliminating signal phase noise, an electronic device, and a storage medium. BACKGROUND

[0002] With the rapid development of wireless Internet of Things technology, phase noise is often generated in the transmission process of signals received by an Internet of Things receiving system. Phase noise has a multiplicative effect on signals, for example, a common phase error (CPE) causes a same rotation of the phase of all subcarriers, and inter-carrier interference (ICI) caused by random phase makes carriers lose orthogonality, thereby affecting the performance of a demodulation device corresponding to the signal.

[0003] To address this issue, there is a need for an efficient method for removing phase noise to improve the performance of a demodulation device. SUMMARY

[0004] Embodiments of the present disclosure provide at least a method and device for eliminating signal phase noise, an electronic device, a storage medium, and a product.

[0005] In a first aspect, embodiments of the present disclosure provide a method for eliminating signal phase noise, comprising:

[0006] processing a target analog signal sent by a sending end to obtain a first signal; wherein the first signal is a carrier signal obtained by demodulating a first digital signal after modulation, and the first digital signal is a digital signal corresponding to the target analog signal;

[0007] performing hard decision processing on the first signal to obtain a second signal;

[0008] performing common phase error estimation and compensation processing based on the second signal to obtain a third signal;

[0009] performing hard decision processing on the third signal to obtain a fourth signal, and performing inter-subcarrier interference estimation and compensation processing on the fourth signal to obtain a target digital signal.

[0010] In an optional implementation, the common phase error estimation and compensation processing based on the second signal to obtain the third signal comprises:

[0011] performing common phase error estimation processing on the second signal and the first signal by using a common phase error estimation algorithm to obtain a common phase error coefficient;

[0012] The first signal and the common phase error coefficient are subjected to common phase error compensation processing by using a common phase error compensation algorithm, so as to obtain the third signal.

[0013] In an alternative embodiment, the estimation and compensation of inter-carrier interference of the fourth signal to obtain a target digital signal comprises:

[0014] The first signal and the common phase error coefficient are subjected to inter-carrier interference estimation processing to obtain an inter-carrier interference estimation result.

[0015] The inter-carrier interference estimation result and the fourth signal are subjected to inter-carrier interference compensation processing to obtain the target digital signal.

[0016] In an alternative embodiment, the processing of the target analog signal transmitted by the transmitting end to obtain the first signal comprises:

[0017] The target analog signal is acquired and subjected to analog-to-digital conversion to obtain a second digital signal.

[0018] The second digital signal is input to a fast Fourier transform and channel estimation circuit for processing, and the processed second digital signal is subjected to interleaving processing to obtain the first signal.

[0019] In an alternative embodiment, the method further comprises:

[0020] After the estimation and compensation of inter-carrier interference of the fourth signal to obtain a target digital signal, the target digital signal is subjected to constellation demapping processing to obtain a processed target digital signal, and the processed target digital signal is output to an external device.

[0021] In an alternative embodiment, the hard decision processing of the first signal to obtain a second signal comprises:

[0022] The hard decision value of the first signal is determined.

[0023] The first signal is subjected to hard decision processing based on the hard decision value of the first signal to obtain the second signal.

[0024] In an alternative embodiment, the hard decision processing of the first signal to obtain the second signal based on the hard decision value of the first signal comprises:

[0025] The decision threshold of the first signal is acquired.

[0026] perform hard decision processing on the first signal based on the decision threshold and a hard decision value of the first signal to obtain the second signal.

[0027] In an alternative implementation, the performing hard decision processing on the first signal based on the decision threshold and a hard decision value of the first signal to obtain the second signal comprises:

[0028] determining decision data of the first signal based on an absolute value of a difference between a signal value of the first signal and the hard decision value of the first signal;

[0029] performing hard decision processing on the first signal based on the decision data and the decision threshold to obtain the second signal.

[0030] In an alternative implementation, the performing hard decision processing on the first signal based on the decision data and the decision threshold to obtain the second signal comprises:

[0031] in a case where the decision data is greater than or equal to the decision threshold, taking the first signal as the second signal;

[0032] in a case where the decision data is less than the decision threshold, taking the hard decision value of the first signal as the second signal.

[0033] In a second aspect, the embodiments of the present disclosure further provide a device for eliminating signal phase noise, comprising:

[0034] a first processing module configured to process a target analog signal sent by a sending end to obtain a first signal; wherein the first signal is a carrier signal obtained after demodulation of a first digital signal corresponding to the target analog signal, and the first digital signal is a digital signal corresponding to the target analog signal;

[0035] a second processing module configured to perform hard decision processing on the first signal to obtain a second signal;

[0036] a third processing module configured to perform common phase error estimation and compensation processing based on the second signal to obtain a third signal;

[0037] a fourth processing module configured to perform hard decision processing on the third signal to obtain a fourth signal, and to perform inter-subcarrier interference estimation and compensation processing on the fourth signal to obtain a target digital signal.

[0038] In a third aspect, the embodiments of the present disclosure further provide an electronic device, comprising a processor, a memory and a bus, the memory stores machine readable instructions executable by the processor, when the electronic device is running, the processor communicates with the memory through the bus, and the machine readable instructions are executed by the processor to perform the steps of the first aspect or any possible implementation manner of the first aspect.

[0039] In a fourth aspect, the embodiments of the present disclosure further provide a computer readable storage medium, the computer readable storage medium stores a computer program, when the computer program is executed by a processor, the steps of the first aspect or any possible implementation manner of the first aspect are performed.

[0040] In a fifth aspect, the embodiments of the present disclosure further provide a computer program product, the computer program product is stored in a storage medium, and the program product is executed by at least one processor to perform the steps of the first aspect or any possible implementation manner of the first aspect.

[0041] In the embodiments of the present disclosure, first, a target analog signal sent by a sending end is processed to obtain a first signal; the first signal is a carrier signal obtained by demodulating a first digital signal after modulation, and the first digital signal is a digital signal corresponding to the target analog signal; second, a hard decision processing is performed on the first signal to obtain a second signal; third, an estimation and compensation processing of common phase error is performed based on the second signal to obtain a third signal; finally, a hard decision processing is performed on the third signal to obtain a fourth signal, and an estimation and compensation processing of inter-carrier interference is performed on the fourth signal to obtain a target digital signal.

[0042] In the above embodiments, when removing the phase noise generated in the transmission process of the received target analog signal, the receiving end considers the common phase error (CPE) and the inter-carrier interference (ICI) of the first signal. The common phase error (CPE) and the inter-carrier interference (ICI) are estimated and compensated, thereby improving the performance of the signal processing of the receiving end and improving the robustness of the signal.

[0043] In order to make the above objectives, characteristics and advantages of the present disclosure more apparent, the following preferred embodiments are specifically described with reference to the attached drawings. BRIEF DESCRIPTION OF DRAWINGS

[0044] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following will briefly introduce the drawings needed to be used in the embodiments. The drawings incorporated into the specification and form a part of the specification, which show the embodiments consistent with the present disclosure, and are used to explain the technical solutions of the present disclosure together with the specification. It should be understood that the following drawings only show some of the embodiments of the present disclosure, and therefore should not be considered as a limitation to the scope, and for those skilled in the art, other related drawings can also be obtained without creative labor.

[0045] Figure 1 A flow chart of a method for eliminating signal phase noise is shown;

[0046] Figure 2 A circuit structure diagram of a method for eliminating signal phase noise is shown;

[0047] Figure 3 A schematic diagram of an apparatus for eliminating signal phase noise is shown;

[0048] Figure 4 A schematic diagram of an electronic device is shown. DETAILED DESCRIPTION

[0049] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the following will combine the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, not all the embodiments. The components of the embodiments of the present disclosure described and shown in the drawings can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure provided in the drawings is not intended to limit the scope of the claimed present disclosure, but only represents selected embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative labor are within the scope of the present disclosure.

[0050] It should be noted that: similar reference numerals and letters represent similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings.

[0051] The term "and / or", merely describes an associated relationship, which means that there can be three relationships, for example, A and / or B, which can represent: A exists alone, A and B exist together, B exists alone. In addition, the term "at least one" herein means any one of the plurality or any combination of at least two of the plurality, for example, at least one of A, B and C includes any one or more elements selected from the set consisting of A, B and C.

[0052] It is found through research that with the rapid development of wireless Internet of Things technology, the signal received in the Internet of Things receiving system often produces phase noise in the transmission process. Phase noise will have a multiplicative effect on the signal, for example, common phase error (CPE) causes a same rotation of the phase of all subcarriers; and random phase causes inter-carrier interference (ICI) to make the carriers lose orthogonality, thereby affecting the performance of the demodulation device corresponding to the signal.

[0053] In view of this situation, a method for efficiently removing phase noise is needed to improve the performance of the demodulation device.

[0054] Based on the above research, the present disclosure provides a method for eliminating signal phase noise. When removing the phase noise generated in the transmission process of the received target analog signal, the receiving end considers the common phase error (CPE) and inter-carrier interference (ICI) of the first signal. The common phase error (CPE) and inter-carrier interference (ICI) are estimated and compensated, thereby improving the performance of the receiving end in processing the signal and improving the robustness of the signal.

[0055] In order to facilitate the understanding of the present embodiment, first, a method for eliminating signal phase noise disclosed by the present embodiment is introduced in detail. The execution subject of the method for eliminating signal phase noise provided by the present embodiment is generally an electronic device with certain computing power. In some possible implementation manners, the method for eliminating signal phase noise can be realized by calling the computer readable instructions stored in the memory by the processor.

[0056] Referring to Figure 1 FIG. 1 shows a flowchart of a method for eliminating signal phase noise provided by the present embodiment, and the method comprises steps S101-S104, wherein:

[0057] S101, processing the target analog signal sent by the sending end to obtain a first signal; wherein the first signal is a carrier signal obtained by demodulating the first digital signal after modulation, and the first digital signal is a digital signal corresponding to the target analog signal.

[0058] In embodiments of the present disclosure, the sending end can package data to be transmitted to obtain a packaged data packet. Then, the sending end can modulate the data packet by using an orthogonal frequency division multiplexing (OFDM) method to obtain a first digital signal.

[0059] Here, the sending end can modulate the data packet by using multiple modes of the orthogonal frequency division multiplexing method. For example, time domain synchronous orthogonal frequency division multiplexing, zero-forcing orthogonal frequency division multiplexing, and pilot orthogonal frequency division multiplexing.

[0060] Here, the sending end can perform digital-to-analog conversion on the modulated first digital signal to obtain a target analog signal, and send the target analog signal to the receiving end.

[0061] S102, performing hard decision processing on the first signal to obtain a second signal.

[0062] In embodiments of the present disclosure, the first signal can be input to a hard decision circuit to perform hard decision processing to obtain a second signal.

[0063] Here, first, a hard decision value of the first signal can be determined. Then, the first signal and the hard decision value of the first signal can be input to a comparison selection circuit to select one of the first signal and the hard decision value of the first signal as the second signal.

[0064] S103, performing common phase error estimation and compensation processing based on the second signal to obtain a third signal.

[0065] In embodiments of the present disclosure, the second signal can be input to a common phase error (CPE) estimation circuit.

[0066] Here, the common phase error estimation circuit can perform common phase error estimation processing based on the second signal to obtain a second intermediate signal.

[0067] Here, the second intermediate signal can be input to a common phase error compensation circuit.

[0068] Here, the common phase error compensation circuit can perform common phase error compensation processing based on the second intermediate signal to obtain the third signal.

[0069] S104, performing hard decision processing on the third signal to obtain a fourth signal, and performing inter-subcarrier interference estimation and compensation processing on the fourth signal to obtain a target digital signal.

[0070] In embodiments of the present disclosure, first, a hard decision value of the third signal can be determined. Then, the third signal can be processed based on the hard decision value of the third signal to obtain a fourth signal.

[0071] Here, first, a hard decision value of the third signal can be determined. Then, the third signal and the hard decision value of the third signal can be input into the comparison selection circuit, and one of the third signal and the hard decision value of the third signal is selected as the fourth signal.

[0072] Here, a decision threshold of the third signal can be determined, and a hard decision processing is performed on the third signal based on the decision threshold of the third signal and the hard decision value of the third signal.

[0073] Here, first, a decision data of the third signal can be determined based on an absolute value of a difference between a signal value of the third signal and the hard decision value of the third signal. Then, a hard decision processing can be performed on the third signal based on the decision data of the third signal and the decision threshold of the third signal, and the fourth signal is obtained.

[0074] In the case that the decision data of the third signal is greater than or equal to the decision threshold of the third data, the third signal is taken as the fourth signal; in the case that the decision data of the third signal is less than the decision threshold of the third data, the hard decision value of the third signal is taken as the fourth signal.

[0075] In the embodiments of the present disclosure, after the decision data of the third signal is calculated, the decision data of the third signal can be compared with the size of the decision threshold, so that the fourth signal is determined from the third signal and the hard decision value of the third signal.

[0076] In the case that the decision data of the third signal is greater than or equal to the decision threshold of the third data, the third signal is taken as the fourth signal; in the case that the decision data of the third signal is less than the decision threshold of the third data, the hard decision value of the third signal is taken as the fourth signal. 2 k The following conditions are met:

[0077]

[0078] In the case that the decision data of the third signal is greater than or equal to the decision threshold of the third data, the third signal is taken as the fourth signal; in the case that the decision data of the third signal is less than the decision threshold of the third data, the hard decision value of the third signal is taken as the fourth signal. 2’ hard，k The following conditions are met: 2 ’ k The following conditions are met:

[0079] In the embodiments of the present disclosure, the fourth signal can be input into an inter-carrier interference (ICI) estimation circuit.

[0080] Here, the inter-carrier interference estimation circuit can perform inter-carrier interference estimation processing based on the fourth signal, and obtain a fourth intermediate signal.

[0081] Here, the fourth intermediate signal can be input into an inter-carrier interference compensation circuit.

[0082] Here, the inter-subcarrier interference compensation circuit can perform compensation processing on the inter-subcarrier interference based on the fourth intermediate signal to obtain a target digital signal.

[0083] In the embodiments of the present disclosure, first, a target analog signal sent by a sending end is processed to obtain a first signal; the first signal is a carrier signal obtained after demodulation of a first digital signal after modulation, and the first digital signal is a digital signal corresponding to the target analog signal; second, a hard decision processing is performed on the first signal to obtain a second signal; third, an estimation and compensation processing of common phase error is performed based on the second signal to obtain a third signal; and finally, a hard decision processing is performed on the third signal to obtain a fourth signal, and an estimation and compensation processing of inter-subcarrier interference is performed on the fourth signal, and the target digital signal is obtained after the processing.

[0084] In the above embodiments, when removing the phase noise generated in the transmission process of the received target analog signal, the receiving end considers the common phase error (CPE) and the inter-subcarrier interference (ICI) of the first signal in combination. The common phase error (CPE) and the inter-subcarrier interference (ICI) are estimated and compensated, thereby improving the performance of the receiving end in processing the signal and improving the robustness of the signal.

[0085] In an optional embodiment, the above step of performing the estimation and compensation processing of the common phase error based on the second signal to obtain the third signal specifically includes the following steps:

[0086] First, a common phase error estimation algorithm is used to perform the estimation processing of the common phase error on the second signal and the first signal to obtain a common phase error coefficient.

[0087] Then, a common phase error compensation algorithm is used to perform the compensation processing of the common phase error on the first signal and the common phase error coefficient to obtain the third signal.

[0088] In the embodiments of the present disclosure, first, the signal values of all subcarrier signals in the second signal and the first signal can be obtained. Then, the estimation processing of the common phase error can be performed on the first signal and the second signal based on the signal values of the subcarrier signals corresponding to the first signal and the second signal to obtain a common phase error coefficient.

[0089] Here, the common phase error estimation algorithm can be to calculate the product of all subcarrier signals of the first signal and the subcarrier signals of the second signal corresponding to the subcarrier signals of the first signal, and then calculate the sum of all subcarrier signal products to obtain the common phase error coefficient.

[0090] Here, according to the common phase error estimation algorithm, first, a first intermediate coefficient Z0 of the common phase error can be calculated, wherein the first intermediate coefficient Z0 satisfies the following condition:

[0091]

[0092] wherein, is a signal value of the kth subcarrier signal of the first signal, k is an integer from 1 to N, N is the number of subcarrier signals in the first signal, is a signal value of the kth subcarrier signal of the second signal.

[0093] Secondly, the second intermediate coefficient D0 can be calculated based on the subcarrier signals of the second signal. The second intermediate coefficient D0 satisfies the following condition:

[0094]

[0095] Finally, the common phase error coefficient Q0 can be calculated based on the first intermediate coefficient Z0 and the second intermediate coefficient D0. The common phase error coefficient Q0 satisfies the following condition:

[0096] Q0 = Z0 / D0.

[0097] In an embodiment of the present disclosure, according to the common phase error compensation algorithm, the second signal can be compensated based on the common phase error coefficient Q0 to obtain a third signal. The kth subcarrier signal of the third signal satisfies the following condition:

[0098]

[0099] In an optional embodiment, the above steps perform the inter-subcarrier interference estimation and compensation processing on the fourth signal, and obtain a target digital signal after the processing, and specifically include the following steps:

[0100] First, the inter-subcarrier interference estimation processing is performed on the first signal and the common phase error coefficient to obtain an inter-subcarrier interference estimation result.

[0101] Then, the inter-subcarrier interference compensation processing is performed on the inter-subcarrier interference estimation result and the fourth signal to obtain the target digital signal.

[0102] In an embodiment of the present disclosure, first, the signal values of all subcarrier signals in the fourth signal can be obtained. Then, the common phase error estimation processing can be performed on the fourth signal based on the signal values of the subcarrier signals corresponding to the fourth signal to obtain the common phase error coefficient.

[0103] Here, the inter-subcarrier interference estimation result includes a first inter-subcarrier interference result and a second inter-subcarrier interference result.

[0104] ​Here, according to the inter-subcarrier interference estimation algorithm, first, a first inter-subcarrier interference estimation result Q of the inter-subcarrier interference can be calculated -1 , wherein the first inter-subcarrier interference estimation result Q -1 meets the following condition:

[0105]

[0106] , wherein Z -1 can be calculated according to the calculation method of the first intermediate coefficient Z0, and D -1 can be calculated according to the calculation method of the second intermediate coefficient D0.

[0107] Then, a second inter-subcarrier interference estimation result Q of the inter-subcarrier interference can be calculated +1 , wherein the second inter-subcarrier interference estimation result Q +1 meets the following condition:

[0108]

[0109] , wherein Z +1 can be calculated according to the calculation method of the first intermediate coefficient Z0, and D +1 can be calculated according to the calculation method of the second intermediate coefficient D0.

[0110] In an embodiment of the present disclosure, according to the compensation algorithm of the inter-subcarrier interference, the fourth signal can be compensated based on the first inter-subcarrier interference estimation result Q -1 and the second inter-subcarrier interference estimation result Q +1 to obtain a target digital signal.

[0111] In the above embodiment, for the problem of non-uniformity of subcarrier phase caused by non-ideal channel estimation, by performing estimation and compensation processing of common phase error and estimation and compensation processing of inter-subcarrier interference, the performance of the receiving section in the non-ideal channel is improved.

[0112] In an optional embodiment, the above steps process a target analog signal sent by a sending end to obtain a first signal, and specifically include the following steps:

[0113] First, a target analog signal is obtained, and the target analog signal is subjected to analog-to-digital conversion to obtain a second digital signal;

[0114] Then, the second digital signal is input to a fast Fourier transform and channel estimation circuit for processing, and the processed second digital signal is subjected to interleaving processing to obtain the first signal.

[0115] In the embodiments of the present disclosure, after the receiving end receives the target analog signal, the target analog signal can be subjected to analog-to-digital conversion to obtain a second digital signal.

[0116] Here, after the receiving end receives the target analog signal, first, the target analog signal can be subjected to up-conversion processing. Second, the target analog signal subjected to up-conversion processing can be subjected to digital-to-analog conversion. Finally, the target analog signal subjected to digital-to-analog conversion can be input to a radio frequency device for modulation to obtain a second digital signal (i.e., a wireless signal).

[0117] In the embodiments of the present disclosure, first, the second digital signal can be input to a fast Fourier transform and channel estimation circuit for demodulation processing. Then, the demodulated second digital signal can be input to an address mapping circuit for interleaving processing of the demodulated second digital signal to obtain a first signal.

[0118] Here, when the demodulated second digital signal is subjected to interleaving processing, the demodulated second digital signal can be evenly divided into m code groups, each code group consisting of n pieces of data (i.e., subcarrier signals) to form an n x m matrix. Each piece of data enters the interleaving matrix in row order, and is sent out from the interleaving matrix in column order after interleaving processing.

[0119] Here, when the common phase error and the inter-subcarrier interference are estimated, the corresponding subcarrier signals can be estimated according to the addresses of the subcarrier signals corresponding to the first signal, the second signal, the third signal, and the fourth signal. For example, the subcarrier signals with addresses 0, 4, 8, 12, and 16 are extracted with addresses 0, 4, 8, 12, and 16. The subcarrier signals with the extracted addresses are subjected to estimation of the common phase error and the inter-subcarrier interference without changing the storage positions of the subcarrier signals.

[0120] In an optional embodiment, the method further comprises the following steps:

[0121] After the inter-subcarrier interference estimation and interference compensation processing of the fourth signal are performed, a target digital signal is obtained, the target digital signal is subjected to constellation demapping processing to obtain a processed target digital signal, and the processed target digital signal is output to an external device.

[0122] In the embodiments of the present disclosure, after the demodulated second digital signal is subjected to interleaving processing to obtain a first signal, after the inter-subcarrier interference estimation and interference compensation processing of the fourth signal are performed, a target digital signal is obtained, the target digital signal is subjected to constellation demapping processing to obtain a processed target digital signal.

[0123] In an optional embodiment, the step of performing hard decision processing on the first signal to obtain the second signal comprises the following steps:

[0124] First, a hard decision value of the first signal is determined.

[0125] Second, the first signal is processed based on the hard decision value of the first signal to obtain the second signal.

[0126] In an embodiment of the present disclosure, the first signal can be input into a hard decision circuit for processing to obtain the hard decision value of the first signal.

[0127] Here, after the hard decision value of the first signal is obtained, the first signal and the hard decision value of the first signal can be input into a comparison selection circuit for processing to obtain the second signal.

[0128] In an optional embodiment, the step of performing hard decision processing on the first signal based on the hard decision value of the first signal to obtain the second signal comprises the following steps:

[0129] First, a decision threshold of the first signal is obtained.

[0130] Then, the first signal is processed based on the decision threshold and the hard decision value of the first signal to obtain the second signal.

[0131] In an embodiment of the present disclosure, the decision threshold of the first signal can be set by the skilled person according to actual needs, which is not specifically limited here.

[0132] Here, the step of performing hard decision processing on the first signal based on the decision threshold and the hard decision value of the first signal to obtain the second signal comprises the following steps:

[0133] First, a decision data of the first signal is determined based on an absolute value of a difference between a signal value of the first signal and the hard decision value of the first signal.

[0134] Then, the first signal is processed based on the decision data and the decision threshold to obtain the second signal.

[0135] In an embodiment of the present disclosure, first, the signal value of the first signal can be subtracted by the hard decision value of the first signal to obtain the difference between the signal value of the first signal and the hard decision value of the first signal. Then, the absolute value of the difference between the signal value of the first signal and the hard decision value of the first signal can be taken as the decision data of the first signal.

[0136] Here, the decision data can be compared with the decision threshold to perform hard decision processing on the first signal to obtain the second signal.

[0137] In an optional embodiment, the above steps perform hard decision processing on the first signal based on the decision data and decision threshold to obtain the second signal, specifically including the following steps:

[0138] If the judgment data is greater than or equal to the judgment threshold, the first signal will be used as the second signal;

[0139] If the judgment data is less than the judgment threshold, the hard judgment value of the first signal is used as the second signal.

[0140] In embodiments of this disclosure, after the decision data is calculated, the decision data can be compared with the size of the decision threshold to determine the second signal from the first signal and the hard decision value of the first signal.

[0141] Among them, the kth subcarrier signal of the second signal The following conditions must be met:

[0142]

[0143] in, Let D be the k-th subcarrier signal that is the hard decision value of the first signal, and D be the decision threshold of the first signal.

[0144] See Figure 2 The diagram shown is a circuit structure diagram of a method for eliminating signal phase noise provided in an embodiment of this disclosure, which includes an address mapping circuit, a hard decision circuit, a comparison selection circuit, a common phase error estimation circuit, a common phase error compensation circuit, an inter-carrier interference estimation circuit, and an inter-carrier interference compensation circuit.

[0145] First, the first digital signal is input to the address mapping circuit to obtain the first signal Y. 1 '. Next, the first signal Y 1 The input is processed by the hard decision circuit to obtain the hard decision value of the first signal.

[0146] Secondly, the first signal Y 1 'and the hard judgment value of the first signal' The input is processed by a comparator selection circuit to obtain the second signal X. 1 Secondly, the second signal X 1 The input is processed by the common phase error estimation circuit to obtain the common phase error coefficient Q0.

[0147] Secondly, the common phase error coefficient Q0 is input to the common phase error compensation circuit for processing to obtain the third signal Y. 2 '. Secondly, the third signal Y 2 The input is processed by the hard decision circuit to obtain the hard decision value of the third signal.

[0148] Secondly, the third signal Y 2 and the hard decision value of the third signal is input into a comparison selection circuit for processing to obtain a fourth signal X 2 Secondly, the fourth signal X 2 is input into a sub-carrier interference estimation circuit for processing to obtain a first sub-carrier interference estimation result Q -1 and a second sub-carrier interference estimation result Q +1 .

[0149] Secondly, the first sub-carrier interference estimation result Q -1 and the second sub-carrier interference estimation result Q +1 are input into an inter-carrier interference compensation circuit for processing to obtain a target digital signal.

[0150] In the above embodiment, the receiving end considers the common phase error (CPE) and the sub-carrier interference (ICI) of the first signal in combination when removing the phase noise generated in the transmission process of the received target analog signal. The common phase error (CPE) and the sub-carrier interference (ICI) are estimated and compensated, thereby improving the performance of the receiving end in processing the signal and improving the robustness of the signal.

[0151] Those skilled in the art can understand that in the above method of the specific implementation, the writing order of each step does not mean a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined according to its function and possible internal logic.

[0152] Based on the same inventive concept, the disclosure embodiments also provide a device for eliminating signal phase noise corresponding to the method for eliminating signal phase noise. Since the principle of solving problems by the device in the disclosure embodiments is similar to the above-mentioned method for eliminating signal phase noise in the disclosure embodiments, the implementation of the device can be referred to the implementation of the method, and the repeated parts will not be described here.

[0153] Referring to Figure 3 , a schematic diagram of a device for eliminating signal phase noise provided by the disclosure embodiments is shown. The device comprises a first processing module 11, a second processing module 12, a third processing module 13, and a fourth processing module 14. Wherein,

[0154] The first processing module is configured to process a target analog signal sent by a sending end to obtain a first signal. The first signal is a carrier signal obtained by demodulating a modulated first digital signal, and the first digital signal is a digital signal corresponding to the target analog signal.

[0155] a second processing module, configured to perform hard decision processing on the first signal to obtain a second signal;

[0156] a third processing module, configured to perform common phase error estimation and compensation processing on the second signal to obtain a third signal;

[0157] a fourth processing module, configured to perform hard decision processing on the third signal to obtain a fourth signal, and perform inter-carrier interference estimation and compensation processing on the fourth signal to obtain a target digital signal.

[0158] In the above embodiment, the receiving end considers the common phase error (CPE) and the inter-carrier interference (ICI) of the first signal when removing the phase noise generated in the transmission process of the received target analog signal. The common phase error (CPE) and the inter-carrier interference (ICI) are estimated and compensated, thereby improving the performance of the receiving end in processing the signal and improving the robustness of the signal.

[0159] In a possible implementation, the third processing module is further configured to: perform common phase error estimation processing on the second signal and the first signal by using a common phase error estimation algorithm to obtain a common phase error coefficient;

[0160] perform common phase error compensation processing on the first signal and the common phase error coefficient by using a common phase error compensation algorithm to obtain the third signal.

[0161] In a possible implementation, the fourth processing module is further configured to: perform inter-carrier interference estimation processing on the first signal and the common phase error coefficient to obtain an inter-carrier interference estimation result;

[0162] perform inter-carrier interference compensation processing on the inter-carrier interference estimation result and the fourth signal to obtain the target digital signal.

[0163] In a possible implementation, the first processing module is further configured to: acquire the target analog signal, and perform analog-to-digital conversion on the target analog signal to obtain a second digital signal;

[0164] input the second digital signal into a fast Fourier transform and channel estimation circuit for processing, and perform interleaving processing on the processed second digital signal to obtain the first signal.

[0165] In a possible implementation, the second processing module is further configured to: determine a hard decision value of the first signal;

[0166] perform hard decision processing on the first signal based on the hard decision value of the first signal to obtain the second signal.

[0167] In a possible implementation, the second processing module is specifically configured to: obtain a decision threshold of the first signal;

[0168] perform hard decision processing on the first signal based on the decision threshold and a hard decision value of the first signal, to obtain the second signal.

[0169] In a possible implementation, the second processing module is specifically configured to: determine decision data of the first signal based on an absolute value of a difference between a signal value of the first signal and the hard decision value of the first signal;

[0170] perform hard decision processing on the first signal based on the decision data and the decision threshold, to obtain the second signal.

[0171] In a possible implementation, the second processing module is specifically configured to: in a case where the decision data is greater than or equal to the decision threshold, take the first signal as the second signal;

[0172] in a case where the decision data is less than the decision threshold, take the hard decision value of the first signal as the second signal.

[0173] The description of the processing procedure of each module in the apparatus and the interaction procedure between the modules can refer to the related description in the method embodiments, and will not be described in detail here.

[0174] Corresponding to the method for eliminating signal phase noise in Figure 1 , the embodiments of the present disclosure further provide an electronic device 400, as shown in Figure 4 , which is a structural schematic diagram of the electronic device 400 provided by the embodiments of the present disclosure, and includes:

[0175] a processor 41, a memory 42, and a bus 43; the memory 42 is configured to store execution instructions, including an internal memory 421 and an external memory 422; the internal memory 421 is also referred to as an internal storage, and is configured to temporarily store operation data in the processor 41 and exchange data with the external memory 422 such as a hard disk; the processor 41 exchanges data with the external memory 422 through the internal memory 421; when the electronic device 400 is running, the processor 41 and the memory 42 communicate through the bus 43, so that the processor 41 executes the following instructions:

[0176] perform processing on a target analog signal sent by a sending end, to obtain a first signal; the first signal is a carrier signal obtained after demodulation of a first digital signal after modulation, and the first digital signal is a digital signal corresponding to the target analog signal;

[0177] perform hard decision processing on the first signal, to obtain a second signal;

[0178] performing estimation and compensation processing of common phase error based on the second signal to obtain a third signal;

[0179] performing hard decision processing on the third signal to obtain a fourth signal, and performing estimation and compensation processing of inter-subcarrier interference on the fourth signal to obtain a target digital signal.

[0180] The embodiment of the present disclosure further provides a computer readable storage medium, which stores a computer program. The computer program is run by a processor to perform the steps of the method for eliminating signal phase noise in the above method embodiment. The storage medium can be a volatile or non-volatile computer readable storage medium.

[0181] The embodiment of the present disclosure further provides a computer program product, which carries a program code. The program code includes instructions for performing the steps of the method for eliminating signal phase noise in the above method embodiment. For details, refer to the above method embodiment, which will not be repeated here.

[0182] The computer program product can be specifically implemented by hardware, software or a combination thereof. In an optional embodiment, the computer program product is specifically embodied as a computer storage medium. In another optional embodiment, the computer program product is specifically embodied as a software product, such as a software development kit (SDK) and the like.

[0183] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the above-described system and device can refer to the corresponding process in the foregoing method embodiment, which will not be repeated here. In several embodiments provided by the present disclosure, it should be understood that the disclosed system, device and method can be implemented by other ways. The above-described device embodiments are only schematic, for example, the division of the units is only a logical function division, and actual implementation can be in another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some communication interface, device or unit, and can be electrical, mechanical or other forms.

[0184] The units described as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, i.e. may be located in one place, or may be distributed on multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment scheme.

[0185] In addition, each functional unit in various embodiments of the present disclosure can be integrated into one processing unit, or each unit can exist physically, or two or more units can be integrated into one unit.

[0186] If the functions are realized in the form of software functional units and sold or used as independent products, they can be stored in a non-volatile computer readable storage medium executable by a processor. Based on this understanding, the technical solutions of the present disclosure essentially or the part of the prior art or the part of the technical solutions can be embodied in the form of a software product, which is stored in a storage medium and includes a number of instructions for making a computer device (which can be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the method described in various embodiments of the present disclosure. The foregoing storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk, and various program code storage media.

[0187] Finally, it should be noted that: the above-described embodiments are only specific embodiments of the present disclosure, used to illustrate the technical solutions of the present disclosure, and not to limit it, the protection scope of the present disclosure is not limited to this, although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand: any person skilled in the art in the technical range disclosed by the present disclosure, it can still modify or easily think of changes to the technical solutions recorded in the foregoing embodiments, or make equivalent replacement to part of the technical features; and these modifications, changes or replacements do not make the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure, and all should be covered in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A method for eliminating signal phase noise, characterized in that, include: The target analog signal transmitted by the transmitting end is processed to obtain a first signal; wherein, the first signal is a carrier signal obtained by demodulating the modulated first digital signal, and the first digital signal is the digital signal corresponding to the target analog signal; The first signal is subjected to hard decision processing to obtain the second signal; Based on the second signal, the common phase error is estimated and compensated to obtain the third signal; The third signal is subjected to hard decision processing to obtain the fourth signal, and the fourth signal is subjected to inter-carrier interference estimation and compensation processing to obtain the target digital signal.

2. The method according to claim 1, characterized in that, The step of performing error estimation and error compensation processing based on the second signal to obtain the third signal includes: Using a common phase error estimation algorithm, the common phase error of the second signal and the first signal is estimated to obtain the common phase error coefficient. The common phase error compensation algorithm is used to compensate for the common phase error of the first signal and the common phase error coefficient to obtain the third signal.

3. The method according to claim 2, characterized in that, The step of estimating and compensating for inter-carrier interference in the fourth signal to obtain the target digital signal includes: The first signal and the common phase error coefficient are subjected to inter-carrier interference estimation processing to obtain the inter-carrier interference estimation result. The inter-carrier interference estimation result and the fourth signal are subjected to inter-carrier interference compensation processing to obtain the target digital signal.

4. The method according to claim 1, characterized in that, The process of processing the target analog signal transmitted by the transmitting end to obtain the first signal includes: The target analog signal is acquired, and the target analog signal is converted from analog to digital to obtain a second digital signal; The second digital signal is input to a fast Fourier transform and channel estimation circuit for processing, and the processed second digital signal is interleaved to obtain the first signal.

5. The method according to claim 1, characterized in that, The method further includes: After estimating and compensating for inter-carrier interference in the fourth signal to obtain the target digital signal, constellation demapping is performed on the target digital signal to obtain the processed target digital signal, and the processed target digital signal is output to an external device.

6. The method according to claim 1, characterized in that, The step of performing hard decision processing on the first signal to obtain the second signal includes: Determine the hard threshold value of the first signal; The first signal is hard-determined based on its hard value to obtain the second signal.

7. The method according to claim 6, characterized in that, The step of performing hard decision processing on the first signal based on the hard decision value of the first signal to obtain the second signal includes: Obtain the decision threshold of the first signal; The first signal is subjected to hard decision processing based on the decision threshold and the hard decision value of the first signal to obtain the second signal.

8. The method according to claim 7, characterized in that, The step of performing hard decision processing on the first signal based on the decision threshold and the hard decision value of the first signal to obtain the second signal includes: The decision data of the first signal is determined based on the absolute value of the difference between the signal value of the first signal and the hard decision value of the first signal. The first signal is subjected to hard decision processing based on the decision data and the decision threshold to obtain the second signal.

9. The method according to claim 8, characterized in that, The step of performing hard decision processing on the first signal based on the decision data and the decision threshold to obtain the second signal includes: If the decision data is greater than or equal to the decision threshold, the first signal is used as the second signal; If the decision data is less than the decision threshold, the hard decision value of the first signal is used as the second signal.

10. An apparatus for eliminating signal phase noise, characterized in that, include: The first processing module is used to process the target analog signal transmitted by the transmitting end to obtain a first signal; wherein, the first signal is a carrier signal obtained by demodulating the modulated first digital signal, and the first digital signal is the digital signal corresponding to the target analog signal; The second processing module is used to perform hard decision processing on the first signal to obtain the second signal; The third processing module is used to estimate and compensate for the common phase error based on the second signal to obtain the third signal; The fourth processing module is used to perform hard decision processing on the third signal to obtain the fourth signal, and to perform inter-carrier interference estimation and compensation processing on the fourth signal to obtain the target digital signal.

11. An electronic device, characterized in that, include: The device includes a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the electronic device is in operation, the processor communicates with the memory via the bus. When the machine-readable instructions are executed by the processor, they perform the steps of the method for eliminating signal phase noise as described in any one of claims 1 to 9.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, performs the steps of the method for eliminating signal phase noise as described in any one of claims 1 to 9.

13. A computer program product, characterized in that, The computer program product is stored in a storage medium, and the program product is executed by at least one processor to implement the steps of the method for eliminating signal phase noise as described in any one of claims 1 to 9.

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