Semiconductor structure manufacturing method and structure thereof

Abstract

The embodiments of the present disclosure relate to the field of semiconductors and provide a method for manufacturing a semiconductor structure and its structure, wherein the method for manufacturing the semiconductor structure includes: providing a substrate; forming a plurality of bit line contact structures arranged at intervals along a first direction and a second direction on the substrate; forming a capacitor contact structure, the capacitor contact structure being located on the substrate and spaced apart from the bit line contact structure; forming a bit line structure extending along the second direction, the bit line structure being in contact and connected with the bit line contact structure arranged along the second direction, and the bit line structure being spaced apart from the capacitor contact structure. A new method for manufacturing a semiconductor structure can be proposed.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and in particular to a method for manufacturing a semiconductor structure and the structure thereof. Background Art

[0002] Memory is a storage component used to store programs and various data. Random Access Memory (RAM) used in general computer systems can be divided into two types: Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM). DRAM is a commonly used semiconductor memory device in computers and is composed of many repeated storage cells.

[0003] A memory cell typically includes a capacitor and a transistor. The drain of the transistor is connected to a bit line structure, and the source is connected to a capacitor. The capacitor includes a capacitor contact structure and a capacitor. The word line structure of the memory cell can control the opening or closing of the channel region of the transistor, thereby reading the data information stored in the capacitor through the bit line structure, or writing the data information into the capacitor for storage through the bit line structure.

[0004] Currently, it is necessary to propose a new method for manufacturing a semiconductor structure. Summary of the Invention

[0005] The embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, which can at least provide a new method for manufacturing a semiconductor structure.

[0006] According to some embodiments of the present disclosure, on one hand, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, comprising: providing a substrate; forming a plurality of bit line contact structures arranged at intervals along a first direction and a second direction on the substrate; forming a capacitor contact structure, wherein the capacitor contact structure is located on the substrate and is spaced apart from the bit line contact structure; forming a bit line structure extending along the second direction, wherein the bit line structure is in contact and connected with the bit line contact structure arranged along the second direction, and the bit line structure is spaced apart from the capacitor contact structure.

[0007] In some embodiments, the process steps for forming the bit line contact structure include: forming a functional layer on the substrate, the functional layer including a plurality of through holes arranged at intervals along the first direction and the second direction; forming a protective layer, the protective layer being located on the side walls of the through holes; forming the bit line contact structure, the bit line contact structure being in contact with the protective layer and being located in the through holes.

[0008] In some embodiments, the material of the functional layer is a conductive material, and the method of forming the capacitor contact structure includes: forming a first conductive layer, wherein the first conductive layer is located on the top surface of the functional layer and above the bit line contact structure; etching the functional layer and the first conductive layer, and the remaining functional layer and the first conductive layer serve as the capacitor contact structure.

[0009] In some embodiments, the method of etching the functional layer and the first conductive layer includes: performing a first etching process on the functional layer and the first conductive layer to form a first groove extending along the first direction; performing a second etching process on the functional layer and the first conductive layer to form a second groove extending along the second direction, the second groove is connected to the first groove, and the functional layer and the first conductive layer surrounded by the first groove and the second groove serve as the capacitor contact structure.

[0010] In some embodiments, the first etching process includes: forming a first mask layer, the first mask layer is located on the top surface of the first conductive layer; etching the first conductive layer and the functional layer using the first mask layer as a mask to form the first groove, the first groove exposing the side wall of the protective layer.

[0011] In some embodiments, after forming the first groove and before forming the second groove, the method further includes: forming a first isolation layer, wherein the first isolation layer covers the sidewall of the protection layer and fills the first groove.

[0012] In some embodiments, along the second direction, the width of the first groove formed is 15-20 nm.

[0013] In some embodiments, the second etching process includes: forming a second mask layer, the second mask layer is located on the top surface of the first conductive layer; etching the first conductive layer and the functional layer using the second mask layer as a mask to form a second groove, the second groove exposing the surface of the substrate, the protective layer and the top surface of the bit line contact structure.

[0014] In some embodiments, after forming the second groove, the method further includes: forming a second isolation layer, the second isolation layer covering the sidewalls of the capacitor contact structure; and forming a filling layer, the filling layer filling the sidewalls of the second isolation layer and also filling the second groove.

[0015] In some embodiments, the functional layer and the first conductive layer are made of the same material.

[0016] In some embodiments, the material of the functional layer is a non-conductive material, and the method of forming the capacitor contact structure includes: removing the functional layer to expose the side wall surface of the protective layer away from the bit line contact structure; forming an initial capacitor contact structure, the initial capacitor contact structure covers the side wall and top surface of the protective layer, and the initial capacitor contact structure is also located on the top surface of the bit line contact structure; etching the initial capacitor contact structure, and the remaining initial capacitor contact structure serves as the capacitor contact structure.

[0017] In some embodiments, the method for forming the bit line structure includes: forming a bit line isolation structure, wherein the bit line isolation structure covers the side wall of the capacitor contact structure; forming a bit line conductive layer, wherein the bit line conductive layer is located on the top surface of the bit line contact structure and contacts the bit line isolation structure; forming a bit line capping layer, wherein the bit line capping layer is located on the top surface of the bit line conductive layer, and the bit line capping layer, the bit line conductive layer and the bit line isolation structure constitute the bit line structure.

[0018] In some embodiments, after forming the bit line structure, the method further includes: etching a portion of the capacitor contact structure, leaving the top surface of the capacitor contact structure higher than the top surface of the bit line conductive layer; etching a portion of the bit line isolation structure, leaving the top surface of the bit line isolation structure flush with the top surface of the capacitor contact structure.

[0019] In some embodiments, the method for forming the bit line isolation structure includes: before forming the capacitor contact structure, forming a second isolation layer, the second isolation layer is located on the bit line contact structure; forming a third isolation layer, the third isolation layer covers the surface of the second isolation layer; after forming the capacitor contact structure, forming a fourth isolation layer, the fourth isolation layer covers the surface of the third isolation layer, and the second isolation layer, the third isolation layer and the fourth isolation layer serve as the bit line isolation structure.

[0020] In some embodiments, after forming the bit line contact structure and before forming the capacitor contact structure, the method further includes: forming an insulating layer, wherein the insulating layer is located on the top surface of the bit line contact structure; after forming the capacitor contact structure and before forming the bit line structure, the method further includes: etching the insulating layer to expose the top surface of the bit line contact structure.

[0021] In some embodiments, after forming the bit line structure, it also includes: a bit line conductive layer, a bit line isolation structure and a bit line capping layer, and etching back the capacitor contact structure. The bit line structure includes: the top surface of the remaining capacitor contact structure is flush with the bit line conductive layer.

[0022] According to some embodiments of the present disclosure, on the other hand, embodiments of the present disclosure further provide a semiconductor structure, comprising: a substrate; a plurality of bit line contact structures located on the substrate and arranged at intervals along a first direction and a second direction; a capacitor contact structure, wherein the capacitor contact structure is located on the substrate and is spaced apart from the bit line contact structure, and the width of the capacitor contact structure close to the substrate in the first direction is greater than the width of the capacitor contact structure away from the substrate in the first direction; a bit line structure, wherein the bit line structure extends along the second direction, the bit line structure is in contact and connected with the bit line contact structures arranged along the second direction, and the bit line structure is spaced apart from the capacitor contact structure.

[0023] In some embodiments, the capacitor contact structure includes: a functional layer, the functional layer is located on the surface of the substrate, and adjacent functional layers are spaced apart from each other; and a first conductive layer, the first conductive layer is located on the top surface of the functional layer.

[0024] In some embodiments, the width of the functional layer close to the substrate in the first direction is greater than the width of the functional layer away from the substrate in the first direction; the width of the first conductive layer close to the functional layer in the first direction is greater than the width of the first conductive layer away from the functional layer in the first direction.

[0025] In some embodiments, the bit line structure includes: a bit line conductive layer, which is located on the top surface of the bit line contact structure and is spaced apart from the capacitor contact structure; a bit line isolation structure, which covers the side walls of the bit line conductive layer and is in contact with the capacitor contact structure; and a bit line capping layer, which is located on the top surface of the bit line conductive layer.

[0026] In some embodiments, a height difference between a top surface of the bit line conductive layer and a top surface of the capacitor contact structure ranges from 0 nm to 10 nm.

[0027] In some embodiments, along the first direction, the width of the bit line structure is 5-30 nm.

[0028] The technical solution provided by the embodiments of the present disclosure has at least the following advantages: a plurality of bit line contact structures arranged at intervals along the first direction and the second direction are first formed on the substrate; after the bit line contact structures are formed, capacitor contact structures spaced from the bit line contact structures are formed; after the capacitor contact structures are formed, a bit line structure connected to the bit line contact structures arranged along the second direction is formed; by forming the capacitor contact structure first and then the bit line structure, the process of forming the capacitor contact structure can be prevented from affecting the process of forming the bit line structure, and a short circuit between the capacitor contact structure and the bit line structure can be avoided; and by forming the capacitor contact structure first, the process depth of filling the capacitor contact structure can be reduced, thereby reducing the process difficulty of forming the capacitor contact structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0030] Figures 1 to 54 A schematic structural diagram corresponding to each step of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0031] The following describes various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to facilitate a better understanding of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can still be implemented.

[0032] refer to Figures 1 to 54 , Figures 1 to 54 A schematic structural diagram corresponding to each step of a method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure.

[0033] In some embodiments, a method for manufacturing a semiconductor structure includes: providing a substrate 100; forming a plurality of bit line contact structures 110 on the substrate 100, the plurality of bit line contact structures 110 being arranged in a first direction X and a second direction Y at intervals; forming a capacitor contact structure 120, the capacitor contact structure 120 being located on the substrate 100 and spaced apart from the bit line contact structure 110; and forming a bit line structure 130 extending in the second direction Y, the bit line structure 130 being in contact and connected with the bit line contact structures 110 arranged in the second direction Y, and the bit line structure 130 being spaced apart from the capacitor contact structure 120.

[0034] By forming the capacitor contact structure 120 first and then the bitline structure 130, an air gap structure can be avoided in the capacitor contact structure 120. Furthermore, by forming the capacitor contact structure 120 first, damage to the bitline structure 130 during the process of forming the capacitor contact structure 120 can be avoided, thereby preventing the reliability of the bitline structure 130 from being affected. Furthermore, after forming the bitline contact structure 110, the required filling depth for forming the capacitor contact structure 120 is actually the space enclosed by the bitline contact structure 110 and the substrate 100. That is, the required filling depth is actually less than or equal to the thickness of the bitline contact structure 110. If the bitline structure 130 is formed first, the required filling depth for forming the capacitor contact structure 120 is actually the space enclosed by the bitline contact structure 110, the bitline structure 130, and the substrate 100. The depth of the latter space is greater than the depth of the former space. Furthermore, the shallower the filling depth, the better the quality and morphology of the formed capacitor contact structure 120. Therefore, forming the capacitor contact structure 120 first can also improve the reliability of the formed semiconductor structure.

[0035] In some embodiments, the material of substrate 100 includes a semiconductor material, such as, but not limited to, silicon. In some embodiments, substrate 100 may include: a base semiconductor, a compound semiconductor, or an alloy semiconductor. For example, a base semiconductor includes germanium; a compound semiconductor includes silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or Group III-V semiconductor materials; and an alloy semiconductor includes silicon germanium, silicon germanium carbide, germanium-tin, silicon-germanium-tin, gallium arsenic phosphide, gallium indium phosphide, gallium indium arsenide, indium gallium arsenide phosphide, aluminum indium arsenide, and / or aluminum gallium arsenide. In some embodiments, substrate 100 may also be a silicon-on-insulator structure, a silicon-germanium-on-insulator structure, a germanium-on-insulator structure, or a combination thereof.

[0036] In addition, the substrate 100 can be doped according to design requirements (e.g., a P-type substrate 100 or an N-type substrate 100). In some embodiments, the substrate 100 can be doped with P-type dopant ions (e.g., boron ions, indium ions, or gallium ions) or N-type dopant ions (e.g., phosphorus ions, arsenic ions, or antimony ions).

[0037] In some embodiments, the substrate 100 may include active regions 101 and isolation structures 102 located between adjacent active regions. The isolation structures 102 may serve as shallow trench isolation (STI) structures to isolate adjacent active regions 101 .

[0038] In some embodiments, the material of the isolation structure 102 may include only silicon oxide; in some embodiments, the material of the isolation structure 102 may be a stack of multiple film layers, such as a stack of a silicon oxide film layer and a silicon nitride film layer.

[0039] In some embodiments, before forming the bit line contact structure 110 , the process may further include forming a word line structure 140 . The word line structure 140 is located in the substrate 100 and is arranged at intervals along the second direction Y.

[0040] In some embodiments, the word line structure 140 may include: a word line conductive layer 141, a word line isolation structure 142 located on the top surface of the word line conductive layer 141, and a word line dielectric layer 143 wrapped around the surface of the word line conductive layer 141 and the word line isolation structure 142. The word line dielectric layer 143 is used to isolate the active area 101 from the word line conductive layer 141, thereby preventing the active area 101 from directly contacting the word line conductive layer 141, and preventing carriers in the active area 101 from directly flowing to the word line conductive layer 141.

[0041] In some embodiments, the word line conductive layer 141 may include a first conductive sublayer 144 and a second conductive sublayer 145, wherein the second conductive sublayer 145 covers a top surface of the first conductive sublayer 144. The first conductive sublayer 144 may be made of a metal material, such as tungsten, and the second conductive sublayer 145 may be made of a semiconductor material, such as polysilicon. By configuring the second conductive sublayer 145 to be a low work function material, the material difference between the second conductive sublayer 145 and the active region 101 can be reduced, thereby reducing leakage of the word line conductive layer 141. By configuring the first conductive sublayer 144 to be a metal material, the resistance can be reduced, thereby increasing the signal transmission rate of the first conductive sublayer 144.

[0042] It should be noted that the low work function material here refers to a material having a work function lower than the mid-gap work function of silicon.

[0043] In some embodiments, the word line conductive layer 141 may also be a single-layer structure or a multi-layer structure, and the present disclosure does not limit the number of layers of the word line conductive layer 141 .

[0044] In some embodiments, the word line dielectric layer 143 can be made of different materials according to actual needs, such as silicon oxide or hafnium oxide.

[0045] In some embodiments, the word line structure 140 may further include: a word line blocking layer (not shown in the figure), which covers the surface of the word line conductive layer 141 and is located between the word line conductive layer 141 and the active area 101. By setting the word line blocking layer, the word line conductive layer 141 can be separated from the active area 101, thereby preventing ions in the word line conductive layer 141 from diffusing into the active area 101, thereby avoiding affecting the performance of the active area 101.

[0046] In some embodiments, the word line conductive layer 141 includes a first conductive sublayer 144 and a second conductive sublayer 145. The word line blocking layer covers the surface of the first conductive sublayer 144, that is, covers the surface of the metal material, thereby preventing metal ions of the metal material from diffusing into the substrate and contaminating the substrate, thereby improving the reliability of the semiconductor structure.

[0047] refer to Figures 1 to 12 , forming a bit line contact structure 110.

[0048] refer to Figures 1 to 4 ,in, Figure 1 A three-dimensional diagram of a semiconductor structure provided by an embodiment of the present disclosure, Figure 2 Provided for the embodiments of the present disclosure Figure 1 A top view of Figure 3 The embodiment of the present disclosure provides Figure 2 Cross-section view in AA' direction, Figure 4 The embodiment of the present disclosure provides Figure 2 Cross-sectional view taken along the BB' direction. In some embodiments, the process steps for forming the bitline contact structure include: forming a functional layer 150 on the substrate 100, wherein the functional layer 150 includes a plurality of through-holes 151 spaced apart along the first direction X and the second direction Y. It will be understood that the functional layer 150 provides a process foundation for forming the bitline contact structure 110. The through-holes 151 on the functional layer 150 define the arrangement of the bitline contact structure 110. The functional layer 150 also serves as a support structure for forming the bitline contact structure 110, thereby preventing material flow of the bitline contact structure 110 during the formation of the bitline contact structure 110 and preventing short circuits between adjacent bitline contact structures 110.

[0049] In some embodiments, along the first direction X, the size of the through hole 151 is 30-40 nm. It should be noted that the size of the through hole 151 here refers to the maximum distance between any two points of the through hole 151 along the first direction X.

[0050] In some embodiments, the thickness of the formed functional layer 150 may be 40-60 nm, for example, 50 nm or 55 nm, etc. The thickness of the formed functional layer 150 may be adjusted according to actual needs.

[0051] refer to Figures 5 to 8 ,in, Figure 5 The embodiment of the present disclosure provides Figure 1 Based on the above, a three-dimensional diagram corresponding to the protection step is formed. Figure 6 Provided for the embodiments of the present disclosure Figure 5 A top view of Figure 7 The embodiment of the present disclosure provides Figure 6 Cross-section view in AA' direction, Figure 8 The embodiment of the present disclosure provides Figure 6 Cross-sectional view taken along the BB' direction. A protective layer 152 is formed on the sidewalls of the through-hole 151. The protective layer 152 protects the sidewalls of the bitline contact structure 110 while also supporting it. Furthermore, the protective layer 152 provides spacing between adjacent bitline contact structures 110, thereby preventing short circuits between adjacent bitline contact structures 110.

[0052] In some embodiments, the protective layer 152 can be a multi-layer structure. Taking a three-layer structure as an example, the protective layer 152 is divided into a first sub-protective layer 153, a second sub-protective layer 154 and a third sub-protective layer 155. The second sub-protective layer 154 is located between the first sub-protective layer 153 and the third sub-protective layer 155, and the first sub-protective layer 153 covers the inner wall of the through hole 151; in some embodiments, the protective layer 152 can also be a single-layer structure, which can be selected according to actual needs.

[0053] In some embodiments, the material of the first sub-protective layer 153 may be silicon nitride, the material of the second sub-protective layer 154 may be silicon oxide, and the material of the third sub-protective layer 155 may be silicon nitride. That is, the protective layer 152 may be a NON (nitride layer-oxide layer-nitride layer) structure. By setting an oxide layer between the two nitride layers, the insulation performance of the protective layer 152 can be improved, and the material of the nitride layer is harder. By setting two nitride layers, the morphology of the protective layer 152 can also be improved.

[0054] In some embodiments, the first subprotecting layer 153 , the second subprotecting layer 154 and the third subprotecting layer 155 may be formed by atomic vapor deposition.

[0055] In some embodiments, as the process proceeds, the top surface of the formed first sub-protective layer 153 is higher than the top surface of the second sub-protective layer 154, and the top surface of the second sub-protective layer 154 is higher than the top surface of the third sub-protective layer 155. In other words, the thickness of the protective layer 152 gradually decreases in the direction from the first sub-protective layer 153 to the third sub-protective layer 155; in some embodiments, the top surfaces of the first sub-protective layer 153, the second sub-protective layer 154 and the third sub-protective layer 155 may also be flush with each other.

[0056] In some embodiments, in the first direction X, the width of the formed protection layer 152 is 8-15 nm, such as 11 nm or 13 nm.

[0057] refer to Figures 9 to 12 ,in, Figure 9 The embodiment of the present disclosure provides Figure 5 A three-dimensional diagram corresponding to the step of forming a bit line contact structure based on the above, Figure 10 Provided for the embodiments of the present disclosure Figure 9 A top view of Figure 11 The embodiment of the present disclosure provides Figure 10 Cross-section view in AA' direction, Figure 12 The embodiment of the present disclosure provides Figure 10 A cross-sectional view along the BB′ direction is shown. A bit line contact structure 110 is formed. The bit line contact structure 110 contacts the protection layer 152 and is located in the through hole 151 .

[0058] In some embodiments, the top surface of the bit line contact structure 110 is lower than the top surface of the functional layer 150; in some embodiments, the top surface of the bit line contact structure 110 is further lower than the top surface of the protective layer 152; in some embodiments, the protective layer 152 includes: a first sub-protective layer 153, a second sub-protective layer 154 and a third sub-protective layer 155, and the top surface of the bit line contact structure 110 is further lower than the top surface of the protective layer 152.

[0059] In some embodiments, in the first direction X, the width of the formed bit line contact structure 110 may be 10-25 nm, such as 12 nm or 20 nm.

[0060] In some embodiments, after forming the bit line contact structure 110 and before forming the capacitor contact structure, the following may also be included: forming an insulating layer 160, wherein the insulating layer 160 is located on the top surface of the bit line contact structure 110. By forming the insulating layer 160, the top surface of the bit line contact structure 110 can be covered, thereby preventing other process steps from damaging the bit line contact structure 110 in subsequent process steps, or when forming other conductive structures, preventing the bit line contact structure 110 from being short-circuited with other structures that do not require electrical connection, thereby improving the reliability of the subsequently formed semiconductor structure.

[0061] In some embodiments, the method of forming the insulating layer 160 can be: forming an initial insulating layer, the initial insulating layer covering the top surface of the functional layer 150, the protective layer 152 and the bit line contact structure 110, grinding the initial insulating layer to expose the top surface of the functional layer 150, and the remaining initial insulating layer serves as the insulating layer 160.

[0062] In some embodiments, the top surface of the protective layer 152 and the top surface of the bit line contact structure 110 are both lower than the top surface of the functional layer 150. That is, the formed protective layer 152 and the bit line contact structure 110 do not fully fill the through hole 151 in the functional layer 150. In the process of forming the insulating layer 160, the through hole 151 is also filled by the insulating layer 160.

[0063] In some embodiments, the top surfaces of the first sub-protective layer 153, the second sub-protective layer 154 and the third sub-protective layer 155 in the protective layer 152 are flush with each other, and in the process of forming the insulating layer 160, the formed insulating layer 160 only covers the top surface of the bit line contact structure 110; in some embodiments, the top surface of the first sub-protective layer 153 in the protective layer 152 is higher than the top surface of the second sub-protective layer 154, the top surface of the second sub-protective layer 154 is higher than the top surface of the third sub-protective layer 155, and the formed insulating layer 160 also covers the top surface of the protective layer 152.

[0064] In some embodiments, the top surface of the formed insulating layer 160 can also be flush with the top surface of the functional layer 150, and the top surface of the insulating layer 160 can be controlled to be flush with the top surface of the functional layer 150 by grinding, thereby improving the reliability of subsequent process steps.

[0065] The flushness here can be that the absolute value of the height difference between the top surface of the insulating layer 160 and the top surface of the functional layer 150 is 0nm~10nm. When the height difference between the top surface of the insulating layer 160 and the top surface of the functional layer 150 is 0nm, that is, the top surface of the insulating layer 160 is completely flush with the top surface of the functional layer 150. When the absolute value of the height difference between the top surface of the insulating layer 160 and the top surface of the functional layer 150 is greater than 0nm and less than 10nm, that is, the height difference between the top surface of the insulating layer 160 and the top surface of the functional layer 150 is within the expected range.

[0066] refer to Figures 13 to 42In some embodiments, the material of the functional layer 150 is a conductive material, and the method of forming the capacitor contact structure 120 may include: forming a first conductive layer 170, the first conductive layer 170 being located on the top surface of the functional layer 150 and above the bitline contact structure 110; and etching the functional layer 150 and the first conductive layer 170, with the remaining functional layer 150 and the first conductive layer 170 serving as the capacitor contact structure 120. By using a conductive material for the functional layer 150, the overall process difficulty and number of process steps can be reduced. Specifically, by dividing the capacitor contact structure 120 into two layers, the process difficulty is reduced compared to a case where the capacitor contact structure 120 is a single layer, and the number of steps required to remove the functional layer 150 is also reduced.

[0067] In some embodiments, the material of the functional layer is a non-conductive material, and the method of forming the capacitor contact structure 120 may include: removing the functional layer to expose the side wall surface of the protective layer away from the bit line contact structure; forming an initial capacitor contact structure, the initial capacitor contact structure covers the side wall and top surface of the protective layer, and the initial capacitor contact structure is also located on the top surface of the bit line contact structure; etching the initial capacitor contact structure, and the remaining initial capacitor contact structure serves as the capacitor contact structure.

[0068] It can be understood that since the functional layer is a non-conductive material and also occupies the space used to form the capacitor contact structure, the functional layer needs to be removed, retaining the formed protective layer 152 and the mutually spaced bit line contact structure. At this time, the conductive material is filled into the surface of the substrate 100 to form an initial capacitor contact structure. The top surface of the initial capacitor contact structure is higher than the top surface of the protective layer 152, and the initial capacitor contact structure is spaced from the bit line contact structure 110. The formation of the initial capacitor contact structure provides a process basis for the subsequent formation of the capacitor contact structure. After the initial capacitor contact structure is formed, the initial capacitor contact structure is patterned, and the remaining initial capacitor contact structure serves as the capacitor contact structure 120.

[0069] Compared with the functional layer 150 being a conductive material, the process of the functional layer being a non-conductive material adds the step of removing the functional layer. At the same time, the initial capacitor contact structure is formed as an integrated structure, and the capacitor contact structure 120 formed by etching the initial capacitor contact structure is also an integrated structure. The capacitor contact structure of the integrated structure is more likely to produce an air gap structure than the capacitor contact structure divided into the functional layer 150 and the first conductive layer 170. In other words, the integrated structure has a deeper filling depth and is more likely to produce an air gap structure itself. The morphology formed by filling the capacitor contact structure formed by the functional layer 150 and the first conductive layer 170 is better.

[0070] It should be noted that the air gap structure here refers to the small bubbles formed inside the structure during the filling process.

[0071] In some embodiments, before removing the functional layer, an insulating layer 160 may be formed on the top surface of the bit line contact structure. The insulating layer 160 may separate the initial capacitor contact structure from the bit line contact structure 110, thereby avoiding the initial capacitor contact structure from being connected to the bit line contact structure 110. The insulating layer 160 may also protect the bit line contact structure 110 during the subsequent etching of the initial capacitor contact structure, thereby avoiding damage to the bit line contact structure 110 during the formation of the capacitor contact structure 120.

[0072] The following description continues to take the functional layer 150 as a conductive material as an example. It should be noted that the following description is also applicable to the case where the functional layer 150 is a non-conductive material. The formation of the first conductive layer 170 and the functional layer 150 in the following description can be regarded as an initial capacitor contact structure.

[0073] refer to Figures 13 to 16 ,in, Figure 13 The embodiment of the present disclosure provides Figure 9 A three-dimensional diagram corresponding to the step of forming the first conductive layer on the basis of Figure 14 Provided for the embodiments of the present disclosure Figure 13 A top view of Figure 15 The embodiment of the present disclosure provides Figure 14 Cross-section view in AA' direction, Figure 16 The embodiment of the present disclosure provides Figure 14 A cross-sectional view along the BB' direction is shown. A first conductive layer 170 is formed.

[0074] In some embodiments, the first conductive layer 170 covers the top surface of the insulating layer 160. It can be understood that by setting the insulating layer 160 to separate the first conductive layer 170 from the bit line contact structure 110, contact between the subsequently formed capacitor contact structure 120 and the bit line contact structure 110 can be avoided, and by forming the insulating layer 160, it can also serve as an etching stop layer for the subsequent etching of the first conductive layer 170, thereby avoiding affecting the bit line contact structure during the etching of the first conductive layer 170.

[0075] In some embodiments, the material of the functional layer 150 may be the same as the material of the first conductive layer 170. By setting the material of the functional layer 150 to be the same as the material of the first conductive layer 170, the interface state between the functional layer 150 and the first conductive layer 170 can be reduced, and at the same time, abnormal signal transmission between the functional layer 150 and the first conductive layer 170 due to material differences can be avoided; in some embodiments, the material of the functional layer 150 may be different from the material of the first conductive layer 170.

[0076] In some embodiments, the material of the functional layer 150 may be polysilicon or the like, and the material of the first conductive layer 170 may be polysilicon or the like.

[0077] In some embodiments, the thickness of the formed first conductive layer 170 may be 40-60 nm, for example, 50 nm or 55 nm.

[0078] refer to Figures 17 to 42 The method for etching the functional layer 150 and the first conductive layer 170 includes: performing a first etching process on the functional layer 150 and the first conductive layer 170 to form a first groove 180 extending along a first direction X; performing a second etching process on the functional layer 150 and the first conductive layer 170 to form a second groove 190 extending along a second direction Y. The second groove 190 is connected to the first groove 180. The functional layer 150 and the first conductive layer 170 enclosed by the first groove 180 and the second groove 190 serve as the capacitor contact structure 120. Through the two etching processes, the functional layer 150 and the first conductive layer 170 can be etched into the capacitor contact structure 120 that is spaced apart from each other.

[0079] refer to Figures 17 to 24 In some embodiments, the first etching process includes: forming a first mask layer 200, the first mask layer 200 being located on a top surface of the first conductive layer 170; etching the first conductive layer 170 and the functional layer 150 using the first mask layer 200 as a mask to form a first groove 180, wherein the first groove 180 exposes the sidewalls of the protective layer 152. The first etching process forms the functional layer 150 and the first conductive layer 170 spaced apart along the second direction Y, thereby providing a process foundation for the subsequent formation of the capacitor contact structure 120 spaced apart along the first direction X and the second direction Y.

[0080] refer to Figures 17 to 20 ,in, Figure 17 The embodiment of the present disclosure provides Figure 13 A three-dimensional diagram corresponding to the step of forming the first mask layer on the basis of Figure 18 Provided for the embodiments of the present disclosure Figure 17 A top view of Figure 19 The embodiment of the present disclosure provides Figure 18 Cross-section view in AA' direction, Figure 20 The embodiment of the present disclosure provides Figure 18 A cross-sectional view along the BB' direction is shown. A first mask layer 200 is formed.

[0081] In some embodiments, the method of forming the first mask layer 200 includes: forming a first initial mask layer, the first initial mask layer covers the entire surface of the functional layer 150, forming a first graphic layer 210 with a pattern, the first graphic layer 210 is located on the surface of the first initial mask layer, and the first initial mask layer is etched using the first graphic layer 210 as a mask, and the remaining first initial mask layer serves as the first mask layer 200.

[0082] In some embodiments, the orthographic projection of the bit line contact structure 110 on the surface of the substrate 100 is located within the orthographic projection of the first mask layer 200 on the surface of the substrate 100, so that the structure on the top surface of the bit line contact structure 110 will not be etched during subsequent etching, thereby protecting the bit line contact structure 110.

[0083] refer to Figures 21 to 24 ,in, Figure 21 The embodiment of the present disclosure provides Figure 17 The three-dimensional diagram corresponding to the step of forming the first groove on the basis of Figure 22 Provided for the embodiments of the present disclosure Figure 21 A top view of Figure 23 The embodiment of the present disclosure provides Figure 22 Cross-section view in AA' direction, Figure 24 The embodiment of the present disclosure provides Figure 22 The first mask layer 200 is used as a mask to etch the functional layer 150 and the first conductive layer 170 to form the first groove 180. After the etching is completed, the first pattern layer 210 is removed (refer to FIG. Figure 20 ).

[0084] In some embodiments, the first etching process exposes the side wall of the protective layer 152 away from the bit line contact structure 110, and also exposes a portion of the top surface of the insulating layer 160. The remaining functional layer 150 is spaced apart from the protective layer 152 in the second direction Y. The remaining first conductive layer 170 partially covers the top surface of the functional layer 150 and partially covers the top surface of the insulating layer 160. The orthographic projection of the portion of the first conductive layer 170 located on the top surface of the insulating layer 160 on the surface of the substrate 100 covers the orthographic projection of the bit line contact structure 110 on the surface of the substrate 100.

[0085] In some embodiments, the protection layer 152 includes a first subprotection layer 153 , a second subprotection layer 154 , and a third subprotection layer 155 . The first etching process exposes the sidewall of the third subprotection layer 155 away from the bit line contact structure 110 .

[0086] It can be understood that, in the process of etching the functional layer 150 and the first conductive layer 170, theoretically, no damage will be caused to the protective layer 152 and the insulating layer 160. Therefore, the first groove 180 can be divided into two parts, the first part is located between the protective layer 152 and the functional layer 150, and the second part is located on the first part, that is, between adjacent first conductive layers 170, and along the second direction Y, the width of the second part of the first groove 180 is greater than or equal to the width of the first part of the first groove 180.

[0087] In some embodiments, the width of the first groove 180 formed along the second direction Y is 15 to 20 nm, for example, 18 nm or 19 nm, etc. It can be understood that the width of the first groove 180 here refers to the distance between the protective layer 152 and the functional layer 150 along the second direction, that is, the width of the first part. However, the larger the width of the first part, the larger the width of the first isolation layer formed subsequently, and the higher the isolation effect brought by the first isolation layer. The smaller the width of the first part, the greater the difficulty of forming the first isolation layer subsequently, and the worse the isolation effect brought by the first isolation layer. Therefore, by setting the width of the first groove 180 to 15 to 20 nm, the first isolation layer formed subsequently can have a better isolation effect, and the difficulty of forming the first isolation layer can be reduced, thereby improving the reliability of the first isolation layer formed subsequently.

[0088] It can be understood that if the width of the first groove 180 formed is less than 15nm, that is, the space used to form the first isolation layer subsequently is less than 15nm, the process of forming the first isolation layer is more difficult, and the morphology of the formed first isolation layer is not good, and the insulation performance brought by the first isolation layer is worse; if the width of the first groove 180 formed is greater than 20nm, when the size of the entire semiconductor structure is constant, the larger the width of the first groove 180, the smaller the width of the functional layer 150 and the first conductive layer 170 retained by etching, which will affect the size of the subsequently formed capacitor contact structure and make the resistance of the subsequently formed capacitor contact structure larger.

[0089] refer to Figures 25 to 28 ,in, Figure 25 The embodiment of the present disclosure provides Figure 21 A three-dimensional diagram corresponding to the step of forming the first isolation layer on the basis of Figure 26 Provided for the embodiments of the present disclosure Figure 25 A top view of Figure 27 The embodiment of the present disclosure provides Figure 26 Cross-section view in AA' direction, Figure 28 The embodiment of the present disclosure provides Figure 26Cross-sectional view along the BB' direction. In some embodiments, after forming the first groove 180 and before forming the second groove, the process further includes: forming a first isolation layer 220, wherein the first isolation layer 220 covers the sidewalls of the protective layer 152 and fills the first groove 180. By forming the first isolation layer 220, the remaining functional layer 150 and the first conductive layer 170 can be separated by the first isolation layer 220, and the first groove 180 can also be filled, thereby supporting the remaining functional layer 150 and the first conductive layer 170. Therefore, the functional layer 150 and the first conductive layer 170 can be supported during subsequent etching, thereby avoiding additional damage to the functional layer 150 and the first conductive layer 170 during the subsequent etching process.

[0090] In some embodiments, the insulating layer 160 covers the top surface of the protection layer 152 . The formed first isolation layer 220 covers the sidewall of the protection layer 152 away from the bit line contact structure 110 . The first isolation layer 220 also covers the top surface of the insulating layer 160 .

[0091] In some embodiments, the insulating layer 160 only covers the top surface of the bit line contact structure 110 , forming a first isolation layer 220 covering the sidewalls of the protection layer 152 away from the bit line contact structure 110 , covering the top surface of the protection layer 152 , and also covering the top surface of the insulating layer 160 .

[0092] refer to Figures 29 to 42 The second etching process includes forming a second mask layer 230, which is located on the top surface of the first conductive layer 170; etching the first conductive layer 170 and the functional layer 150 using the second mask layer 230 as a mask to form a second recess 190. The second recess 190 exposes the surface of the substrate 100, the protective layer 152, and the top surface of the bit line contact structure 110. By first forming the second mask layer 230 and then etching the first conductive layer 170 and the functional layer 150 using the second mask layer 230 as a mask to form the capacitor contact structure, the morphology of the capacitor contact structure can be improved, thereby further improving the reliability of the semiconductor structure.

[0093] In some embodiments, reference Figures 29 to 36 , forming a second mask layer 230 .

[0094] In some embodiments, the method of forming the second mask layer 230 may be: forming a second initial mask layer 231, the second initial mask layer 231 covering the top surface of the first conductive layer 170 and the first isolation layer 220; forming a second graphic layer 240 with a pattern, the second graphic layer 240 is located on the top surface of the second initial mask layer; etching the second initial mask layer 231 using the second graphic layer 240 as a mask, and the remaining second initial mask layer 231 serves as the second mask layer 230.

[0095] In some embodiments, the material of the second mask layer 230 may be an insulating material such as silicon oxide or silicon nitride, and the material of the second pattern layer 240 may be photoresist.

[0096] refer to Figures 29 to 32 ,in, Figure 29 The embodiment of the present disclosure provides Figure 25 A three-dimensional diagram corresponding to the step of forming a second initial mask layer and a second pattern layer on the basis of Figure 30 Provided for the embodiments of the present disclosure Figure 29 A top view of Figure 31 The embodiment of the present disclosure provides Figure 30 Cross-section view in AA' direction, Figure 32 The embodiment of the present disclosure provides Figure 30 A second initial mask layer 231 and a second pattern layer 240 are formed.

[0097] In some embodiments, the orthographic projection of the second graphic layer 240 on the surface of the substrate 100 is at least partially separated from the orthographic projection of the bit line contact structure 110 on the surface of the substrate. By setting the orthographic projection of the second graphic layer 240 on the surface of the substrate 100 and the orthographic projection of the bit line contact structure 110 on the surface of the substrate to be at least partially separated, a process basis is provided for subsequent etching to expose the top surface of the bit line contact structure 110. By exposing the top surface of the bit line contact structure 110, a process basis can be provided for the subsequent formation of a bit line structure connected to the bit line contact structure 110.

[0098] refer to Figures 33 to 36 ,in, Figure 33 The embodiment of the present disclosure provides Figure 29 A three-dimensional diagram corresponding to the step of forming a second mask layer on the basis of Figure 34 Provided for the embodiments of the present disclosure Figure 33 A top view of Figure 35 The embodiment of the present disclosure provides Figure 34 Cross-section view in AA' direction, Figure 36 The embodiment of the present disclosure provides Figure 34 A second mask layer 230 is formed, and the first conductive layer 170 is etched using the second mask layer 230 as a mask, and the etching process is stopped when the top surface of the insulating layer 160 is exposed by controlling the etching process.

[0099] In some embodiments, after forming the second mask layer 230, the following steps may be further performed: removing the second pattern layer 240 (refer to Figure 31 ).

[0100] In some embodiments, a portion of the first isolation layer 220 is also etched during the etching of the first conductive layer 170 .

[0101] It can be understood that as the etching process proceeds, along the first direction X, the first conductive layer 170 after etching will have a smaller width in the portion away from the substrate 100 and a larger width in the portion close to the substrate 100. In other words, the width of the first conductive layer 170 gradually increases in the direction from away from the substrate 100 to close to the substrate 100.

[0102] refer to Figures 37 to 40 ,in, Figure 37 The embodiment of the present disclosure provides Figure 33 A three-dimensional diagram corresponding to the steps of forming the second isolation layer and the third isolation layer on the basis of Figure 38 Provided for the embodiments of the present disclosure Figure 37 A top view of Figure 39 The embodiment of the present disclosure provides Figure 38 Cross-section view in AA' direction, Figure 40 The embodiment of the present disclosure provides Figure 38 Cross-sectional view along the BB' direction. In some embodiments, before forming the capacitor contact structure, the process further includes: forming a second isolation layer 250, the second isolation layer 250 being located on the bitline contact structure 110; and forming a third isolation layer 260, the third isolation layer 260 covering the surface of the second isolation layer 250. The formation of the second isolation layer 250 and the third isolation layer 260 can serve as part of the later formation of the bitline isolation structure.

[0103] In some embodiments, the formed second isolation layer 250 covers the side walls of the first conductive layer 170, the top surface of the functional layer 150 and the top surface of the protective layer 152, and the third isolation layer 260 covers the surface of the second isolation layer 250 away from the substrate 100; in some embodiments, the formed third isolation layer 260 also covers the side walls and top surface of the second mask layer 230. By forming the second isolation layer 250 and the third isolation layer 260, the side walls of the first conductive layer 170 can be protected, thereby reducing damage to the first conductive layer 170 in subsequent processes and further improving the reliability of the semiconductor structure.

[0104] In some embodiments, the material of the second isolation layer 250 may be silicon nitride, and the material of the third isolation layer 260 may be silicon oxide.

[0105] refer to Figures 41 to 42 ,in, Figure 41 The embodiment of the present disclosure provides Figure 39 The structural diagram corresponding to the back etching processing steps is performed based on the Figure 42 Provided in the embodiment of the present disclosure Figure 40The functional layer 150 is further etched using the second mask layer 230 as a mask to form a second groove 190 and a capacitor contact structure 120 at the same time.

[0106] In some embodiments, before etching the functional layer 150, the third isolation layer 260 may also be ground to expose the top surface of the second mask layer 230 and the surface of the second isolation layer 250 located on the top surface of the functional layer 150, and then the third isolation layer 260, the insulating layer 160 and the functional layer 150 are etched using the second mask layer 230 as a mask to form a second groove 190.

[0107] In some embodiments, the capacitor contact structure is formed with a larger width on the side close to the substrate 100 , which increases the distance between the subsequently formed bit line conductive layer and the active area, thereby reducing the risk of leakage.

[0108] refer to Figures 43 to 52 , forming a bit line structure 130 .

[0109] refer to Figures 43 to 46 , forming a bit line isolation structure 270 , which covers the top surface of the capacitor contact structure 120 .

[0110] In some embodiments, after forming the capacitor contact structure 120, a fourth isolation layer 280 is formed. The fourth isolation layer 280 covers the surface of the third isolation layer 260. The second isolation layer 250, the third isolation layer 260, and the fourth isolation layer 280 serve as a bit line isolation structure 270. By forming the bit line isolation structure 270, a subsequently formed bit line conductive layer can be separated from the formed capacitor contact structure 120, thereby preventing the formed bit line structure from being electrically connected to the capacitor contact structure.

[0111] In some embodiments, using the second isolation layer 250 and the third isolation layer 260 formed in the previous process as the bit line isolation structure 270 of the bit line structure formed later can reduce the process steps of forming the bit line structure and shorten the process time of the entire manufacturing method.

[0112] refer to Figure 43 and Figure 44 ,in, Figure 43 The embodiment of the present disclosure provides Figure 41 A schematic structural diagram corresponding to the step of forming the fourth initial isolation layer on the basis of FIG. Figure 44 Provided in the embodiment of the present disclosure Figure 42In some embodiments, the method of forming the fourth isolation layer 280 may include forming a fourth initial isolation layer 281, wherein the fourth initial isolation layer 281 covers the surface of the third isolation layer 260 and further covers the top surface of the bit line contact structure 110.

[0113] refer to Figure 45 and Figure 46 ,in, Figure 45 The embodiment of the present disclosure provides Figure 43 A schematic structural diagram corresponding to the step of forming a fourth isolation layer on the basis of FIG. Figure 46 Provided in the embodiment of the present disclosure Figure 44 Schematic diagram of the structure corresponding to the step of forming a fourth isolation layer on the basis of the second mask layer 230. The fourth initial isolation layer 281 is ground until the top surface of the bit line contact structure 110 is exposed, and the remaining fourth initial isolation layer 281 serves as the fourth isolation layer 280. In some embodiments, the process of grinding the fourth initial isolation layer 281 also includes removing the fourth initial isolation layer 281 located on the top surface of the second mask layer 230.

[0114] In some embodiments, the fourth isolation layer 280 may be made of an insulating material such as silicon nitride.

[0115] refer to Figure 47 and Figure 48 ,in, Figure 47 The embodiment of the present disclosure provides Figure 45 A schematic structural diagram corresponding to the step of forming a bit line conductive layer based on FIG. Figure 48 Provided in the embodiment of the present disclosure Figure 46 Schematic diagram of the structure corresponding to the step of forming a bitline conductive layer on the basis of FIG. Bitline conductive layer 290 is formed. Bitline conductive layer 290 is located on the top surface of bitline contact structure 110 and contacts bitline contact structure 110. Bitline conductive layer 290 is the portion of the bitline structure used for transmitting data. Forming bitline conductive layer 290 enables the signal transmission capability of the bitline structure.

[0116] In some embodiments, the bit line conductive layer 290 may be a single-layer film structure. In some embodiments, the bit line conductive layer 290 may be a multi-layer film structure stacked together. The composition of the bit line conductive layer 290 may be adjusted according to actual needs.

[0117] In some embodiments, the material of the bit line conductive layer 290 may include at least one of conductive materials such as tungsten or copper.

[0118] In some embodiments, during the process of filling the conductive material to form the bit line conductive layer 290 , the filling opening is larger on the side away from the substrate 100 and smaller on the side close to the substrate 100 , thereby increasing the process window for filling the conductive material and improving the filling quality of the formed bit line conductive layer 290 .

[0119] refer to Figures 49 to 52 , forming a bit line capping layer 300, which is located on the top surface of the bit line conductive layer 290. The bit line capping layer 300, the bit line conductive layer 290, and the bit line isolation structure 270 constitute the bit line structure 130. By forming the bit line capping layer 300, the top surface of the bit line conductive layer 290 can be covered, thereby preventing the subsequent process of forming the capacitor structure from affecting the bit line conductive layer 290, thereby improving the reliability of the semiconductor structure.

[0120] refer to Figure 49 and Figure 50 ,in, Figure 49 The embodiment of the present disclosure provides Figure 47 The structural diagram corresponding to the step of forming the initial bit line cap layer on the basis of FIG. Figure 50 Provided in the embodiment of the present disclosure Figure 48 Schematic diagram of the structure corresponding to the step of forming an initial bit line capping layer based on the second mask layer 230. In some embodiments, the method of forming the bit line capping layer 300 may include: forming an initial bit line capping layer 301, wherein the initial bit line capping layer 301 completely fills the second groove 190, and the top surface of the initial bit line capping layer 301 is flush with the top surface of the second mask layer 230.

[0121] refer to Figure 51 and Figure 52 ,in, Figure 51 The embodiment of the present disclosure provides Figure 49 A schematic structural diagram corresponding to the step of forming a bit line cap layer based on FIG. Figure 52 Provided in the embodiment of the present disclosure Figure 50 The initial bit line capping layer 301 and the second mask layer 230 are ground until the top surface of the capacitor contact structure 120 is exposed, and the remaining initial bit line capping layer 301 serves as the bit line capping layer 300.

[0122] refer to Figure 53 and Figure 54 ,in, Figure 53 The embodiment of the present disclosure provides Figure 51 Based on the structural diagram corresponding to the step of etching back the capacitor contact structure, Figure 54 Provided in the embodiment of the present disclosure Figure 52Schematic diagram of the structure corresponding to the step of etching back the capacitor contact structure based on the bitline structure 130. In some embodiments, the bitline structure 130 includes: a bitline conductive layer 290, a bitline isolation structure 270, and a bitline capping layer 300. After forming the bitline structure 130, the step further includes etching back the capacitor contact structure 120, with the absolute value of the height difference between the top surface of the remaining capacitor contact structure 120 and the top surface of the bitline conductive layer 290 ranging from 0 nm to 10 nm.

[0123] If the height difference between the top surface of the capacitor contact structure 120 and the top surface of the bit line conductive layer 290 is 0 nm, that is, the top surface of the capacitor contact structure 120 is completely flush with the top surface of the bit line conductive layer 290, and the height difference between the top surface of the capacitor contact structure 120 and the top surface of the bit line conductive layer 290 is greater than 0 nm, that is, the height difference between the top surface of the capacitor contact structure 120 and the top surface of the bit line conductive layer 290 is within the expected range.

[0124] It can be understood that in the process of forming the capacitor contact structure 120, the first conductive layer 170 formed is trapezoidal, that is, the width on the side away from the substrate 100 is small, and the width on the side close to the substrate 100 is large. By back-etching the capacitor contact structure 120, the contact area between the capacitor contact structure 120 and the subsequently formed capacitor structure can be increased, and the contact resistance between the capacitor contact structure 120 and the subsequently formed capacitor structure can be reduced. It can also reduce the height of the subsequently formed capacitor structure and improve the integration of the semiconductor structure. By back-etching the capacitor contact structure 120, the filling defects of the capacitor contact structure 120 can also be reduced, the formation of the air gap structure can be avoided, the quality of the formed structure can be ensured, and the reliability of the semiconductor structure can be improved.

[0125] In some embodiments, etching back the capacitor contact structure 120 also includes etching back the bit line isolation structure 270. In some embodiments, the bit line isolation structure 270 includes: a second isolation layer 250, a third isolation layer 260 and a fourth isolation layer 280. Etching back the bit line isolation structure 270 also includes: etching back the second isolation layer 250, the third isolation layer 260 and the fourth isolation layer 280.

[0126] In some embodiments, after etching back the capacitor contact structure 120, a capacitor structure (not shown in the figure) can be formed on the top surface of the capacitor contact structure 120; in some embodiments, after etching back the capacitor contact structure 120, a landing pad can be formed first, and the arrangement of the capacitor structure can be changed through the landing pad, and the capacitor structure can be formed after the landing pad is formed.

[0127] It should be noted that the top surface in all the above embodiments refers to the surface away from the side of the substrate 100, and the height difference range of 0nm to 10nm means that the absolute value of the height difference between the film layers is 0nm to 10nm, where the height difference is 0nm, that is, the film layers are completely flush with each other, and the height difference is greater than 0nm, that is, the height difference between the film layers is within the expected range.

[0128] In the embodiment of the present disclosure, by forming the capacitor contact structure 120 first and then the bitline structure 130, an air gap structure can be avoided in the capacitor contact structure 120. Furthermore, by forming the capacitor contact structure 120 first, damage to the bitline structure 130 during the process of forming the capacitor contact structure 120 can be avoided, thereby preventing the reliability of the bitline structure 130 from being affected. Furthermore, after forming the bitline contact structure 110, the required filling depth for forming the capacitor contact structure 120 is actually the space enclosed by the bitline contact structure 110 and the substrate 100, i.e., the required filling depth is actually less than or equal to the thickness of the bitline contact structure 110. If the bitline structure 130 is formed first, the required filling depth for forming the capacitor contact structure 120 is actually the space enclosed by the bitline contact structure 110, the bitline structure 130, and the substrate 100, with the latter space having a greater depth than the former space. Furthermore, the shallower the filling depth, the better the quality and morphology of the formed capacitor contact structure 120. Therefore, forming the capacitor contact structure 120 first can also improve the reliability of the formed semiconductor structure.

[0129] Another embodiment of the present disclosure further provides a semiconductor structure, which can be formed by the manufacturing method of all or part of the above-mentioned semiconductor structure. The semiconductor structure provided by another embodiment of the present disclosure will be described below with reference to the accompanying drawings. It should be noted that the parts that are the same or corresponding to the above-mentioned embodiments can refer to the corresponding description of the above-mentioned embodiments and will not be repeated below.

[0130] refer to Figure 53 and Figure 54 , the semiconductor structure provided by the embodiment of the present disclosure includes: a substrate 100.

[0131] In some embodiments, the semiconductor structure further includes: a plurality of bit line contact structures 110 located on the substrate 100 and arranged at intervals along the first direction X and the second direction Y.

[0132] In some embodiments, the semiconductor structure further includes: a capacitor contact structure 120, the capacitor contact structure 120 being located on the substrate 100 and spaced apart from the bit line contact structure 110, and the width of the capacitor contact structure 120 close to the substrate 100 in the first direction X is greater than the width of the capacitor contact structure 120 away from the substrate 100 in the first direction X.

[0133] In some embodiments, the semiconductor structure further includes a bit line structure 130 , which extends along the second direction Y. The bit line structure 130 is in contact with the bit line contact structure 110 arranged along the second direction Y, and is spaced apart from the capacitor contact structure 120 .

[0134] In the embodiment of the present disclosure, the width of the capacitor contact structure 120 close to the substrate 100 in the first direction X is set to be greater than the width of the capacitor contact structure 120 away from the substrate 100 in the first direction X. By setting the widths of the capacitor contact structures 120 to be different, the top surface area of ​​the capacitor contact structure 120 can be increased, thereby increasing the contact area between the subsequently formed capacitor structure and the capacitor contact structure 120, thereby reducing the contact resistance between the capacitor contact structure 120 and the capacitor structure.

[0135] In some embodiments, the capacitor contact structure 120 includes: a functional layer 150, which is located on the surface of the substrate 100, with adjacent functional layers 150 spaced apart from each other; and a first conductive layer 170, which is located on top of the functional layer 150. By providing the capacitor contact structure 120 with the functional layer 150 and the first conductive layer 170, the manufacturing difficulty of the semiconductor structure can be reduced, facilitating the manufacturing process of the entire semiconductor structure.

[0136] In some embodiments, the width of the functional layer 150 close to the substrate 100 in the first direction X is greater than the width of the functional layer 150 away from the substrate 100 in the first direction X. It is understood that by setting the width of the functional layer 150 close to the substrate 100 to be greater, the reliability of the connection between the capacitor contact structure 120 and the substrate 100 can be increased, thereby improving the reliability of the entire semiconductor structure.

[0137] In some embodiments, the width of the first conductive layer 170 proximate to the functional layer 150 in the first direction X is greater than the width of the first conductive layer 170 distal to the functional layer 150 in the first direction X. By setting the first conductive layer 170 proximate to the functional layer 150 to have a larger width, the reliability of the connection between the functional layer 150 and the first conductive layer 170 can be increased, thereby improving the reliability of the entire semiconductor structure. Furthermore, by setting the first conductive layers 170 to have different widths, the contact area between a subsequently formed capacitor structure and the first conductive layer 170 can be increased, thereby reducing the contact resistance between the first conductive layer 170 and the capacitor structure. Furthermore, by setting the first conductive layer 170 proximate to the functional layer 150 to have a larger width in the first direction X, the distance between adjacent bit line structures 130 can be increased, thereby reducing the coupling capacitance between adjacent bit line structures 130.

[0138] In some embodiments, the bitline structure 130 includes: a bitline conductive layer 290, which is located on a top surface of the bitline contact structure 110 and spaced apart from the capacitor contact structure 120; a bitline isolation structure 270, which covers the sidewalls of the bitline conductive layer 290 and contacts the capacitor contact structure 120; and a bitline capping layer 300, which is located on a top surface of the bitline conductive layer 290. The bitline conductive layer 290 is the portion of the bitline structure 130 used for transmitting signals. The bitline isolation structure 270 and the bitline capping layer 300 are the portions of the bitline structure 130 used for protecting the bitline conductive layer 290. The bitline isolation structure 270 also serves to separate the bitline structure 130 from the capacitor contact structure 120, thereby preventing electrical connection between the bitline structure 130 and the capacitor contact structure 120.

[0139] In some embodiments, the height difference between the top surface of the bit line conductive layer 290 and the top surface of the capacitor contact structure 120 is in the range of 0 nm to 10 nm, for example, 0 nm or 5 nm. It will be appreciated that by setting the height difference between the top surface of the bit line conductive layer 290 and the top surface of the capacitor contact structure 120 in the range of 0 nm to 10 nm, the contact area between the capacitor contact structure and a subsequently formed capacitor structure can be increased, and the height of the subsequently formed capacitor structure can be reduced, thereby improving the integration of the entire semiconductor structure.

[0140] In some embodiments, the width of the bitline structure 130 along the first direction X is 5-30 nm, for example, 10 nm or 20 nm. It is understood that the smaller the width of the bitline structure 130, the greater the resistance of the bitline structure 130 itself. The larger the width of the bitline structure 130, the smaller the size of the capacitor contact structure 120 will be when the size of the semiconductor structure remains constant, and the smaller the spacing between the bitline structure 130 and the capacitor contact structure 120. By setting the width of the bitline structure 130 to 5-30 nm, the bitline structure 130 can be ensured to have a low resistance while not affecting the performance of other structures within the semiconductor structure.

[0141] If the width of the bit line structure 130 is less than 5 nm, the process of forming the bit line structure 130 is difficult, and the resistance of the formed bit line structure 130 is large. If the width of the bit line structure 130 is greater than 30 nm, the size of other structures in the semiconductor structure will be compressed, causing abnormalities in other structures of the semiconductor structure.

[0142] In the embodiment of the present disclosure, the width of the capacitor contact structure 120 close to the substrate 100 in the first direction X is set to be greater than the width of the capacitor contact structure 120 away from the substrate 100 in the first direction X. By setting the widths of the capacitor contact structures 120 to be different, the top surface area of ​​the capacitor contact structure 120 can be increased, thereby increasing the contact area between the subsequently formed capacitor structure and the capacitor contact structure 120, thereby reducing the contact resistance between the capacitor contact structure 120 and the capacitor structure.

[0143] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present disclosure, and in actual applications, various changes may be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the scope of protection of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: providing a substrate; forming a plurality of bit line contact structures on the substrate and arranged at intervals along a first direction and a second direction; forming a capacitor contact structure, the capacitor contact structure being located on the substrate and spaced apart from the bit line contact structure; A bit line structure extending along the second direction is formed, wherein the bit line structure is in contact with and connected to the bit line contact structure arranged along the second direction, and the bit line structure is spaced apart from the capacitor contact structure.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein: The process steps of forming the bit line contact structure include: forming a functional layer on the substrate, wherein the functional layer comprises a plurality of through holes spaced apart along a first direction and a second direction; forming a protective layer, wherein the protective layer is located on a sidewall of the through hole; The bit line contact structure is formed, and the bit line contact structure contacts the protection layer and is located in the through hole.

3. The method for manufacturing a semiconductor structure according to claim 2, wherein: The material of the functional layer is a conductive material, and the method for forming the capacitor contact structure includes: forming a first conductive layer, wherein the first conductive layer is located on a top surface of the functional layer and on the bit line contact structure; The functional layer and the first conductive layer are etched, and the remaining functional layer and the first conductive layer serve as the capacitor contact structure.

4. The method for manufacturing a semiconductor structure according to claim 3, wherein: The method of etching the functional layer and the first conductive layer includes: performing a first etching process on the functional layer and the first conductive layer to form a first groove extending along the first direction; The functional layer and the first conductive layer are subjected to a second etching process to form a second groove extending along the second direction, the second groove is connected to the first groove, and the functional layer and the first conductive layer surrounded by the first groove and the second groove serve as the capacitor contact structure.

5. The method for manufacturing a semiconductor structure according to claim 4, wherein: The first etching process includes: forming a first mask layer, wherein the first mask layer is located on a top surface of the first conductive layer; The first conductive layer and the functional layer are etched using the first mask layer as a mask to form the first groove, wherein the first groove exposes the sidewall of the protection layer.

6. The method for manufacturing a semiconductor structure according to claim 4 or 5, characterized in that: After forming the first groove and before forming the second groove, the method further includes: forming a first isolation layer, wherein the first isolation layer covers the sidewall of the protection layer and fills the first groove.

7. The method for manufacturing a semiconductor structure according to claim 4, wherein: Along the second direction, the width of the formed first groove is 15-20 nm.

8. The method for manufacturing a semiconductor structure according to claim 4, wherein: The second etching process includes: forming a second mask layer, wherein the second mask layer is located on a top surface of the first conductive layer; The first conductive layer and the functional layer are etched using the second mask layer as a mask to form a second groove, wherein the second groove exposes the surface of the substrate, the protection layer, and the top surface of the bit line contact structure.

9. The method for manufacturing a semiconductor structure according to claim 4 or 8, wherein: After forming the second groove, the method further includes: forming a second isolation layer, wherein the second isolation layer covers the sidewall of the capacitor contact structure; A filling layer is formed, wherein the filling layer fills the sidewalls of the second isolation layer and also fills the second groove.

10. The method for manufacturing a semiconductor structure according to claim 3, wherein: The functional layer and the first conductive layer are made of the same material.

11. The method for manufacturing a semiconductor structure according to claim 2, wherein: The material of the functional layer is a non-conductive material, and the method for forming the capacitor contact structure includes: removing the functional layer to expose the sidewall surface of the protection layer away from the bit line contact structure; forming an initial capacitor contact structure, wherein the initial capacitor contact structure covers the sidewalls and the top surface of the protection layer, and the initial capacitor contact structure is also located on the top surface of the bit line contact structure; The initial capacitor contact structure is etched, and the remaining initial capacitor contact structure serves as the capacitor contact structure.

12. The method for manufacturing a semiconductor structure according to claim 1, wherein: The method of forming the bit line structure includes: forming a bit line isolation structure, wherein the bit line isolation structure covers a sidewall of the capacitor contact structure; forming a bit line conductive layer, wherein the bit line conductive layer is located on a top surface of the bit line contact structure and contacts the bit line isolation structure; A bit line capping layer is formed, wherein the bit line capping layer is located on a top surface of the bit line conductive layer. The bit line capping layer, the bit line conductive layer and the bit line isolation structure constitute the bit line structure.

13. The method for manufacturing a semiconductor structure according to claim 12, wherein: After forming the bit line structure, the method further includes: etching a portion of the capacitor contact structure, so that a top surface of the remaining capacitor contact structure is higher than a top surface of the bit line conductive layer; A portion of the bit line isolation structure is etched, and the top surface of the remaining bit line isolation structure is flush with the top surface of the capacitor contact structure.

14. The method for manufacturing a semiconductor structure according to claim 12, wherein: The method of forming the bit line isolation structure includes: Before forming the capacitor contact structure, forming a second isolation layer, wherein the second isolation layer is located on the bit line contact structure; forming a third isolation layer, wherein the third isolation layer covers a surface of the second isolation layer; After forming the capacitor contact structure, a fourth isolation layer is formed, wherein the fourth isolation layer covers the surface of the third isolation layer. The second isolation layer, the third isolation layer and the fourth isolation layer serve as the bit line isolation structure.

15. The method for manufacturing a semiconductor structure according to claim 1, wherein: After forming the bit line contact structure and before forming the capacitor contact structure, the method further includes: forming an insulating layer, wherein the insulating layer is located on a top surface of the bit line contact structure; After forming the capacitor contact structure and before forming the bit line structure, the method further includes: etching the insulating layer to expose the top surface of the bit line contact structure.

16. The method for manufacturing a semiconductor structure according to claim 1, wherein: The bit line structure includes: a bit line conductive layer, a bit line isolation structure and a bit line capping layer. After the bit line structure is formed, the following further includes: The capacitor contact structure is etched back, and the top surface of the remaining capacitor contact structure is flush with the bit line conductive layer.

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