Array substrate and display panel

Abstract

This application discloses an array substrate and a display panel. The array substrate includes a substrate, a first electrode disposed on one side of the substrate, an active portion disposed on the surface of the first electrode away from the substrate, a second electrode disposed on the surface of the active portion away from the substrate, and a gate disposed on the side of the second electrode away from the substrate. The gate and the active portion are at least partially overlapped. The first electrode, the active portion, the second electrode, and the gate form a closed-loop structure. By setting the first electrode, the active portion, the second electrode, and the gate into a closed-loop structure, and stacking the first electrode, the active portion, and the second electrode, the channel length of the transistor is reduced by using the thickness of the active portion as the channel length. At the same time, the channel width of the transistor is changed to the sum of the lengths of the inner and outer rings of the active portion, thereby increasing the channel width of the transistor and improving the mobility of the transistor.

Description

Technical Field

[0001] This application relates to the field of display, and more particularly to an array substrate and a display panel. Background Technology

[0002] Common materials for the active layer of thin-film transistors (TFTs) include amorphous silicon, low-temperature polycrystalline silicon, and oxides. Oxide TFTs are widely used in TFT devices in the display industry due to their low leakage current and high mobility.

[0003] As the size of thin-film transistors (TFTs) decreases, their channels also become smaller, leading to decreased stability and increased leakage current. Current ultra-short channel TFTs have channel lengths of approximately 2 to 3 micrometers. The channel size of TFTs is mainly limited by the precision of the exposure equipment, preventing further reduction in channel size and thus failing to meet the requirements of existing high-mobility devices. Summary of the Invention

[0004] This application provides an array substrate and a display panel to improve the problem that the channel size of existing thin-film transistors cannot be reduced.

[0005] To address the above issues, the technical solution provided in this application is as follows:

[0006] This application provides an array substrate, comprising:

[0007] Substrate;

[0008] The first electrode is disposed on one side of the substrate;

[0009] The active portion is disposed on the surface of the first electrode on the side away from the substrate;

[0010] The second electrode is disposed on the surface of the active portion away from the substrate;

[0011] A gate is disposed on the side of the second electrode away from the substrate, and the gate is at least partially overlapped with the active portion;

[0012] The first electrode, the active part, the second electrode, and the gate are in a closed-loop structure.

[0013] In the array substrate of this application, the closed-loop structure is a circular ring structure or an elliptical ring structure.

[0014] In the array substrate of this application, the first electrode has a plurality of first hollow patterns, and the second electrode has a plurality of second hollow patterns.

[0015] The orthographic projections of the plurality of second hollow patterns onto the film layer where the first electrode is located do not overlap with the plurality of first hollow patterns.

[0016] In the array substrate of this application, a plurality of first hollow patterns are spaced apart on the first electrode, and a plurality of second hollow patterns are spaced apart on the second electrode;

[0017] The orthographic projections of the plurality of second hollow patterns onto the film layer where the first electrode is located are arranged alternately with the plurality of first hollow patterns.

[0018] In the array substrate of this application, the channel length of the active portion is equal to the thickness of the active portion, and the channel width of the active portion is the sum of the lengths of the inner ring and the outer ring of the active portion.

[0019] In the array substrate of this application, the gate includes an inner ring segment, an outer ring segment, and a connecting segment. The inner ring segment is located inside the outer ring segment, and the connecting segment connects the inner ring segment and the outer ring segment. The inner diameter of the inner ring segment is smaller than the inner diameter of the outer ring segment.

[0020] In the array substrate of this application, the orthographic projection of the first cutout pattern on the film layer where the gate is located does not overlap with the inner ring segment and the outer ring segment, and the orthographic projection of the second cutout pattern on the film layer where the gate is located does not overlap with the inner ring segment and the outer ring segment.

[0021] In the array substrate of this application, the orthographic projection of the connection segment on the film layer where the second electrode is located does not overlap with the second hollow pattern.

[0022] In the array substrate of this application, the inner diameter of the inner ring segment is smaller than the inner diameter of the inner ring of the first electrode, and the outer diameter of the outer ring segment is larger than the outer diameter of the outer ring of the first electrode.

[0023] Wherein, the difference between the inner diameter of the inner ring of the first electrode and the inner diameter of the inner ring segment ranges from 1 micrometer to 2 micrometers, and the difference between the outer diameter of the outer ring segment and the outer diameter of the outer ring of the first electrode ranges from 1 micrometer to 2 micrometers.

[0024] In the array substrate of this application, the array substrate further includes a buffer layer disposed on the side of the active portion away from the substrate, and the buffer layer has an opening;

[0025] The second electrode is attached to the surface of the buffer layer away from the substrate and extends into the opening, and the second electrode is in contact with the surface of the active portion in the opening away from the substrate.

[0026] In the array substrate of this application, the array substrate further includes a gate insulating layer, the gate insulating layer is disposed on the side of the buffer layer away from the substrate, and the gate insulating layer covers the sidewall and bottom of the opening, the gate is disposed on the side of the gate insulating layer away from the substrate, a portion of the gate overlaps with the second electrode, and another portion of the gate extends to the sidewall and bottom of the opening.

[0027] This application also proposes a display panel, which includes the above-described array substrate and a light-emitting component located on one side of the array substrate, wherein the array substrate and the light-emitting component are integrated into one unit.

[0028] Beneficial Effects: This application discloses an array substrate and a display panel. The array substrate includes a substrate, a first electrode disposed on one side of the substrate, an active portion disposed on the surface of the first electrode away from the substrate, a second electrode disposed on the surface of the active portion away from the substrate, and a gate disposed on the side of the second electrode away from the substrate. The gate and the active portion are at least partially overlapped. The first electrode, the active portion, the second electrode, and the gate form a closed-loop structure. By setting the first electrode, the active portion, the second electrode, and the gate into a closed-loop structure, and stacking the first electrode, the active portion, and the second electrode, the channel length of the transistor is reduced by using the thickness of the active portion as the channel length. At the same time, the channel width of the transistor is changed to the sum of the lengths of the inner and outer rings of the active portion, thereby increasing the channel width of the transistor and improving the transistor mobility. Attached Figure Description

[0029] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0030] Figure 1A This is the structure of the first electrode in the array substrate of this application;

[0031] Figure 1B The structure of the active portion in the array substrate of this application;

[0032] Figure 1C This is the structure of the second electrode in the array substrate of this application;

[0033] Figure 1D This is a stacked diagram of the first electrode, the active part, and the second electrode in the array substrate of this application;

[0034] Figure 1E This is the structure of the gate in the array substrate of this application;

[0035] Figure 1F This is a stacked diagram of the gate and active portion in the array substrate of this application;

[0036] Figure 1GThis is a stacked diagram of the first electrode, active portion, second electrode, and gate in the array substrate of this application;

[0037] Figure 1H This is a stacked diagram of the first electrode and the gate electrode in the array substrate of this application;

[0038] Figure 2 for Figure 1G Cross-sectional view of the mid-section MM;

[0039] Figure 3 This is a step diagram illustrating the fabrication process of the array substrate in this application;

[0040] Figures 4A to 4I This is a diagram showing the fabrication process steps of the array substrate in this application. Detailed Implementation

[0041] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0042] Existing array substrates typically employ dual-gate or dual-active-layer structures to improve the mobility of oxide TFTs. Dual-gate structures generally only improve the mobility of oxide TFTs by about 1.4 times that of single-gate structures. In dual-active-layer structures, the thickness of each active layer is difficult to control due to the stacked arrangement of two active layers, resulting in poor device uniformity. Therefore, this application proposes an array substrate to address the aforementioned technical problems.

[0043] Please see Figures 1A to 1G and Figure 2 , Figure 2 for Figure 1G Cross-sectional view of the mid-section MM. This application provides an array substrate 100, which includes a substrate 110, a first electrode 121 disposed on one side of the substrate 110, an active portion 131 disposed on the surface of the first electrode 121 away from the substrate 110, a second electrode 151 disposed on the surface of the active portion 131 away from the substrate 110, and a gate 171 disposed on the side of the second electrode 151 away from the substrate 110, wherein the gate 171 and the active portion 131 are at least partially overlapped.

[0044] In this embodiment, the first electrode 121, the active part 131, the second electrode 151 and the gate 171 form a closed-loop structure.

[0045] This application sets the first electrode 121, active portion 131, second electrode 151, and gate 171 into a closed-loop structure, and stacks the first electrode 121, active portion 131, and second electrode 151. The thickness of the active portion 131 is used as the channel length of the transistor, thereby reducing the channel length of the transistor. At the same time, the channel width of the transistor is changed to the sum of the lengths of the inner ring AA and the outer ring BB of the active portion, thereby increasing the channel width of the transistor and improving the device effect of the transistor.

[0046] In this embodiment, the closed-loop structure can be a circular ring structure, an elliptical ring structure, or a ring structure in the form of a quadrilateral or a triangle.

[0047] Please see Figure 2 and Figures 1A to 1G The array substrate 100 may include a substrate 110 and a driving circuit layer disposed on the substrate 110, and the driving circuit layer may include a plurality of thin film transistors.

[0048] In this embodiment, the substrate 110 can be made of materials such as glass, quartz, or polyimide.

[0049] In this embodiment, please refer to Figure 2 The array substrate 100 may include a first electrode layer 120. The material of the first electrode layer 120 may include metals such as Cr, W, Ti, Ta, Mo, Al, Cu, or a single-layer or multi-layer metal structure composed of at least two of the above metals. For example, the material of the first electrode layer 120 may be Mo, Mo / Al, Mo / Cu, MoTi / Cu, MoTi / Cu / MoTi, Ti / Al / Ti, Ti / Cu / Ti, Mo / Cu / IZO, IZO / Cu / IZO, Mo / Cu / ITO, etc.

[0050] In this embodiment, please refer to Figure 2 The array substrate 100 may further include an active layer 130 disposed on the side of the first electrode layer 120 away from the substrate 110. The active layer 130 includes an active portion 131. The material of the active layer 130 may be a metal oxide, such as IGZO, IGTO, Ln-IZO, ITZO, ITGZO, HIZO, IZO (InZnO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, Cd-Sn-O or other metal oxides. The following embodiments of this application use IGZO as an example for illustration.

[0051] In this embodiment, please refer to Figure 2The array substrate 100 may further include a buffer layer 140 disposed on the substrate 110. The material of the buffer layer 140 may include a compound composed of nitrogen, silicon and oxygen elements. For example, the material of the buffer layer 140 may include a single layer of silicon oxide film, or a stacked structure of silicon oxide, silicon nitride, aluminum oxide, etc.

[0052] In this embodiment, please refer to Figure 2 The array substrate 100 may further include a second electrode layer 150 disposed on the side of the buffer layer 140 away from the substrate 110. The material of the second electrode layer 150 may include metals such as Cr, W, Ti, Ta, Mo, Al, Cu, or a single-layer or multi-layer metal structure composed of at least two of the above metals. For example, the material of the second electrode layer 150 may be Mo, Mo / Al, Mo / Cu, MoTi / Cu, MoTi / Cu / MoTi, Ti / Al / Ti, Ti / Cu / Ti, Mo / Cu / IZO, IZO / Cu / IZO, Mo / Cu / ITO, etc.

[0053] In this embodiment, please refer to Figure 2 The buffer layer 140 has an opening 141. The second electrode 151 overlaps the surface of the buffer layer 140 away from the substrate 110 and extends into the opening 141. The second electrode 151 is in contact with the surface of the active part 131 in the opening 141 away from the substrate 110.

[0054] In this embodiment, please refer to Figure 2 The array substrate 100 may further include a gate insulating layer 160 disposed on the side of the second electrode layer 150 away from the substrate 110. The material of the gate insulating layer 160 may include a compound composed of nitrogen, silicon and oxygen, such as a single layer of silicon oxide, silicon nitride or silicon oxynitride, or multiple layers of the above-mentioned inorganic film layers.

[0055] In this embodiment, please refer to Figure 2 The array substrate 100 may further include a gate layer 170 disposed on the side of the gate insulating layer 160 away from the substrate 110. The material of the gate layer 170 may include metals such as Cr, W, Ti, Ta, Mo, Al, Cu, or alloys composed of at least two of the above metals. For example, the material of the gate layer 170 may be Mo, Mo / Al, Mo / Cu, MoTi / Cu, MoTi / Cu / MoTi, Ti / Al / Ti, Ti / Cu / Ti, Mo / Cu / IZO, IZO / Cu / IZO, Mo / Cu / ITO, etc.

[0056] In this embodiment, please refer to Figure 2The gate insulating layer 160 covers the sidewall and bottom of the opening 141, and the gate 171 is disposed on the side of the gate insulating layer 160 away from the substrate 110. A portion of the gate 171 overlaps with the second electrode 151, and another portion of the gate 171 extends to the sidewall and bottom of the opening 141.

[0057] In this embodiment, please refer to Figure 2 The array substrate 100 may further include a passivation layer 180 disposed on the side of the gate layer 170 away from the substrate 110. The material of the passivation layer 180 may include a compound composed of nitrogen, silicon and oxygen, such as a single layer of silicon oxide, silicon nitride or silicon oxynitride, or multiple layers of the above-mentioned inorganic film layers.

[0058] In this embodiment, please refer to Figure 2 The array substrate 100 may further include a pixel electrode 190 disposed on the side of the passivation layer 180 away from the substrate 110. The material of the pixel electrode 190 may include ITO, IZO, ITO / Ag / ITO, IZO / Ag / IZO, Mo / Cu, MoTi / Cu / MoTi.

[0059] Please see Figure 2 and Figure 1A , Figure 1A The structure of the first electrode in the array substrate of this application is shown. The first electrode layer 120 includes a first electrode 121, which can be a ring structure with an outer circle and an inner circle.

[0060] Please see Figure 2 and Figure 1B , Figure 1B The active portion of the array substrate of this application is an active layer 130 including an active portion 131. The active portion 131 is in direct contact with the first electrode 121. The active portion 131 can be a ring structure with an inner ring AA and an outer ring BB. For example, the ring structure can be a circular ring structure. The orthogonal projection of the active portion 131 on the first electrode layer 120 is located inside the first electrode 121.

[0061] Please see Figure 2 and Figure 1C , Figure 1CThe structure of the second electrode in the array substrate of this application is as follows: the second electrode layer 150 includes a second electrode 151, which can be a ring structure with an outer circle and an inner circle. The orthographic projection of the second electrode 151 on the active layer 130 is located within the active portion 131. Simultaneously, the second electrode 151 is in direct contact with a portion of the surface of the active portion 131 away from the substrate 110; for example, the second electrode 151 contacts the end of the active portion 131 near the inner circle, or / and the second electrode 151 contacts the end of the active portion 131 near the outer circle.

[0062] In this embodiment, the first electrode 121, the active portion 131 and the first electrode 121 are stacked, and the thickness of the active portion 131 is used as the channel length of the active portion 131, thereby further reducing the channel length of the transistor.

[0063] It should be noted that the first electrode 121 and the second electrode 151 in this application can be either the source or the drain of a thin-film transistor, which are different from each other.

[0064] It should be noted that when processing the second electrode 151, the first electrode 121, the active portion 131, and the edge of the first electrode 121 can be patterned using a self-aligning process so that the stacked first electrode 121, the active portion 131, and the edge of the first electrode 121 are located on the same inclined plane. For example, the acute angle between the inclined plane and the substrate 110 can be 30 degrees to 60 degrees.

[0065] Since the first electrode 121 and the second electrode 151 are stacked, there is a parasitic capacitance between the first electrode 121 and the second electrode 151. Therefore, in order to reduce the parasitic capacitance between the first electrode 121 and the second electrode 151, this application can open hollow patterns on the first electrode 121 and the second electrode 151 respectively.

[0066] Please see Figures 1A to 1D , Figure 1D This is a superimposed diagram of the first electrode, the active part, and the second electrode in the array substrate of this application. The first electrode 121 has a plurality of first hollow patterns 121A, and the second electrode 151 has a plurality of second hollow patterns 151A. The orthographic projection of the plurality of second hollow patterns 151A on the film layer where the first electrode 121 is located does not overlap with the plurality of first hollow patterns 121A.

[0067] Please see Figures 1A to 1DMultiple first hollow patterns 121A are spaced apart on the first electrode 121, and multiple second hollow patterns 151A are spaced apart on the second electrode 151. The orthographic projections of the multiple second hollow patterns 151A on the film layer where the first electrode 121 is located are spaced apart from the multiple first hollow patterns 121A.

[0068] In this embodiment, the arrangement of the first hollow pattern 121A and the second hollow pattern 151A reduces the overlapping area of ​​the first electrode 121 and the second electrode 151, thereby reducing the parasitic capacitance between the first electrode 121 and the second electrode 151.

[0069] It should be noted that the active part 131 may also be provided with a hollow pattern corresponding to the first hollow pattern 121A or / and the second hollow pattern 151A.

[0070] In this embodiment, the shapes of the first hollow pattern 121A and the second hollow pattern 151A can be elliptical, circular, or quadrilateral. Figures 1A to 1D The example is an ellipse.

[0071] In this embodiment, the area of ​​the first hollow pattern 121A and the area of ​​the second hollow pattern 151A may not be equal. For example, the area of ​​the first hollow pattern 121A may be greater than the area of ​​the second hollow pattern 151A, or the area of ​​the first hollow pattern 121A may be less than the area of ​​the second hollow pattern 151A.

[0072] In this embodiment, the area of ​​the first hollow pattern 121A and the area of ​​the second hollow pattern 151A can be equal.

[0073] Please see Figure 2 , Figure 1E and Figure 1F , Figure 1E This is the structure of the gate in the array substrate of this application. Figure 1F This is a stacked diagram of the gate and active portion in the array substrate of this application. The gate layer 170 may include the gate 171. The gate 171 includes an inner ring segment 171B located inside the gate 171, an outer ring segment 171A located outside the gate 171, and a connecting segment 171C connecting the inner ring segment 171B and the outer ring segment 171A. Both the inner ring segment 171B and the outer ring are circular ring structures. The inner diameter of the inner ring segment 171B is smaller than the inner diameter of the outer ring segment 171A.

[0074] In this embodiment, the widths of the inner ring segment 171B and the outer ring segment 171A can be equal.

[0075] In this embodiment, the gate 171 is composed of two spaced and connected rings, and the inner ring segment 171B overlaps with the inner end of the active portion 131, and the outer ring segment 171A overlaps with the outer end of the active portion 131, that is, each ring overlaps with a part of the active portion 131.

[0076] Secondly, in the appendix Figure 2 In the structure, the distance between the end of the gate 171 near the substrate 110 and the substrate 110 must be less than or equal to the distance between the active portion 131 and the substrate 110. That is, both ends of the gate 171 need to extend towards the substrate 110. Thus, the orthographic projection of the gate 171 onto the side of the active portion 131 at least fully covers that side. Meanwhile, since the gate 171 of this application has an inner ring segment 171B and an outer ring segment 171A, the end of the active portion 131 corresponding to the inner ring segment 171B is the inner ring channel, and the end of the active portion 131 corresponding to the outer ring segment 171A is the outer ring channel. That is, the channel length of the active portion 131 of this application is the sum of the perimeter of the inner ring channel and the perimeter of the outer ring channel. When the channel length of the active portion 131 decreases, the channel width of the active portion 131 increases, further improving the mobility of the thin film transistor in the array substrate 100 of this application.

[0077] Secondly, since the gate 171 overlaps with the first electrode 121 and the second electrode 151, and there is a parasitic capacitance between the gate 171 and the first electrode 121 and the second electrode 151, in order to reduce the parasitic capacitance between the gate 171 and the first electrode 121 and the second electrode 151, this application provides two connected ring structures for the gate 171.

[0078] Please see Figure 1G , Figure 1G This is a superimposed diagram of the first electrode, active portion, second electrode, and gate in the array substrate of this application. The orthographic projection of the first cutout pattern 121A on the film layer where the gate 171 is located does not overlap with the inner ring segment 171B and the outer ring segment 171A. The orthographic projection of the second cutout pattern 151A on the film layer where the gate 171 is located does not overlap with the inner ring segment 171B and the outer ring segment 171A. That is, both the first cutout pattern 121A and the second cutout pattern 151A are located between the inner ring segment 171B and the outer ring segment 171A.

[0079] Please also see Figure 1G The orthographic projection of the connecting segment 171C onto the film layer containing the second electrode 151 does not overlap with the second hollow pattern 151A. (See also...) Figure 1GSince the connecting segment 171C is electrically connected to the inner ring segment 171B and the outer ring segment 171A, and the second electrode 151 has a plurality of second hollow patterns 151A, which expose the active part 131, if the connecting segment 171C overlaps with the second hollow part, the voltage on the gate will affect the movement direction of the charge carriers, thereby affecting the mobility of the transistor. Therefore, this application makes the orthographic projection of the connecting segment 171C on the film layer where the second electrode 151 is located non-overlap with the second hollow pattern 151A, which can further improve the stability of the device.

[0080] Please see Figure 1G and Figure 1H , Figure 1H This is a stacked diagram of the first electrode and the gate in the array substrate of this application. In order to ensure that the gate 171 fully covers the portion of the active part 131 near the edge, the inner diameter of the inner ring segment 171B of this application is smaller than the inner diameter of the inner ring of the first electrode 121, and the outer diameter of the outer ring segment 171A is larger than the outer diameter of the outer ring of the first electrode 121.

[0081] In this embodiment, the difference between the inner diameter of the inner ring of the first electrode 121 and the inner diameter of the inner ring segment 171B is in the range of 1 micrometer to 2 micrometers, and the difference between the outer diameter of the outer ring segment 171A and the outer diameter of the outer ring of the first electrode 121 is in the range of 1 micrometer to 2 micrometers.

[0082] In this embodiment, since the first electrode 121, the active portion 131, and the second electrode 151 are stacked, the channel length of the active portion 131 is equal to the thickness of the active portion 131. Simultaneously, the arrangement of the inner ring segment 171B and the outer ring segment 171A in the gate 171 results in the end of the active portion 131 corresponding to the inner ring segment 171B being the inner ring channel, and the end of the active portion 131 corresponding to the outer ring segment 171A being the outer ring channel. Therefore, the channel width of the active portion 131 in this application is the sum of the lengths of the inner ring segment 171B and the outer ring segment 171A, increasing the channel width of the transistor and further improving the mobility of the thin-film transistor in the array substrate 100 of this application.

[0083] In this embodiment, the channel length ranges from 0.05 micrometers to 0.6 micrometers.

[0084] Please see Figure 2The first electrode layer 120 further includes a first conductive block 122 electrically connected to the first electrode 121, the second electrode layer 150 further includes a second conductive block 152 insulated from the second electrode 151, the gate layer 170 further includes a third conductive block 172 insulated from the gate 171, the second conductive block 152 passes through a via on the passivation layer 180 and is electrically connected to the first conductive block 122, the third conductive block 172 passes through a via on the gate insulating layer 160 and is electrically connected to the second conductive block 152, and the pixel electrode 190 passes through a via on the passivation layer 180 and is electrically connected to the third conductive block 172.

[0085] This application also proposes a display panel, which includes the array substrate 100 and a light-emitting component located on one side of the array substrate 100, wherein the array substrate 100 and the light-emitting component are integrated into one unit.

[0086] For example, when the display panel is a liquid crystal display panel, the structure of the array substrate 100 can serve as the array layer of the liquid crystal display panel; when the display panel is a self-emissive display panel, the structure of the array substrate 100 can serve as the array layer of the self-emissive display panel, and the light-emitting device can be MiniLED or MicroLED.

[0087] Please see Figure 3 This application proposes a method for fabricating an array substrate 100, comprising:

[0088] S10, a substrate 110 is provided, and a first electrode layer 120 including a first electrode 121 and a first conductive block 122 is formed on the substrate 110, wherein the first electrode 121 is electrically connected to the first conductive block 122.

[0089] Please see Figure 4A The substrate 110 can be made of materials such as glass, quartz, or polyimide.

[0090] In this embodiment, the material of the first electrode layer 120 may include metals such as Cr, W, Ti, Ta, Mo, Al, and Cu, or a single-layer or multi-layer metal structure composed of at least two of the above metals; for example, the material of the first electrode layer 120 may be Mo, Mo / Al, Mo / Cu, MoTi / Cu, MoTi / Cu / MoTi, Ti / Al / Ti, Ti / Cu / Ti, Mo / Cu / IZO, IZO / Cu / IZO, Mo / Cu / ITO, etc.

[0091] Please see Figure 4A and Figure 1AThe first electrode 121 can be a ring structure with an outer circle and an inner circle. Furthermore, the first electrode 121 has multiple first hollow patterns 121A, the shape of which can be elliptical, circular, or quadrilateral. Figure 1A The example is an ellipse.

[0092] S20, an active layer 130 including an active portion 131 is formed on the first electrode layer 120;

[0093] Please see Figure 4B and Figure 1B The active part 131 is in direct contact with the first electrode 121. The active part 131 can be a ring structure with an outer circle and an inner circle. The orthogonal projection of the active part 131 on the first electrode layer 120 is located inside the first electrode 121.

[0094] In this embodiment, the active layer 130 can be a metal oxide, such as IGZO, IGTO, Ln-IZO, ITZO, ITGZO, HIZO, IZO (InZnO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, Cd-Sn-O or other metal oxides. The following embodiments of this application use IGZO as an example for illustration.

[0095] S30, a buffer layer 140 is formed on the active layer 130;

[0096] Please see Figure 4C The buffer layer 140 has an opening 141 and a first via 142. The opening 141 exposes a portion of the stacked first electrode 121 and active portion 131, and the first via 142 exposes a portion of the first conductive block 122.

[0097] In this embodiment, the material of the buffer layer 140 may be a compound composed of nitrogen, silicon and oxygen. For example, the material of the buffer layer 140 may be a single layer of silicon oxide film, or a stacked structure of silicon oxide, silicon nitride, aluminum oxide, etc.

[0098] S40, a second electrode layer 150 including a second electrode 151 and a second conductive block 152 is formed on the buffer layer 140;

[0099] Please see Figure 4D The second electrode 151 is attached to the surface of the buffer layer 140 away from the substrate 110 and extends into the opening 141, and the second electrode 151 is in contact with the surface of the active portion 131 in the opening 141 away from the substrate 110.

[0100] Please see Figure 4D and Figure 1C The second electrode 151 can be a ring structure with an outer circle and an inner circle. The orthographic projection of the second electrode 151 on the active layer 130 is located within the active portion 131. Simultaneously, the second electrode 151 is in direct contact with a portion of the surface of the active portion 131 away from the substrate 110; for example, the second electrode 151 contacts the end of the active portion 131 near the inner circle, or / and the second electrode 151 contacts the end of the active portion 131 near the outer circle. Meanwhile, the second conductive block 152 passes through the first via 142 and is electrically connected to the first conductive block 122.

[0101] In this embodiment, the edges of the first electrode 121 and the active portion 131 extend beyond the edge of the second electrode 151.

[0102] In this embodiment, the material of the second electrode layer 150 can be the same as the material of the first electrode layer 120.

[0103] S50, the first electrode 121, the second electrode 151 and the active part 131 stacked together are patterned using a self-alignment process;

[0104] Please see Figure 4E The first electrode 121, the active portion 131, and the edge of the first electrode 121 are patterned using a self-aligning process so that the stacked first electrode 121, the active portion 131, and the edge of the first electrode 121 are located on the same inclined plane. For example, the acute angle between the inclined plane and the substrate 110 can be 30 degrees to 60 degrees.

[0105] S60, a gate insulating layer 160 is formed on the second electrode layer 150;

[0106] Please see Figure 4F The gate insulating layer 160 covers the sidewall and bottom of the opening 141, and a second via 161 is provided on the gate insulating layer 160. The material of the gate insulating layer 160 may include a compound composed of nitrogen, silicon and oxygen, such as a single layer of silicon oxide, silicon nitride or silicon oxynitride, or multiple layers of the above inorganic film.

[0107] S70, a gate layer 170 including a gate 171 and a third conductive block 172 is formed on the gate insulating layer 160;

[0108] Please see Figure 4GThe gate 171 is disposed on the side of the gate insulating layer 160 away from the substrate 110, a portion of the gate 171 overlaps with the second electrode 151, and another portion of the gate 171 extends to the sidewall and bottom of the opening 141.

[0109] Please see Figure 4G and Figure 1E The gate 171 includes an inner ring segment 171B located inside the gate 171, an outer ring segment 171A located outside the gate 171, and a connecting segment 171C connecting the inner ring segment 171B and the outer ring segment 171A. The inner ring segment 171B and the outer ring are both circular ring structures. The inner diameter of the inner ring segment 171B is smaller than the inner diameter of the outer ring segment 171A. The inner ring segment 171B overlaps with the inner end of the active portion 131, and the outer ring segment 171A overlaps with the outer end of the active portion 131. Meanwhile, the third conductive block 172 passes through the second via 161 and is electrically connected to the second conductive block 152.

[0110] Please see Figure 1G and Figure 1H In order to ensure that the gate 171 fully covers the portion of the active part 131 near the edge, the inner diameter of the inner ring segment 171B is smaller than the inner diameter of the inner ring of the first electrode 121, and the outer diameter of the outer ring segment 171A is larger than the outer diameter of the outer ring of the first electrode 121.

[0111] In this embodiment, the material of the gate layer 170 may include metals such as Cr, W, Ti, Ta, Mo, Al, and Cu, or alloys composed of at least two of the above metals; for example, the material of the gate layer 170 may be Mo, Mo / Al, Mo / Cu, MoTi / Cu, MoTi / Cu / MoTi, Ti / Al / Ti, Ti / Cu / Ti, Mo / Cu / IZO, IZO / Cu / IZO, Mo / Cu / ITO, etc.

[0112] S80, a passivation layer 180 is formed on the gate layer 170, and a third via 181 is formed on the passivation layer 180;

[0113] Please see Figure 4H The material of the passivation layer 180 may include a compound composed of nitrogen, silicon and oxygen, such as a single layer of silicon oxide, silicon nitride or silicon oxynitride, or multiple layers of the above inorganic film.

[0114] S90, a pixel electrode 190 is formed on the passivation layer 180, and the pixel electrode 190 passes through the third via 182 and is electrically connected to the third conductive block 172.

[0115] Please see Figure 4I The material of the pixel electrode 190 may include ITO, IZO, ITO / Ag / ITO, IZO / Ag / IZO, Mo / Cu, and MoTi / Cu / MoTi.

[0116] It should be noted that the annular structure of the first electrode 121, the active part 131, the second electrode 151 and the gate 171 in this application is only one embodiment of this application. It is only necessary to make the first electrode 121, the active part 131, the second electrode 151 and the gate 171 a closed-loop structure. For example, the closed-loop structure can be a circular ring structure, an elliptical ring structure, or a ring structure in the shape of a quadrilateral or a triangle.

[0117] This application also proposes a mobile terminal, which includes a terminal body and the aforementioned display panel, wherein the terminal body and the display panel are integrated into one unit. The terminal body may include components such as a circuit board bonded to the display panel, and a cover plate disposed on the display panel. The mobile terminal may include electronic devices such as mobile phones, televisions, and laptops.

[0118] This application discloses an array substrate and a display panel. The array substrate includes a substrate, a first electrode disposed on one side of the substrate, an active portion disposed on the surface of the first electrode away from the substrate, a second electrode disposed on the surface of the active portion away from the substrate, and a gate disposed on the side of the second electrode away from the substrate. The gate and the active portion are at least partially overlapped. The first electrode, the active portion, the second electrode, and the gate form a closed-loop structure. By setting the first electrode, the active portion, the second electrode, and the gate into a closed-loop structure, and stacking the first electrode, the active portion, and the second electrode, the channel length of the transistor is reduced by using the thickness of the active portion as the channel length. At the same time, the channel width of the transistor is changed to the sum of the lengths of the inner and outer rings of the active portion, thereby increasing the channel width of the transistor and improving the mobility of the transistor.

[0119] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0120] The above provides a detailed description of an array substrate and display panel provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. An array substrate, characterized in that, include: Substrate; The first electrode is disposed on one side of the substrate; The active portion is disposed on the surface of the first electrode on the side away from the substrate; The second electrode is disposed on the surface of the active portion away from the substrate; A gate is disposed on the side of the second electrode away from the substrate, and the gate is at least partially overlapped with the active portion; The first electrode, the active part, the second electrode, and the gate are all closed-loop structures. The first electrode has multiple first hollow patterns, and the second electrode has multiple second hollow patterns. The orthographic projection of the multiple second hollow patterns on the film layer where the first electrode is located does not overlap with the multiple first hollow patterns.

2. The array substrate according to claim 1, characterized in that, The closed-loop structure is either a circular ring structure or an elliptical ring structure.

3. The array substrate according to claim 2, characterized in that, Multiple first hollow patterns are spaced apart on the first electrode, and multiple second hollow patterns are spaced apart on the second electrode; The orthographic projections of the plurality of second hollow patterns onto the film layer where the first electrode is located are arranged alternately with the plurality of first hollow patterns.

4. The array substrate according to claim 2, characterized in that, The channel length of the active part is equal to the thickness of the active part, and the channel width of the active part is the sum of the lengths of the inner ring and the outer ring of the active part.

5. The array substrate according to any one of claims 2 to 4, characterized in that, The gate includes an inner ring segment, an outer ring segment, and a connecting segment. The inner ring segment is located inside the outer ring segment, and the connecting segment connects the inner ring segment and the outer ring segment. The inner diameter of the inner ring segment is smaller than the inner diameter of the outer ring segment.

6. The array substrate according to claim 5, characterized in that, The first hollow pattern's orthographic projection on the film layer where the gate is located does not overlap with the inner ring segment and the outer ring segment, and the second hollow pattern's orthographic projection on the film layer where the gate is located does not overlap with the inner ring segment and the outer ring segment.

7. The array substrate according to claim 5, characterized in that, The orthographic projection of the connecting segment onto the film layer where the second electrode is located does not overlap with the second hollow pattern.

8. The array substrate according to claim 5, characterized in that, The inner diameter of the inner ring segment is smaller than the inner diameter of the inner ring of the first electrode, and the outer diameter of the outer ring segment is larger than the outer diameter of the outer ring of the first electrode. Wherein, the difference between the inner diameter of the inner ring of the first electrode and the inner diameter of the inner ring segment ranges from 1 micrometer to 2 micrometers, and the difference between the outer diameter of the outer ring segment and the outer diameter of the outer ring of the first electrode ranges from 1 micrometer to 2 micrometers.

9. The array substrate according to any one of claims 2 to 4, characterized in that, The array substrate further includes a buffer layer disposed on the side of the active portion away from the substrate, and the buffer layer has an opening; The second electrode is attached to the surface of the buffer layer away from the substrate and extends into the opening, and the second electrode is in contact with the surface of the active portion in the opening away from the substrate.

10. The array substrate according to claim 9, characterized in that, The array substrate further includes a gate insulating layer disposed on the side of the buffer layer away from the substrate, and the gate insulating layer covers the sidewall and bottom of the opening. The gate is disposed on the side of the gate insulating layer away from the substrate, a portion of the gate overlaps with the second electrode, and another portion of the gate extends to the sidewall and bottom of the opening.

11. A display panel, characterized in that, The display panel includes an array substrate as described in any one of claims 1 to 10 and a light-emitting component located on one side of the array substrate, wherein the array substrate and the light-emitting component are integrated into one unit.

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