A ferroelectric thin film and p-gan gate stack hemt device and method of fabrication thereof

Abstract

The present application relates to a kind of ferroelectric thin film and p-GaN gate stack HEMT device and its preparation method, it relates to high electron mobility transistor technical field, the ferroelectric thin film and p-GaN gate stack HEMT device includes: substrate, nucleation layer, buffer layer, channel layer, barrier layer, source electrode, drain electrode, gate structure, passivation layer, first via, second via, third via, source contact point, drain contact point and gate contact point, the gate structure from bottom to top respectively by p-GaN layer on the barrier layer, ferroelectric thin film layer and gate electrode stack composition;The present application can prepare ferroelectric thin film and p-GaN gate stack HEMT device, realize the switching of enhancement and depletion mode, with very large threshold voltage tuning range, and with anticlockwise hysteresis with the change of voltage sweep scanning range and pulse parameter, can further improve radio frequency performance.

Description

Technical Field

[0001] This invention relates to the field of high electron mobility transistor technology, specifically to a HEMT device with a ferroelectric thin film and a p-GaN gate stack and its fabrication method. Background Technology

[0002] GaN-based high-electron-mobility transistors (HEMTs) have been extensively studied for high-frequency and power applications due to their high electron mobility and wide bandgap. In recent years, GaN-based CMOS circuits have shown promise for developing GaN-based integrated circuits and systems with energy efficiency and high-density integration. However, the thick GaN layer and short channel effect of GaN-based HEMTs limit the possibility of GaN channel scaling. Therefore, a reconfigurable GaN-based HEMT is needed as an alternative device. Summary of the Invention

[0003] The purpose of this invention is to overcome at least one of the defects of the prior art by providing a HEMT device with ferroelectric thin film and p-GaN gate stack and its fabrication method. This device can achieve switching between enhancement and depletion modes, achieve a very large threshold voltage tuning range, and has a counterclockwise hysteresis with changes in voltage scan range and pulse parameters, which can further improve radio frequency performance.

[0004] The combination of ferroelectric materials and group III nitrides is an emerging research field. Integrating ferroelectric materials with switchable polarization orientations with HEMTs enables dynamic and non-volatile threshold voltage control for memory and reconfigurable RF / microwave applications. Furthermore, adjusting the polarization intensity of the ferroelectric layer can help deplete carriers in the channel, enabling enhancement-mode HEMTs. In addition, ferroelectric gate stacking has been shown to enhance gate controllability in the form of negative capacitance field-effect transistors. p-GaN gates are a widely adopted method for realizing normally-off GaN-based HEMTs. In this method, the conduction band of AlGaN / GaN at the channel below the gate is boosted by the p-type doped GaN at the gate, depleting the two-dimensional electron gas (2DEG) beneath the gate. Therefore, the inventors believe that the combination of suitable ferroelectric thin films with appropriately structured HEMT devices is of great significance.

[0005] The objective of this invention can be achieved through the following technical solutions:

[0006] One of the objectives of this invention is to provide a HEMT device consisting of a ferroelectric thin film and a p-GaN gate stack, comprising a substrate, and a nucleation layer, a buffer layer, a channel layer and a barrier layer stacked sequentially on the substrate, and further comprising a p-GaN layer, a ferroelectric thin film layer and a gate electrode stacked sequentially on the barrier layer.

[0007] The source electrode and drain electrode are covered on the upper surface of the buffer layer on the side away from the nucleation layer. They are arranged opposite each other and both penetrate the channel layer and the barrier layer in sequence along their vertical direction.

[0008] The source electrode, drain electrode, barrier layer, p-GaN layer, ferroelectric thin film layer and gate electrode are covered with a passivation layer.

[0009] The passivation layer has a source contact, a drain contact, and a gate contact on its upper surface. The source contact, drain contact, and gate contact are connected to the corresponding source electrode, drain electrode, and gate electrode through a conductive material disposed within the passivation layer.

[0010] Furthermore, the passivation layer has a first via, a second via, and a third via that communicate with the source electrode, the drain electrode, and the gate electrode; the source contact is connected to the source electrode through a conductive material filled in the first via; the drain contact is connected to the drain electrode through a conductive material filled in the third via; and the gate contact is connected to the gate electrode through a conductive material filled in the second via.

[0011] Furthermore, the p-GaN layer is p-type doped by doping with Mg ions, with a doping concentration of 3 × 10⁻⁶. 17 ~5×10 19 cm -3 Preferably, the thickness of the p-GaN layer is 50–100 nm.

[0012] Further, the ferroelectric thin film layer includes one or more of the following: scandium-doped aluminum nitride ferroelectric layer, lithium niobate ferroelectric layer, barium titanate ferroelectric layer, lead zirconate titanate ferroelectric layer, or zirconium-doped hafnium oxide ferroelectric layer. Preferably, the thickness of the ferroelectric thin film layer is 5–50 nm.

[0013] For HEMT devices :

[0014] In this invention, the substrate includes one or more of a Si substrate, a SiC substrate, or a sapphire substrate;

[0015] In this invention, the nucleation layer is an AlN nucleation layer;

[0016] In this invention, the buffer layer is a GaN buffer layer;

[0017] In this invention, the channel layer is a GaN channel layer;

[0018] In this invention, the barrier layer is an AlGaN barrier layer;

[0019] In this invention, the passivation layer is Si. x N y Passivation layer.

[0020] In this invention, the thickness of the nucleation layer is 20–200 nm;

[0021] In this invention, the thickness of the buffer layer is 1–5 μm;

[0022] In this invention, the thickness of the channel layer is 10–300 nm;

[0023] In this invention, the thickness of the barrier layer is 20–50 nm;

[0024] In this invention, the thickness of the passivation layer is 120–200 nm.

[0025] In this invention, the material of the gate electrode includes one or more of Mo, Ni, Ti, or Au;

[0026] In this invention, the source electrode and drain electrode are made of one or more of Ti, Al, Ni or Au.

[0027] In this invention, the conductive material is made of one or more of Au, Cu, Ni, Wu, Al, or Ti.

[0028] A second objective of this invention is a method for fabricating a HEMT device consisting of a ferroelectric thin film and a p-GaN gate stack as described in any one of claims 1-9, characterized in that it comprises:

[0029] S1. From bottom to top, a substrate, a nucleation layer, and a buffer layer are sequentially arranged to obtain an epitaxial wafer;

[0030] S2. A channel layer and a barrier layer are grown on the epitaxial wafer by metal-organic chemical vapor deposition (MOCVD).

[0031] S3. Photoresist is applied to the barrier layer and exposed and developed at the source and drain. Then, inductively coupled plasma reactive ion etching (ICP-RIE) is performed to form the source and drain regions. Then, source and drain metals are deposited by electron beam evaporation. The metals are removed and annealed in a nitrogen atmosphere at at least 600°C for at least 5 minutes to form ohmic contacts, thereby forming the source and drain electrodes.

[0032] S4. A GaN layer is deposited on the buffer layer by metal-organic chemical vapor deposition, dopant ions are implanted into the GaN layer and annealed to form a p-GaN layer.

[0033] S5. A ferroelectric thin film layer is deposited on the p-GaN layer using physical vapor deposition (PVD), and then a gate metal is deposited to form the gate electrode.

[0034] S6. Use the gate as a self-aligned mask for chemical etching to preserve the gate structure region;

[0035] S7. A passivation layer is deposited using plasma-enhanced chemical vapor deposition (PECVD).

[0036] S8. Etch the passivation layer to form the first through-hole, the second through-hole and the third through-hole, and deposit conductive material into the three through-holes;

[0037] S9. Deposit and pattern conductive material on the passivation layer to form source contact, drain contact and gate contact, thus obtaining a HEMT device with ferroelectric thin film and p-GaN gate stack.

[0038] Compared with existing technologies, this invention can fabricate HEMT devices with ferroelectric thin films and p-GaN gate stacks, realize the switching between enhancement and depletion modes, have a very large threshold voltage tuning range, and exhibit counterclockwise hysteresis with changes in voltage scan range and pulse parameters, which can further improve RF performance. Attached Figure Description

[0039] Figure 1 This is a side view of the epitaxial wafer provided in an embodiment of the present invention;

[0040] Figure 2 This is a side view of a trench layer and a barrier layer grown on an epitaxial wafer in an embodiment of the present invention;

[0041] Figure 3 This is a side view of the etching of the source and drain regions and the deposition of the source and drain electrodes in an embodiment of the present invention.

[0042] Figure 4 This is a side view of a p-GaN layer grown on a barrier layer in an embodiment of the present invention;

[0043] Figure 5 This is a side view of the ferroelectric thin film layer and gate electrode grown on the p-GaN layer in an embodiment of the present invention;

[0044] Figure 6 This is a side view of the gate structure etched using the gate as a self-aligned mask in an embodiment of the present invention.

[0045] Figure 7 This is a side view of the growth of the passivation layer in an embodiment of the present invention;

[0046] Figure 8 This is a side view of the etched through-hole in an embodiment of the present invention;

[0047] Figure 9 A side view showing the filling of conductive material in an embodiment of the present invention;

[0048] Figure 10 This is a graphical side view of the conductive material in an embodiment of the present invention;

[0049] The labels in the figure are as follows: 101: Substrate; 102: Nucleation layer; 103: Buffer layer; 104: Channel layer; 105: Barrier layer; 106: Source electrode; 107: Drain electrode; 201: p-GaN layer; 202: Ferroelectric thin film layer; 203: Gate electrode; 108: Passivation layer; 1081: First via; 1082: Second via; 1083: Third via; 1091: Source contact; 1092: Gate contact; 1093: Drain contact. Detailed Implementation

[0050] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments. These embodiments are implemented based on the technical solution of the present invention, providing detailed implementation methods and specific operating procedures. However, the scope of protection of the present invention is not limited to the following embodiments.

[0051] A HEMT device consisting of a ferroelectric thin film and a p-GaN gate stack includes a substrate 101, and a nucleation layer 102, a buffer layer 103, a channel layer 104 and a barrier layer 105 stacked sequentially on the substrate 101. It also includes a p-GaN layer 201, a ferroelectric thin film layer 202 and a gate electrode 203 stacked sequentially on the barrier layer 105. A source electrode 106 and a drain electrode 107 are disposed opposite to each other on the upper surface of the buffer layer 103 on the side away from the nucleation layer 102, and both penetrate the channel layer 104 and the barrier layer 105 sequentially along their vertical direction.

[0052] A passivation layer 108 covers the source electrode 106, drain electrode 107, barrier layer 105, p-GaN layer 201, ferroelectric thin film layer 202, and gate electrode 203. A source contact point 1091, a drain contact point 1093, and a gate contact point 1092 are provided on the upper surface of the passivation layer. The source contact point 1091, drain contact point 1093, and gate contact point 1092 are connected to the corresponding source electrode 106, drain electrode 107, and gate electrode 203 through a conductive material disposed in the passivation layer.

[0053] More specifically, the passivation layer has a first via 1081, a second via 1082, and a third via 1083 that communicate with the source electrode 106, the drain electrode 107, and the gate electrode 203; the source contact 1091 is connected to the source electrode 106 through a conductive material filled in the first via 1081; the drain contact 1093 is connected to the drain electrode 107 through a conductive material filled in the third via 1083; and the gate contact 1092 is connected to the gate electrode 203 through a conductive material filled in the second via 1082.

[0054] Example

[0055] like Figure 10 As shown, this embodiment provides a HEMT device stacked with a ferroelectric thin film and a p-GaN gate, comprising:

[0056] Substrate 101, nucleation layer 102, buffer layer 103, channel layer 104, barrier layer 105, source electrode 106, drain electrode 107, p-GaN layer 201, ferroelectric thin film layer 202, gate electrode 203, passivation layer 108, first via 1081, second via 1082, third via 1083, source contact 1091, gate contact 1092, and drain contact 1093.

[0057] The nucleation layer 102 is grown on the substrate 101, the buffer layer 103 is grown on the nucleation layer 102, the channel layer 104 is grown on the buffer layer 103, the barrier layer 105 is grown on the channel layer 104, and the passivation layer 108 is grown on the barrier layer 105. The gate structure is located inside the passivation layer 108, and the gate structure, from bottom to top, consists of a p-GaN layer 201, a ferroelectric thin film layer 202, and a gate electrode 203 on the barrier layer 105. The passivation layer 108 is stacked, and three vias are etched at corresponding positions of the source electrode 106, drain electrode 107, and gate electrode 203, namely the first via 1081, the third via 1083, and the second via 1082. The three vias are filled with conductive material, so that the source electrode 106, drain electrode 107, and gate electrode 203 are connected to the source contact point 1091, drain contact point 1093, and gate contact point on the outer surface of the passivation layer, respectively, 1092.

[0058] In this embodiment, the substrate 101 is made of silicon, silicon carbide, or sapphire. The nucleation layer 102 is an AlN nucleation layer with a thickness of 20–200 nm. The buffer layer 103 is a GaN buffer layer with a thickness of 1–5 μm. The channel layer 104 is a GaN channel layer with a thickness of 10–300 nm. The barrier layer 105 is an AlGaN barrier layer with a thickness of 20–50 nm. The p-GaN layer 201 has a thickness of 50–100 nm and is p-type doped by incorporating Mg ions with a doping concentration of 3 × 10⁻⁶. 17 ~5×10 19 cm -3 The ferroelectric thin film layer 202 includes scandium-doped aluminum nitride (Al). 1-x Sc x N) Ferroelectric layer, lithium niobate (LiNbO3) ferroelectric layer, barium titanate (BaTiO3) ferroelectric layer, lead zirconate titanate (PbZr) x Ti 1-x O3) ferroelectric layer and zirconium-doped hafnium oxide (Hf) x Zr 1-x The O2 ferroelectric layer has a thickness of 5–50 nm. The passivation layer 108 is made of Si. x N y The thickness is 120–200 nm.

[0059] Please refer to the following: Figure 1-10 The present invention also provides a method for fabricating a HEMT device consisting of a ferroelectric thin film and a p-GaN gate stack, comprising:

[0060] S1. Obtain an epitaxial wafer; the epitaxial wafer includes, from bottom to top, a substrate 101, a nucleation layer 102, and a buffer layer 103, as shown below. Figure 1 As shown;

[0061] S2. A channel layer 104 and a barrier layer 105 are grown on the buffer layer 103 using metal-organic chemical vapor deposition (MOCVD), as follows: Figure 2 As shown;

[0062] S3. Apply photoresist and expose and develop at the source and drain electrodes. Then, perform inductively coupled plasma reactive ion etching (ICP-RIE) to create the source and drain regions. Next, deposit source electrodes 106 and drain electrodes 107 by electron beam evaporation. Remove the electrodes and anneal them in a nitrogen atmosphere at 600°C for 5 minutes to form ohmic contacts, thus forming source electrodes 106 and drain electrodes 107. Figure 3 As shown;

[0063] S4. A GaN layer is deposited on the buffer layer using MOCVD, dopant ions are implanted into the GaN layer and annealed to form a p-GaN layer 201, as shown. Figure 4 As shown;

[0064] S5. A ferroelectric thin film layer 202 is deposited on the p-GaN layer 201 using physical vapor deposition (PVD), followed by the deposition of gate metal to form the gate electrode 203. Figure 5 As shown;

[0065] S6. Use the gate as a self-aligned mask for chemical etching, preserving the gate structure region, such as... Figure 6 As shown;

[0066] S7. A passivation layer 108 is deposited using plasma-enhanced chemical vapor deposition (PECVD), such as... Figure 7 As shown;

[0067] S8. The passivation layer 108 is etched to form a first via 1081, a second via 1082, and a third via 1083, and conductive material is deposited into the three vias, such as... Figure 8 As shown;

[0068] S9. A conductive material is deposited and patterned on the passivation layer 108 to form source contact 1091, drain contact 1093, and gate contact 1092, as shown below. Figure 9 and Figure 10 As shown.

[0069] In this embodiment, the gate electrode 203 is made of at least one of Mo, Ni, Ti, or Au. The source electrode 106 and drain electrode 107 are both made of at least one of Ti, Al, Ni, or Au. The conductive material is made of at least one of Au, Cu, Ni, Wu, Al, or Ti.

[0070] The device prepared in this embodiment has the following beneficial effects:

[0071] This embodiment fabricates a reconfigurable GaN-based HEMT device by stacking a ferroelectric thin film with a p-GaN gate. On one hand, the conduction band of the AlGaN / GaN at the channel below the gate is boosted to a quasi-Fermi level above electrons by the p-type doped GaN at the gate, depleting the 2DEG in the channel below the gate. This makes the device a normally-off device, thus a preferred choice for high-efficiency power supply applications. On the other hand, the high polarization intensity and switchable ferroelectric polarization of the ferroelectric thin film, together with the discontinuous polarization at the channel / barrier layer interface, modulate the channel carrier concentration. When the polarity of the ferroelectric thin film switches to the opposite polarity to that of the channel / barrier layer, the polarization of the ferroelectric thin film helps to deplete the 2DEG in the channel. When the polarity of the ferroelectric thin film switches to parallel to the polarity of the channel / barrier layer, the polarization of the ferroelectric thin film helps to attract electrons and increase the 2DEG density in the channel. The enhanced modulation of 2DEG by ferroelectric polarization enhances the controllability of the gate and improves the subthreshold oscillation beyond the basic Boltzmann limit through the so-called negative capacitance effect. This allows the device to switch between enhancement and depletion modes, achieve a very large threshold voltage tuning range, and exhibits counterclockwise hysteresis as the voltage scan range and pulse parameters change, further improving RF performance.

[0072] In summary, the HEMT device with ferroelectric thin film and p-GaN gate stack provided in this embodiment and its fabrication method can meet the needs of multiple application fields and have important practical application value.

[0073] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0074] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention in any other way. Any person skilled in the art may make changes or modifications to the above-disclosed technical content to create equivalent embodiments. However, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the protection scope of the present invention.

Claims

1. A HEMT device consisting of a ferroelectric thin film and a p-GaN gate stack, comprising a substrate (101), and a nucleation layer (102), a buffer layer (103), a channel layer (104), and a barrier layer (105) sequentially stacked on the substrate (101), characterized in that, It also includes a p-GaN layer (201), a ferroelectric thin film layer (202) and a gate electrode (203) stacked sequentially on the barrier layer (105). The source electrode (106) and drain electrode (107) are located on the upper surface of the buffer layer (103) away from the nucleation layer (102). They are arranged opposite to each other and both penetrate the channel layer (104) and the barrier layer (105) in sequence along their vertical direction. The source electrode (106), drain electrode (107), barrier layer (105), p-GaN layer (201), ferroelectric thin film layer (202) and gate electrode (203) are covered with a passivation layer (108). The passivation layer has a source contact (1091), a drain contact (1093), and a gate contact (1092) on its upper surface. The source contact (1091), drain contact (1093), and gate contact (1092) are connected to the corresponding source electrode (106), drain electrode (107), and gate electrode (203) through a conductive material disposed in the passivation layer (108). The passivation layer has a first via (1081), a second via (1082), and a third via (1083) that are connected to the source electrode (106), the drain electrode (107), and the gate electrode (203). The source contact point (1091) is connected to the source electrode (106) through a conductive material filled in the first through hole (1081); The drain contact point (1093) is connected to the drain electrode (107) through a conductive material filled in the third through hole (1083); The gate contact (1092) is connected to the gate electrode (203) through a conductive material filled in the second through hole (1082); The p-GaN layer (201) is p-type doped by doping with Mg ions, with a doping concentration of 3 × 10⁻⁶. 17 ~5×10 19 cm -3 ; The thickness of the p-GaN layer (201) is 50~100 nm; The ferroelectric thin film layer (202) includes one or more of the following: scandium-doped aluminum nitride ferroelectric layer, lithium niobate ferroelectric layer, barium titanate ferroelectric layer, lead zirconate titanate ferroelectric layer, or zirconium-doped hafnium oxide ferroelectric layer; The thickness of the ferroelectric thin film layer (202) is 5~50 nm; When the polarity of the ferroelectric thin film layer (202) is switched to be opposite to the polarity of the channel layer (104) / barrier layer (105) interface, the polarization of the ferroelectric thin film layer (202) helps to deplete the 2DEG in the channel; when the polarity of the ferroelectric thin film layer (202) is switched to be parallel to the polarity of the channel layer (104) / barrier layer (105) interface, the polarization of the ferroelectric thin film layer (202) helps to attract electrons and increase the 2DEG density in the channel.

2. The HEMT device based on a ferroelectric thin film and a p-GaN gate stack according to claim 1, characterized in that, The HEMT device satisfies at least one of the following conditions: ①The substrate (101) includes one or more of Si substrate, SiC substrate or sapphire substrate; ②The nucleation layer (102) is an AlN nucleation layer; ③The buffer layer (103) is a GaN buffer layer; ④ The channel layer (104) is a GaN channel layer; ⑤ The barrier layer (105) is an AlGaN barrier layer; ⑥ The passivation layer (108) is Si x N y Passivation layer.

3. The HEMT device based on a ferroelectric thin film and a p-GaN gate stack according to claim 1, characterized in that, The HEMT device satisfies at least one of the following conditions: ① The thickness of the nucleation layer (102) is 20~200 nm; ②The thickness of the buffer layer (103) is 1~5 μm; ③ The thickness of the channel layer (104) is 10~300 nm; ④ The thickness of the barrier layer (105) is 20~50 nm; ⑥ The thickness of the passivation layer (108) is 120~200 nm.

4. The HEMT device of ferroelectric thin film and p-GaN gate stack according to claim 1, characterized in that, The HEMT device satisfies at least one of the following conditions: ①The material of the gate electrode (203) includes one or more of Mo, Ni, Ti or Au; ②The source electrode (106) and drain electrode (107) are made of one or more of Ti, Al, Ni or Au; ③ The conductive material includes one or more of Au, Cu, Ni, Wu, Al, or Ti.

5. A method for fabricating a HEMT device stacked with a ferroelectric thin film and a p-GaN gate as described in any one of claims 1-4, characterized in that, include: S1. A substrate (101), a nucleation layer (102), and a buffer layer (103) are sequentially arranged from bottom to top to obtain an epitaxial wafer; S2. A channel layer (104) and a barrier layer (105) are grown on the epitaxial wafer by metal-organic chemical vapor deposition. S3. Photoresist is applied to the barrier layer (105) and exposed and developed at the source and drain. Then, inductively coupled plasma reactive ion etching is performed to form the source and drain regions. Then, source and drain metals are deposited by electron beam evaporation. The metals are removed and annealed in a nitrogen atmosphere at at least 600°C for at least 5 minutes to form ohmic contacts, thereby forming the source electrode (106) and drain electrode (107). S4. A GaN layer is deposited on the buffer layer by metal-organic chemical vapor deposition, doped ions are implanted into the GaN layer and annealed to form a p-GaN layer (201). S5. A ferroelectric thin film layer (202) is deposited on the p-GaN layer (201) by physical vapor deposition, and then a gate metal is deposited to form a gate electrode (203). S6. Use the gate as a self-aligned mask for chemical etching to preserve the gate structure region; S7. A passivation layer (108) is deposited using plasma-enhanced chemical vapor deposition. S8. Etch the passivation layer to form the first via (1081), the second via (1082) and the third via (1083), and deposit conductive material into the three vias; S9. A conductive material is deposited and patterned on the passivation layer (108) to form a source contact (1091), a drain contact (1093), and a gate contact (1092), thus obtaining a HEMT device with a ferroelectric thin film and a p-GaN gate stack.

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