A lateral variable doping channel enhancement type gallium oxide MOS device and its preparation method

Abstract

The present invention discloses a lateral variable doping channel enhancement type gallium oxide MOS device and a preparation method thereof, which relates to the technical field of semiconductor devices, and includes, from bottom to top, an Fe-doped semi-insulating substrate, an unintentionally doped UID layer, and a Si-doped conductive channel region; a p-doped region is arranged on the left side of the Si-doped conductive channel region, an n+ region is arranged on the left side of the p-doped region, an n-type doped region is arranged on the right side of the Si-doped conductive channel region, an n+ region is arranged on the right side of the n-type doped region, and a source metal, a gate dielectric, a drain metal, and a gate metal are arranged above the Si-doped conductive channel region. In the device and its preparation method, the lateral planar structure of the gate improves the stability of the device in a high temperature environment; through the optimization of the internal doping gradient, an excellent balance between low resistance and high withstand voltage is achieved, and the application range is expanded; the formed pn junction effectively shuts off the leakage current when it is not turned on, and improves the electrical performance of the device.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a lateral variable doping channel enhancement type gallium oxide MOS device and a preparation method thereof. Background Art

[0002] Gallium oxide (GaN) semiconductor materials have shown great application potential in high-frequency and high-power electronic devices due to their excellent thermal stability, high electron mobility and large bandgap characteristics. Existing GaN-based MOS devices mostly use a vertical structure. Although these devices perform well in high-voltage applications, their complex manufacturing process and limitations in gate control accuracy are still obstacles to technological progress. In addition, traditional vertical structure devices are prone to current leakage and breakdown problems under high voltage, limiting the further improvement of device performance.

[0003] In this case, the present invention proposes a lateral variable doping channel enhancement type gallium oxide MOS device. This new structure adopts a lateral planar gate design, which effectively improves the reliability of the gate, and optimizes the structure of the conductive channel through lateral variable doping technology, achieving the dual advantages of low on-resistance and high withstand voltage. In addition, the design adopts a specific doping gradient and pn structure, which effectively suppresses the leakage current in the non-conducting state and significantly improves the switching ratio and overall performance of the device. Summary of the invention

[0004] In view of the deficiencies in the prior art, the present invention provides a lateral variable doping channel enhancement gallium oxide MOS device and a preparation method thereof to solve the problems raised in the above background technology.

[0005] To achieve the above object, the present invention provides the following technical solution: a laterally variable doped channel enhanced gallium oxide MOS device, comprising an Fe-doped semi-insulating substrate, the Fe-doped semi-insulating substrate being located at the bottom of the device, an unintentionally doped UID layer being disposed above the Fe-doped semi-insulating substrate, and a Si-doped conductive channel region being disposed above the unintentionally doped UID layer;

[0006] A p-doped region is disposed on the left side of the Si-doped conductive channel region, an n+ region is disposed on the left side of the p-doped region, an n-type doped region is disposed on the right side of the Si-doped conductive channel region, and an n+ region is disposed on the right side of the n-type doped region;

[0007] A source metal and a drain metal are respectively arranged above the n+ region, a gate dielectric located above the Si-doped conductive channel region, the n-type doped region and the p-doped region is arranged between the source metal and the drain metal, and a gate metal is arranged above the gate dielectric.

[0008] To further optimize the technical solution, the p-doped region is not only arranged in the Si-doped conductive channel region, but also in the unintentionally doped UID layer;

[0009] Although the unintentionally doped UID layer is not intentionally doped, it has low-concentration Si doping due to diffusion, and a pn junction is formed through the distribution of the p-doped region inside it.

[0010] To further optimize the technical solution, the thickness of the Fe-doped semi-insulating substrate is 2 μm, the thickness of the unintentionally doped UID layer is 600 nm, the thickness of the Si-doped conductive channel region is 100 nm, the thickness of the p-doped region is 400 nm, and the thickness of the gate dielectric is 20 nm.

[0011] Further optimizing the technical solution, the doping concentration of the unintentionally doped UID layer is 2×10 16 cm -3 The doping concentration of the Si-doped conductive channel region is 1×10 17 cm -3 The doping concentration of the n+ region is 8×10 18 cm -3 The doping concentration of the n-type doping region is 2×10 18 cm -3 The doping concentration of the p-doped region is 5×10 18 cm -3 .

[0012] To further optimize the technical solution, the source metal and the drain metal both adopt a Ti-Au double-layer metal structure, the gate metal is a Ni material, the gate dielectric is an aluminum oxide material, and the thickness of the gate dielectric is 20 nm.

[0013] A method for preparing a lateral variable doping channel enhancement type gallium oxide MOS device is prepared based on the above-mentioned lateral variable doping channel enhancement type gallium oxide MOS device, comprising the following specific steps:

[0014] S1, growing an unintentionally doped UID layer on an Fe-doped semi-insulating substrate by hydride vapor phase epitaxy;

[0015] S2, epitaxially growing a layer of Si-doped conductive channel region on the unintentionally doped UID layer by MOCVD;

[0016] S3, depositing a barrier layer on the Si-doped conductive channel region, etching a through hole in the n+ region, and implanting Mg ions into the Si-doped conductive channel region, with an ion implantation energy of 10-40kev;

[0017] S4, removing the barrier layer formed in step S3, depositing a new barrier layer on the Si-doped conductive channel region and the n+ region, etching a through hole in the n-type doped region, and implanting Si ions into the Si-doped conductive channel region, with an ion implantation energy of 10-40kev;

[0018] S5, removing the barrier layer formed in step S4, depositing a new barrier layer on the Si-doped conductive channel region, the n-type doped region and the n+ region, etching a through hole in the p-doped region, and implanting Si ions into the Si-doped conductive channel region, with an ion implantation energy of 10-140kev;

[0019] S6, removing the barrier layer in step S5, re-depositing a new barrier layer on the n+ region, and etching out a gate dielectric region;

[0020] S7, removing the barrier layer in step S6, re-depositing a new barrier layer on the gate dielectric, and etching source metal and drain metal through holes;

[0021] S8, removing the barrier layer in step S7, depositing a new barrier layer, etching out a gate metal region, and depositing a gate metal.

[0022] The technical solution is further optimized. In step S1, the growth conditions are 900°C, the molar fraction of GaCl is 0.5; the intake speed of O2 is 0.03m / s; the molar fraction of O2 is 0.5; the intake speed of the separation gas N2 is 2.8m / s; and the distance between the Fe-doped semi-insulating substrate and the nozzle is 15cm.

[0023] To further optimize the technical solution, in step S2, under the growth condition of 860° C., triethylgallium is used as the organic source, high-purity oxygen is used as the oxygen source as the reaction source, SiH4 is used as the doped Si source, and high-purity argon is used as the carrier gas for the organic source and the doping gas.

[0024] To further optimize the technical solution, in step S6, the aluminum metal organic matter is gasified at 1200° C. and then introduced into the square gallium oxide material reaction chamber together with carrier gas and oxygen to cause a chemical reaction, and the reaction product is deposited on the upper surface of the device to form an aluminum oxide film.

[0025] To further optimize the technical solution, in step S7, magnetron sputtering is used along the through hole. In an argon atmosphere, high pressure produces glow discharge on the argon gas, which hits the Ti metal target, causing it to splash and deposit on the upper surface of the device. The sputtering time is 5 minutes. After 5 minutes, the Ti metal target is replaced with an Au metal target, and the sputtering time is 1 minute.

[0026] Compared with the prior art, the present invention provides a lateral variable doping channel enhancement gallium oxide MOS device and a preparation method thereof, which has the following beneficial effects:

[0027] The lateral variable doping channel enhancement gallium oxide MOS device and its preparation method, the lateral planar structure of the gate improves the stability and reliability of the device in a high temperature environment; through the optimization of the internal doping gradient, an excellent balance between low resistance and high withstand voltage is achieved, and the application range of the device is expanded; the formed pn junction effectively shuts off the leakage current when not conducting, significantly improving the electrical performance of the device, especially the performance in high voltage applications; the device not only provides an important improvement on the traditional GaN device structure, but also opens up a new path for the development of high-performance electronic devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A schematic cross-sectional view of a laterally variable doping channel enhancement type gallium oxide MOS device proposed by the present invention;

[0029] Figure 2 A schematic cross-sectional view of a device in step S1 of a method for preparing a laterally variable doped channel-enhanced gallium oxide MOS device proposed in the present invention;

[0030] Figure 3 A schematic cross-sectional view of a device in step S2 of a method for preparing a laterally variable doped channel-enhanced gallium oxide MOS device proposed by the present invention;

[0031] Figure 4 A schematic cross-sectional view of a device in step S3 of a method for preparing a laterally variable-doped channel-enhanced gallium oxide MOS device proposed in the present invention;

[0032] Figure 5 A schematic cross-sectional view of a device in step S4 of a method for preparing a laterally variable doped channel-enhanced gallium oxide MOS device proposed by the present invention;

[0033] Figure 6 It is a schematic cross-sectional view of a device in step S5 of a method for preparing a laterally variable doped channel-enhanced gallium oxide MOS device proposed by the present invention;

[0034] Figure 7 A schematic cross-sectional view of a device in step S6 of a method for preparing a laterally variable doped channel-enhanced gallium oxide MOS device proposed in the present invention;

[0035] Figure 8 A schematic cross-sectional view of a device in step S7 of a method for preparing a laterally variable doped channel-enhanced gallium oxide MOS device proposed by the present invention;

[0036] Fig. 9It is a schematic cross-sectional view of a device in step S8 of a method for preparing a laterally variable doping channel enhancement gallium oxide MOS device proposed by the present invention.

[0037] In the figure: 1. Fe-doped semi-insulating substrate; 2. Unintentionally doped UID layer; 3. Si-doped conductive channel region; 4. n+ region; 5. n-type doped region; 6. p-doped region; 7. source metal; 8. gate dielectric; 9. gate metal; 10. drain metal. DETAILED DESCRIPTION

[0038] The following will be combined with the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Example

[0039] See also Figure 1 , a laterally variable doped channel enhanced gallium oxide MOS device, the device adopts a laterally variable doped channel, and by constructing a concentration gradient of the conductive channel, it can reduce the on-resistance of the device while improving the withstand voltage of the device, including an Fe-doped semi-insulating substrate 1, the Fe-doped semi-insulating substrate 1 is located at the bottom of the device, and is used to support the device to complete subsequent processes and reduce the substrate leakage of the device, an unintentionally doped UID layer 2 is arranged above the Fe-doped semi-insulating substrate 1, which is a buffer layer for the device substrate and structure, and prevents defects of the device substrate from being introduced into a Si-doped conductive channel region 3, but due to the diffusion effect of the Si-doped conductive channel region 3, low-concentration doping will be generated inside it, and a Si-doped conductive channel region 3 is arranged above the unintentionally doped UID layer 2, which is the conductive layer of the device and includes the gate control region of the device.

[0040] The left side of the Si-doped conductive channel region 3 is provided with a p-doped region 6 for achieving both low on-resistance and high withstand voltage of the device, the left side of the p-doped region 6 is provided with an n+ region 4, the right side of the Si-doped conductive channel region 3 is provided with an n-type doped region 5, and the right side of the n-type doped region 5 is provided with an n+ region 4. The n+ region 4 is to form a low-resistance ohmic contact with the source and drain and reduce the low resistance of the device from the source (and drain) to the device gate to control the conductive channel, thereby reducing the overall on-resistance of the device.

[0041] The p-doped region 6 is not only arranged in the Si-doped conductive channel region 3, but also in the unintentionally doped UID layer 2. Although the unintentionally doped UID layer 2 is not intentionally doped, it has low-concentration Si doping due to diffusion, and a pn junction is formed through the distribution of the p-doped region 6 inside it. This allows the leakage current of the unintentionally doped UID layer 2 to be turned off when the device is not turned on, thereby improving the device switching ratio.

[0042] A source metal 7 and a drain metal 10 are respectively arranged above the n+ region 4, a gate dielectric 8 is arranged between the source metal 7 and the drain metal 10 and is located above the Si-doped conductive channel region 3, the n-type doped region 5 and the p-doped region 6, and a gate metal 9 is arranged above the gate dielectric 8.

[0043] When a positive voltage is applied to the gate of the device, inversion begins from the p-doped region 6 close to the gate side to form an electron channel, forming a full electron conductive channel from the source to the drain, and the device is turned on.

[0044] The source metal 7 and the drain metal 10 both adopt a Ti-Au double-layer metal structure. This is because the work function difference between Ti metal and gallium oxide is small, and it is easier to form an ohmic contact. Au is used to prevent oxidation on the surface of the device. The gate metal 9 is selected to improve the high temperature resistance of the device gate. The gate metal 9 is Ni material, the gate dielectric is aluminum oxide material, and the thickness of the gate dielectric is 20nm.

[0045] Among them, the thickness of the Fe-doped semi-insulating substrate 1 is 2 μm, the thickness of the unintentionally doped UID layer 2 is 600 nm, the thickness of the Si-doped conductive channel region 3 is 100 nm, the thickness of the p-doped region 6 is 400 nm, and the thickness of the gate dielectric 8 is 20 nm.

[0046] The doping concentration of the unintentionally doped UID layer 2 is 2×10 16 cm -3 The doping concentration of the Si-doped conductive channel region 3 is 1×10 17 cm -3 The doping concentration of the n+ region 4 is 8×10 18 cm -3 The doping concentration of the n-type doping region 5 is 2×10 18 cm -3 The doping concentration of the p-doped region 6 is 5×10 18 cm -3 . Example

[0047] A method for preparing a lateral variable doping channel enhancement type gallium oxide MOS device is prepared based on the lateral variable doping channel enhancement type gallium oxide MOS device described in Example 1, and comprises the following specific steps:

[0048] S1, such as Figure 2 As shown, a non-intentionally doped UID layer 2 is grown on a Fe-doped semi-insulating substrate 1 using a hydride vapor phase epitaxy method.

[0049] The growth conditions are 900°C, the molar fraction of GaCl is 0.5; the intake speed of O2 is 0.03m / s; the molar fraction of O2 is 0.5; the intake speed of the separation gas N2 is 2.8m / s; and the distance between the Fe-doped semi-insulating substrate 1 and the nozzle is 15cm.

[0050] S2, such as Figure 3 As shown, a Si-doped conductive channel region 3 is epitaxially grown on the unintentionally doped UID layer 2 by using the MOCVD method.

[0051] Under the growth condition of 860° C., triethylgallium (TEGa) is used as the organic source, high-purity oxygen (6N) is used as the oxygen source as the reaction source, SiH4 is used as the doped Si source, and high-purity argon (6N) is used as the carrier gas for the organic source and the doping gas.

[0052] S3, such as Figure 4 As shown, a barrier layer is deposited on the Si-doped conductive channel region 3, a through hole of the n+ region 4 is etched, and Mg ions are implanted into the Si-doped conductive channel region 3, and the ion implantation energy is 10-40kev.

[0053] S4, such as Figure 5 As shown, the barrier layer formed in step S3 is removed, a new barrier layer is deposited on the Si-doped conductive channel region 3 and the n+ region 4, a through hole of the n-type doped region 5 is etched, and Si ions are implanted into the Si-doped conductive channel region 3, with an ion implantation energy of 10-40kev.

[0054] S5, such as Figure 6 As shown, the barrier layer formed in step S4 is removed, a new barrier layer is deposited on the Si-doped conductive channel region 3, the n-type doped region 5 and the n+ region 4, a through hole of the p-doped region 6 is etched, and Si ions are implanted into the Si-doped conductive channel region 3, and the ion implantation energy is 10-140kev.

[0055] S6, such as Figure 7 As shown, the barrier layer in step S5 is removed, a new barrier layer is re-deposited on the n+ region 4, and the region of the gate dielectric 8 is etched out.

[0056] At 1200°C (in order to increase the deposition rate of aluminum oxide), the aluminum metal organic matter is vaporized and then introduced into the square gallium oxide material reaction chamber together with a carrier gas (usually argon) and oxygen (the ratio of aluminum metal organic matter to oxygen is 1:1), whereupon a chemical reaction occurs and the reaction products are deposited on the upper surface of the device to form an aluminum oxide film.

[0057] S7, such as Figure 8 As shown, the barrier layer in step S6 is removed, a new barrier layer is re-deposited on the gate dielectric 8, and source metal 7 and drain metal 10 through holes are etched.

[0058] Magnetron sputtering is adopted along the through hole. In an argon atmosphere, high voltage produces glow discharge on argon gas, which hits the Ti metal target, causing it to splash and deposit on the upper surface of the device. The sputtering time is 5 minutes. After 5 minutes, the Ti metal target is replaced with an Au metal target, and the sputtering time is 1 minute.

[0059] S8, such as Fig. 9 As shown, the barrier layer in step S7 is removed, a new barrier layer is deposited, the region of the gate metal 9 is etched out, and the gate metal 9 is deposited.

[0060] The beneficial effects of the present invention are:

[0061] The lateral variable doping channel enhancement gallium oxide MOS device and its preparation method, the lateral planar structure of the gate improves the stability and reliability of the device in a high temperature environment; through the optimization of the internal doping gradient, an excellent balance between low resistance and high withstand voltage is achieved, and the application range of the device is expanded; the formed pn junction effectively shuts off the leakage current when not conducting, significantly improving the electrical performance of the device, especially the performance in high voltage applications; the device not only provides an important improvement on the traditional GaN device structure, but also opens up a new path for the development of high-performance electronic devices.

[0062] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0063] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A laterally variable doped channel enhanced gallium oxide MOS device, characterized in that: It comprises an Fe-doped semi-insulating substrate, wherein the Fe-doped semi-insulating substrate is located at the bottom of the device, an unintentionally doped UID layer is arranged above the Fe-doped semi-insulating substrate, and a Si-doped conductive channel region is arranged above the unintentionally doped UID layer; A p-doped region is disposed on the left side of the Si-doped conductive channel region, an n+ region is disposed on the left side of the p-doped region, an n-type doped region is disposed on the right side of the Si-doped conductive channel region, and an n+ region is disposed on the right side of the n-type doped region; A source metal and a drain metal are respectively arranged above the n+ region, a gate dielectric located above the Si-doped conductive channel region, the n-type doped region and the p-doped region is arranged between the source metal and the drain metal, and a gate metal is arranged above the gate dielectric; The p-doped region is not only arranged in the Si-doped conductive channel region, but also in the unintentionally doped UID layer; Although the unintentionally doped UID layer is not intentionally doped, it has low-concentration Si doping due to diffusion, and a pn junction is formed through the distribution of the p-doped region inside it.

2. A laterally variable doped channel enhanced gallium oxide MOS device according to claim 1, characterized in that: The thickness of the Fe-doped semi-insulating substrate is 2 μm, the thickness of the unintentionally doped UID layer is 600 nm, the thickness of the Si-doped conductive channel region is 100 nm, the thickness of the p-doped region is 400 nm, and the thickness of the gate dielectric is 20 nm.

3. The laterally variable doped channel enhanced gallium oxide MOS device according to claim 1, characterized in that: The doping concentration of the unintentionally doped UID layer is 2×10 16 cm -3 The doping concentration of the Si-doped conductive channel region is 1×10 17 cm -3 The doping concentration of the n+ region is 8×10 18 cm -3 The doping concentration of the n-type doping region is 2×10 18 cm -3 The doping concentration of the p-doped region is 5×10 18 cm -3 .

4. The laterally variable doped channel enhanced gallium oxide MOS device according to claim 1, characterized in that: The source metal and the drain metal both adopt a Ti-Au double-layer metal structure, the gate metal is a Ni material, the gate dielectric is an aluminum oxide material, and the thickness of the gate dielectric is 20 nm.

5. A method for preparing a lateral variable doping channel enhancement type gallium oxide MOS device, based on the lateral variable doping channel enhancement type gallium oxide MOS device according to any one of claims 1 to 4, characterized in that: The specific steps include: S1, growing an unintentionally doped UID layer on an Fe-doped semi-insulating substrate by hydride vapor phase epitaxy; S2, epitaxially growing a layer of Si-doped conductive channel region on the unintentionally doped UID layer by MOCVD; S3, depositing a barrier layer on the Si-doped conductive channel region, etching a through hole in the n+ region, and implanting Mg ions into the Si-doped conductive channel region, with an ion implantation energy of 10-40kev; S4, removing the barrier layer formed in step S3, depositing a new barrier layer on the Si-doped conductive channel region and the n+ region, etching a through hole in the n-type doped region, and implanting Si ions into the Si-doped conductive channel region, with an ion implantation energy of 10-40kev; S5, removing the barrier layer formed in step S4, depositing a new barrier layer on the Si-doped conductive channel region, the n-type doped region and the n+ region, etching a through hole in the p-doped region, and implanting Si ions into the Si-doped conductive channel region, with an ion implantation energy of 10-140kev; S6, removing the barrier layer in step S5, re-depositing a new barrier layer on the n+ region, and etching out a gate dielectric region; S7, removing the barrier layer in step S6, re-depositing a new barrier layer on the gate dielectric, and etching source metal and drain metal through holes; S8, removing the barrier layer in step S7, depositing a new barrier layer, etching out a gate metal region, and depositing a gate metal.

6. The method for preparing a lateral variable doping channel enhancement gallium oxide MOS device according to claim 5, characterized in that: In step S1, the growth conditions are 900° C., the molar fraction of GaCl is 0.5; the intake speed of O2 is 0.03 m / s; the molar fraction of O2 is 0.5; the intake speed of the separation gas N2 is 2.8 m / s; and the distance between the Fe-doped semi-insulating substrate and the nozzle is 15 cm.

7. The method for preparing a lateral variable doping channel enhancement type gallium oxide MOS device according to claim 5, characterized in that: In the step S2, under the growth condition of 860° C., triethylgallium is used as the organic source, high-purity oxygen is used as the oxygen source as the reaction source, SiH4 is used as the doped Si source, and high-purity argon is used as the carrier gas for the organic source and the doping gas.

8. The method for preparing a lateral variable doping channel enhancement type gallium oxide MOS device according to claim 5, characterized in that: In step S6, the aluminum metal organic matter is gasified at 1200° C. and then introduced into the square gallium oxide material reaction chamber together with carrier gas and oxygen to cause a chemical reaction, and the reaction product is deposited on the upper surface of the device to form an aluminum oxide film.

9. The method for preparing a lateral variable doping channel enhancement type gallium oxide MOS device according to claim 5, characterized in that: In step S7, magnetron sputtering is used along the through hole. In an argon atmosphere, high voltage produces glow discharge on the argon gas, which hits the Ti metal target, causing it to splash and deposit on the upper surface of the device. The sputtering time is 5 minutes. After 5 minutes, the Ti metal target is replaced with an Au metal target, and the sputtering time is 1 minute.

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