A voltage loss protection circuit for electric energy meter

Abstract

The invention discloses a voltage loss protection circuit for an electric energy meter, comprising a first operational amplifier, a second trigger, a third operational amplifier, a fourth operational amplifier, a second field effect tube, a third resistor, an eighth resistor, a first diode and a second diode; the first operational amplifier inverting end is connected to the third operational amplifier inverting end and a J1 end, the first operational amplifier output end is connected to the second diode anode, the second diode cathode is connected to the first diode cathode, one end of the third resistor and the third pin of the second trigger, the second pin of the second trigger is connected to the second trigger sixth pin, the second trigger fifth pin is connected to the second field effect tube base, the second field effect tube drain is connected to the third operational amplifier output end, the second field effect tube source is connected to the fourth operational amplifier inverting end and one end of the eighth resistor, and the fourth operational amplifier output end is connected to the first diode anode.

Description

Technical Field

[0001] The present invention relates to the technical field of electric power detection, and in particular to a voltage loss protection circuit for an electric energy meter. Background Art

[0002] Voltage loss is one of the working conditions for power theft detection. According to the DL / T556 standard, if the current phase voltage is lower than 78% of the upper limit of the voltage trigger of the voltage loss event and the time is greater than 60 seconds, it can be determined that the current state is in a voltage loss state. The recovery standard requires the phase voltage to recover to 85% of the lower limit of the voltage recovery within a certain period of time. At this time, it can be determined that the current state is a normal power supply state. By setting reference signals for the upper and lower limits and comparing the current voltage, if it is lower than the upper limit of the voltage trigger of the voltage loss event, the timing will begin, and if it is higher than the lower limit of the voltage recovery, the timing will stop. However, the problem is that the voltage loss fluctuations are not all caused by power theft. For example, equipment startup, direct large-area power supply without classification after power failure, etc. will also cause voltage loss. When the voltage loss is between the two and then recovers to the lower limit of the voltage recovery, it will cause a signal fault indication. Summary of the invention

[0003] In view of the above technical problems, the object of the present invention is to provide an electric energy meter undervoltage protection circuit, including a first operational amplifier U1, a second trigger U2, a third operational amplifier U3, a fourth operational amplifier U4, a second field effect transistor Q2, a third resistor R3, an eighth resistor R8, a first diode D1, and a second diode D2;

[0004] The inverting end of the first operational amplifier U1 is connected to the non-inverting end of the third operational amplifier U3 and the J1 end, the output end of the first operational amplifier U1 is connected to the anode of the second diode D2, the cathode of the second diode D2 is connected to the cathode of the first diode D1, one end of the third resistor R3, and the third pin of the second trigger U2, the second pin of the second trigger U2 is connected to the sixth pin of the second trigger U2, the fifth pin of the second trigger U2 is connected to the base of the second field effect transistor Q2, the drain of the second field effect transistor Q2 is connected to the output end of the third operational amplifier U3, the source of the second field effect transistor Q2 is connected to the non-inverting end of the fourth operational amplifier U4 and one end of the eighth resistor R8, the output end of the fourth operational amplifier U4 is connected to the anode of the first diode D1, and the other end of the third resistor R3 and the other end of the eighth resistor R8 are connected to the ground end.

[0005] Furthermore, it also includes a fifth operational amplifier U5, a sixth inverter U6, a first transistor Q1, a third transistor Q3, a ninth resistor R9, and a first capacitor C1;

[0006] The collector of the first transistor Q1 is connected to the power supply, the base of the first transistor Q1 is connected to the output end of the sixth inverter U6, the emitter of the first transistor Q1 is connected to one end of the ninth resistor R9, the input end of the sixth inverter U6 is connected to the base of the third transistor Q3 and the sixth pin of the second trigger U2, the collector of the third transistor Q3 is connected to one end of the first capacitor C1, the in-phase end of the fifth operational amplifier U5, and the other end of the ninth resistor R9, the output end of the fifth operational amplifier U5 is connected to J2, and the other end of the first capacitor C1, the emitter of the third transistor Q3 and the ground end are connected.

[0007] Furthermore, it also includes a fourth field effect transistor Q4, a fifth field effect transistor Q5, a sixth transistor Q6, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18, a first connector K1, and a first switch S1;

[0008] One end of the first switch S1, the source of the fifth field effect transistor Q5, and one end of the fourteenth resistor R14 are connected to the power supply, the other end of the first switch S1 is connected to the gate of the fifth field effect transistor Q5, the base of the sixth transistor Q6, and one end of the sixteenth resistor R16, the drain of the fifth field effect transistor Q5 is connected to the first pin of the second trigger U2, and one end of the eighteenth resistor R18, the collector of the sixth transistor Q6 is connected to one end of the thirteenth resistor R13, one end of the seventeenth resistor R17, and the first connection end of the first connector K1, and the second connection end of the first connector K1 is connected to The fourth field effect transistor Q4 is connected to the J2 end, the source of the fourth field effect transistor Q4 is connected to the other end of the fourteenth resistor R14 and one end of the fifteenth resistor R15, the base of the fourth field effect transistor Q4 is connected to the other end of the seventeenth resistor R17, the drain of the fourth field effect transistor Q4 is connected to the fourth pin of the second trigger U2 and one end of the twelfth resistor R12, the other end of the twelfth resistor R12, the other end of the thirteenth resistor R13, the other end of the fifteenth resistor R15, the other end of the sixteenth resistor R16, the other end of the eighteenth resistor R18, the emitter of the sixth transistor Q6 and the ground terminal are connected.

[0009] Furthermore, it also includes a first resistor R1, a second resistor R2, a fourth resistor R4, and a fifth resistor R5;

[0010] One end of the second resistor R2 and one end of the fourth resistor R4 are connected to the power supply, one end of the first resistor R1 and the other end of the second resistor R2 and the in-phase end of the first operational amplifier U1 are connected, one end of the fifth resistor R5 and the other end of the fourth resistor R4 and the inverting end of the third operational amplifier U3 are connected, and the other end of the first resistor R1 and the other end of the fifth resistor R5 are connected to the ground.

[0011] Furthermore, it also includes a sixth resistor R6 and a seventh resistor R7;

[0012] One end of the seventh resistor R7 is connected to the power supply, one end of the sixth resistor R6 is connected to the other end of the seventh resistor R7 and the inverting end of the fourth operational amplifier U4, and the other end of the sixth resistor R6 is connected to the ground.

[0013] Furthermore, it also includes a tenth resistor R10 and an eleventh resistor R11;

[0014] One end of the eleventh resistor R11 is connected to the power supply, one end of the tenth resistor R10 is connected to the other end of the eleventh resistor R11 and the inverting end of the fifth operational amplifier U5, and the other end of the tenth resistor R10 is connected to the ground.

[0015] Furthermore, it also includes a first light emitting diode LED1;

[0016] The anode of the first light emitting diode LED1 is connected to the second pin of the second trigger U2, and the cathode of the first light emitting diode LED1 is connected to the ground terminal.

[0017] The beneficial effects of the present invention compared with the prior art are:

[0018] The present invention can cut off the detection signal in the interval to avoid fault output when the detected voltage is in the trigger and recovery interval during the voltage loss period. In addition, after the power theft in the time period, a quick indication can be given and a one-key reset can be performed after the fault is eliminated. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the prior art and the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0020] Figure 1 This is a structural diagram of the voltage loss protection circuit provided by the present invention. DETAILED DESCRIPTION

[0021] In order to make the objects and advantages of the present invention more clearly understood, the present invention is specifically described below in conjunction with embodiments. It should be understood that the following text is only used to describe one or several specific implementations of the present invention, and does not strictly limit the scope of protection specifically requested by the present invention.

[0022] The present invention discloses an electric energy meter undervoltage protection circuit, comprising a first operational amplifier U1, a second trigger U2, a third operational amplifier U3, a fourth operational amplifier U4, a second field effect transistor Q2, a third resistor R3, an eighth resistor R8, a first diode D1, and a second diode D2;

[0023] The inverting end of the first operational amplifier U1 is connected to the non-inverting end of the third operational amplifier U3 and the J1 end, the output end of the first operational amplifier U1 is connected to the anode of the second diode D2, the cathode of the second diode D2 is connected to the cathode of the first diode D1, one end of the third resistor R3, and the third pin of the second trigger U2, the second pin of the second trigger U2 is connected to the sixth pin of the second trigger U2, the fifth pin of the second trigger U2 is connected to the base of the second field effect transistor Q2, the drain of the second field effect transistor Q2 is connected to the output end of the third operational amplifier U3, the source of the second field effect transistor Q2 is connected to the non-inverting end of the fourth operational amplifier U4 and one end of the eighth resistor R8, the output end of the fourth operational amplifier U4 is connected to the anode of the first diode D1, and the other end of the third resistor R3 and the other end of the eighth resistor R8 are connected to the ground end.

[0024] Specifically, it also includes a fifth operational amplifier U5, a sixth inverter U6, a first transistor Q1, a third transistor Q3, a ninth resistor R9, and a first capacitor C1;

[0025] The collector of the first transistor Q1 is connected to the power supply, the base of the first transistor Q1 is connected to the output end of the sixth inverter U6, the emitter of the first transistor Q1 is connected to one end of the ninth resistor R9, the input end of the sixth inverter U6 is connected to the base of the third transistor Q3 and the sixth pin of the second trigger U2, the collector of the third transistor Q3 is connected to one end of the first capacitor C1, the in-phase end of the fifth operational amplifier U5, and the other end of the ninth resistor R9, the output end of the fifth operational amplifier U5 is connected to J2, and the other end of the first capacitor C1, the emitter of the third transistor Q3 and the ground end are connected.

[0026] Specifically, it also includes a fourth field effect transistor Q4, a fifth field effect transistor Q5, a sixth transistor Q6, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18, a first connector K1, and a first switch S1;

[0027] One end of the first switch S1, the source of the fifth field effect transistor Q5, and one end of the fourteenth resistor R14 are connected to the power supply, the other end of the first switch S1 is connected to the gate of the fifth field effect transistor Q5, the base of the sixth transistor Q6, and one end of the sixteenth resistor R16, the drain of the fifth field effect transistor Q5 is connected to the first pin of the second trigger U2, and one end of the eighteenth resistor R18, the collector of the sixth transistor Q6 is connected to one end of the thirteenth resistor R13, one end of the seventeenth resistor R17, and the first connection end of the first connector K1, and the second connection end of the first connector K1 is connected to The fourth field effect transistor Q4 is connected to the J2 end, the source of the fourth field effect transistor Q4 is connected to the other end of the fourteenth resistor R14 and one end of the fifteenth resistor R15, the base of the fourth field effect transistor Q4 is connected to the other end of the seventeenth resistor R17, the drain of the fourth field effect transistor Q4 is connected to the fourth pin of the second trigger U2 and one end of the twelfth resistor R12, the other end of the twelfth resistor R12, the other end of the thirteenth resistor R13, the other end of the fifteenth resistor R15, the other end of the sixteenth resistor R16, the other end of the eighteenth resistor R18, the emitter of the sixth transistor Q6 and the ground terminal are connected.

[0028] Specifically, it also includes a first resistor R1, a second resistor R2, a fourth resistor R4, and a fifth resistor R5;

[0029] One end of the second resistor R2 and one end of the fourth resistor R4 are connected to the power supply, one end of the first resistor R1 and the other end of the second resistor R2 and the in-phase end of the first operational amplifier U1 are connected, one end of the fifth resistor R5 and the other end of the fourth resistor R4 and the inverting end of the third operational amplifier U3 are connected, and the other end of the first resistor R1 and the other end of the fifth resistor R5 are connected to the ground.

[0030] Specifically, it also includes a sixth resistor R6 and a seventh resistor R7;

[0031] One end of the seventh resistor R7 is connected to the power supply, one end of the sixth resistor R6 is connected to the other end of the seventh resistor R7 and the inverting end of the fourth operational amplifier U4, and the other end of the sixth resistor R6 is connected to the ground.

[0032] Specifically, it also includes a tenth resistor R10 and an eleventh resistor R11;

[0033] One end of the eleventh resistor R11 is connected to the power supply, one end of the tenth resistor R10 is connected to the other end of the eleventh resistor R11 and the inverting end of the fifth operational amplifier U5, and the other end of the tenth resistor R10 is connected to the ground.

[0034] Specifically, it also includes a first light emitting diode LED1;

[0035] The anode of the first light emitting diode LED1 is connected to the second pin of the second trigger U2, and the cathode of the first light emitting diode LED1 is connected to the ground terminal.

[0036] In order to avoid fault output when the detected voltage is in the trigger and recovery interval during the voltage loss period, J1 is used to input the phase voltage, and the J1 signal is fed back to the inverting end of the first operational amplifier U1 and the non-inverting end of the third operational amplifier U3. The first operational amplifier U1 non-inverting end inputs the voltage loss voltage trigger upper limit voltage signal, and the inverting end of the third operational amplifier U3 sets the voltage loss voltage recovery lower limit voltage signal, which can be set by power supply or resistor voltage division. In this embodiment, the fourth pin and the first pin of the second trigger U2 are not connected in series with components and are directly powered by the power supply. In the initial state, it is assumed that the phase voltage signal of J1 is higher than the voltage loss voltage recovery lower limit voltage signal set by the third operational amplifier U3, and the first operational amplifier U1 and the third operational amplifier U3 have no output. , the fifth pin of the second trigger U2 has no output, the sixth pin outputs, the second field effect tube Q2 is in the cut-off state, when the J1 phase voltage is lower than the first operational amplifier U1 in-phase input voltage loss triggering upper limit voltage signal, the first operational amplifier U1 output signal is fed back to the third pin of the second trigger U2 through the second diode D2, at this time, the fifth pin of the second trigger U2 outputs a signal to the gate of the second field effect tube Q2, the sixth pin is cut off and outputs a signal to the base of the first transistor Q1 after being reversed by the sixth inverter U6, the first transistor Q1 is turned on, the collector power supply signal of the first transistor Q1 is fed back to the first capacitor C1 through the emitter of the first transistor Q1 and the ninth resistor R9, the first capacitor C1 and the ninth resistor R9 are integrated, when the first When the capacitor C1 voltage is at the alarm protection mechanism voltage, the fifth operational amplifier U5 outputs a signal J2 to alarm. The integration rate of the first capacitor C1 is regulated by the resistance value of the ninth resistor R9 to control the voltage rise rate of J2. At this time, assuming that the current voltage loss is caused by the equipment or power-on startup voltage loss, the voltage at the first capacitor C1 end is lower than the alarm protection mechanism voltage set at the reverse end of the fifth operational amplifier U5, and J1 is higher than the voltage loss voltage recovery lower limit voltage signal set at the inverting end of the third operational amplifier U3. The output signal of the third operational amplifier U3 can be fed back to the fourth operational amplifier U4 through the drain and source of the second field effect tube Q2. The fourth operational amplifier U4 is used to output the second trigger U2 control voltage to avoid the second field effect tube Q2 voltage drop and the second trigger The device U2 cannot work normally, the output signal of the fourth operational amplifier U4 is fed back to the third pin of the second trigger U2 through the first diode D1, the second trigger U2 is set to have no output at the fifth pin, the second field effect tube Q2 is cut off, the third pin of the second trigger U2 is reset after passing through the third resistor R3 loop, the sixth pin of the second trigger U2 outputs a signal to the sixth inverter U6 which inverts and controls the first transistor Q1 to be cut off, and at the same time, the sixth pin of the second trigger U2 also outputs a signal to the base of the third transistor Q3, the third transistor Q3 is turned on, and the voltage at the first capacitor C1 is released through the collector and emitter grounding loop of the third transistor Q3, so as to avoid fault judgment when J1 is at the upper limit of the undervoltage voltage trigger and the lower limit of the undervoltage voltage recovery;

[0037] Taking into account the need to avoid electricity theft in different time periods, it is necessary to re-screen previous data after the voltage returns to normal. In order to provide quick indication and perform a one-key reset after troubleshooting, in this embodiment, the fourth pin of the second trigger U2 is removed and the first pin is directly connected to the power supply, and the J2 signal is fed back to the fourth pin of the second trigger U2 through the first connector K1 and the fourth field effect transistor Q4. The first pin of the second trigger U2 is connected to the power supply through the fifth field effect transistor Q5. When the J1 phase voltage reaches the undervoltage voltage input at the same phase end of the first operational amplifier U1 to trigger the upper limit signal and satisfies the integration time of the ninth resistor R9 and the first capacitor C1 to make the fifth operational amplifier U5 output, the J2 signal is fed back to the fourth pin of the second trigger U2 through the first connector K1 and the fourth field effect transistor Q4. The first pin of the second trigger U2 is connected to the power supply through the fifth field effect transistor Q5. When the J1 phase voltage reaches the undervoltage voltage trigger upper limit signal input at the same phase end of the first operational amplifier U1 and satisfies the integration time of the ninth resistor R9 and the first capacitor C1 to make the fifth operational amplifier U5 output. The seventeenth resistor R17 is input to the gate of the fourth field effect transistor Q4, the fourth field effect transistor Q4 is cut off, the fourth pin of the second trigger U2 is forced to be set to the fifth pin output through the twelfth resistor R12 loop, and the second trigger U2 is forced to be set to the fifth pin output, so as to avoid that when the J1 phase voltage is lower than the voltage recovery lower limit voltage signal set at the inverting end of the third operational amplifier U3, the fourth operational amplifier U4 output changes the state of the fifth pin of the second trigger U2 through the first diode D1 through the above embodiment loop, and when the on-site fault repair is completed, the first switch S1 is closed, and the power supply is fed back to the base of the sixth transistor Q6 through the first switch S1, and the sixth transistor Q6 is turned on to transmit the J2 signal through the collector, emitter, and ground terminal of the sixth transistor Q6. The loop is pulled down, the fourth field effect tube Q4 re-enters the on state, and the fifth field effect tube Q5 is turned off. The first pin of the second trigger U2 sets the sixth pin to the output state after passing through the eighteenth resistor R18 loop. The fifth pin is turned off to complete the reset after the fault is eliminated. The fourteenth resistor R14 and the fifteenth resistor R15 are used for the fourth field effect tube Q4 voltage division power supply to prevent J2 from failing to reach the fourth field effect tube Q4 threshold voltage when the fifth operational amplifier U5 is in non-rail-to-rail state. The seventeenth resistor R17 is used for the fourth field effect tube Q4 current limiting and J2 can pull down the loop when the sixth transistor Q6 is turned on. The thirteenth resistor R13 is used for the fourth field effect tube Q4 gate parasitic loop when the sixth transistor Q6 is turned off. The sixteenth resistor R15 is used for the fourth field effect tube Q4 gate parasitic loop when the sixth transistor Q6 is turned off. Resistor R16 is used for the gate parasitic loop of the fifth field effect transistor Q5, the second resistor R2 and the first resistor R1 are used for setting the upper limit voltage signal of the undervoltage voltage trigger at the same phase end of the first operational amplifier U1, the fourth resistor R4 and the fifth resistor R5 are used for setting the lower limit voltage signal of the undervoltage voltage recovery at the inverting end of the third operational amplifier U3, the eighth resistor R8 is used for the grounding loop of the same phase end of the fourth operational amplifier U4 when the second field effect transistor Q2 is cut off to avoid the output of a virtual short fault, the sixth resistor R6 and the seventh resistor R7 are used to set the reference signal of the fourth operational amplifier U4, and the signal is lower than the voltage drop voltage of the second field effect transistor Q2, the eleventh resistor R11 and the tenth resistor R10 are used for setting the alarm protection mechanism voltage signal of the fifth operational amplifier U5.

[0038] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations within the meaning and scope of the equivalent elements of the claims be included in the invention. Any marking in a claim should not be considered as limiting the claim to which it relates.

Claims

1. An electric energy meter undervoltage protection circuit, characterized in that: It includes a first operational amplifier, a second trigger, a third operational amplifier, a fourth operational amplifier, a second field effect transistor, a third resistor, an eighth resistor, a first diode, and a second diode; The inverting end of the first operational amplifier is connected to the non-inverting end of the third operational amplifier and the J1 end, the output end of the first operational amplifier is connected to the anode of the second diode, the cathode of the second diode is connected to the cathode of the first diode, one end of the third resistor, and the third pin of the second trigger, the second pin of the second trigger is connected to the sixth pin of the second trigger, the fifth pin of the second trigger is connected to the base of the second field effect transistor, the drain of the second field effect transistor is connected to the output end of the third operational amplifier, the source of the second field effect transistor is connected to the non-inverting end of the fourth operational amplifier and one end of the eighth resistor, the output end of the fourth operational amplifier is connected to the anode of the first diode, and the other end of the third resistor, the other end of the eighth resistor and the ground end are connected.

2. The electric energy meter undervoltage protection circuit according to claim 1, characterized in that: It also includes a fifth operational amplifier, a sixth inverter, a first triode, a third triode, a ninth resistor, and a first capacitor; The collector of the first transistor is connected to the power supply, the base of the first transistor is connected to the output end of the sixth inverter, the emitter of the first transistor is connected to one end of the ninth resistor, the input end of the sixth inverter is connected to the base of the third transistor and the sixth pin of the second trigger, the collector of the third transistor is connected to one end of the first capacitor, the in-phase end of the fifth operational amplifier, and the other end of the ninth resistor, the output end of the fifth operational amplifier is connected to J2, and the other end of the first capacitor, the emitter of the third transistor and the ground are connected.

3. The electric energy meter undervoltage protection circuit according to claim 1, characterized in that: Also includes a fourth field effect transistor, a fifth field effect transistor, a sixth triode, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a first connector, and a first switch; One end of the first switch, the source of the fifth field effect transistor, and one end of the fourteenth resistor are connected to the power supply, the other end of the first switch is connected to the gate of the fifth field effect transistor, the base of the sixth transistor, and one end of the sixteenth resistor, the drain of the fifth field effect transistor is connected to the first pin of the second trigger and one end of the eighteenth resistor, the collector of the sixth transistor is connected to one end of the thirteenth resistor, one end of the seventeenth resistor, and the first connecting end of the first connector, the second connecting end of the first connector is connected to the J2 end, the source of the fourth field effect transistor is connected to the other end of the fourteenth resistor and one end of the fifteenth resistor, the base of the fourth field effect transistor is connected to the other end of the seventeenth resistor, the drain of the fourth field effect transistor is connected to the fourth pin of the second trigger and one end of the twelfth resistor, the other end of the twelfth resistor, the other end of the thirteenth resistor, the other end of the fifteenth resistor, the other end of the sixteenth resistor, the other end of the eighteenth resistor, the emitter of the sixth transistor and the ground are connected.

4. The electric energy meter undervoltage protection circuit according to claim 1, characterized in that: Also includes a first resistor, a second resistor, a fourth resistor, and a fifth resistor; One end of the second resistor and one end of the fourth resistor are connected to the power supply, one end of the first resistor and the other end of the second resistor are connected to the non-inverting end of the first operational amplifier, one end of the fifth resistor and the other end of the fourth resistor are connected to the inverting end of the third operational amplifier, and the other end of the first resistor and the other end of the fifth resistor are connected to the ground.

5. The electric energy meter undervoltage protection circuit according to claim 1, characterized in that: Also includes a sixth resistor and a seventh resistor; One end of the seventh resistor is connected to the power supply, one end of the sixth resistor is connected to the other end of the seventh resistor and the inverting end of the fourth operational amplifier, and the other end of the sixth resistor is connected to the ground.

6. The electric energy meter undervoltage protection circuit according to claim 2, characterized in that: Also includes a tenth resistor and an eleventh resistor; One end of the eleventh resistor is connected to the power supply, one end of the tenth resistor is connected to the other end of the eleventh resistor and the inverting end of the fifth operational amplifier, and the other end of the tenth resistor is connected to the ground.

7. The electric energy meter undervoltage protection circuit according to claim 1, characterized in that: Also includes a first light emitting diode; The anode of the first light emitting diode is connected to the second pin of the second trigger, and the cathode of the first light emitting diode is connected to the ground terminal.

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