Current sampling circuit and power supply device

Abstract

The present application relates to a current sampling module and a power supply device. The current sampling module includes: a delay unit, which obtains a pulse width control signal of a power tube and is configured to generate a delay control signal with a specified delay based on the pulse width control signal; a current sampling unit, which is configured to obtain a voltage signal related to the current in the power tube and generate a sampling current proportional to the current in the power tube based on the voltage signal and the delay control signal; and a resistance calibration unit, which is configured to provide a calibration resistor under the influence of the resistance control signal to generate a sampling voltage based on the sampling current.

Description

Technical Field

[0001] The present application belongs to the field of integrated circuit design, and in particular relates to a current sampling circuit and a power supply device. Background Art

[0002] At present, two control methods are generally used for power switch converters, namely voltage or current control. For the current control method, the current sampling circuit module can sample the inductor current signal and output the current sensing signal to control the working state of the converter. Commonly used methods include resistor sampling, MOS power tube sampling and DCR DC resistance sampling. The inductor current signal obtained by sampling needs to flow through the sampling resistor to generate a sampling voltage signal to control the working state of the power converter.

[0003] However, in the actual production process of the chip, there will be certain deviations in the process angle, and changes in temperature and power supply voltage (PVT) will cause the sampling accuracy of the sampling circuit to deviate from the actual calibration value. For the current mode control method, poor sampling accuracy and large changes will affect the system load capacity of the power converter and reduce the performance of the power converter. Secondly, for MOS power tube sampling technology, multiple sampling of half-cycle inductor current signals, because the power tube of the power converter will have a large voltage pulse at the drain of the power tube when it is turned on and off, it will cause the sampling result to have a spike voltage at the moment of switching, which can easily cause the power converter to make erroneous logical judgments. Therefore, in view of these situations, it is indeed necessary to provide a current sampling circuit calibration and delay protection design method to solve the above defects.

[0004] Therefore, there is an urgent need for a current sampling circuit that is highly applicable and easy to implement, as well as a corresponding calibration and delay protection method. Summary of the invention

[0005] In view of the technical problems existing in the prior art, the present application proposes a current sampling circuit with a delay characteristic, which not only achieves accurate current sampling but also avoids system misjudgment.

[0006] On the one hand, the present application provides a current sampling module coupled to a power conversion module, the power conversion module including a power tube, the current sampling module including: a delay unit, which obtains a pulse width control signal of the power tube and is configured to generate a delay control signal with a specified delay based on the pulse width control signal; a current sampling unit, configured to obtain a voltage signal related to the current in the power tube, and generate a sampling current proportional to the current in the power tube based on the voltage signal and the delay control signal; and a resistance calibration unit, configured to provide a calibration resistor under the influence of the resistance control signal to generate a sampling voltage based on the sampling current.

[0007] In one embodiment, the current sampling module further includes: a control unit configured to generate the resistance control signal, and determine whether to update the resistance control signal based on the sampled voltage.

[0008] In one embodiment, the delay unit includes: a transmission chain component, configured to generate a first delay control signal and a second delay control signal based on the pulse width control signal, wherein the first delay control signal is consistent in phase with the pulse width control signal, and the first delay control signal and the second delay control signal are inverted to each other; a delay component, which is coupled to a delay node in the transmission chain component and is configured to make the voltage at the delay node change to a threshold voltage in a specified time length, so that the first and second delay control signals have a specified delay compared to the pulse width control signal.

[0009] In one embodiment, the transmission chain component includes an inverter group and an AND gate, wherein the receiving end of the inverter group obtains the pulse width control signal, the output end is coupled to the first input end of the AND gate, the second input end of the AND gate receives the pulse width control signal, and the inverter group includes a first even number of inverters; the delay component includes a constant current source and a delay capacitor, the delay capacitor is coupled to the delay node, and a second even number of inverters is included between the delay node and the receiving end of the inverter group, wherein the second even number is smaller than the first even number, wherein the output end of the AND gate outputs the first delay control signal, and the inverting node in the inverter group outputs the second delay control signal, wherein an odd number of inverters is included between the inverting node and the receiving end of the inverter group.

[0010] In one embodiment, the inverter group includes first, second, third and fourth inverters connected in series in sequence, wherein the delay node is located at the output end of the second inverter, and the inverting node is located at the output end of the third inverter.

[0011] In one embodiment, the current sampling unit includes: an operational amplifier subunit; a first transistor, whose source is coupled to the drain of the power tube, whose drain is coupled to the first input terminal of the operational amplifier subunit, and whose gate receives the first delay control signal; and a second transistor, whose source is coupled to a low level, whose drain is coupled to the second input terminal of the operational amplifier subunit, and whose gate receives the first delay control signal, wherein the size of the second transistor is configured to be proportional to the size of the power tube, and the second transistor and the power tube are the same type of MOS tube. It can be understood that the value of the ratio can be the size ratio of the power tube to the second transistor.

[0012] In one embodiment, the current sampling unit includes: a third transistor, whose source is coupled to a low level, whose drain is coupled to the first input terminal of the operational amplifier subunit, and whose gate receives the second delay control signal; and a fourth transistor, whose source is coupled to a low level, whose drain is coupled to the second input terminal of the operational amplifier subunit, and whose gate receives the second delay control signal.

[0013] In one embodiment, the resistance calibration unit includes: a first detection resistor; a detection resistor array, which is connected in series with the first detection resistor and includes multiple detection branches, and the detection branches include switches and sub-resistors connected in series, wherein the switches are controlled by the resistance control signal.

[0014] In one embodiment, the resistance calibration unit includes: a second detection resistor; a third detection resistor connected in series with the second detection resistor; and a fourth detection resistor connected in parallel with the third detection resistor via a switch, wherein the switch is controlled by the resistance control signal.

[0015] On the other hand, the present application proposes a power supply device, including: a power conversion module, including a power tube, the power conversion module is configured to provide an output voltage with load capacity at the load end under the influence of a pulse width control signal; a current sampling module as in any of the preceding items, configured to generate a sampling current based on the current in the power tube and then generate a sampling voltage; and a power control module, configured to adjust the pulse width control signal based on the sampling voltage.

[0016] Compared with the prior art, the technical solution in this application has the following beneficial effects:

[0017] By controlling the resistance calibration module to achieve accurate sampling gain, the influence of PVT that causes the sampling accuracy of the power converter to deteriorate, thereby improving the sampling accuracy of the traditional sampling circuit; secondly, by providing a delay module, it is possible to prevent the sampling circuit from collecting erroneous current information, thereby causing the power converter to make erroneous logical judgments. In addition, the sampling module has a certain delay function. During the power tube current conversion process, the sampling module can avoid sampling an excessively high output voltage of the power conversion module, thereby causing damage to the internal transistors of the sampling module. At the same time, the delay module has low power consumption, low design cost, and is easy to promote and use. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Below, the preferred embodiments of the present application will be further described in detail with reference to the accompanying drawings, wherein:

[0019] Figure 1 is a structural diagram of a power supply device according to an embodiment of the present application;

[0020] Figure 2is a circuit schematic diagram of a current sampling unit according to an embodiment of the present application;

[0021] Figure 3 is a circuit schematic diagram of a delay unit according to an embodiment of the present application;

[0022] Figure 4 is a schematic diagram of a resistance calibration unit according to an embodiment of the present application;

[0023] Figure 5 is a schematic diagram of a delay signal according to an embodiment of the present application;

[0024] Figure 6 FIG. 4 is a schematic diagram of a sampling voltage according to an embodiment of the present application. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0026] In the following detailed description, reference may be made to the various specification drawings that are part of the present application and are used to illustrate specific embodiments of the present application. In the accompanying drawings, similar reference numerals describe substantially similar components in different figures. The various specific embodiments of the present application are described below in sufficient detail so that a person of ordinary skill in the art with relevant knowledge and skills in the art can implement the technical solutions of the present application. It should be understood that other embodiments may also be used or structural, logical or electrical changes may be made to the embodiments of the present application.

[0027] The technologies, methods and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods and devices shall be considered as part of the specification. The lines between the units in the drawings are only for the convenience of explanation, indicating that at least the units at both ends of the lines are communicating with each other, and are not intended to limit the unconnected units from being unable to communicate. In addition, the number of lines between two units is intended to indicate at least the number of signals involved in the communication between the two units or at least the output terminals, and is not configured to limit the two units to only communicate with each other through the signals shown in the figure.

[0028] Figure 1 is a structural diagram of a power supply device according to an embodiment of the present application.

[0029] like Figure 1As shown, the power supply device includes a power conversion module 11 and a current sampling module, wherein the current sampling module includes a current sampling unit 12 , a resistance calibration unit 13 , a delay unit 14 and a control unit 15 .

[0030] The power conversion module 11 includes an inductor L, a diode D, a power tube M1, a resistor R and a capacitor C. The power tube M1 works based on a specified duty cycle under the control of a pulse width control signal PWM, thereby adjusting the working state of the inductor L and the capacitor C. When the power tube M1 is turned on, the diode D is reverse biased and cut off, the inductor L stores energy, and the capacitor C supplies energy to the load R. L Provide energy; when the power tube M1 is turned off, the diode D is turned on, the inductor L charges the capacitor C through the diode D, and supplies power to the load R L Provide energy.

[0031] The current sampling unit 12 provides a sampling current that is proportional to the current in the power tube M1, and the resistance calibration unit 13 generates a sampling voltage Vsense based on the sampling current. The output end of the resistance calibration unit 13 is coupled to the input end of the control unit 15, and the output end of the control unit 15 is coupled to the control end of the resistance calibration unit 13, so as to control the size of the resistance value provided by the resistance calibration unit 13 by generating a resistance control signal, and then adjust the sampling accuracy by adjusting the resistance value. The control unit 15 can also determine whether to update the resistance control signal based on the sampling voltage. The delay unit 14 obtains the pulse width control signal PWM and is coupled to the control end of the current sampling unit 12. The delay unit 14 is configured to generate a delay signal of a certain time based on the pulse width control signal to avoid misadjustment of the working mode of the current sampling unit 12.

[0032] In other words, the current detection unit 12 obtains a voltage signal related to the current in the power tube M1 (eg, the drain voltage of the power tube M1 ), and generates a sampling current proportional to the current in the power tube based on the voltage signal and the delay control signal.

[0033] In one embodiment, the control unit 15 can also adjust the duty cycle of the PWM signal according to the value of Vsense, thereby adjusting the working state of the power tube M1. It can be understood that the power supply device in the current control mode has a good load transient response.

[0034] Figure 2 is a circuit schematic diagram of a current sampling unit according to an embodiment of the present application.

[0035] like Figure 2As shown, the current sampling unit 12 includes an operational amplifier subunit 121, a first transistor MN5 and a second transistor M2, wherein the source of the first transistor MN5 is coupled to the drain of the power tube M1 to obtain the voltage signal Vsw, the drain of the first transistor MN5 is coupled to the first input terminal (negative input terminal) of the operational amplifier subunit 121, and the gate receives the first delay control signal VQ. Similarly, the source of the second transistor M2 is coupled to a low level, the drain is coupled to the second input terminal (positive input terminal) of the operational amplifier subunit 121, and the gate receives the first delay control signal VQ. The size of the second transistor is configured to be proportional to the size of the power tube M1.

[0036] The current sampling unit 12 includes a third transistor MN3 and a fourth transistor MN4, wherein the source of the third transistor MN3 is coupled to a low level, the drain is coupled to the positive input terminal of the operational amplifier subunit 121, and the gate receives the second delay control signal VQ'. The source of the fourth transistor MN4 is coupled to a low level, the drain is coupled to the second input terminal of the operational amplifier subunit, and the gate receives the second delay control signal VQ'.

[0037] It can be understood that the signals VQ and VQ' are inversely proportional to each other, VQ is consistent with the PWM signal and has a certain delay compared to PWM.

[0038] Figure 3 4 is a circuit diagram of a delay unit according to an embodiment of the present application.

[0039] The delay unit 14 includes a transmission chain component 141 and a delay component 142, wherein the transmission chain component 141 obtains the pulse width control signal PWM at the receiving end, and provides a first delay control signal VQ and a second delay control signal VQ' which are consistent with the phase of the pulse width control signal PWM at the output end, and the two signals are inverted.

[0040] The delay element 142 transmits a delay node in the chain element so that the voltage at the node changes to a threshold voltage in a specified time period, so that the first and second delay control signals have a specified delay compared to the pulse width control signal.

[0041] Specifically, the transmission chain component 141 includes inverters U1-U4 and an AND gate AND1 connected in series, and the delay component 142 includes a current source IB2, a transistor MP9, a transistor MP10, and a delay capacitor C1. The input end of the inverter U1 receives the pulse width control signal PWM, and the output end is coupled to the input end of the inverter U2, the output end of the inverter U2 is coupled to the input end of the inverter U3, the output end of the inverter U3 is coupled to the input end of the inverter U4, the output end of the inverter U4 is coupled to the first input end of the AND gate AND1, and the second input end of the AND gate AND1 receives the pulse width control signal PWM. In this embodiment, the transistors MP9 and MP10 have the same width-to-length ratio, the drain of the transistor MP10 and one end of the delay capacitor C1 are both connected to the output end of the inverter U2, the drain of the transistor MP9 is connected to one end of the current source IB2, and the other ends of the current source IB2 and the capacitor C1 are both grounded.

[0042] It can be understood that the output end of the inverter U2 can be a delay node in this embodiment, and an even number of inverters are included between the delay node and the receiving end of the inverter group, so that the voltage at the node is consistent with the phase change polarity of the pulse width control signal PWM. The output end of the inverter U3 can be used as an inverting node to obtain the second delay control signal VQ'. It can be understood that an odd number of inverters are included between the inverting node and the receiving end of the inverter group.

[0043] The constant current source IB2 charges the capacitor C1 through the transistor MP10. When the flip threshold voltage VTH of the inverter U3 is known, the delay caused by the delay unit 14 can be determined by setting the values ​​of the constant current source IB2 and the capacitor C1.

[0044] It is understandable that each logic gate will introduce a certain delay. Therefore, when determining the delay length of the delay control signals VQ and VQ′, the delay caused by each logic gate should also be considered.

[0045] Combine the following Figure 1-3 The process of current detection is explained.

[0046] The pulse width control signal PWM is sent to the input end of the delay unit 14. When the pulse width control signal PWM is at a high level, the output end of the inverter U1 is at a low level. The current source IB2 charges the delay capacitor C1 through transistors MP9 and MP10. It can be understood that due to the existence of the delay capacitor C1, there is a certain delay between the output end signal of the inverter U2 and the pulse width control signal PWM, and then the first delay control signal VQ is output through the inverters U3, U4 and the AND gate AND1.

[0047] Figure 5 Schematic diagram of a delay signal according to an embodiment of the present application.

[0048] like Figure 5 As shown, compared with the first delay control signal VQ, the second delay control signal VQ' is not transmitted through the AND gate AND1, so the second delay control signal VQ' will first turn off the transistors MN3 and MN4, and then the first delay control signal VQ controls the transistor MN5 to turn on. At this time, the drain voltage signal Vsw of the power tube M1 is transmitted to the reverse input terminal of the operational amplifier subunit 121 under the condition of a certain delay. When the pulse width control signal PWM is at a high level, the power tube M1 is turned on, and its drain voltage Vsw is at a low level. The operational amplifier subunit 121 and the transistors MP1-MP4 and M2 form negative feedback, so the drain voltage of the transistor M2 is the same as the drain voltage of the power tube M1. Since the size of the power tube M1 is K times the size of the transistor M2, and the transistors M2 and the power tube M1 both work in the linear region, the branch where the transistor M2 is located can copy the current on the power tube M1 in proportion, that is, obtain the sampling current.

[0049] Figure 6 FIG. 4 is a schematic diagram of a sampling voltage according to an embodiment of the present application.

[0050] The transistors MP5 and MP6 copy the sampled current and pass it through the resistor calibration unit 13, thereby generating a sampled voltage Vsense. Figure 6 As shown. It can be understood that, under the premise that the first delay control signal VQ has a certain delay compared to PWM, the overshoot caused by the sudden opening of the power tube M1 can be avoided. In other words, the drain produces a large rate of change (dV / dt) when the power tube M1 is turned on and off. By introducing a certain delay, it can avoid the current sampling unit 12 collecting erroneous current information, thereby causing the power converter to make erroneous logical judgments. Specifically, if the voltage in the dotted box exceeds the voltage corresponding to the pulse width control signal PWM when it is turned off, it will cause the pulse width control signal PWM to flip incorrectly. For a sampling module with a certain delay function, during the current commutation process of the power tube M1, the current sampling unit 12 can avoid sampling the output voltage that is too high after the conversion of the power conversion module 11, thereby causing damage to the first transistor MN5.

[0051] During the actual chip production process, there will be certain deviations in the process angle, and changes in temperature and power supply voltage (PVT) will cause the sampling accuracy of the sampling circuit to deviate from the actual calibration value. Therefore, when the above deviations occur, the control module 15 can adjust the sampling accuracy of the sampling circuit by controlling the resistance calibration unit 13.

[0052] Figure 4 FIG. 4 is a schematic diagram of a resistance calibration unit according to an embodiment of the present application.

[0053] like Figure 4 As shown, the resistance calibration unit 13 includes: a first detection resistor Rsen; a detection resistor array 131, which is connected in series with the first detection resistor Rsen. The detection resistor array 131 includes a plurality of detection branches, and the detection branch includes a switch Sn and a sub-resistor Rcaln connected in series, wherein the switch Sn is controlled by a resistance control signal from the control module 15.

[0054] like Figure 4 As shown, the detection resistor array 131 includes switches S1-S4 and adjustment resistors Rcal1-Rcal5, wherein switches S1-S4 can be used to determine whether the detection resistors Rcal1, Rcal2, Rcal4, and Rcal5 are connected to the circuit, and then adjust the equivalent resistance of the detection resistor array 131, so as to obtain more accurate sampling accuracy, avoid the influence of PVT and cause the sampling accuracy of the power converter to deteriorate, and then improve the sampling accuracy of the traditional sampling circuit. It can be understood that the maximum equivalent resistance of the detection resistor array is Rcal3 at this time.

[0055] When the switches S1-S4 of the resistance calibration unit are all disconnected, the sampling voltage Vsense is the maximum sampling value; when the switches S1-S4 of the resistance calibration unit are all closed, the sampling voltage Vsense is the minimum sampling voltage. In practical applications, when it is found that the influence of PVT causes the sampling voltage to be offset, the resistance value in the resistance calibration unit can be adjusted to obtain a more ideal Vsense voltage. Therefore, through the resistance calibration unit 13, the output load Io of the power conversion module 11 and the inductor current I L There is the following relationship: I L =Io / (1-D), where D is the actual duty cycle of the system. Therefore, the relationship between the sampling current Isen of the current sampling unit 12 and the load Io is Isen=Io / K (1-D), which can obtain an accurate sampling voltage and thus avoid the process deviation from affecting the load capacity of the converter.

[0056] In one embodiment, the detection resistor Rcal3 may also be connected in series with the switch S5 (not shown). Therefore, the maximum equivalent resistance of the detection resistor array is affected by the resistance control signal, and the maximum equivalent resistance may be any one of Rcal1-Rcal5.

[0057] The above embodiments are only used to illustrate the present application, and are not intended to limit the present application. Ordinary technicians in the relevant technical field may make various changes and modifications without departing from the scope of the present application. Therefore, all equivalent technical solutions should also fall within the scope disclosed in the present application.

Claims

1. A current sampling module coupled to a power conversion module, wherein the power conversion module includes a power tube, characterized in that: include: A delay unit is configured to obtain a pulse width control signal of the power tube and generate a delay control signal with a specified delay based on the pulse width control signal, wherein the delay unit includes: A transmission chain component, configured to generate a first delay control signal and a second delay control signal based on the pulse width control signal, wherein the first delay control signal is consistent in phase with the pulse width control signal and is in anti-phase with the second delay control signal; A delay component, coupled to a delay node in the transmission chain component, configured to make the voltage at the delay node change to a threshold voltage within a specified time length, so that the first and second delay control signals respectively have corresponding delays compared to the pulse width control signal, wherein the delay of the second delay control signal is less than the delay of the first delay control signal; a current sampling unit configured to obtain a voltage signal related to the current in the power tube, and generate a sampling current proportional to the current in the power tube based on the voltage signal and the delay control signal; and, The resistance calibration unit is configured to provide a calibration resistance under the influence of a resistance control signal to generate a sampling voltage based on the sampling current.

2. The current sampling module according to claim 1, characterized in that: The current sampling module also includes: The control unit is configured to generate the resistance control signal and determine whether to update the resistance control signal based on the sampled voltage.

3. The current sampling module according to claim 1, characterized in that: The transmission chain component includes an inverter group and an AND gate, wherein a receiving end of the inverter group obtains the pulse width control signal, an output end is coupled to a first input end of the AND gate, a second input end of the AND gate receives the pulse width control signal, and the inverter group includes a first even number of inverters; The delay component includes a constant current source and a delay capacitor, the delay capacitor is coupled to the delay node, and a second even number of inverters is included between the delay node and the receiving end of the inverter group, wherein the second even number is smaller than the first even number, The output end of the AND gate outputs the first delay control signal, the inverting node in the inverter group outputs the second delay control signal, and an odd number of inverters are included between the inverting node and the receiving end of the inverter group.

4. The current sampling module according to claim 3, characterized in that: The inverter group includes first, second, third and fourth inverters connected in series in sequence, wherein the delay node is located at the output end of the second inverter, and the inversion node is located at the output end of the third inverter.

5. The current sampling module according to claim 1, characterized in that: The current sampling unit comprises: Operational amplifier subunit; a first transistor, whose source is coupled to the drain of the power tube, whose drain is coupled to the first input terminal of the operational amplifier subunit, and whose gate receives the first delay control signal; and A second transistor, whose source is coupled to a low level, whose drain is coupled to the second input terminal of the operational amplifier subunit, and whose gate receives the first delay control signal, wherein the size of the second transistor is configured to be proportional to the size of the power tube, and the second transistor and the power tube are the same type of transistors.

6. The current sampling module according to claim 5, characterized in that: The current sampling unit comprises: A third transistor, whose source is coupled to a low level, whose drain is coupled to the first input terminal of the operational amplifier subunit, and whose gate receives the second delay control signal; and A fourth transistor has a source coupled to a low level, a drain coupled to the second input terminal of the operational amplifier subunit, and a gate receiving the second delay control signal.

7. The current sampling module according to claim 1, characterized in that: The resistance calibration unit comprises: a first detection resistor; A detection resistor array is connected in series with the first detection resistor and includes a plurality of detection branches. The detection branches include switches and sub-resistors connected in series, wherein the switches are controlled by the resistance control signal.

8. The current sampling module according to claim 1, characterized in that: The resistance calibration unit comprises: A second detection resistor; A third detection resistor connected in series with the second detection resistor; and A fourth detection resistor is connected in parallel with the third detection resistor via a switch, wherein the switch is controlled by the resistance control signal.

9. A power supply device, characterized in that: include: A power conversion module, comprising a power tube, configured to provide an output voltage having load capacity at a load end under the influence of a pulse width control signal; The current sampling module according to any one of claims 1 to 8, configured to generate a sampling current and then generate a sampling voltage based on the current in the power tube; and The power control module is configured to adjust the pulse width control signal based on the sampled voltage.

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