A packaging structure integrating MEMS and ASIC and a manufacturing method thereof

Abstract

The present application relates to a packaging structure integrating MEMS and ASIC and a manufacturing method thereof, and belongs to the field of resonator manufacturing technology. It includes an SOI wafer, and the top silicon surface of the SOI wafer is provided with a first area and a second area, an ASIC driving circuit unit is provided in the first area, and a MEMS resonator unit is provided in the second area. A metal connection layer is provided on the surface of the SOI wafer, and the ASIC driving circuit unit and the MEMS resonator unit are connected through the metal connection layer. The ASIC driving circuit unit is used to excite the vibration of the MEMS resonator unit and process the output signal of the MEMS resonator unit. By arranging the MEMS resonator unit and the ASIC driving circuit unit on the same SOI wafer, there is no need to stack and thin the MEMS resonator unit and the ASIC driving circuit unit, so the volume of the packaging shell can be made smaller, so that the degree of integration between the MEMS resonator unit and the ASIC driving circuit unit is higher.

Description

Technical Field

[0001] The present application belongs to the technical field of resonator manufacturing, and specifically relates to a packaging structure integrating MEMS and ASIC and a manufacturing method thereof. Background Art

[0002] Traditional clock devices usually generate high-precision oscillation frequencies based on the piezoelectric effect of quartz crystals. Quartz crystal oscillators are widely used in electronic devices for time and frequency control and stability, but they have poor compatibility with CMOS processes and cannot meet the needs of high integration. Therefore, with the development of technology, MEMS (micro-electromechanical systems) clock devices with better compatibility with CMOS processes have gradually become a substitute for quartz crystal oscillators.

[0003] The packaging of MEMS clock devices in the prior art is mainly divided into a MEMS resonator part and a CMOS drive circuit part, and mainly adopts QFN, SOT, LCC, CSP and other packaging forms to integrate MEMS Die and CMOS Die in a stacked manner.

[0004] However, in the process of packaging the MEMS Die and the CMOS Die, in order to meet the requirements of the packaging size, the MEMS Die and the CMOS Die need to be thinned, which makes the packaging method complicated. Summary of the invention

[0005] The embodiment of the present application provides a packaging structure integrating MEMS and ASIC and a manufacturing method thereof, which is used to solve the problem that in the process of packaging MEMS Die and CMOS Die in the prior art, in order to meet the requirements of packaging size, MEMS Die and CMOS Die need to be thinned, resulting in a complicated packaging method.

[0006] In a first aspect, an embodiment of the present application provides a packaging structure integrating MEMS and ASIC, including an SOI wafer, wherein a top silicon surface of the SOI wafer is provided with a first area and a second area, an ASIC driving circuit unit is provided in the first area, and a MEMS resonator unit is provided in the second area;

[0007] A metal connection layer is provided on the surface of the SOI wafer, and the ASIC driving circuit unit and the MEMS resonator unit are connected via the metal connection layer. The ASIC driving circuit unit is used to excite the vibration of the MEMS resonator unit and process the output signal of the MEMS resonator unit.

[0008] In the embodiment of the present application, a passivation layer is provided on the surface of the ASIC driving circuit unit, and the passivation layer is used to isolate the ASIC driving circuit unit from contact with the outside air.

[0009] In the embodiment of the present application, a groove is provided on the SOI wafer, and a cantilever beam is provided on the MEMS resonator unit, and the cantilever beam is located above the groove.

[0010] In a second aspect, a method for manufacturing a packaging structure integrating MEMS and ASIC is also proposed, providing an SOI wafer, and dividing a top silicon surface of the SOI wafer into a first area and a second area;

[0011] Fabricating an ASIC driving circuit unit in the first area;

[0012] A MEMS resonator unit is manufactured in the second region and connected to an ASIC driving circuit unit through a metal connection layer.

[0013] In the embodiment of the present application, the thickness of the substrate silicon in the SOI wafer is 300-800 microns, the thickness of the buried oxide layer is 1-5 microns, and the thickness of the top silicon layer is 2-20 microns.

[0014] In the embodiment of the present application, the ASIC driving circuit unit is manufactured in the first area, and the specific method is as follows:

[0015] In the first area on the top silicon layer, an ASIC driving circuit unit is manufactured using a 40-80 nanometer CMOS process.

[0016] In the embodiment of the present application, after the ASIC driving circuit unit is manufactured in the first area, the ASIC driving circuit unit is passivated using a passivation material to form a passivation layer on the surface of the ASIC driving circuit unit, and the passivation layer on the PAD electrode in the ASIC driving circuit unit is removed by photolithography and etching processes.

[0017] In the embodiment of the present application, the MEMS resonator unit is manufactured in the second region and connected to the ASIC driving circuit unit through the metal connection layer. The specific method is:

[0018] Depositing a bottom electrode metal layer on the top surface of the top silicon layer by a deposition process, and performing a patterning process on the bottom electrode metal layer in the second region;

[0019] Depositing a piezoelectric layer metal layer on top of the bottom electrode metal layer using a deposition process;

[0020] Depositing a top electrode metal layer on top of the piezoelectric layer metal layer by a deposition process, and performing a patterning process on the top electrode metal layer in the second region;

[0021] The bottom electrode metal layer, the piezoelectric layer metal layer and the top electrode metal layer constitute a metal connection layer, and the metal connection layer in the second area is subjected to photolithography and corrosion processes to remove excess metal layers, and the cantilever beam is released to obtain a MEMS resonator unit;

[0022] The metal connection layer in the first area is removed with photolithography and etching processes to remove excess metal connection layer, leaving only the metal connection layer for connecting the PAD electrode in the ASIC driving circuit with the MEMS resonator unit, so that the MEMS resonator unit is connected to the ASIC driving circuit.

[0023] In the embodiment of the present application, the metal connection layer in the second region is subjected to photolithography and etching processes to remove the excess metal connection layer, and the cantilever beam is released to obtain a MEMS resonator unit, specifically,

[0024] After removing the excess metal connection layer from the metal connection layer in the second area by photolithography and etching processes, the top silicon layer and the buried oxide layer of the SOI wafer are etched by an etching process to obtain grooves, thereby releasing the cantilever beam to obtain a MEMS resonator unit.

[0025] In the embodiment of the present application, the bottom electrode metal layer material is molybdenum, the piezoelectric layer metal layer material is aluminum nitride, and the top electrode metal layer material is molybdenum.

[0026] The packaging structure and manufacturing method of the integrated MEMS and ASIC provided in the embodiment of the present application include an SOI wafer, wherein the top silicon surface of the SOI wafer is provided with a first area and a second area, wherein an ASIC driving circuit unit is provided in the first area, and wherein a MEMS resonator unit is provided in the second area. A metal connection layer is provided on the surface of the SOI wafer, and the ASIC driving circuit unit and the MEMS resonator unit are connected via the metal connection layer, and the ASIC driving circuit unit is used to excite the vibration of the MEMS resonator unit and process the output signal of the MEMS resonator unit. By arranging the MEMS resonator unit and the ASIC driving circuit unit on the same SOI wafer, there is no need to stack and thin the MEMS resonator unit and the ASIC driving circuit unit, so the volume of the packaging shell can be made smaller, so that the degree of integration between the MEMS resonator unit and the ASIC driving circuit unit is higher. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings herein are incorporated in and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the description, are used to explain the principles of the embodiments of the present application.

[0028] Figure 1A top view of the packaging structure integrating MEMS and ASIC provided in this application;

[0029] Figure 2 A flowchart of a method for manufacturing a packaging structure integrating MEMS and ASIC provided in the present application;

[0030] Figure 3 A schematic diagram of the structure of the integrated MEMS and ASIC packaging structure provided in the present application without metal deposition;

[0031] Figure 4 A schematic diagram of the structure of the integrated MEMS and ASIC packaging structure provided in the present application after three metal layers are deposited;

[0032] Figure 5 for Figure 4 Schematic diagram of the structure after removing the top electrode metal layer;

[0033] Figure 6 for Figure 5 Schematic diagram of the structure after removing the metal layer of the piezoelectric layer;

[0034] Figure 7 for Figure 6 Schematic diagram of the structure after removing the bottom electrode metal layer;

[0035] Figure 8 for Figure 7 Schematic diagram of the structure after removing part of the top silicon layer;

[0036] Fig. 9 for Figure 8 Schematic diagram of the structure after removing part of the buried oxide layer to form a groove.

[0037] Reference numerals:

[0038] 100-SOI wafer; 110-substrate silicon; 120-buried oxide layer; 130-top silicon; 140-groove;

[0039] 200-ASIC driving circuit unit; 210-PAD electrode;

[0040] 300-MEMS resonator unit; 310-cantilever beam;

[0041] 400 - metal connection layer; 410 - bottom electrode metal layer; 420 - piezoelectric layer metal layer; 430 - top electrode metal layer;

[0042] 500-passivation layer.

[0043] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be clearly and completely described below in conjunction with the drawings in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0045] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present application described herein can, for example, be implemented in an order other than those illustrated or described herein.

[0046] In the embodiments of the present application, the words "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0047] In the description of the embodiments of the present application, it should be understood that the terms "inside", "outside", "top", "bottom", "front", "back", etc. indicating the orientation or position relationship (if any) are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.

[0048] Glossary: ​​MEMS (Micro-Electro-Mechanical Systems) is a microsystem that integrates microelectronics, micromechanical and microsensor technologies. MEMS Die is a micro-electromechanical system bare chip. MEMS resonator is a miniature resonant device manufactured using micro-electromechanical system technology. ASIC drive circuit is an integrated circuit designed and optimized for specific applications, used to control and drive other electronic components or systems, and is used to drive MEMS resonators in this application. CMOS process is a complementary metal oxide semiconductor process and is the current mainstream integrated circuit manufacturing technology with the advantages of low power consumption, high speed and high density.

[0049] The packaging of the MEMS clock device in the prior art is mainly divided into a MEMS resonator part and a CMOS drive circuit part, and mainly adopts QFN, SOT, LCC, CSP and other packaging forms to integrate the MEMS Die and CMOS Die in a stacked manner.

[0050] However, in the process of packaging the MEMS Die and the CMOS Die, in order to meet the requirements of the packaging size, the MEMS Die and the CMOS Die need to be thinned, which makes the packaging method complicated.

[0051] Therefore, the embodiment of the present application provides a packaging structure integrating MEMS and ASIC and a manufacturing method thereof, by arranging the MEMS resonator unit and the ASIC driving circuit unit on the same SOI wafer, there is no need to stack the MEMS resonator unit and the ASIC driving circuit unit, so that the integration degree between the MEMS resonator unit and the ASIC driving circuit unit is higher. The present application will be described below in conjunction with the accompanying drawings.

[0052] in, Figure 1 A top view of the packaging structure integrating MEMS and ASIC provided in this application. Figure 2 This is a schematic diagram of the structure of the packaging structure integrating MEMS and ASIC provided in the present application without metal deposition. Figure 3 The present application provides a schematic diagram of the structure of the integrated MEMS and ASIC packaging structure after three metal layers are deposited. Figure 4 for Figure 3 Schematic diagram of the structure after removing the top electrode metal layer. Figure 5 for Figure 4 Schematic diagram of the structure after removing the metal layer of the piezoelectric layer. Figure 6 for Figure 5 Schematic diagram of the structure after removing the bottom electrode metal layer. Figure 7 for Figure 6 Schematic diagram of the structure after removing part of the top silicon. Figure 8 for Figure 7Schematic diagram of the structure after removing part of the buried oxide layer to form a groove.

[0053] like Figure 1 As shown, an embodiment of the present application provides a packaging structure integrating MEMS and ASIC, including an SOI wafer 100, wherein a first area and a second area are arranged on the surface of a top silicon 130 of the SOI wafer 100, an ASIC driving circuit unit 200 is arranged in the first area, and a MEMS resonator unit 300 is arranged in the second area.

[0054] A metal connection layer 400 is disposed on the surface of the SOI wafer 100 , and the ASIC driving circuit unit 200 and the MEMS resonator unit 300 are connected via the metal connection layer 400 . The ASIC driving circuit unit 200 is used to excite the vibration of the MEMS resonator unit 300 and process the output signal of the MEMS resonator unit 300 .

[0055] The SOI wafer 100 may be a wafer with a diameter of 10 cm, 15 cm, or 20 cm. The SOI wafer 100 is divided in the middle, wherein the right side is a first area, and the left side is a second area.

[0056] By placing the MEMS resonator unit 300 and the ASIC driving circuit unit 200 on the same SOI wafer 100 and connecting them through the metal connection layer 400, there is no need to stack and thin the MEMS resonator unit 300 and the ASIC driving circuit unit 200, so the volume of the packaging shell can be made smaller, making the integration between the MEMS resonator unit 300 and the ASIC driving circuit unit 200 higher.

[0057] At the same time, the MEMS resonator unit 300 and the ASIC driving circuit unit 200 are arranged on the same SOI wafer 100 and connected through the metal connection layer 400, without the need for additional connection lines, thus reducing the electrical interconnection between chips, and reducing power consumption and noise.

[0058] In the embodiment of the present application, a passivation layer 500 is disposed on the surface of the ASIC driving circuit unit 200 , and the passivation layer 500 is used to isolate the ASIC driving circuit unit 200 from contact with the outside air.

[0059] A passivation layer 500 is disposed on the surface of the ASIC driving circuit unit 200 by chemical vapor deposition (CVD) or physical vapor deposition (PVD), wherein the material of the passivation layer 500 is silicon oxide, silicon nitride or polyimide. One or more passivation layers 500 may be disposed according to actual needs. The main function of the passivation layer 500 is to protect the circuit from the influence of the external environment (such as moisture and pollutants in the air) on the circuit, thereby improving the reliability and life of the circuit.

[0060] In the embodiment of the present application, a groove 140 is provided on the SOI wafer 100 , and a cantilever beam 310 is provided on the MEMS resonator unit 300 . The cantilever beam 310 is located above the groove 140 .

[0061] The cantilever beam 310 is used to realize a high-precision and high-stability resonance function, and is a main component for the MEMS resonator unit 300 to generate a resonance signal.

[0062] In the embodiment of the present application, a dual cantilever beam 310 structure is adopted, and the two cantilever beams 310 are respectively located on two opposite sides of the MEMS resonator unit 300. Each cantilever beam 310 has a length of 150 microns, a width of 15 microns, and a thickness of 3 microns.

[0063] like Figure 2 As shown, for the above-mentioned packaging structure integrating MEMS and ASIC, the present application also proposes a method for manufacturing a packaging structure integrating MEMS and ASIC, including:

[0064] S100, providing an SOI wafer 100, and dividing a surface of a top silicon 130 of the SOI wafer 100 into a first region and a second region;

[0065] S200, manufacturing an ASIC driving circuit unit 200 in a first area;

[0066] S300 , manufacturing a MEMS resonator unit 300 in the second region, and connecting it to the ASIC driving circuit unit 200 through a metal connection layer 400 .

[0067] In the embodiment of the present application, the thickness of the substrate silicon 110 in the SOI wafer is 300-800 microns, the thickness of the buried oxide layer 120 is 1-5 microns, and the thickness of the top silicon 130 is 2-20 microns.

[0068] In the embodiment of the present application, the ASIC driving circuit unit 200 is manufactured in the first area, and the specific method is as follows:

[0069] In the first region on the top silicon layer 130 , the ASIC driving circuit unit 200 is manufactured using a 40-80 nanometer CMOS process.

[0070] Specifically, the ASIC driving circuit unit 200 is manufactured in the first region on the top silicon 130 using an 80-nanometer CMOS process. The ASIC driving circuit unit 200 includes an input interface, a signal processing unit, a power amplifier, and an output interface. Through the steps of photolithography, ion implantation, thin film deposition, and etching, a low-power, high-speed integrated circuit is formed.

[0071] like Figure 3As shown, in the embodiment of the present application, after the ASIC driving circuit unit 200 is manufactured in the first area, the ASIC driving circuit unit 200 is passivated using a passivation material to form a passivation layer 500 on the surface of the ASIC driving circuit unit 200, and the passivation layer 500 on the PAD electrode 210 in the ASIC driving circuit unit 200 is removed by photolithography and etching processes.

[0072] The PAD electrode 210 after the passivation layer 500 is removed is used to connect with the MEMS resonator unit 300 and to connect with an external circuit or pin.

[0073] Combination Figure 4-9 As shown, in the embodiment of the present application, a MEMS resonator unit 300 is manufactured in the second region and connected to the ASIC driving circuit unit 200 through a metal connection layer 400. The specific method is as follows:

[0074] Depositing a bottom electrode metal layer 410 on the upper surface of the top silicon layer 130 by a deposition process, and performing a patterning process on the bottom electrode metal layer 410 in the second region;

[0075] Depositing a piezoelectric metal layer 420 on top of the bottom electrode metal layer 410 using a deposition process;

[0076] Depositing a top electrode metal layer 430 on the top of the piezoelectric metal layer 420 by a deposition process, and performing a patterning process on the top electrode metal layer 430 in the second region;

[0077] The bottom electrode metal layer 410, the piezoelectric layer metal layer 420 and the top electrode metal layer 430 constitute a metal connection layer 400. The metal connection layer 400 in the second region is removed by photolithography and etching processes, and the cantilever beam 310 is released to obtain a MEMS resonator unit 300.

[0078] The metal connection layer 400 in the first region is removed by photolithography and etching processes, and only the metal connection layer 400 for connecting the PAD electrode 210 in the ASIC driving circuit and the MEMS resonator unit 300 is retained, so that the MEMS resonator unit 300 is connected to the ASIC driving circuit.

[0079] The bottom electrode metal layer 410 , the piezoelectric metal layer 420 , and the top electrode metal layer 430 are deposited on the upper surface of the top silicon layer 130 by a deposition process, and a chemical vapor deposition (CVD) or physical vapor deposition (PVD) method may be used.

[0080] In the embodiment of the present application, the metal connection layer 400 in the second region is subjected to photolithography and etching processes to remove the redundant metal connection layer 400 and release the cantilever beam 310 to obtain the MEMS resonator unit 300, specifically,

[0081] After removing the excess metal connection layer 400 in the second region by photolithography and etching, the top silicon 130 and the buried oxide layer 120 of the SOI wafer 100 are etched by etching to obtain the groove 140, thereby releasing the cantilever beam 310 and obtaining the MEMS resonator unit 300.

[0082] in, Figure 5-Figure 9 It is a schematic diagram of the steps of sequentially removing the top electrode metal layer 430 , the piezoelectric metal layer 420 , the bottom electrode metal layer 410 , the top silicon layer 130 and the buried oxide layer 120 to release the cantilever beam 310 .

[0083] In an embodiment of the present application, the material of the bottom electrode metal layer 410 is metal molybdenum, gold or platinum, with a thickness of 20 to 100 nm, the material of the piezoelectric layer metal layer 420 is aluminum nitride, lead zirconate titanate or zinc oxide, with a deposition thickness of 500 to 2000 nm, and the material of the top electrode metal layer 430 is molybdenum, gold or platinum, with a thickness of 20 to 100 nm.

[0084] In the present application, by setting the MEMS resonator unit 300 and the ASIC driving circuit unit 200 on the same SOI wafer 100, there is no need to stack and thin the MEMS resonator unit 300 and the ASIC driving circuit unit 200, so the volume of the packaging shell can be made smaller, so that the degree of integration between the MEMS resonator unit 300 and the ASIC driving circuit unit 200 is higher.

[0085] So far, the technical solution of the present application has been described in conjunction with the preferred embodiments shown in the accompanying drawings. However, it is easy for those skilled in the art to understand that the protection scope of the present application is obviously not limited to these specific embodiments. The above embodiments are only used to illustrate the technical solution of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

[0086] In general, terms should be understood, at least in part, by the context in which they are used. For example, the terms "one or more" as used herein may be used to describe any feature, structure, or characteristic in a singular sense, or may be used to describe a combination of features, structures, or characteristics in a plural sense, depending, at least in part, on the context. Similarly, terms such as "one" or "a plurality of" may also be understood to convey singular usage or to convey plural usage, depending, at least in part, on the context.

[0087] It should be easily understood that “on,” “above,” and “over” in the present disclosure should be interpreted in the broadest manner, so that “on” not only means “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “above” or “over” not only includes the meaning of “above” or “over,” but also may include the meaning of “above” or “over something” with no intervening features or layers therebetween (i.e., directly on something).

Claims

1. A method for manufacturing a packaging structure integrating MEMS and ASIC, characterized in that: The method comprises: Providing an SOI wafer (100), and dividing a surface of a top silicon layer (130) of the SOI wafer (100) into a first region and a second region; Fabricate an ASIC driving circuit unit (200) in the first area; A MEMS resonator unit (300) is manufactured in the second region, and connected to the ASIC driving circuit unit (200) via a metal connection layer (400); The MEMS resonator unit (300) is manufactured in the second region and connected to the ASIC driving circuit unit (200) via a metal connection layer (400), and the specific method is: Depositing a bottom electrode metal layer (410) on the upper surface of the top silicon layer (130) using a deposition process, and performing a patterning process on the bottom electrode metal layer (410) in the second region; Depositing a piezoelectric layer metal layer (420) on top of the bottom electrode metal layer (410) using a deposition process; Depositing a top electrode metal layer (430) on top of the piezoelectric layer metal layer (420) using a deposition process, and performing a patterning process on the top electrode metal layer (430) in the second region; The metal connection layer (400) comprises a bottom electrode metal layer (410), a piezoelectric layer metal layer (420) and a top electrode metal layer (430); the metal connection layer (400) in the second region is subjected to photolithography and etching processes to remove excess metal connection layer (400) and release the cantilever beam (310), thereby obtaining the MEMS resonator unit (300); The metal connection layer (400) in the first area is removed from excess metal connection layer (400) by photolithography and etching processes, and only the metal connection layer (400) for connecting the PAD electrode (210) in the ASIC drive circuit with the MEMS resonator unit (300) is retained, so that the MEMS resonator unit (300) is connected to the ASIC drive circuit.

2. The method for manufacturing a package structure integrating MEMS and ASIC according to claim 1, characterized in that: The thickness of the substrate silicon (110) in the SOI wafer is 300-800 microns, the thickness of the buried oxide layer (120) is 1-5 microns, and the thickness of the top silicon (130) is 2-20 microns.

3. The method for manufacturing a package structure integrating MEMS and ASIC according to claim 2, characterized in that: The ASIC driving circuit unit (200) is manufactured in the first area, and the specific method is: In the first region on the top silicon (130), an ASIC driving circuit unit (200) is manufactured using a 40-80 nanometer CMOS process.

4. The method for manufacturing a package structure integrating MEMS and ASIC according to claim 3, characterized in that: After the ASIC driving circuit unit (200) is manufactured in the first region, a passivation material is used to perform a passivation treatment on the ASIC driving circuit unit (200) to form a passivation layer (500) on the surface of the ASIC driving circuit unit (200), and the passivation layer (500) on the PAD electrode (210) in the ASIC driving circuit unit (200) is removed by photolithography and etching processes.

5. The method for manufacturing a package structure integrating MEMS and ASIC according to claim 1, characterized in that: The metal connection layer (400) in the second region is subjected to photolithography and etching processes to remove excess metal connection layer (400), and the cantilever beam (310) is released to obtain a MEMS resonator unit (300), specifically, After removing excess metal connection layer (400) from the metal connection layer (400) in the second region using photolithography and etching processes, the top silicon (130) and buried oxide layer (120) of the SOI wafer (100) are etched using an etching process to obtain a groove (140), thereby releasing the cantilever beam (310) and obtaining a MEMS resonator unit (300).

6. The method for manufacturing a package structure integrating MEMS and ASIC according to claim 5, characterized in that: The material of the bottom electrode metal layer (410) is molybdenum, the material of the piezoelectric layer metal layer (420) is aluminum nitride, and the material of the top electrode metal layer (430) is molybdenum.

7. A packaging structure integrating MEMS and ASIC, characterized in that: The integrated MEMS and ASIC packaging structure is used to execute the integrated MEMS and ASIC packaging structure manufacturing method according to any one of claims 1 to 6, the packaging structure comprising an SOI wafer (100), a top silicon (130) surface of the SOI wafer (100) being provided with a first area and a second area, the first area being provided with an ASIC driving circuit unit (200), and the second area being provided with a MEMS resonator unit (300); A metal connection layer (400) is provided on the surface of the SOI wafer (100); the ASIC driving circuit unit (200) and the MEMS resonator unit (300) are connected via the metal connection layer (400); the ASIC driving circuit unit (200) is used to excite the vibration of the MEMS resonator unit (300) and process an output signal of the MEMS resonator unit (300).

8. The packaging structure integrating MEMS and ASIC according to claim 7, characterized in that: A passivation layer (500) is provided on the surface of the ASIC driving circuit unit (200), and the passivation layer (500) is used to isolate the ASIC driving circuit unit (200) from contact with external air.

9. The packaging structure integrating MEMS and ASIC according to claim 8, characterized in that: The SOI wafer (100) is provided with a groove (140), and the MEMS resonator unit (300) is provided with a cantilever beam (310), wherein the cantilever beam (310) is located above the groove (140).

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